1 /* 2 * Driver for the Conexant CX23885 PCIe bridge 3 * 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * 15 * GNU General Public License for more details. 16 */ 17 18 #include <linux/init.h> 19 #include <linux/module.h> 20 #include <linux/pci.h> 21 #include <linux/delay.h> 22 #include <media/drv-intf/cx25840.h> 23 #include <linux/firmware.h> 24 #include <misc/altera.h> 25 26 #include "cx23885.h" 27 #include "tuner-xc2028.h" 28 #include "netup-eeprom.h" 29 #include "netup-init.h" 30 #include "altera-ci.h" 31 #include "xc4000.h" 32 #include "xc5000.h" 33 #include "cx23888-ir.h" 34 35 static unsigned int netup_card_rev = 4; 36 module_param(netup_card_rev, int, 0644); 37 MODULE_PARM_DESC(netup_card_rev, 38 "NetUP Dual DVB-T/C CI card revision"); 39 static unsigned int enable_885_ir; 40 module_param(enable_885_ir, int, 0644); 41 MODULE_PARM_DESC(enable_885_ir, 42 "Enable integrated IR controller for supported\n" 43 "\t\t CX2388[57] boards that are wired for it:\n" 44 "\t\t\tHVR-1250 (reported safe)\n" 45 "\t\t\tTerraTec Cinergy T PCIe Dual (not well tested, appears to be safe)\n" 46 "\t\t\tTeVii S470 (reported unsafe)\n" 47 "\t\t This can cause an interrupt storm with some cards.\n" 48 "\t\t Default: 0 [Disabled]"); 49 50 /* ------------------------------------------------------------------ */ 51 /* board config info */ 52 53 struct cx23885_board cx23885_boards[] = { 54 [CX23885_BOARD_UNKNOWN] = { 55 .name = "UNKNOWN/GENERIC", 56 /* Ensure safe default for unknown boards */ 57 .clk_freq = 0, 58 .input = {{ 59 .type = CX23885_VMUX_COMPOSITE1, 60 .vmux = 0, 61 }, { 62 .type = CX23885_VMUX_COMPOSITE2, 63 .vmux = 1, 64 }, { 65 .type = CX23885_VMUX_COMPOSITE3, 66 .vmux = 2, 67 }, { 68 .type = CX23885_VMUX_COMPOSITE4, 69 .vmux = 3, 70 } }, 71 }, 72 [CX23885_BOARD_HAUPPAUGE_HVR1800lp] = { 73 .name = "Hauppauge WinTV-HVR1800lp", 74 .portc = CX23885_MPEG_DVB, 75 .input = {{ 76 .type = CX23885_VMUX_TELEVISION, 77 .vmux = 0, 78 .gpio0 = 0xff00, 79 }, { 80 .type = CX23885_VMUX_DEBUG, 81 .vmux = 0, 82 .gpio0 = 0xff01, 83 }, { 84 .type = CX23885_VMUX_COMPOSITE1, 85 .vmux = 1, 86 .gpio0 = 0xff02, 87 }, { 88 .type = CX23885_VMUX_SVIDEO, 89 .vmux = 2, 90 .gpio0 = 0xff02, 91 } }, 92 }, 93 [CX23885_BOARD_HAUPPAUGE_HVR1800] = { 94 .name = "Hauppauge WinTV-HVR1800", 95 .porta = CX23885_ANALOG_VIDEO, 96 .portb = CX23885_MPEG_ENCODER, 97 .portc = CX23885_MPEG_DVB, 98 .tuner_type = TUNER_PHILIPS_TDA8290, 99 .tuner_addr = 0x42, /* 0x84 >> 1 */ 100 .tuner_bus = 1, 101 .input = {{ 102 .type = CX23885_VMUX_TELEVISION, 103 .vmux = CX25840_VIN7_CH3 | 104 CX25840_VIN5_CH2 | 105 CX25840_VIN2_CH1, 106 .amux = CX25840_AUDIO8, 107 .gpio0 = 0, 108 }, { 109 .type = CX23885_VMUX_COMPOSITE1, 110 .vmux = CX25840_VIN7_CH3 | 111 CX25840_VIN4_CH2 | 112 CX25840_VIN6_CH1, 113 .amux = CX25840_AUDIO7, 114 .gpio0 = 0, 115 }, { 116 .type = CX23885_VMUX_SVIDEO, 117 .vmux = CX25840_VIN7_CH3 | 118 CX25840_VIN4_CH2 | 119 CX25840_VIN8_CH1 | 120 CX25840_SVIDEO_ON, 121 .amux = CX25840_AUDIO7, 122 .gpio0 = 0, 123 } }, 124 }, 125 [CX23885_BOARD_HAUPPAUGE_HVR1250] = { 126 .name = "Hauppauge WinTV-HVR1250", 127 .porta = CX23885_ANALOG_VIDEO, 128 .portc = CX23885_MPEG_DVB, 129 #ifdef MT2131_NO_ANALOG_SUPPORT_YET 130 .tuner_type = TUNER_PHILIPS_TDA8290, 131 .tuner_addr = 0x42, /* 0x84 >> 1 */ 132 .tuner_bus = 1, 133 #endif 134 .force_bff = 1, 135 .input = {{ 136 #ifdef MT2131_NO_ANALOG_SUPPORT_YET 137 .type = CX23885_VMUX_TELEVISION, 138 .vmux = CX25840_VIN7_CH3 | 139 CX25840_VIN5_CH2 | 140 CX25840_VIN2_CH1, 141 .amux = CX25840_AUDIO8, 142 .gpio0 = 0xff00, 143 }, { 144 #endif 145 .type = CX23885_VMUX_COMPOSITE1, 146 .vmux = CX25840_VIN7_CH3 | 147 CX25840_VIN4_CH2 | 148 CX25840_VIN6_CH1, 149 .amux = CX25840_AUDIO7, 150 .gpio0 = 0xff02, 151 }, { 152 .type = CX23885_VMUX_SVIDEO, 153 .vmux = CX25840_VIN7_CH3 | 154 CX25840_VIN4_CH2 | 155 CX25840_VIN8_CH1 | 156 CX25840_SVIDEO_ON, 157 .amux = CX25840_AUDIO7, 158 .gpio0 = 0xff02, 159 } }, 160 }, 161 [CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP] = { 162 .name = "DViCO FusionHDTV5 Express", 163 .portb = CX23885_MPEG_DVB, 164 }, 165 [CX23885_BOARD_HAUPPAUGE_HVR1500Q] = { 166 .name = "Hauppauge WinTV-HVR1500Q", 167 .portc = CX23885_MPEG_DVB, 168 }, 169 [CX23885_BOARD_HAUPPAUGE_HVR1500] = { 170 .name = "Hauppauge WinTV-HVR1500", 171 .porta = CX23885_ANALOG_VIDEO, 172 .portc = CX23885_MPEG_DVB, 173 .tuner_type = TUNER_XC2028, 174 .tuner_addr = 0x61, /* 0xc2 >> 1 */ 175 .input = {{ 176 .type = CX23885_VMUX_TELEVISION, 177 .vmux = CX25840_VIN7_CH3 | 178 CX25840_VIN5_CH2 | 179 CX25840_VIN2_CH1, 180 .gpio0 = 0, 181 }, { 182 .type = CX23885_VMUX_COMPOSITE1, 183 .vmux = CX25840_VIN7_CH3 | 184 CX25840_VIN4_CH2 | 185 CX25840_VIN6_CH1, 186 .gpio0 = 0, 187 }, { 188 .type = CX23885_VMUX_SVIDEO, 189 .vmux = CX25840_VIN7_CH3 | 190 CX25840_VIN4_CH2 | 191 CX25840_VIN8_CH1 | 192 CX25840_SVIDEO_ON, 193 .gpio0 = 0, 194 } }, 195 }, 196 [CX23885_BOARD_HAUPPAUGE_HVR1200] = { 197 .name = "Hauppauge WinTV-HVR1200", 198 .portc = CX23885_MPEG_DVB, 199 }, 200 [CX23885_BOARD_HAUPPAUGE_HVR1700] = { 201 .name = "Hauppauge WinTV-HVR1700", 202 .portc = CX23885_MPEG_DVB, 203 }, 204 [CX23885_BOARD_HAUPPAUGE_HVR1400] = { 205 .name = "Hauppauge WinTV-HVR1400", 206 .portc = CX23885_MPEG_DVB, 207 }, 208 [CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP] = { 209 .name = "DViCO FusionHDTV7 Dual Express", 210 .portb = CX23885_MPEG_DVB, 211 .portc = CX23885_MPEG_DVB, 212 }, 213 [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP] = { 214 .name = "DViCO FusionHDTV DVB-T Dual Express", 215 .portb = CX23885_MPEG_DVB, 216 .portc = CX23885_MPEG_DVB, 217 }, 218 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H] = { 219 .name = "Leadtek Winfast PxDVR3200 H", 220 .portc = CX23885_MPEG_DVB, 221 }, 222 [CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200] = { 223 .name = "Leadtek Winfast PxPVR2200", 224 .porta = CX23885_ANALOG_VIDEO, 225 .tuner_type = TUNER_XC2028, 226 .tuner_addr = 0x61, 227 .tuner_bus = 1, 228 .input = {{ 229 .type = CX23885_VMUX_TELEVISION, 230 .vmux = CX25840_VIN2_CH1 | 231 CX25840_VIN5_CH2, 232 .amux = CX25840_AUDIO8, 233 .gpio0 = 0x704040, 234 }, { 235 .type = CX23885_VMUX_COMPOSITE1, 236 .vmux = CX25840_COMPOSITE1, 237 .amux = CX25840_AUDIO7, 238 .gpio0 = 0x704040, 239 }, { 240 .type = CX23885_VMUX_SVIDEO, 241 .vmux = CX25840_SVIDEO_LUMA3 | 242 CX25840_SVIDEO_CHROMA4, 243 .amux = CX25840_AUDIO7, 244 .gpio0 = 0x704040, 245 }, { 246 .type = CX23885_VMUX_COMPONENT, 247 .vmux = CX25840_VIN7_CH1 | 248 CX25840_VIN6_CH2 | 249 CX25840_VIN8_CH3 | 250 CX25840_COMPONENT_ON, 251 .amux = CX25840_AUDIO7, 252 .gpio0 = 0x704040, 253 } }, 254 }, 255 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000] = { 256 .name = "Leadtek Winfast PxDVR3200 H XC4000", 257 .porta = CX23885_ANALOG_VIDEO, 258 .portc = CX23885_MPEG_DVB, 259 .tuner_type = TUNER_XC4000, 260 .tuner_addr = 0x61, 261 .radio_type = UNSET, 262 .radio_addr = ADDR_UNSET, 263 .input = {{ 264 .type = CX23885_VMUX_TELEVISION, 265 .vmux = CX25840_VIN2_CH1 | 266 CX25840_VIN5_CH2 | 267 CX25840_NONE0_CH3, 268 }, { 269 .type = CX23885_VMUX_COMPOSITE1, 270 .vmux = CX25840_COMPOSITE1, 271 }, { 272 .type = CX23885_VMUX_SVIDEO, 273 .vmux = CX25840_SVIDEO_LUMA3 | 274 CX25840_SVIDEO_CHROMA4, 275 }, { 276 .type = CX23885_VMUX_COMPONENT, 277 .vmux = CX25840_VIN7_CH1 | 278 CX25840_VIN6_CH2 | 279 CX25840_VIN8_CH3 | 280 CX25840_COMPONENT_ON, 281 } }, 282 }, 283 [CX23885_BOARD_COMPRO_VIDEOMATE_E650F] = { 284 .name = "Compro VideoMate E650F", 285 .portc = CX23885_MPEG_DVB, 286 }, 287 [CX23885_BOARD_TBS_6920] = { 288 .name = "TurboSight TBS 6920", 289 .portb = CX23885_MPEG_DVB, 290 }, 291 [CX23885_BOARD_TBS_6980] = { 292 .name = "TurboSight TBS 6980", 293 .portb = CX23885_MPEG_DVB, 294 .portc = CX23885_MPEG_DVB, 295 }, 296 [CX23885_BOARD_TBS_6981] = { 297 .name = "TurboSight TBS 6981", 298 .portb = CX23885_MPEG_DVB, 299 .portc = CX23885_MPEG_DVB, 300 }, 301 [CX23885_BOARD_TEVII_S470] = { 302 .name = "TeVii S470", 303 .portb = CX23885_MPEG_DVB, 304 }, 305 [CX23885_BOARD_DVBWORLD_2005] = { 306 .name = "DVBWorld DVB-S2 2005", 307 .portb = CX23885_MPEG_DVB, 308 }, 309 [CX23885_BOARD_NETUP_DUAL_DVBS2_CI] = { 310 .ci_type = 1, 311 .name = "NetUP Dual DVB-S2 CI", 312 .portb = CX23885_MPEG_DVB, 313 .portc = CX23885_MPEG_DVB, 314 }, 315 [CX23885_BOARD_HAUPPAUGE_HVR1270] = { 316 .name = "Hauppauge WinTV-HVR1270", 317 .portc = CX23885_MPEG_DVB, 318 }, 319 [CX23885_BOARD_HAUPPAUGE_HVR1275] = { 320 .name = "Hauppauge WinTV-HVR1275", 321 .portc = CX23885_MPEG_DVB, 322 }, 323 [CX23885_BOARD_HAUPPAUGE_HVR1255] = { 324 .name = "Hauppauge WinTV-HVR1255", 325 .porta = CX23885_ANALOG_VIDEO, 326 .portc = CX23885_MPEG_DVB, 327 .tuner_type = TUNER_ABSENT, 328 .tuner_addr = 0x42, /* 0x84 >> 1 */ 329 .force_bff = 1, 330 .input = {{ 331 .type = CX23885_VMUX_TELEVISION, 332 .vmux = CX25840_VIN7_CH3 | 333 CX25840_VIN5_CH2 | 334 CX25840_VIN2_CH1 | 335 CX25840_DIF_ON, 336 .amux = CX25840_AUDIO8, 337 }, { 338 .type = CX23885_VMUX_COMPOSITE1, 339 .vmux = CX25840_VIN7_CH3 | 340 CX25840_VIN4_CH2 | 341 CX25840_VIN6_CH1, 342 .amux = CX25840_AUDIO7, 343 }, { 344 .type = CX23885_VMUX_SVIDEO, 345 .vmux = CX25840_VIN7_CH3 | 346 CX25840_VIN4_CH2 | 347 CX25840_VIN8_CH1 | 348 CX25840_SVIDEO_ON, 349 .amux = CX25840_AUDIO7, 350 } }, 351 }, 352 [CX23885_BOARD_HAUPPAUGE_HVR1255_22111] = { 353 .name = "Hauppauge WinTV-HVR1255", 354 .porta = CX23885_ANALOG_VIDEO, 355 .portc = CX23885_MPEG_DVB, 356 .tuner_type = TUNER_ABSENT, 357 .tuner_addr = 0x42, /* 0x84 >> 1 */ 358 .force_bff = 1, 359 .input = {{ 360 .type = CX23885_VMUX_TELEVISION, 361 .vmux = CX25840_VIN7_CH3 | 362 CX25840_VIN5_CH2 | 363 CX25840_VIN2_CH1 | 364 CX25840_DIF_ON, 365 .amux = CX25840_AUDIO8, 366 }, { 367 .type = CX23885_VMUX_SVIDEO, 368 .vmux = CX25840_VIN7_CH3 | 369 CX25840_VIN4_CH2 | 370 CX25840_VIN8_CH1 | 371 CX25840_SVIDEO_ON, 372 .amux = CX25840_AUDIO7, 373 } }, 374 }, 375 [CX23885_BOARD_HAUPPAUGE_HVR1210] = { 376 .name = "Hauppauge WinTV-HVR1210", 377 .portc = CX23885_MPEG_DVB, 378 }, 379 [CX23885_BOARD_MYGICA_X8506] = { 380 .name = "Mygica X8506 DMB-TH", 381 .tuner_type = TUNER_XC5000, 382 .tuner_addr = 0x61, 383 .tuner_bus = 1, 384 .porta = CX23885_ANALOG_VIDEO, 385 .portb = CX23885_MPEG_DVB, 386 .input = { 387 { 388 .type = CX23885_VMUX_TELEVISION, 389 .vmux = CX25840_COMPOSITE2, 390 }, 391 { 392 .type = CX23885_VMUX_COMPOSITE1, 393 .vmux = CX25840_COMPOSITE8, 394 }, 395 { 396 .type = CX23885_VMUX_SVIDEO, 397 .vmux = CX25840_SVIDEO_LUMA3 | 398 CX25840_SVIDEO_CHROMA4, 399 }, 400 { 401 .type = CX23885_VMUX_COMPONENT, 402 .vmux = CX25840_COMPONENT_ON | 403 CX25840_VIN1_CH1 | 404 CX25840_VIN6_CH2 | 405 CX25840_VIN7_CH3, 406 }, 407 }, 408 }, 409 [CX23885_BOARD_MAGICPRO_PROHDTVE2] = { 410 .name = "Magic-Pro ProHDTV Extreme 2", 411 .tuner_type = TUNER_XC5000, 412 .tuner_addr = 0x61, 413 .tuner_bus = 1, 414 .porta = CX23885_ANALOG_VIDEO, 415 .portb = CX23885_MPEG_DVB, 416 .input = { 417 { 418 .type = CX23885_VMUX_TELEVISION, 419 .vmux = CX25840_COMPOSITE2, 420 }, 421 { 422 .type = CX23885_VMUX_COMPOSITE1, 423 .vmux = CX25840_COMPOSITE8, 424 }, 425 { 426 .type = CX23885_VMUX_SVIDEO, 427 .vmux = CX25840_SVIDEO_LUMA3 | 428 CX25840_SVIDEO_CHROMA4, 429 }, 430 { 431 .type = CX23885_VMUX_COMPONENT, 432 .vmux = CX25840_COMPONENT_ON | 433 CX25840_VIN1_CH1 | 434 CX25840_VIN6_CH2 | 435 CX25840_VIN7_CH3, 436 }, 437 }, 438 }, 439 [CX23885_BOARD_HAUPPAUGE_HVR1850] = { 440 .name = "Hauppauge WinTV-HVR1850", 441 .porta = CX23885_ANALOG_VIDEO, 442 .portb = CX23885_MPEG_ENCODER, 443 .portc = CX23885_MPEG_DVB, 444 .tuner_type = TUNER_ABSENT, 445 .tuner_addr = 0x42, /* 0x84 >> 1 */ 446 .force_bff = 1, 447 .input = {{ 448 .type = CX23885_VMUX_TELEVISION, 449 .vmux = CX25840_VIN7_CH3 | 450 CX25840_VIN5_CH2 | 451 CX25840_VIN2_CH1 | 452 CX25840_DIF_ON, 453 .amux = CX25840_AUDIO8, 454 }, { 455 .type = CX23885_VMUX_COMPOSITE1, 456 .vmux = CX25840_VIN7_CH3 | 457 CX25840_VIN4_CH2 | 458 CX25840_VIN6_CH1, 459 .amux = CX25840_AUDIO7, 460 }, { 461 .type = CX23885_VMUX_SVIDEO, 462 .vmux = CX25840_VIN7_CH3 | 463 CX25840_VIN4_CH2 | 464 CX25840_VIN8_CH1 | 465 CX25840_SVIDEO_ON, 466 .amux = CX25840_AUDIO7, 467 } }, 468 }, 469 [CX23885_BOARD_COMPRO_VIDEOMATE_E800] = { 470 .name = "Compro VideoMate E800", 471 .portc = CX23885_MPEG_DVB, 472 }, 473 [CX23885_BOARD_HAUPPAUGE_HVR1290] = { 474 .name = "Hauppauge WinTV-HVR1290", 475 .portc = CX23885_MPEG_DVB, 476 }, 477 [CX23885_BOARD_MYGICA_X8558PRO] = { 478 .name = "Mygica X8558 PRO DMB-TH", 479 .portb = CX23885_MPEG_DVB, 480 .portc = CX23885_MPEG_DVB, 481 }, 482 [CX23885_BOARD_LEADTEK_WINFAST_PXTV1200] = { 483 .name = "LEADTEK WinFast PxTV1200", 484 .porta = CX23885_ANALOG_VIDEO, 485 .tuner_type = TUNER_XC2028, 486 .tuner_addr = 0x61, 487 .tuner_bus = 1, 488 .input = {{ 489 .type = CX23885_VMUX_TELEVISION, 490 .vmux = CX25840_VIN2_CH1 | 491 CX25840_VIN5_CH2 | 492 CX25840_NONE0_CH3, 493 }, { 494 .type = CX23885_VMUX_COMPOSITE1, 495 .vmux = CX25840_COMPOSITE1, 496 }, { 497 .type = CX23885_VMUX_SVIDEO, 498 .vmux = CX25840_SVIDEO_LUMA3 | 499 CX25840_SVIDEO_CHROMA4, 500 }, { 501 .type = CX23885_VMUX_COMPONENT, 502 .vmux = CX25840_VIN7_CH1 | 503 CX25840_VIN6_CH2 | 504 CX25840_VIN8_CH3 | 505 CX25840_COMPONENT_ON, 506 } }, 507 }, 508 [CX23885_BOARD_GOTVIEW_X5_3D_HYBRID] = { 509 .name = "GoTView X5 3D Hybrid", 510 .tuner_type = TUNER_XC5000, 511 .tuner_addr = 0x64, 512 .tuner_bus = 1, 513 .porta = CX23885_ANALOG_VIDEO, 514 .portb = CX23885_MPEG_DVB, 515 .input = {{ 516 .type = CX23885_VMUX_TELEVISION, 517 .vmux = CX25840_VIN2_CH1 | 518 CX25840_VIN5_CH2, 519 .gpio0 = 0x02, 520 }, { 521 .type = CX23885_VMUX_COMPOSITE1, 522 .vmux = CX23885_VMUX_COMPOSITE1, 523 }, { 524 .type = CX23885_VMUX_SVIDEO, 525 .vmux = CX25840_SVIDEO_LUMA3 | 526 CX25840_SVIDEO_CHROMA4, 527 } }, 528 }, 529 [CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF] = { 530 .ci_type = 2, 531 .name = "NetUP Dual DVB-T/C-CI RF", 532 .porta = CX23885_ANALOG_VIDEO, 533 .portb = CX23885_MPEG_DVB, 534 .portc = CX23885_MPEG_DVB, 535 .num_fds_portb = 2, 536 .num_fds_portc = 2, 537 .tuner_type = TUNER_XC5000, 538 .tuner_addr = 0x64, 539 .input = { { 540 .type = CX23885_VMUX_TELEVISION, 541 .vmux = CX25840_COMPOSITE1, 542 } }, 543 }, 544 [CX23885_BOARD_MPX885] = { 545 .name = "MPX-885", 546 .porta = CX23885_ANALOG_VIDEO, 547 .input = {{ 548 .type = CX23885_VMUX_COMPOSITE1, 549 .vmux = CX25840_COMPOSITE1, 550 .amux = CX25840_AUDIO6, 551 .gpio0 = 0, 552 }, { 553 .type = CX23885_VMUX_COMPOSITE2, 554 .vmux = CX25840_COMPOSITE2, 555 .amux = CX25840_AUDIO6, 556 .gpio0 = 0, 557 }, { 558 .type = CX23885_VMUX_COMPOSITE3, 559 .vmux = CX25840_COMPOSITE3, 560 .amux = CX25840_AUDIO7, 561 .gpio0 = 0, 562 }, { 563 .type = CX23885_VMUX_COMPOSITE4, 564 .vmux = CX25840_COMPOSITE4, 565 .amux = CX25840_AUDIO7, 566 .gpio0 = 0, 567 } }, 568 }, 569 [CX23885_BOARD_MYGICA_X8507] = { 570 .name = "Mygica X8502/X8507 ISDB-T", 571 .tuner_type = TUNER_XC5000, 572 .tuner_addr = 0x61, 573 .tuner_bus = 1, 574 .porta = CX23885_ANALOG_VIDEO, 575 .portb = CX23885_MPEG_DVB, 576 .input = { 577 { 578 .type = CX23885_VMUX_TELEVISION, 579 .vmux = CX25840_COMPOSITE2, 580 .amux = CX25840_AUDIO8, 581 }, 582 { 583 .type = CX23885_VMUX_COMPOSITE1, 584 .vmux = CX25840_COMPOSITE8, 585 .amux = CX25840_AUDIO7, 586 }, 587 { 588 .type = CX23885_VMUX_SVIDEO, 589 .vmux = CX25840_SVIDEO_LUMA3 | 590 CX25840_SVIDEO_CHROMA4, 591 .amux = CX25840_AUDIO7, 592 }, 593 { 594 .type = CX23885_VMUX_COMPONENT, 595 .vmux = CX25840_COMPONENT_ON | 596 CX25840_VIN1_CH1 | 597 CX25840_VIN6_CH2 | 598 CX25840_VIN7_CH3, 599 .amux = CX25840_AUDIO7, 600 }, 601 }, 602 }, 603 [CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL] = { 604 .name = "TerraTec Cinergy T PCIe Dual", 605 .portb = CX23885_MPEG_DVB, 606 .portc = CX23885_MPEG_DVB, 607 }, 608 [CX23885_BOARD_TEVII_S471] = { 609 .name = "TeVii S471", 610 .portb = CX23885_MPEG_DVB, 611 }, 612 [CX23885_BOARD_PROF_8000] = { 613 .name = "Prof Revolution DVB-S2 8000", 614 .portb = CX23885_MPEG_DVB, 615 }, 616 [CX23885_BOARD_HAUPPAUGE_HVR4400] = { 617 .name = "Hauppauge WinTV-HVR4400/HVR5500", 618 .porta = CX23885_ANALOG_VIDEO, 619 .portb = CX23885_MPEG_DVB, 620 .portc = CX23885_MPEG_DVB, 621 .tuner_type = TUNER_NXP_TDA18271, 622 .tuner_addr = 0x60, /* 0xc0 >> 1 */ 623 .tuner_bus = 1, 624 }, 625 [CX23885_BOARD_HAUPPAUGE_STARBURST] = { 626 .name = "Hauppauge WinTV Starburst", 627 .portb = CX23885_MPEG_DVB, 628 }, 629 [CX23885_BOARD_AVERMEDIA_HC81R] = { 630 .name = "AVerTV Hybrid Express Slim HC81R", 631 .tuner_type = TUNER_XC2028, 632 .tuner_addr = 0x61, /* 0xc2 >> 1 */ 633 .tuner_bus = 1, 634 .porta = CX23885_ANALOG_VIDEO, 635 .input = {{ 636 .type = CX23885_VMUX_TELEVISION, 637 .vmux = CX25840_VIN2_CH1 | 638 CX25840_VIN5_CH2 | 639 CX25840_NONE0_CH3 | 640 CX25840_NONE1_CH3, 641 .amux = CX25840_AUDIO8, 642 }, { 643 .type = CX23885_VMUX_SVIDEO, 644 .vmux = CX25840_VIN8_CH1 | 645 CX25840_NONE_CH2 | 646 CX25840_VIN7_CH3 | 647 CX25840_SVIDEO_ON, 648 .amux = CX25840_AUDIO6, 649 }, { 650 .type = CX23885_VMUX_COMPONENT, 651 .vmux = CX25840_VIN1_CH1 | 652 CX25840_NONE_CH2 | 653 CX25840_NONE0_CH3 | 654 CX25840_NONE1_CH3, 655 .amux = CX25840_AUDIO6, 656 } }, 657 }, 658 [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2] = { 659 .name = "DViCO FusionHDTV DVB-T Dual Express2", 660 .portb = CX23885_MPEG_DVB, 661 .portc = CX23885_MPEG_DVB, 662 }, 663 [CX23885_BOARD_HAUPPAUGE_IMPACTVCBE] = { 664 .name = "Hauppauge ImpactVCB-e", 665 .tuner_type = TUNER_ABSENT, 666 .porta = CX23885_ANALOG_VIDEO, 667 .input = {{ 668 .type = CX23885_VMUX_COMPOSITE1, 669 .vmux = CX25840_VIN7_CH3 | 670 CX25840_VIN4_CH2 | 671 CX25840_VIN6_CH1, 672 .amux = CX25840_AUDIO7, 673 }, { 674 .type = CX23885_VMUX_SVIDEO, 675 .vmux = CX25840_VIN7_CH3 | 676 CX25840_VIN4_CH2 | 677 CX25840_VIN8_CH1 | 678 CX25840_SVIDEO_ON, 679 .amux = CX25840_AUDIO7, 680 } }, 681 }, 682 [CX23885_BOARD_DVBSKY_T9580] = { 683 .name = "DVBSky T9580", 684 .portb = CX23885_MPEG_DVB, 685 .portc = CX23885_MPEG_DVB, 686 }, 687 [CX23885_BOARD_DVBSKY_T980C] = { 688 .name = "DVBSky T980C", 689 .portb = CX23885_MPEG_DVB, 690 }, 691 [CX23885_BOARD_DVBSKY_S950C] = { 692 .name = "DVBSky S950C", 693 .portb = CX23885_MPEG_DVB, 694 }, 695 [CX23885_BOARD_TT_CT2_4500_CI] = { 696 .name = "Technotrend TT-budget CT2-4500 CI", 697 .portb = CX23885_MPEG_DVB, 698 }, 699 [CX23885_BOARD_DVBSKY_S950] = { 700 .name = "DVBSky S950", 701 .portb = CX23885_MPEG_DVB, 702 }, 703 [CX23885_BOARD_DVBSKY_S952] = { 704 .name = "DVBSky S952", 705 .portb = CX23885_MPEG_DVB, 706 .portc = CX23885_MPEG_DVB, 707 }, 708 [CX23885_BOARD_DVBSKY_T982] = { 709 .name = "DVBSky T982", 710 .portb = CX23885_MPEG_DVB, 711 .portc = CX23885_MPEG_DVB, 712 }, 713 [CX23885_BOARD_HAUPPAUGE_HVR5525] = { 714 .name = "Hauppauge WinTV-HVR5525", 715 .portb = CX23885_MPEG_DVB, 716 .portc = CX23885_MPEG_DVB, 717 }, 718 [CX23885_BOARD_VIEWCAST_260E] = { 719 .name = "ViewCast 260e", 720 .porta = CX23885_ANALOG_VIDEO, 721 .force_bff = 1, 722 .input = {{ 723 .type = CX23885_VMUX_COMPOSITE1, 724 .vmux = CX25840_VIN6_CH1, 725 .amux = CX25840_AUDIO7, 726 }, { 727 .type = CX23885_VMUX_SVIDEO, 728 .vmux = CX25840_VIN7_CH3 | 729 CX25840_VIN5_CH1 | 730 CX25840_SVIDEO_ON, 731 .amux = CX25840_AUDIO7, 732 }, { 733 .type = CX23885_VMUX_COMPONENT, 734 .vmux = CX25840_VIN7_CH3 | 735 CX25840_VIN6_CH2 | 736 CX25840_VIN5_CH1 | 737 CX25840_COMPONENT_ON, 738 .amux = CX25840_AUDIO7, 739 } }, 740 }, 741 [CX23885_BOARD_VIEWCAST_460E] = { 742 .name = "ViewCast 460e", 743 .porta = CX23885_ANALOG_VIDEO, 744 .force_bff = 1, 745 .input = {{ 746 .type = CX23885_VMUX_COMPOSITE1, 747 .vmux = CX25840_VIN4_CH1, 748 .amux = CX25840_AUDIO7, 749 }, { 750 .type = CX23885_VMUX_SVIDEO, 751 .vmux = CX25840_VIN7_CH3 | 752 CX25840_VIN6_CH1 | 753 CX25840_SVIDEO_ON, 754 .amux = CX25840_AUDIO7, 755 }, { 756 .type = CX23885_VMUX_COMPONENT, 757 .vmux = CX25840_VIN7_CH3 | 758 CX25840_VIN6_CH1 | 759 CX25840_VIN5_CH2 | 760 CX25840_COMPONENT_ON, 761 .amux = CX25840_AUDIO7, 762 }, { 763 .type = CX23885_VMUX_COMPOSITE2, 764 .vmux = CX25840_VIN6_CH1, 765 .amux = CX25840_AUDIO7, 766 } }, 767 }, 768 }; 769 const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards); 770 771 /* ------------------------------------------------------------------ */ 772 /* PCI subsystem IDs */ 773 774 struct cx23885_subid cx23885_subids[] = { 775 { 776 .subvendor = 0x0070, 777 .subdevice = 0x3400, 778 .card = CX23885_BOARD_UNKNOWN, 779 }, { 780 .subvendor = 0x0070, 781 .subdevice = 0x7600, 782 .card = CX23885_BOARD_HAUPPAUGE_HVR1800lp, 783 }, { 784 .subvendor = 0x0070, 785 .subdevice = 0x7800, 786 .card = CX23885_BOARD_HAUPPAUGE_HVR1800, 787 }, { 788 .subvendor = 0x0070, 789 .subdevice = 0x7801, 790 .card = CX23885_BOARD_HAUPPAUGE_HVR1800, 791 }, { 792 .subvendor = 0x0070, 793 .subdevice = 0x7809, 794 .card = CX23885_BOARD_HAUPPAUGE_HVR1800, 795 }, { 796 .subvendor = 0x0070, 797 .subdevice = 0x7911, 798 .card = CX23885_BOARD_HAUPPAUGE_HVR1250, 799 }, { 800 .subvendor = 0x18ac, 801 .subdevice = 0xd500, 802 .card = CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP, 803 }, { 804 .subvendor = 0x0070, 805 .subdevice = 0x7790, 806 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q, 807 }, { 808 .subvendor = 0x0070, 809 .subdevice = 0x7797, 810 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q, 811 }, { 812 .subvendor = 0x0070, 813 .subdevice = 0x7710, 814 .card = CX23885_BOARD_HAUPPAUGE_HVR1500, 815 }, { 816 .subvendor = 0x0070, 817 .subdevice = 0x7717, 818 .card = CX23885_BOARD_HAUPPAUGE_HVR1500, 819 }, { 820 .subvendor = 0x0070, 821 .subdevice = 0x71d1, 822 .card = CX23885_BOARD_HAUPPAUGE_HVR1200, 823 }, { 824 .subvendor = 0x0070, 825 .subdevice = 0x71d3, 826 .card = CX23885_BOARD_HAUPPAUGE_HVR1200, 827 }, { 828 .subvendor = 0x0070, 829 .subdevice = 0x8101, 830 .card = CX23885_BOARD_HAUPPAUGE_HVR1700, 831 }, { 832 .subvendor = 0x0070, 833 .subdevice = 0x8010, 834 .card = CX23885_BOARD_HAUPPAUGE_HVR1400, 835 }, { 836 .subvendor = 0x18ac, 837 .subdevice = 0xd618, 838 .card = CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP, 839 }, { 840 .subvendor = 0x18ac, 841 .subdevice = 0xdb78, 842 .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP, 843 }, { 844 .subvendor = 0x107d, 845 .subdevice = 0x6681, 846 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H, 847 }, { 848 .subvendor = 0x107d, 849 .subdevice = 0x6f21, 850 .card = CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200, 851 }, { 852 .subvendor = 0x107d, 853 .subdevice = 0x6f39, 854 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000, 855 }, { 856 .subvendor = 0x185b, 857 .subdevice = 0xe800, 858 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E650F, 859 }, { 860 .subvendor = 0x6920, 861 .subdevice = 0x8888, 862 .card = CX23885_BOARD_TBS_6920, 863 }, { 864 .subvendor = 0x6980, 865 .subdevice = 0x8888, 866 .card = CX23885_BOARD_TBS_6980, 867 }, { 868 .subvendor = 0x6981, 869 .subdevice = 0x8888, 870 .card = CX23885_BOARD_TBS_6981, 871 }, { 872 .subvendor = 0xd470, 873 .subdevice = 0x9022, 874 .card = CX23885_BOARD_TEVII_S470, 875 }, { 876 .subvendor = 0x0001, 877 .subdevice = 0x2005, 878 .card = CX23885_BOARD_DVBWORLD_2005, 879 }, { 880 .subvendor = 0x1b55, 881 .subdevice = 0x2a2c, 882 .card = CX23885_BOARD_NETUP_DUAL_DVBS2_CI, 883 }, { 884 .subvendor = 0x0070, 885 .subdevice = 0x2211, 886 .card = CX23885_BOARD_HAUPPAUGE_HVR1270, 887 }, { 888 .subvendor = 0x0070, 889 .subdevice = 0x2215, 890 .card = CX23885_BOARD_HAUPPAUGE_HVR1275, 891 }, { 892 .subvendor = 0x0070, 893 .subdevice = 0x221d, 894 .card = CX23885_BOARD_HAUPPAUGE_HVR1275, 895 }, { 896 .subvendor = 0x0070, 897 .subdevice = 0x2251, 898 .card = CX23885_BOARD_HAUPPAUGE_HVR1255, 899 }, { 900 .subvendor = 0x0070, 901 .subdevice = 0x2259, 902 .card = CX23885_BOARD_HAUPPAUGE_HVR1255_22111, 903 }, { 904 .subvendor = 0x0070, 905 .subdevice = 0x2291, 906 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 907 }, { 908 .subvendor = 0x0070, 909 .subdevice = 0x2295, 910 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 911 }, { 912 .subvendor = 0x0070, 913 .subdevice = 0x2299, 914 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 915 }, { 916 .subvendor = 0x0070, 917 .subdevice = 0x229d, 918 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */ 919 }, { 920 .subvendor = 0x0070, 921 .subdevice = 0x22f0, 922 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 923 }, { 924 .subvendor = 0x0070, 925 .subdevice = 0x22f1, 926 .card = CX23885_BOARD_HAUPPAUGE_HVR1255, 927 }, { 928 .subvendor = 0x0070, 929 .subdevice = 0x22f2, 930 .card = CX23885_BOARD_HAUPPAUGE_HVR1275, 931 }, { 932 .subvendor = 0x0070, 933 .subdevice = 0x22f3, 934 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */ 935 }, { 936 .subvendor = 0x0070, 937 .subdevice = 0x22f4, 938 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 939 }, { 940 .subvendor = 0x0070, 941 .subdevice = 0x22f5, 942 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */ 943 }, { 944 .subvendor = 0x14f1, 945 .subdevice = 0x8651, 946 .card = CX23885_BOARD_MYGICA_X8506, 947 }, { 948 .subvendor = 0x14f1, 949 .subdevice = 0x8657, 950 .card = CX23885_BOARD_MAGICPRO_PROHDTVE2, 951 }, { 952 .subvendor = 0x0070, 953 .subdevice = 0x8541, 954 .card = CX23885_BOARD_HAUPPAUGE_HVR1850, 955 }, { 956 .subvendor = 0x1858, 957 .subdevice = 0xe800, 958 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E800, 959 }, { 960 .subvendor = 0x0070, 961 .subdevice = 0x8551, 962 .card = CX23885_BOARD_HAUPPAUGE_HVR1290, 963 }, { 964 .subvendor = 0x14f1, 965 .subdevice = 0x8578, 966 .card = CX23885_BOARD_MYGICA_X8558PRO, 967 }, { 968 .subvendor = 0x107d, 969 .subdevice = 0x6f22, 970 .card = CX23885_BOARD_LEADTEK_WINFAST_PXTV1200, 971 }, { 972 .subvendor = 0x5654, 973 .subdevice = 0x2390, 974 .card = CX23885_BOARD_GOTVIEW_X5_3D_HYBRID, 975 }, { 976 .subvendor = 0x1b55, 977 .subdevice = 0xe2e4, 978 .card = CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF, 979 }, { 980 .subvendor = 0x14f1, 981 .subdevice = 0x8502, 982 .card = CX23885_BOARD_MYGICA_X8507, 983 }, { 984 .subvendor = 0x153b, 985 .subdevice = 0x117e, 986 .card = CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL, 987 }, { 988 .subvendor = 0xd471, 989 .subdevice = 0x9022, 990 .card = CX23885_BOARD_TEVII_S471, 991 }, { 992 .subvendor = 0x8000, 993 .subdevice = 0x3034, 994 .card = CX23885_BOARD_PROF_8000, 995 }, { 996 .subvendor = 0x0070, 997 .subdevice = 0xc108, 998 .card = CX23885_BOARD_HAUPPAUGE_HVR4400, /* Hauppauge WinTV HVR-4400 (Model 121xxx, Hybrid DVB-T/S2, IR) */ 999 }, { 1000 .subvendor = 0x0070, 1001 .subdevice = 0xc138, 1002 .card = CX23885_BOARD_HAUPPAUGE_HVR4400, /* Hauppauge WinTV HVR-5500 (Model 121xxx, Hybrid DVB-T/C/S2, IR) */ 1003 }, { 1004 .subvendor = 0x0070, 1005 .subdevice = 0xc12a, 1006 .card = CX23885_BOARD_HAUPPAUGE_STARBURST, /* Hauppauge WinTV Starburst (Model 121x00, DVB-S2, IR) */ 1007 }, { 1008 .subvendor = 0x0070, 1009 .subdevice = 0xc1f8, 1010 .card = CX23885_BOARD_HAUPPAUGE_HVR4400, /* Hauppauge WinTV HVR-5500 (Model 121xxx, Hybrid DVB-T/C/S2, IR) */ 1011 }, { 1012 .subvendor = 0x1461, 1013 .subdevice = 0xd939, 1014 .card = CX23885_BOARD_AVERMEDIA_HC81R, 1015 }, { 1016 .subvendor = 0x0070, 1017 .subdevice = 0x7133, 1018 .card = CX23885_BOARD_HAUPPAUGE_IMPACTVCBE, 1019 }, { 1020 .subvendor = 0x18ac, 1021 .subdevice = 0xdb98, 1022 .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2, 1023 }, { 1024 .subvendor = 0x4254, 1025 .subdevice = 0x9580, 1026 .card = CX23885_BOARD_DVBSKY_T9580, 1027 }, { 1028 .subvendor = 0x4254, 1029 .subdevice = 0x980c, 1030 .card = CX23885_BOARD_DVBSKY_T980C, 1031 }, { 1032 .subvendor = 0x4254, 1033 .subdevice = 0x950c, 1034 .card = CX23885_BOARD_DVBSKY_S950C, 1035 }, { 1036 .subvendor = 0x13c2, 1037 .subdevice = 0x3013, 1038 .card = CX23885_BOARD_TT_CT2_4500_CI, 1039 }, { 1040 .subvendor = 0x4254, 1041 .subdevice = 0x0950, 1042 .card = CX23885_BOARD_DVBSKY_S950, 1043 }, { 1044 .subvendor = 0x4254, 1045 .subdevice = 0x0952, 1046 .card = CX23885_BOARD_DVBSKY_S952, 1047 }, { 1048 .subvendor = 0x4254, 1049 .subdevice = 0x0982, 1050 .card = CX23885_BOARD_DVBSKY_T982, 1051 }, { 1052 .subvendor = 0x0070, 1053 .subdevice = 0xf038, 1054 .card = CX23885_BOARD_HAUPPAUGE_HVR5525, 1055 }, { 1056 .subvendor = 0x1576, 1057 .subdevice = 0x0260, 1058 .card = CX23885_BOARD_VIEWCAST_260E, 1059 }, { 1060 .subvendor = 0x1576, 1061 .subdevice = 0x0460, 1062 .card = CX23885_BOARD_VIEWCAST_460E, 1063 }, 1064 }; 1065 const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids); 1066 1067 void cx23885_card_list(struct cx23885_dev *dev) 1068 { 1069 int i; 1070 1071 if (0 == dev->pci->subsystem_vendor && 1072 0 == dev->pci->subsystem_device) { 1073 printk(KERN_INFO 1074 "%s: Board has no valid PCIe Subsystem ID and can't\n" 1075 "%s: be autodetected. Pass card=<n> insmod option\n" 1076 "%s: to workaround that. Redirect complaints to the\n" 1077 "%s: vendor of the TV card. Best regards,\n" 1078 "%s: -- tux\n", 1079 dev->name, dev->name, dev->name, dev->name, dev->name); 1080 } else { 1081 printk(KERN_INFO 1082 "%s: Your board isn't known (yet) to the driver.\n" 1083 "%s: Try to pick one of the existing card configs via\n" 1084 "%s: card=<n> insmod option. Updating to the latest\n" 1085 "%s: version might help as well.\n", 1086 dev->name, dev->name, dev->name, dev->name); 1087 } 1088 printk(KERN_INFO "%s: Here is a list of valid choices for the card=<n> insmod option:\n", 1089 dev->name); 1090 for (i = 0; i < cx23885_bcount; i++) 1091 printk(KERN_INFO "%s: card=%d -> %s\n", 1092 dev->name, i, cx23885_boards[i].name); 1093 } 1094 1095 static void viewcast_eeprom(struct cx23885_dev *dev, u8 *eeprom_data) 1096 { 1097 u32 sn; 1098 1099 /* The serial number record begins with tag 0x59 */ 1100 if (*(eeprom_data + 0x00) != 0x59) { 1101 pr_info("%s() eeprom records are undefined, no serial number\n", 1102 __func__); 1103 return; 1104 } 1105 1106 sn = (*(eeprom_data + 0x06) << 24) | 1107 (*(eeprom_data + 0x05) << 16) | 1108 (*(eeprom_data + 0x04) << 8) | 1109 (*(eeprom_data + 0x03)); 1110 1111 pr_info("%s: card '%s' sn# MM%d\n", 1112 dev->name, 1113 cx23885_boards[dev->board].name, 1114 sn); 1115 } 1116 1117 static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data) 1118 { 1119 struct tveeprom tv; 1120 1121 tveeprom_hauppauge_analog(&dev->i2c_bus[0].i2c_client, &tv, 1122 eeprom_data); 1123 1124 /* Make sure we support the board model */ 1125 switch (tv.model) { 1126 case 22001: 1127 /* WinTV-HVR1270 (PCIe, Retail, half height) 1128 * ATSC/QAM and basic analog, IR Blast */ 1129 case 22009: 1130 /* WinTV-HVR1210 (PCIe, Retail, half height) 1131 * DVB-T and basic analog, IR Blast */ 1132 case 22011: 1133 /* WinTV-HVR1270 (PCIe, Retail, half height) 1134 * ATSC/QAM and basic analog, IR Recv */ 1135 case 22019: 1136 /* WinTV-HVR1210 (PCIe, Retail, half height) 1137 * DVB-T and basic analog, IR Recv */ 1138 case 22021: 1139 /* WinTV-HVR1275 (PCIe, Retail, half height) 1140 * ATSC/QAM and basic analog, IR Recv */ 1141 case 22029: 1142 /* WinTV-HVR1210 (PCIe, Retail, half height) 1143 * DVB-T and basic analog, IR Recv */ 1144 case 22101: 1145 /* WinTV-HVR1270 (PCIe, Retail, full height) 1146 * ATSC/QAM and basic analog, IR Blast */ 1147 case 22109: 1148 /* WinTV-HVR1210 (PCIe, Retail, full height) 1149 * DVB-T and basic analog, IR Blast */ 1150 case 22111: 1151 /* WinTV-HVR1270 (PCIe, Retail, full height) 1152 * ATSC/QAM and basic analog, IR Recv */ 1153 case 22119: 1154 /* WinTV-HVR1210 (PCIe, Retail, full height) 1155 * DVB-T and basic analog, IR Recv */ 1156 case 22121: 1157 /* WinTV-HVR1275 (PCIe, Retail, full height) 1158 * ATSC/QAM and basic analog, IR Recv */ 1159 case 22129: 1160 /* WinTV-HVR1210 (PCIe, Retail, full height) 1161 * DVB-T and basic analog, IR Recv */ 1162 case 71009: 1163 /* WinTV-HVR1200 (PCIe, Retail, full height) 1164 * DVB-T and basic analog */ 1165 case 71100: 1166 /* WinTV-ImpactVCB-e (PCIe, Retail, half height) 1167 * Basic analog */ 1168 case 71359: 1169 /* WinTV-HVR1200 (PCIe, OEM, half height) 1170 * DVB-T and basic analog */ 1171 case 71439: 1172 /* WinTV-HVR1200 (PCIe, OEM, half height) 1173 * DVB-T and basic analog */ 1174 case 71449: 1175 /* WinTV-HVR1200 (PCIe, OEM, full height) 1176 * DVB-T and basic analog */ 1177 case 71939: 1178 /* WinTV-HVR1200 (PCIe, OEM, half height) 1179 * DVB-T and basic analog */ 1180 case 71949: 1181 /* WinTV-HVR1200 (PCIe, OEM, full height) 1182 * DVB-T and basic analog */ 1183 case 71959: 1184 /* WinTV-HVR1200 (PCIe, OEM, full height) 1185 * DVB-T and basic analog */ 1186 case 71979: 1187 /* WinTV-HVR1200 (PCIe, OEM, half height) 1188 * DVB-T and basic analog */ 1189 case 71999: 1190 /* WinTV-HVR1200 (PCIe, OEM, full height) 1191 * DVB-T and basic analog */ 1192 case 76601: 1193 /* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual 1194 channel ATSC and MPEG2 HW Encoder */ 1195 case 77001: 1196 /* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC 1197 and Basic analog */ 1198 case 77011: 1199 /* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC 1200 and Basic analog */ 1201 case 77041: 1202 /* WinTV-HVR1500Q (Express Card, OEM, No IR, ATSC/QAM 1203 and Basic analog */ 1204 case 77051: 1205 /* WinTV-HVR1500Q (Express Card, Retail, No IR, ATSC/QAM 1206 and Basic analog */ 1207 case 78011: 1208 /* WinTV-HVR1800 (PCIe, Retail, 3.5mm in, IR, No FM, 1209 Dual channel ATSC and MPEG2 HW Encoder */ 1210 case 78501: 1211 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM, 1212 Dual channel ATSC and MPEG2 HW Encoder */ 1213 case 78521: 1214 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM, 1215 Dual channel ATSC and MPEG2 HW Encoder */ 1216 case 78531: 1217 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, No FM, 1218 Dual channel ATSC and MPEG2 HW Encoder */ 1219 case 78631: 1220 /* WinTV-HVR1800 (PCIe, OEM, No IR, No FM, 1221 Dual channel ATSC and MPEG2 HW Encoder */ 1222 case 79001: 1223 /* WinTV-HVR1250 (PCIe, Retail, IR, full height, 1224 ATSC and Basic analog */ 1225 case 79101: 1226 /* WinTV-HVR1250 (PCIe, Retail, IR, half height, 1227 ATSC and Basic analog */ 1228 case 79501: 1229 /* WinTV-HVR1250 (PCIe, No IR, half height, 1230 ATSC [at least] and Basic analog) */ 1231 case 79561: 1232 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height, 1233 ATSC and Basic analog */ 1234 case 79571: 1235 /* WinTV-HVR1250 (PCIe, OEM, No IR, full height, 1236 ATSC and Basic analog */ 1237 case 79671: 1238 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height, 1239 ATSC and Basic analog */ 1240 case 80019: 1241 /* WinTV-HVR1400 (Express Card, Retail, IR, 1242 * DVB-T and Basic analog */ 1243 case 81509: 1244 /* WinTV-HVR1700 (PCIe, OEM, No IR, half height) 1245 * DVB-T and MPEG2 HW Encoder */ 1246 case 81519: 1247 /* WinTV-HVR1700 (PCIe, OEM, No IR, full height) 1248 * DVB-T and MPEG2 HW Encoder */ 1249 break; 1250 case 85021: 1251 /* WinTV-HVR1850 (PCIe, Retail, 3.5mm in, IR, FM, 1252 Dual channel ATSC and MPEG2 HW Encoder */ 1253 break; 1254 case 85721: 1255 /* WinTV-HVR1290 (PCIe, OEM, RCA in, IR, 1256 Dual channel ATSC and Basic analog */ 1257 case 150329: 1258 /* WinTV-HVR5525 (PCIe, DVB-S/S2, DVB-T/T2/C) */ 1259 break; 1260 default: 1261 printk(KERN_WARNING "%s: warning: " 1262 "unknown hauppauge model #%d\n", 1263 dev->name, tv.model); 1264 break; 1265 } 1266 1267 printk(KERN_INFO "%s: hauppauge eeprom: model=%d\n", 1268 dev->name, tv.model); 1269 } 1270 1271 /* Some TBS cards require initing a chip using a bitbanged SPI attached 1272 to the cx23885 gpio's. If this chip doesn't get init'ed the demod 1273 doesn't respond to any command. */ 1274 static void tbs_card_init(struct cx23885_dev *dev) 1275 { 1276 int i; 1277 const u8 buf[] = { 1278 0xe0, 0x06, 0x66, 0x33, 0x65, 1279 0x01, 0x17, 0x06, 0xde}; 1280 1281 switch (dev->board) { 1282 case CX23885_BOARD_TBS_6980: 1283 case CX23885_BOARD_TBS_6981: 1284 cx_set(GP0_IO, 0x00070007); 1285 usleep_range(1000, 10000); 1286 cx_clear(GP0_IO, 2); 1287 usleep_range(1000, 10000); 1288 for (i = 0; i < 9 * 8; i++) { 1289 cx_clear(GP0_IO, 7); 1290 usleep_range(1000, 10000); 1291 cx_set(GP0_IO, 1292 ((buf[i >> 3] >> (7 - (i & 7))) & 1) | 4); 1293 usleep_range(1000, 10000); 1294 } 1295 cx_set(GP0_IO, 7); 1296 break; 1297 } 1298 } 1299 1300 int cx23885_tuner_callback(void *priv, int component, int command, int arg) 1301 { 1302 struct cx23885_tsport *port = priv; 1303 struct cx23885_dev *dev = port->dev; 1304 u32 bitmask = 0; 1305 1306 if ((command == XC2028_RESET_CLK) || (command == XC2028_I2C_FLUSH)) 1307 return 0; 1308 1309 if (command != 0) { 1310 printk(KERN_ERR "%s(): Unknown command 0x%x.\n", 1311 __func__, command); 1312 return -EINVAL; 1313 } 1314 1315 switch (dev->board) { 1316 case CX23885_BOARD_HAUPPAUGE_HVR1400: 1317 case CX23885_BOARD_HAUPPAUGE_HVR1500: 1318 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 1319 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: 1320 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200: 1321 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: 1322 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: 1323 case CX23885_BOARD_COMPRO_VIDEOMATE_E800: 1324 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200: 1325 /* Tuner Reset Command */ 1326 bitmask = 0x04; 1327 break; 1328 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP: 1329 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: 1330 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2: 1331 /* Two identical tuners on two different i2c buses, 1332 * we need to reset the correct gpio. */ 1333 if (port->nr == 1) 1334 bitmask = 0x01; 1335 else if (port->nr == 2) 1336 bitmask = 0x04; 1337 break; 1338 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID: 1339 /* Tuner Reset Command */ 1340 bitmask = 0x02; 1341 break; 1342 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: 1343 altera_ci_tuner_reset(dev, port->nr); 1344 break; 1345 case CX23885_BOARD_AVERMEDIA_HC81R: 1346 /* XC3028L Reset Command */ 1347 bitmask = 1 << 2; 1348 break; 1349 } 1350 1351 if (bitmask) { 1352 /* Drive the tuner into reset and back out */ 1353 cx_clear(GP0_IO, bitmask); 1354 mdelay(200); 1355 cx_set(GP0_IO, bitmask); 1356 } 1357 1358 return 0; 1359 } 1360 1361 void cx23885_gpio_setup(struct cx23885_dev *dev) 1362 { 1363 switch (dev->board) { 1364 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1365 /* GPIO-0 cx24227 demodulator reset */ 1366 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */ 1367 break; 1368 case CX23885_BOARD_HAUPPAUGE_HVR1500: 1369 /* GPIO-0 cx24227 demodulator */ 1370 /* GPIO-2 xc3028 tuner */ 1371 1372 /* Put the parts into reset */ 1373 cx_set(GP0_IO, 0x00050000); 1374 cx_clear(GP0_IO, 0x00000005); 1375 msleep(5); 1376 1377 /* Bring the parts out of reset */ 1378 cx_set(GP0_IO, 0x00050005); 1379 break; 1380 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 1381 /* GPIO-0 cx24227 demodulator reset */ 1382 /* GPIO-2 xc5000 tuner reset */ 1383 cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */ 1384 break; 1385 case CX23885_BOARD_HAUPPAUGE_HVR1800: 1386 /* GPIO-0 656_CLK */ 1387 /* GPIO-1 656_D0 */ 1388 /* GPIO-2 8295A Reset */ 1389 /* GPIO-3-10 cx23417 data0-7 */ 1390 /* GPIO-11-14 cx23417 addr0-3 */ 1391 /* GPIO-15-18 cx23417 READY, CS, RD, WR */ 1392 /* GPIO-19 IR_RX */ 1393 1394 /* CX23417 GPIO's */ 1395 /* EIO15 Zilog Reset */ 1396 /* EIO14 S5H1409/CX24227 Reset */ 1397 mc417_gpio_enable(dev, GPIO_15 | GPIO_14, 1); 1398 1399 /* Put the demod into reset and protect the eeprom */ 1400 mc417_gpio_clear(dev, GPIO_15 | GPIO_14); 1401 mdelay(100); 1402 1403 /* Bring the demod and blaster out of reset */ 1404 mc417_gpio_set(dev, GPIO_15 | GPIO_14); 1405 mdelay(100); 1406 1407 /* Force the TDA8295A into reset and back */ 1408 cx23885_gpio_enable(dev, GPIO_2, 1); 1409 cx23885_gpio_set(dev, GPIO_2); 1410 mdelay(20); 1411 cx23885_gpio_clear(dev, GPIO_2); 1412 mdelay(20); 1413 cx23885_gpio_set(dev, GPIO_2); 1414 mdelay(20); 1415 break; 1416 case CX23885_BOARD_HAUPPAUGE_HVR1200: 1417 /* GPIO-0 tda10048 demodulator reset */ 1418 /* GPIO-2 tda18271 tuner reset */ 1419 1420 /* Put the parts into reset and back */ 1421 cx_set(GP0_IO, 0x00050000); 1422 mdelay(20); 1423 cx_clear(GP0_IO, 0x00000005); 1424 mdelay(20); 1425 cx_set(GP0_IO, 0x00050005); 1426 break; 1427 case CX23885_BOARD_HAUPPAUGE_HVR1700: 1428 /* GPIO-0 TDA10048 demodulator reset */ 1429 /* GPIO-2 TDA8295A Reset */ 1430 /* GPIO-3-10 cx23417 data0-7 */ 1431 /* GPIO-11-14 cx23417 addr0-3 */ 1432 /* GPIO-15-18 cx23417 READY, CS, RD, WR */ 1433 1434 /* The following GPIO's are on the interna AVCore (cx25840) */ 1435 /* GPIO-19 IR_RX */ 1436 /* GPIO-20 IR_TX 416/DVBT Select */ 1437 /* GPIO-21 IIS DAT */ 1438 /* GPIO-22 IIS WCLK */ 1439 /* GPIO-23 IIS BCLK */ 1440 1441 /* Put the parts into reset and back */ 1442 cx_set(GP0_IO, 0x00050000); 1443 mdelay(20); 1444 cx_clear(GP0_IO, 0x00000005); 1445 mdelay(20); 1446 cx_set(GP0_IO, 0x00050005); 1447 break; 1448 case CX23885_BOARD_HAUPPAUGE_HVR1400: 1449 /* GPIO-0 Dibcom7000p demodulator reset */ 1450 /* GPIO-2 xc3028L tuner reset */ 1451 /* GPIO-13 LED */ 1452 1453 /* Put the parts into reset and back */ 1454 cx_set(GP0_IO, 0x00050000); 1455 mdelay(20); 1456 cx_clear(GP0_IO, 0x00000005); 1457 mdelay(20); 1458 cx_set(GP0_IO, 0x00050005); 1459 break; 1460 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP: 1461 /* GPIO-0 xc5000 tuner reset i2c bus 0 */ 1462 /* GPIO-1 s5h1409 demod reset i2c bus 0 */ 1463 /* GPIO-2 xc5000 tuner reset i2c bus 1 */ 1464 /* GPIO-3 s5h1409 demod reset i2c bus 0 */ 1465 1466 /* Put the parts into reset and back */ 1467 cx_set(GP0_IO, 0x000f0000); 1468 mdelay(20); 1469 cx_clear(GP0_IO, 0x0000000f); 1470 mdelay(20); 1471 cx_set(GP0_IO, 0x000f000f); 1472 break; 1473 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: 1474 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2: 1475 /* GPIO-0 portb xc3028 reset */ 1476 /* GPIO-1 portb zl10353 reset */ 1477 /* GPIO-2 portc xc3028 reset */ 1478 /* GPIO-3 portc zl10353 reset */ 1479 1480 /* Put the parts into reset and back */ 1481 cx_set(GP0_IO, 0x000f0000); 1482 mdelay(20); 1483 cx_clear(GP0_IO, 0x0000000f); 1484 mdelay(20); 1485 cx_set(GP0_IO, 0x000f000f); 1486 break; 1487 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: 1488 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200: 1489 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: 1490 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: 1491 case CX23885_BOARD_COMPRO_VIDEOMATE_E800: 1492 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200: 1493 /* GPIO-2 xc3028 tuner reset */ 1494 1495 /* The following GPIO's are on the internal AVCore (cx25840) */ 1496 /* GPIO-? zl10353 demod reset */ 1497 1498 /* Put the parts into reset and back */ 1499 cx_set(GP0_IO, 0x00040000); 1500 mdelay(20); 1501 cx_clear(GP0_IO, 0x00000004); 1502 mdelay(20); 1503 cx_set(GP0_IO, 0x00040004); 1504 break; 1505 case CX23885_BOARD_TBS_6920: 1506 case CX23885_BOARD_TBS_6980: 1507 case CX23885_BOARD_TBS_6981: 1508 case CX23885_BOARD_PROF_8000: 1509 cx_write(MC417_CTL, 0x00000036); 1510 cx_write(MC417_OEN, 0x00001000); 1511 cx_set(MC417_RWD, 0x00000002); 1512 mdelay(200); 1513 cx_clear(MC417_RWD, 0x00000800); 1514 mdelay(200); 1515 cx_set(MC417_RWD, 0x00000800); 1516 mdelay(200); 1517 break; 1518 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 1519 /* GPIO-0 INTA from CiMax1 1520 GPIO-1 INTB from CiMax2 1521 GPIO-2 reset chips 1522 GPIO-3 to GPIO-10 data/addr for CA 1523 GPIO-11 ~CS0 to CiMax1 1524 GPIO-12 ~CS1 to CiMax2 1525 GPIO-13 ADL0 load LSB addr 1526 GPIO-14 ADL1 load MSB addr 1527 GPIO-15 ~RDY from CiMax 1528 GPIO-17 ~RD to CiMax 1529 GPIO-18 ~WR to CiMax 1530 */ 1531 cx_set(GP0_IO, 0x00040000); /* GPIO as out */ 1532 /* GPIO1 and GPIO2 as INTA and INTB from CiMaxes, reset low */ 1533 cx_clear(GP0_IO, 0x00030004); 1534 mdelay(100);/* reset delay */ 1535 cx_set(GP0_IO, 0x00040004); /* GPIO as out, reset high */ 1536 cx_write(MC417_CTL, 0x00000037);/* enable GPIO3-18 pins */ 1537 /* GPIO-15 IN as ~ACK, rest as OUT */ 1538 cx_write(MC417_OEN, 0x00001000); 1539 /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */ 1540 cx_write(MC417_RWD, 0x0000c300); 1541 /* enable irq */ 1542 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/ 1543 break; 1544 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1545 case CX23885_BOARD_HAUPPAUGE_HVR1275: 1546 case CX23885_BOARD_HAUPPAUGE_HVR1255: 1547 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 1548 case CX23885_BOARD_HAUPPAUGE_HVR1210: 1549 /* GPIO-5 RF Control: 0 = RF1 Terrestrial, 1 = RF2 Cable */ 1550 /* GPIO-6 I2C Gate which can isolate the demod from the bus */ 1551 /* GPIO-9 Demod reset */ 1552 1553 /* Put the parts into reset and back */ 1554 cx23885_gpio_enable(dev, GPIO_9 | GPIO_6 | GPIO_5, 1); 1555 cx23885_gpio_set(dev, GPIO_9 | GPIO_6 | GPIO_5); 1556 cx23885_gpio_clear(dev, GPIO_9); 1557 mdelay(20); 1558 cx23885_gpio_set(dev, GPIO_9); 1559 break; 1560 case CX23885_BOARD_MYGICA_X8506: 1561 case CX23885_BOARD_MAGICPRO_PROHDTVE2: 1562 case CX23885_BOARD_MYGICA_X8507: 1563 /* GPIO-0 (0)Analog / (1)Digital TV */ 1564 /* GPIO-1 reset XC5000 */ 1565 /* GPIO-2 demod reset */ 1566 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1 | GPIO_2, 1); 1567 cx23885_gpio_clear(dev, GPIO_1 | GPIO_2); 1568 mdelay(100); 1569 cx23885_gpio_set(dev, GPIO_0 | GPIO_1 | GPIO_2); 1570 mdelay(100); 1571 break; 1572 case CX23885_BOARD_MYGICA_X8558PRO: 1573 /* GPIO-0 reset first ATBM8830 */ 1574 /* GPIO-1 reset second ATBM8830 */ 1575 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1, 1); 1576 cx23885_gpio_clear(dev, GPIO_0 | GPIO_1); 1577 mdelay(100); 1578 cx23885_gpio_set(dev, GPIO_0 | GPIO_1); 1579 mdelay(100); 1580 break; 1581 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1582 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1583 /* GPIO-0 656_CLK */ 1584 /* GPIO-1 656_D0 */ 1585 /* GPIO-2 Wake# */ 1586 /* GPIO-3-10 cx23417 data0-7 */ 1587 /* GPIO-11-14 cx23417 addr0-3 */ 1588 /* GPIO-15-18 cx23417 READY, CS, RD, WR */ 1589 /* GPIO-19 IR_RX */ 1590 /* GPIO-20 C_IR_TX */ 1591 /* GPIO-21 I2S DAT */ 1592 /* GPIO-22 I2S WCLK */ 1593 /* GPIO-23 I2S BCLK */ 1594 /* ALT GPIO: EXP GPIO LATCH */ 1595 1596 /* CX23417 GPIO's */ 1597 /* GPIO-14 S5H1411/CX24228 Reset */ 1598 /* GPIO-13 EEPROM write protect */ 1599 mc417_gpio_enable(dev, GPIO_14 | GPIO_13, 1); 1600 1601 /* Put the demod into reset and protect the eeprom */ 1602 mc417_gpio_clear(dev, GPIO_14 | GPIO_13); 1603 mdelay(100); 1604 1605 /* Bring the demod out of reset */ 1606 mc417_gpio_set(dev, GPIO_14); 1607 mdelay(100); 1608 1609 /* CX24228 GPIO */ 1610 /* Connected to IF / Mux */ 1611 break; 1612 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID: 1613 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */ 1614 break; 1615 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: 1616 /* GPIO-0 ~INT in 1617 GPIO-1 TMS out 1618 GPIO-2 ~reset chips out 1619 GPIO-3 to GPIO-10 data/addr for CA in/out 1620 GPIO-11 ~CS out 1621 GPIO-12 ADDR out 1622 GPIO-13 ~WR out 1623 GPIO-14 ~RD out 1624 GPIO-15 ~RDY in 1625 GPIO-16 TCK out 1626 GPIO-17 TDO in 1627 GPIO-18 TDI out 1628 */ 1629 cx_set(GP0_IO, 0x00060000); /* GPIO-1,2 as out */ 1630 /* GPIO-0 as INT, reset & TMS low */ 1631 cx_clear(GP0_IO, 0x00010006); 1632 mdelay(100);/* reset delay */ 1633 cx_set(GP0_IO, 0x00000004); /* reset high */ 1634 cx_write(MC417_CTL, 0x00000037);/* enable GPIO-3..18 pins */ 1635 /* GPIO-17 is TDO in, GPIO-15 is ~RDY in, rest is out */ 1636 cx_write(MC417_OEN, 0x00005000); 1637 /* ~RD, ~WR high; ADDR low; ~CS high */ 1638 cx_write(MC417_RWD, 0x00000d00); 1639 /* enable irq */ 1640 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/ 1641 break; 1642 case CX23885_BOARD_HAUPPAUGE_HVR4400: 1643 case CX23885_BOARD_HAUPPAUGE_STARBURST: 1644 /* GPIO-8 tda10071 demod reset */ 1645 /* GPIO-9 si2165 demod reset (only HVR4400/HVR5500)*/ 1646 1647 /* Put the parts into reset and back */ 1648 cx23885_gpio_enable(dev, GPIO_8 | GPIO_9, 1); 1649 1650 cx23885_gpio_clear(dev, GPIO_8 | GPIO_9); 1651 mdelay(100); 1652 cx23885_gpio_set(dev, GPIO_8 | GPIO_9); 1653 mdelay(100); 1654 1655 break; 1656 case CX23885_BOARD_AVERMEDIA_HC81R: 1657 cx_clear(MC417_CTL, 1); 1658 /* GPIO-0,1,2 setup direction as output */ 1659 cx_set(GP0_IO, 0x00070000); 1660 mdelay(10); 1661 /* AF9013 demod reset */ 1662 cx_set(GP0_IO, 0x00010001); 1663 mdelay(10); 1664 cx_clear(GP0_IO, 0x00010001); 1665 mdelay(10); 1666 cx_set(GP0_IO, 0x00010001); 1667 mdelay(10); 1668 /* demod tune? */ 1669 cx_clear(GP0_IO, 0x00030003); 1670 mdelay(10); 1671 cx_set(GP0_IO, 0x00020002); 1672 mdelay(10); 1673 cx_set(GP0_IO, 0x00010001); 1674 mdelay(10); 1675 cx_clear(GP0_IO, 0x00020002); 1676 /* XC3028L tuner reset */ 1677 cx_set(GP0_IO, 0x00040004); 1678 cx_clear(GP0_IO, 0x00040004); 1679 cx_set(GP0_IO, 0x00040004); 1680 mdelay(60); 1681 break; 1682 case CX23885_BOARD_DVBSKY_T9580: 1683 case CX23885_BOARD_DVBSKY_S952: 1684 case CX23885_BOARD_DVBSKY_T982: 1685 /* enable GPIO3-18 pins */ 1686 cx_write(MC417_CTL, 0x00000037); 1687 cx23885_gpio_enable(dev, GPIO_2 | GPIO_11, 1); 1688 cx23885_gpio_clear(dev, GPIO_2 | GPIO_11); 1689 mdelay(100); 1690 cx23885_gpio_set(dev, GPIO_2 | GPIO_11); 1691 break; 1692 case CX23885_BOARD_DVBSKY_T980C: 1693 case CX23885_BOARD_DVBSKY_S950C: 1694 case CX23885_BOARD_TT_CT2_4500_CI: 1695 /* 1696 * GPIO-0 INTA from CiMax, input 1697 * GPIO-1 reset CiMax, output, high active 1698 * GPIO-2 reset demod, output, low active 1699 * GPIO-3 to GPIO-10 data/addr for CAM 1700 * GPIO-11 ~CS0 to CiMax1 1701 * GPIO-12 ~CS1 to CiMax2 1702 * GPIO-13 ADL0 load LSB addr 1703 * GPIO-14 ADL1 load MSB addr 1704 * GPIO-15 ~RDY from CiMax 1705 * GPIO-17 ~RD to CiMax 1706 * GPIO-18 ~WR to CiMax 1707 */ 1708 1709 cx_set(GP0_IO, 0x00060002); /* GPIO 1/2 as output */ 1710 cx_clear(GP0_IO, 0x00010004); /* GPIO 0 as input */ 1711 mdelay(100); /* reset delay */ 1712 cx_set(GP0_IO, 0x00060004); /* GPIO as out, reset high */ 1713 cx_clear(GP0_IO, 0x00010002); 1714 cx_write(MC417_CTL, 0x00000037); /* enable GPIO3-18 pins */ 1715 1716 /* GPIO-15 IN as ~ACK, rest as OUT */ 1717 cx_write(MC417_OEN, 0x00001000); 1718 1719 /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */ 1720 cx_write(MC417_RWD, 0x0000c300); 1721 1722 /* enable irq */ 1723 cx_write(GPIO_ISM, 0x00000000); /* INTERRUPTS active low */ 1724 break; 1725 case CX23885_BOARD_DVBSKY_S950: 1726 cx23885_gpio_enable(dev, GPIO_2, 1); 1727 cx23885_gpio_clear(dev, GPIO_2); 1728 msleep(100); 1729 cx23885_gpio_set(dev, GPIO_2); 1730 break; 1731 case CX23885_BOARD_HAUPPAUGE_HVR5525: 1732 /* 1733 * GPIO-00 IR_WIDE 1734 * GPIO-02 wake# 1735 * GPIO-03 VAUX Pres. 1736 * GPIO-07 PROG# 1737 * GPIO-08 SAT_RESN 1738 * GPIO-09 TER_RESN 1739 * GPIO-10 B2_SENSE 1740 * GPIO-11 B1_SENSE 1741 * GPIO-15 IR_LED_STATUS 1742 * GPIO-19 IR_NARROW 1743 * GPIO-20 Blauster1 1744 * ALTGPIO VAUX_SWITCH 1745 * AUX_PLL_CLK : Blaster2 1746 */ 1747 /* Put the parts into reset and back */ 1748 cx23885_gpio_enable(dev, GPIO_8 | GPIO_9, 1); 1749 cx23885_gpio_clear(dev, GPIO_8 | GPIO_9); 1750 msleep(100); 1751 cx23885_gpio_set(dev, GPIO_8 | GPIO_9); 1752 msleep(100); 1753 break; 1754 case CX23885_BOARD_VIEWCAST_260E: 1755 case CX23885_BOARD_VIEWCAST_460E: 1756 /* For documentation purposes, it's worth noting that this 1757 * card does not have any GPIO's connected to subcomponents. 1758 */ 1759 break; 1760 } 1761 } 1762 1763 int cx23885_ir_init(struct cx23885_dev *dev) 1764 { 1765 static struct v4l2_subdev_io_pin_config ir_rxtx_pin_cfg[] = { 1766 { 1767 .flags = V4L2_SUBDEV_IO_PIN_INPUT, 1768 .pin = CX23885_PIN_IR_RX_GPIO19, 1769 .function = CX23885_PAD_IR_RX, 1770 .value = 0, 1771 .strength = CX25840_PIN_DRIVE_MEDIUM, 1772 }, { 1773 .flags = V4L2_SUBDEV_IO_PIN_OUTPUT, 1774 .pin = CX23885_PIN_IR_TX_GPIO20, 1775 .function = CX23885_PAD_IR_TX, 1776 .value = 0, 1777 .strength = CX25840_PIN_DRIVE_MEDIUM, 1778 } 1779 }; 1780 const size_t ir_rxtx_pin_cfg_count = ARRAY_SIZE(ir_rxtx_pin_cfg); 1781 1782 static struct v4l2_subdev_io_pin_config ir_rx_pin_cfg[] = { 1783 { 1784 .flags = V4L2_SUBDEV_IO_PIN_INPUT, 1785 .pin = CX23885_PIN_IR_RX_GPIO19, 1786 .function = CX23885_PAD_IR_RX, 1787 .value = 0, 1788 .strength = CX25840_PIN_DRIVE_MEDIUM, 1789 } 1790 }; 1791 const size_t ir_rx_pin_cfg_count = ARRAY_SIZE(ir_rx_pin_cfg); 1792 1793 struct v4l2_subdev_ir_parameters params; 1794 int ret = 0; 1795 switch (dev->board) { 1796 case CX23885_BOARD_HAUPPAUGE_HVR1500: 1797 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 1798 case CX23885_BOARD_HAUPPAUGE_HVR1800: 1799 case CX23885_BOARD_HAUPPAUGE_HVR1200: 1800 case CX23885_BOARD_HAUPPAUGE_HVR1400: 1801 case CX23885_BOARD_HAUPPAUGE_HVR1275: 1802 case CX23885_BOARD_HAUPPAUGE_HVR1255: 1803 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 1804 case CX23885_BOARD_HAUPPAUGE_HVR1210: 1805 /* FIXME: Implement me */ 1806 break; 1807 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1808 ret = cx23888_ir_probe(dev); 1809 if (ret) 1810 break; 1811 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR); 1812 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config, 1813 ir_rx_pin_cfg_count, ir_rx_pin_cfg); 1814 break; 1815 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1816 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1817 ret = cx23888_ir_probe(dev); 1818 if (ret) 1819 break; 1820 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR); 1821 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config, 1822 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg); 1823 /* 1824 * For these boards we need to invert the Tx output via the 1825 * IR controller to have the LED off while idle 1826 */ 1827 v4l2_subdev_call(dev->sd_ir, ir, tx_g_parameters, ¶ms); 1828 params.enable = false; 1829 params.shutdown = false; 1830 params.invert_level = true; 1831 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, ¶ms); 1832 params.shutdown = true; 1833 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, ¶ms); 1834 break; 1835 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 1836 case CX23885_BOARD_TEVII_S470: 1837 case CX23885_BOARD_MYGICA_X8507: 1838 case CX23885_BOARD_TBS_6980: 1839 case CX23885_BOARD_TBS_6981: 1840 case CX23885_BOARD_DVBSKY_T9580: 1841 case CX23885_BOARD_DVBSKY_T980C: 1842 case CX23885_BOARD_DVBSKY_S950C: 1843 case CX23885_BOARD_TT_CT2_4500_CI: 1844 case CX23885_BOARD_DVBSKY_S950: 1845 case CX23885_BOARD_DVBSKY_S952: 1846 case CX23885_BOARD_DVBSKY_T982: 1847 if (!enable_885_ir) 1848 break; 1849 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE); 1850 if (dev->sd_ir == NULL) { 1851 ret = -ENODEV; 1852 break; 1853 } 1854 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config, 1855 ir_rx_pin_cfg_count, ir_rx_pin_cfg); 1856 break; 1857 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1858 if (!enable_885_ir) 1859 break; 1860 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE); 1861 if (dev->sd_ir == NULL) { 1862 ret = -ENODEV; 1863 break; 1864 } 1865 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config, 1866 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg); 1867 break; 1868 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: 1869 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2: 1870 request_module("ir-kbd-i2c"); 1871 break; 1872 } 1873 1874 return ret; 1875 } 1876 1877 void cx23885_ir_fini(struct cx23885_dev *dev) 1878 { 1879 switch (dev->board) { 1880 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1881 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1882 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1883 cx23885_irq_remove(dev, PCI_MSK_IR); 1884 cx23888_ir_remove(dev); 1885 dev->sd_ir = NULL; 1886 break; 1887 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 1888 case CX23885_BOARD_TEVII_S470: 1889 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1890 case CX23885_BOARD_MYGICA_X8507: 1891 case CX23885_BOARD_TBS_6980: 1892 case CX23885_BOARD_TBS_6981: 1893 case CX23885_BOARD_DVBSKY_T9580: 1894 case CX23885_BOARD_DVBSKY_T980C: 1895 case CX23885_BOARD_DVBSKY_S950C: 1896 case CX23885_BOARD_TT_CT2_4500_CI: 1897 case CX23885_BOARD_DVBSKY_S950: 1898 case CX23885_BOARD_DVBSKY_S952: 1899 case CX23885_BOARD_DVBSKY_T982: 1900 cx23885_irq_remove(dev, PCI_MSK_AV_CORE); 1901 /* sd_ir is a duplicate pointer to the AV Core, just clear it */ 1902 dev->sd_ir = NULL; 1903 break; 1904 } 1905 } 1906 1907 static int netup_jtag_io(void *device, int tms, int tdi, int read_tdo) 1908 { 1909 int data; 1910 int tdo = 0; 1911 struct cx23885_dev *dev = (struct cx23885_dev *)device; 1912 /*TMS*/ 1913 data = ((cx_read(GP0_IO)) & (~0x00000002)); 1914 data |= (tms ? 0x00020002 : 0x00020000); 1915 cx_write(GP0_IO, data); 1916 1917 /*TDI*/ 1918 data = ((cx_read(MC417_RWD)) & (~0x0000a000)); 1919 data |= (tdi ? 0x00008000 : 0); 1920 cx_write(MC417_RWD, data); 1921 if (read_tdo) 1922 tdo = (data & 0x00004000) ? 1 : 0; /*TDO*/ 1923 1924 cx_write(MC417_RWD, data | 0x00002000); 1925 udelay(1); 1926 /*TCK*/ 1927 cx_write(MC417_RWD, data); 1928 1929 return tdo; 1930 } 1931 1932 void cx23885_ir_pci_int_enable(struct cx23885_dev *dev) 1933 { 1934 switch (dev->board) { 1935 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1936 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1937 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1938 if (dev->sd_ir) 1939 cx23885_irq_add_enable(dev, PCI_MSK_IR); 1940 break; 1941 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 1942 case CX23885_BOARD_TEVII_S470: 1943 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1944 case CX23885_BOARD_MYGICA_X8507: 1945 case CX23885_BOARD_TBS_6980: 1946 case CX23885_BOARD_TBS_6981: 1947 case CX23885_BOARD_DVBSKY_T9580: 1948 case CX23885_BOARD_DVBSKY_T980C: 1949 case CX23885_BOARD_DVBSKY_S950C: 1950 case CX23885_BOARD_TT_CT2_4500_CI: 1951 case CX23885_BOARD_DVBSKY_S950: 1952 case CX23885_BOARD_DVBSKY_S952: 1953 case CX23885_BOARD_DVBSKY_T982: 1954 if (dev->sd_ir) 1955 cx23885_irq_add_enable(dev, PCI_MSK_AV_CORE); 1956 break; 1957 } 1958 } 1959 1960 void cx23885_card_setup(struct cx23885_dev *dev) 1961 { 1962 struct cx23885_tsport *ts1 = &dev->ts1; 1963 struct cx23885_tsport *ts2 = &dev->ts2; 1964 1965 static u8 eeprom[256]; 1966 1967 if (dev->i2c_bus[0].i2c_rc == 0) { 1968 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1; 1969 tveeprom_read(&dev->i2c_bus[0].i2c_client, 1970 eeprom, sizeof(eeprom)); 1971 } 1972 1973 switch (dev->board) { 1974 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1975 if (dev->i2c_bus[0].i2c_rc == 0) { 1976 if (eeprom[0x80] != 0x84) 1977 hauppauge_eeprom(dev, eeprom+0xc0); 1978 else 1979 hauppauge_eeprom(dev, eeprom+0x80); 1980 } 1981 break; 1982 case CX23885_BOARD_HAUPPAUGE_HVR1500: 1983 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 1984 case CX23885_BOARD_HAUPPAUGE_HVR1400: 1985 if (dev->i2c_bus[0].i2c_rc == 0) 1986 hauppauge_eeprom(dev, eeprom+0x80); 1987 break; 1988 case CX23885_BOARD_HAUPPAUGE_HVR1800: 1989 case CX23885_BOARD_HAUPPAUGE_HVR1800lp: 1990 case CX23885_BOARD_HAUPPAUGE_HVR1200: 1991 case CX23885_BOARD_HAUPPAUGE_HVR1700: 1992 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1993 case CX23885_BOARD_HAUPPAUGE_HVR1275: 1994 case CX23885_BOARD_HAUPPAUGE_HVR1255: 1995 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 1996 case CX23885_BOARD_HAUPPAUGE_HVR1210: 1997 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1998 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1999 case CX23885_BOARD_HAUPPAUGE_HVR4400: 2000 case CX23885_BOARD_HAUPPAUGE_STARBURST: 2001 case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE: 2002 case CX23885_BOARD_HAUPPAUGE_HVR5525: 2003 if (dev->i2c_bus[0].i2c_rc == 0) 2004 hauppauge_eeprom(dev, eeprom+0xc0); 2005 break; 2006 case CX23885_BOARD_VIEWCAST_260E: 2007 case CX23885_BOARD_VIEWCAST_460E: 2008 dev->i2c_bus[1].i2c_client.addr = 0xa0 >> 1; 2009 tveeprom_read(&dev->i2c_bus[1].i2c_client, 2010 eeprom, sizeof(eeprom)); 2011 if (dev->i2c_bus[0].i2c_rc == 0) 2012 viewcast_eeprom(dev, eeprom); 2013 break; 2014 } 2015 2016 switch (dev->board) { 2017 case CX23885_BOARD_AVERMEDIA_HC81R: 2018 /* Defaults for VID B */ 2019 ts1->gen_ctrl_val = 0x4; /* Parallel */ 2020 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2021 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2022 /* Defaults for VID C */ 2023 /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */ 2024 ts2->gen_ctrl_val = 0x10e; 2025 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2026 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2027 break; 2028 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP: 2029 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: 2030 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2: 2031 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2032 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2033 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2034 /* break omitted intentionally */ 2035 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP: 2036 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2037 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2038 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2039 break; 2040 case CX23885_BOARD_HAUPPAUGE_HVR1850: 2041 case CX23885_BOARD_HAUPPAUGE_HVR1800: 2042 /* Defaults for VID B - Analog encoder */ 2043 /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */ 2044 ts1->gen_ctrl_val = 0x10e; 2045 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2046 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2047 2048 /* APB_TSVALERR_POL (active low)*/ 2049 ts1->vld_misc_val = 0x2000; 2050 ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc); 2051 cx_write(0x130184, 0xc); 2052 2053 /* Defaults for VID C */ 2054 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2055 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2056 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2057 break; 2058 case CX23885_BOARD_TBS_6920: 2059 ts1->gen_ctrl_val = 0x4; /* Parallel */ 2060 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2061 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2062 break; 2063 case CX23885_BOARD_TEVII_S470: 2064 case CX23885_BOARD_TEVII_S471: 2065 case CX23885_BOARD_DVBWORLD_2005: 2066 case CX23885_BOARD_PROF_8000: 2067 case CX23885_BOARD_DVBSKY_T980C: 2068 case CX23885_BOARD_DVBSKY_S950C: 2069 case CX23885_BOARD_TT_CT2_4500_CI: 2070 case CX23885_BOARD_DVBSKY_S950: 2071 ts1->gen_ctrl_val = 0x5; /* Parallel */ 2072 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2073 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2074 break; 2075 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 2076 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: 2077 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 2078 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2079 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2080 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2081 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2082 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2083 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2084 break; 2085 case CX23885_BOARD_TBS_6980: 2086 case CX23885_BOARD_TBS_6981: 2087 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2088 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2089 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2090 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2091 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2092 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2093 tbs_card_init(dev); 2094 break; 2095 case CX23885_BOARD_MYGICA_X8506: 2096 case CX23885_BOARD_MAGICPRO_PROHDTVE2: 2097 case CX23885_BOARD_MYGICA_X8507: 2098 ts1->gen_ctrl_val = 0x5; /* Parallel */ 2099 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2100 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2101 break; 2102 case CX23885_BOARD_MYGICA_X8558PRO: 2103 ts1->gen_ctrl_val = 0x5; /* Parallel */ 2104 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2105 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2106 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2107 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2108 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2109 break; 2110 case CX23885_BOARD_HAUPPAUGE_HVR4400: 2111 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2112 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2113 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2114 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2115 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2116 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2117 break; 2118 case CX23885_BOARD_HAUPPAUGE_STARBURST: 2119 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2120 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2121 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2122 break; 2123 case CX23885_BOARD_DVBSKY_T9580: 2124 case CX23885_BOARD_DVBSKY_T982: 2125 ts1->gen_ctrl_val = 0x5; /* Parallel */ 2126 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2127 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2128 ts2->gen_ctrl_val = 0x8; /* Serial bus */ 2129 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2130 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2131 break; 2132 case CX23885_BOARD_DVBSKY_S952: 2133 ts1->gen_ctrl_val = 0x5; /* Parallel */ 2134 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2135 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2136 ts2->gen_ctrl_val = 0xe; /* Serial bus */ 2137 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2138 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2139 break; 2140 case CX23885_BOARD_HAUPPAUGE_HVR5525: 2141 ts1->gen_ctrl_val = 0x5; /* Parallel */ 2142 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2143 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2144 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2145 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2146 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2147 break; 2148 case CX23885_BOARD_HAUPPAUGE_HVR1250: 2149 case CX23885_BOARD_HAUPPAUGE_HVR1500: 2150 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 2151 case CX23885_BOARD_HAUPPAUGE_HVR1800lp: 2152 case CX23885_BOARD_HAUPPAUGE_HVR1200: 2153 case CX23885_BOARD_HAUPPAUGE_HVR1700: 2154 case CX23885_BOARD_HAUPPAUGE_HVR1400: 2155 case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE: 2156 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: 2157 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200: 2158 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: 2159 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: 2160 case CX23885_BOARD_HAUPPAUGE_HVR1270: 2161 case CX23885_BOARD_HAUPPAUGE_HVR1275: 2162 case CX23885_BOARD_HAUPPAUGE_HVR1255: 2163 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 2164 case CX23885_BOARD_HAUPPAUGE_HVR1210: 2165 case CX23885_BOARD_COMPRO_VIDEOMATE_E800: 2166 case CX23885_BOARD_HAUPPAUGE_HVR1290: 2167 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID: 2168 default: 2169 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 2170 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 2171 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 2172 } 2173 2174 /* Certain boards support analog, or require the avcore to be 2175 * loaded, ensure this happens. 2176 */ 2177 switch (dev->board) { 2178 case CX23885_BOARD_TEVII_S470: 2179 /* Currently only enabled for the integrated IR controller */ 2180 if (!enable_885_ir) 2181 break; 2182 case CX23885_BOARD_HAUPPAUGE_HVR1250: 2183 case CX23885_BOARD_HAUPPAUGE_HVR1800: 2184 case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE: 2185 case CX23885_BOARD_HAUPPAUGE_HVR1800lp: 2186 case CX23885_BOARD_HAUPPAUGE_HVR1700: 2187 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: 2188 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200: 2189 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: 2190 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: 2191 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 2192 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: 2193 case CX23885_BOARD_COMPRO_VIDEOMATE_E800: 2194 case CX23885_BOARD_HAUPPAUGE_HVR1255: 2195 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 2196 case CX23885_BOARD_HAUPPAUGE_HVR1270: 2197 case CX23885_BOARD_HAUPPAUGE_HVR1850: 2198 case CX23885_BOARD_MYGICA_X8506: 2199 case CX23885_BOARD_MAGICPRO_PROHDTVE2: 2200 case CX23885_BOARD_HAUPPAUGE_HVR1290: 2201 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200: 2202 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID: 2203 case CX23885_BOARD_HAUPPAUGE_HVR1500: 2204 case CX23885_BOARD_MPX885: 2205 case CX23885_BOARD_MYGICA_X8507: 2206 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 2207 case CX23885_BOARD_AVERMEDIA_HC81R: 2208 case CX23885_BOARD_TBS_6980: 2209 case CX23885_BOARD_TBS_6981: 2210 case CX23885_BOARD_DVBSKY_T9580: 2211 case CX23885_BOARD_DVBSKY_T980C: 2212 case CX23885_BOARD_DVBSKY_S950C: 2213 case CX23885_BOARD_TT_CT2_4500_CI: 2214 case CX23885_BOARD_DVBSKY_S950: 2215 case CX23885_BOARD_DVBSKY_S952: 2216 case CX23885_BOARD_DVBSKY_T982: 2217 case CX23885_BOARD_VIEWCAST_260E: 2218 case CX23885_BOARD_VIEWCAST_460E: 2219 dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev, 2220 &dev->i2c_bus[2].i2c_adap, 2221 "cx25840", 0x88 >> 1, NULL); 2222 if (dev->sd_cx25840) { 2223 dev->sd_cx25840->grp_id = CX23885_HW_AV_CORE; 2224 v4l2_subdev_call(dev->sd_cx25840, core, load_fw); 2225 } 2226 break; 2227 } 2228 2229 switch (dev->board) { 2230 case CX23885_BOARD_VIEWCAST_260E: 2231 v4l2_i2c_new_subdev(&dev->v4l2_dev, 2232 &dev->i2c_bus[0].i2c_adap, 2233 "cs3308", 0x82 >> 1, NULL); 2234 break; 2235 case CX23885_BOARD_VIEWCAST_460E: 2236 /* This cs3308 controls the audio from the breakout cable */ 2237 v4l2_i2c_new_subdev(&dev->v4l2_dev, 2238 &dev->i2c_bus[0].i2c_adap, 2239 "cs3308", 0x80 >> 1, NULL); 2240 /* This cs3308 controls the audio from the onboard header */ 2241 v4l2_i2c_new_subdev(&dev->v4l2_dev, 2242 &dev->i2c_bus[0].i2c_adap, 2243 "cs3308", 0x82 >> 1, NULL); 2244 break; 2245 } 2246 2247 /* AUX-PLL 27MHz CLK */ 2248 switch (dev->board) { 2249 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 2250 netup_initialize(dev); 2251 break; 2252 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: { 2253 int ret; 2254 const struct firmware *fw; 2255 const char *filename = "dvb-netup-altera-01.fw"; 2256 char *action = "configure"; 2257 static struct netup_card_info cinfo; 2258 struct altera_config netup_config = { 2259 .dev = dev, 2260 .action = action, 2261 .jtag_io = netup_jtag_io, 2262 }; 2263 2264 netup_initialize(dev); 2265 2266 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo); 2267 if (netup_card_rev) 2268 cinfo.rev = netup_card_rev; 2269 2270 switch (cinfo.rev) { 2271 case 0x4: 2272 filename = "dvb-netup-altera-04.fw"; 2273 break; 2274 default: 2275 filename = "dvb-netup-altera-01.fw"; 2276 break; 2277 } 2278 printk(KERN_INFO "NetUP card rev=0x%x fw_filename=%s\n", 2279 cinfo.rev, filename); 2280 2281 ret = request_firmware(&fw, filename, &dev->pci->dev); 2282 if (ret != 0) 2283 printk(KERN_ERR "did not find the firmware file. (%s) " 2284 "Please see linux/Documentation/dvb/ for more details " 2285 "on firmware-problems.", filename); 2286 else 2287 altera_init(&netup_config, fw); 2288 2289 release_firmware(fw); 2290 break; 2291 } 2292 } 2293 } 2294