1 /* 2 * Driver for the Conexant CX23885 PCIe bridge 3 * 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 */ 21 22 #include <linux/init.h> 23 #include <linux/module.h> 24 #include <linux/pci.h> 25 #include <linux/delay.h> 26 #include <media/cx25840.h> 27 #include <linux/firmware.h> 28 #include <misc/altera.h> 29 30 #include "cx23885.h" 31 #include "tuner-xc2028.h" 32 #include "netup-eeprom.h" 33 #include "netup-init.h" 34 #include "altera-ci.h" 35 #include "xc4000.h" 36 #include "xc5000.h" 37 #include "cx23888-ir.h" 38 39 static unsigned int netup_card_rev = 4; 40 module_param(netup_card_rev, int, 0644); 41 MODULE_PARM_DESC(netup_card_rev, 42 "NetUP Dual DVB-T/C CI card revision"); 43 static unsigned int enable_885_ir; 44 module_param(enable_885_ir, int, 0644); 45 MODULE_PARM_DESC(enable_885_ir, 46 "Enable integrated IR controller for supported\n" 47 "\t\t CX2388[57] boards that are wired for it:\n" 48 "\t\t\tHVR-1250 (reported safe)\n" 49 "\t\t\tTerraTec Cinergy T PCIe Dual (not well tested, appears to be safe)\n" 50 "\t\t\tTeVii S470 (reported unsafe)\n" 51 "\t\t This can cause an interrupt storm with some cards.\n" 52 "\t\t Default: 0 [Disabled]"); 53 54 /* ------------------------------------------------------------------ */ 55 /* board config info */ 56 57 struct cx23885_board cx23885_boards[] = { 58 [CX23885_BOARD_UNKNOWN] = { 59 .name = "UNKNOWN/GENERIC", 60 /* Ensure safe default for unknown boards */ 61 .clk_freq = 0, 62 .input = {{ 63 .type = CX23885_VMUX_COMPOSITE1, 64 .vmux = 0, 65 }, { 66 .type = CX23885_VMUX_COMPOSITE2, 67 .vmux = 1, 68 }, { 69 .type = CX23885_VMUX_COMPOSITE3, 70 .vmux = 2, 71 }, { 72 .type = CX23885_VMUX_COMPOSITE4, 73 .vmux = 3, 74 } }, 75 }, 76 [CX23885_BOARD_HAUPPAUGE_HVR1800lp] = { 77 .name = "Hauppauge WinTV-HVR1800lp", 78 .portc = CX23885_MPEG_DVB, 79 .input = {{ 80 .type = CX23885_VMUX_TELEVISION, 81 .vmux = 0, 82 .gpio0 = 0xff00, 83 }, { 84 .type = CX23885_VMUX_DEBUG, 85 .vmux = 0, 86 .gpio0 = 0xff01, 87 }, { 88 .type = CX23885_VMUX_COMPOSITE1, 89 .vmux = 1, 90 .gpio0 = 0xff02, 91 }, { 92 .type = CX23885_VMUX_SVIDEO, 93 .vmux = 2, 94 .gpio0 = 0xff02, 95 } }, 96 }, 97 [CX23885_BOARD_HAUPPAUGE_HVR1800] = { 98 .name = "Hauppauge WinTV-HVR1800", 99 .porta = CX23885_ANALOG_VIDEO, 100 .portb = CX23885_MPEG_ENCODER, 101 .portc = CX23885_MPEG_DVB, 102 .tuner_type = TUNER_PHILIPS_TDA8290, 103 .tuner_addr = 0x42, /* 0x84 >> 1 */ 104 .tuner_bus = 1, 105 .input = {{ 106 .type = CX23885_VMUX_TELEVISION, 107 .vmux = CX25840_VIN7_CH3 | 108 CX25840_VIN5_CH2 | 109 CX25840_VIN2_CH1, 110 .amux = CX25840_AUDIO8, 111 .gpio0 = 0, 112 }, { 113 .type = CX23885_VMUX_COMPOSITE1, 114 .vmux = CX25840_VIN7_CH3 | 115 CX25840_VIN4_CH2 | 116 CX25840_VIN6_CH1, 117 .amux = CX25840_AUDIO7, 118 .gpio0 = 0, 119 }, { 120 .type = CX23885_VMUX_SVIDEO, 121 .vmux = CX25840_VIN7_CH3 | 122 CX25840_VIN4_CH2 | 123 CX25840_VIN8_CH1 | 124 CX25840_SVIDEO_ON, 125 .amux = CX25840_AUDIO7, 126 .gpio0 = 0, 127 } }, 128 }, 129 [CX23885_BOARD_HAUPPAUGE_HVR1250] = { 130 .name = "Hauppauge WinTV-HVR1250", 131 .porta = CX23885_ANALOG_VIDEO, 132 .portc = CX23885_MPEG_DVB, 133 #ifdef MT2131_NO_ANALOG_SUPPORT_YET 134 .tuner_type = TUNER_PHILIPS_TDA8290, 135 .tuner_addr = 0x42, /* 0x84 >> 1 */ 136 .tuner_bus = 1, 137 #endif 138 .force_bff = 1, 139 .input = {{ 140 #ifdef MT2131_NO_ANALOG_SUPPORT_YET 141 .type = CX23885_VMUX_TELEVISION, 142 .vmux = CX25840_VIN7_CH3 | 143 CX25840_VIN5_CH2 | 144 CX25840_VIN2_CH1, 145 .amux = CX25840_AUDIO8, 146 .gpio0 = 0xff00, 147 }, { 148 #endif 149 .type = CX23885_VMUX_COMPOSITE1, 150 .vmux = CX25840_VIN7_CH3 | 151 CX25840_VIN4_CH2 | 152 CX25840_VIN6_CH1, 153 .amux = CX25840_AUDIO7, 154 .gpio0 = 0xff02, 155 }, { 156 .type = CX23885_VMUX_SVIDEO, 157 .vmux = CX25840_VIN7_CH3 | 158 CX25840_VIN4_CH2 | 159 CX25840_VIN8_CH1 | 160 CX25840_SVIDEO_ON, 161 .amux = CX25840_AUDIO7, 162 .gpio0 = 0xff02, 163 } }, 164 }, 165 [CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP] = { 166 .name = "DViCO FusionHDTV5 Express", 167 .portb = CX23885_MPEG_DVB, 168 }, 169 [CX23885_BOARD_HAUPPAUGE_HVR1500Q] = { 170 .name = "Hauppauge WinTV-HVR1500Q", 171 .portc = CX23885_MPEG_DVB, 172 }, 173 [CX23885_BOARD_HAUPPAUGE_HVR1500] = { 174 .name = "Hauppauge WinTV-HVR1500", 175 .porta = CX23885_ANALOG_VIDEO, 176 .portc = CX23885_MPEG_DVB, 177 .tuner_type = TUNER_XC2028, 178 .tuner_addr = 0x61, /* 0xc2 >> 1 */ 179 .input = {{ 180 .type = CX23885_VMUX_TELEVISION, 181 .vmux = CX25840_VIN7_CH3 | 182 CX25840_VIN5_CH2 | 183 CX25840_VIN2_CH1, 184 .gpio0 = 0, 185 }, { 186 .type = CX23885_VMUX_COMPOSITE1, 187 .vmux = CX25840_VIN7_CH3 | 188 CX25840_VIN4_CH2 | 189 CX25840_VIN6_CH1, 190 .gpio0 = 0, 191 }, { 192 .type = CX23885_VMUX_SVIDEO, 193 .vmux = CX25840_VIN7_CH3 | 194 CX25840_VIN4_CH2 | 195 CX25840_VIN8_CH1 | 196 CX25840_SVIDEO_ON, 197 .gpio0 = 0, 198 } }, 199 }, 200 [CX23885_BOARD_HAUPPAUGE_HVR1200] = { 201 .name = "Hauppauge WinTV-HVR1200", 202 .portc = CX23885_MPEG_DVB, 203 }, 204 [CX23885_BOARD_HAUPPAUGE_HVR1700] = { 205 .name = "Hauppauge WinTV-HVR1700", 206 .portc = CX23885_MPEG_DVB, 207 }, 208 [CX23885_BOARD_HAUPPAUGE_HVR1400] = { 209 .name = "Hauppauge WinTV-HVR1400", 210 .portc = CX23885_MPEG_DVB, 211 }, 212 [CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP] = { 213 .name = "DViCO FusionHDTV7 Dual Express", 214 .portb = CX23885_MPEG_DVB, 215 .portc = CX23885_MPEG_DVB, 216 }, 217 [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP] = { 218 .name = "DViCO FusionHDTV DVB-T Dual Express", 219 .portb = CX23885_MPEG_DVB, 220 .portc = CX23885_MPEG_DVB, 221 }, 222 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H] = { 223 .name = "Leadtek Winfast PxDVR3200 H", 224 .portc = CX23885_MPEG_DVB, 225 }, 226 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000] = { 227 .name = "Leadtek Winfast PxDVR3200 H XC4000", 228 .porta = CX23885_ANALOG_VIDEO, 229 .portc = CX23885_MPEG_DVB, 230 .tuner_type = TUNER_XC4000, 231 .tuner_addr = 0x61, 232 .radio_type = UNSET, 233 .radio_addr = ADDR_UNSET, 234 .input = {{ 235 .type = CX23885_VMUX_TELEVISION, 236 .vmux = CX25840_VIN2_CH1 | 237 CX25840_VIN5_CH2 | 238 CX25840_NONE0_CH3, 239 }, { 240 .type = CX23885_VMUX_COMPOSITE1, 241 .vmux = CX25840_COMPOSITE1, 242 }, { 243 .type = CX23885_VMUX_SVIDEO, 244 .vmux = CX25840_SVIDEO_LUMA3 | 245 CX25840_SVIDEO_CHROMA4, 246 }, { 247 .type = CX23885_VMUX_COMPONENT, 248 .vmux = CX25840_VIN7_CH1 | 249 CX25840_VIN6_CH2 | 250 CX25840_VIN8_CH3 | 251 CX25840_COMPONENT_ON, 252 } }, 253 }, 254 [CX23885_BOARD_COMPRO_VIDEOMATE_E650F] = { 255 .name = "Compro VideoMate E650F", 256 .portc = CX23885_MPEG_DVB, 257 }, 258 [CX23885_BOARD_TBS_6920] = { 259 .name = "TurboSight TBS 6920", 260 .portb = CX23885_MPEG_DVB, 261 }, 262 [CX23885_BOARD_TEVII_S470] = { 263 .name = "TeVii S470", 264 .portb = CX23885_MPEG_DVB, 265 }, 266 [CX23885_BOARD_DVBWORLD_2005] = { 267 .name = "DVBWorld DVB-S2 2005", 268 .portb = CX23885_MPEG_DVB, 269 }, 270 [CX23885_BOARD_NETUP_DUAL_DVBS2_CI] = { 271 .ci_type = 1, 272 .name = "NetUP Dual DVB-S2 CI", 273 .portb = CX23885_MPEG_DVB, 274 .portc = CX23885_MPEG_DVB, 275 }, 276 [CX23885_BOARD_HAUPPAUGE_HVR1270] = { 277 .name = "Hauppauge WinTV-HVR1270", 278 .portc = CX23885_MPEG_DVB, 279 }, 280 [CX23885_BOARD_HAUPPAUGE_HVR1275] = { 281 .name = "Hauppauge WinTV-HVR1275", 282 .portc = CX23885_MPEG_DVB, 283 }, 284 [CX23885_BOARD_HAUPPAUGE_HVR1255] = { 285 .name = "Hauppauge WinTV-HVR1255", 286 .porta = CX23885_ANALOG_VIDEO, 287 .portc = CX23885_MPEG_DVB, 288 .tuner_type = TUNER_ABSENT, 289 .tuner_addr = 0x42, /* 0x84 >> 1 */ 290 .force_bff = 1, 291 .input = {{ 292 .type = CX23885_VMUX_TELEVISION, 293 .vmux = CX25840_VIN7_CH3 | 294 CX25840_VIN5_CH2 | 295 CX25840_VIN2_CH1 | 296 CX25840_DIF_ON, 297 .amux = CX25840_AUDIO8, 298 }, { 299 .type = CX23885_VMUX_COMPOSITE1, 300 .vmux = CX25840_VIN7_CH3 | 301 CX25840_VIN4_CH2 | 302 CX25840_VIN6_CH1, 303 .amux = CX25840_AUDIO7, 304 }, { 305 .type = CX23885_VMUX_SVIDEO, 306 .vmux = CX25840_VIN7_CH3 | 307 CX25840_VIN4_CH2 | 308 CX25840_VIN8_CH1 | 309 CX25840_SVIDEO_ON, 310 .amux = CX25840_AUDIO7, 311 } }, 312 }, 313 [CX23885_BOARD_HAUPPAUGE_HVR1255_22111] = { 314 .name = "Hauppauge WinTV-HVR1255", 315 .porta = CX23885_ANALOG_VIDEO, 316 .portc = CX23885_MPEG_DVB, 317 .tuner_type = TUNER_ABSENT, 318 .tuner_addr = 0x42, /* 0x84 >> 1 */ 319 .force_bff = 1, 320 .input = {{ 321 .type = CX23885_VMUX_TELEVISION, 322 .vmux = CX25840_VIN7_CH3 | 323 CX25840_VIN5_CH2 | 324 CX25840_VIN2_CH1 | 325 CX25840_DIF_ON, 326 .amux = CX25840_AUDIO8, 327 }, { 328 .type = CX23885_VMUX_SVIDEO, 329 .vmux = CX25840_VIN7_CH3 | 330 CX25840_VIN4_CH2 | 331 CX25840_VIN8_CH1 | 332 CX25840_SVIDEO_ON, 333 .amux = CX25840_AUDIO7, 334 } }, 335 }, 336 [CX23885_BOARD_HAUPPAUGE_HVR1210] = { 337 .name = "Hauppauge WinTV-HVR1210", 338 .portc = CX23885_MPEG_DVB, 339 }, 340 [CX23885_BOARD_MYGICA_X8506] = { 341 .name = "Mygica X8506 DMB-TH", 342 .tuner_type = TUNER_XC5000, 343 .tuner_addr = 0x61, 344 .tuner_bus = 1, 345 .porta = CX23885_ANALOG_VIDEO, 346 .portb = CX23885_MPEG_DVB, 347 .input = { 348 { 349 .type = CX23885_VMUX_TELEVISION, 350 .vmux = CX25840_COMPOSITE2, 351 }, 352 { 353 .type = CX23885_VMUX_COMPOSITE1, 354 .vmux = CX25840_COMPOSITE8, 355 }, 356 { 357 .type = CX23885_VMUX_SVIDEO, 358 .vmux = CX25840_SVIDEO_LUMA3 | 359 CX25840_SVIDEO_CHROMA4, 360 }, 361 { 362 .type = CX23885_VMUX_COMPONENT, 363 .vmux = CX25840_COMPONENT_ON | 364 CX25840_VIN1_CH1 | 365 CX25840_VIN6_CH2 | 366 CX25840_VIN7_CH3, 367 }, 368 }, 369 }, 370 [CX23885_BOARD_MAGICPRO_PROHDTVE2] = { 371 .name = "Magic-Pro ProHDTV Extreme 2", 372 .tuner_type = TUNER_XC5000, 373 .tuner_addr = 0x61, 374 .tuner_bus = 1, 375 .porta = CX23885_ANALOG_VIDEO, 376 .portb = CX23885_MPEG_DVB, 377 .input = { 378 { 379 .type = CX23885_VMUX_TELEVISION, 380 .vmux = CX25840_COMPOSITE2, 381 }, 382 { 383 .type = CX23885_VMUX_COMPOSITE1, 384 .vmux = CX25840_COMPOSITE8, 385 }, 386 { 387 .type = CX23885_VMUX_SVIDEO, 388 .vmux = CX25840_SVIDEO_LUMA3 | 389 CX25840_SVIDEO_CHROMA4, 390 }, 391 { 392 .type = CX23885_VMUX_COMPONENT, 393 .vmux = CX25840_COMPONENT_ON | 394 CX25840_VIN1_CH1 | 395 CX25840_VIN6_CH2 | 396 CX25840_VIN7_CH3, 397 }, 398 }, 399 }, 400 [CX23885_BOARD_HAUPPAUGE_HVR1850] = { 401 .name = "Hauppauge WinTV-HVR1850", 402 .porta = CX23885_ANALOG_VIDEO, 403 .portb = CX23885_MPEG_ENCODER, 404 .portc = CX23885_MPEG_DVB, 405 .tuner_type = TUNER_ABSENT, 406 .tuner_addr = 0x42, /* 0x84 >> 1 */ 407 .force_bff = 1, 408 .input = {{ 409 .type = CX23885_VMUX_TELEVISION, 410 .vmux = CX25840_VIN7_CH3 | 411 CX25840_VIN5_CH2 | 412 CX25840_VIN2_CH1 | 413 CX25840_DIF_ON, 414 .amux = CX25840_AUDIO8, 415 }, { 416 .type = CX23885_VMUX_COMPOSITE1, 417 .vmux = CX25840_VIN7_CH3 | 418 CX25840_VIN4_CH2 | 419 CX25840_VIN6_CH1, 420 .amux = CX25840_AUDIO7, 421 }, { 422 .type = CX23885_VMUX_SVIDEO, 423 .vmux = CX25840_VIN7_CH3 | 424 CX25840_VIN4_CH2 | 425 CX25840_VIN8_CH1 | 426 CX25840_SVIDEO_ON, 427 .amux = CX25840_AUDIO7, 428 } }, 429 }, 430 [CX23885_BOARD_COMPRO_VIDEOMATE_E800] = { 431 .name = "Compro VideoMate E800", 432 .portc = CX23885_MPEG_DVB, 433 }, 434 [CX23885_BOARD_HAUPPAUGE_HVR1290] = { 435 .name = "Hauppauge WinTV-HVR1290", 436 .portc = CX23885_MPEG_DVB, 437 }, 438 [CX23885_BOARD_MYGICA_X8558PRO] = { 439 .name = "Mygica X8558 PRO DMB-TH", 440 .portb = CX23885_MPEG_DVB, 441 .portc = CX23885_MPEG_DVB, 442 }, 443 [CX23885_BOARD_LEADTEK_WINFAST_PXTV1200] = { 444 .name = "LEADTEK WinFast PxTV1200", 445 .porta = CX23885_ANALOG_VIDEO, 446 .tuner_type = TUNER_XC2028, 447 .tuner_addr = 0x61, 448 .tuner_bus = 1, 449 .input = {{ 450 .type = CX23885_VMUX_TELEVISION, 451 .vmux = CX25840_VIN2_CH1 | 452 CX25840_VIN5_CH2 | 453 CX25840_NONE0_CH3, 454 }, { 455 .type = CX23885_VMUX_COMPOSITE1, 456 .vmux = CX25840_COMPOSITE1, 457 }, { 458 .type = CX23885_VMUX_SVIDEO, 459 .vmux = CX25840_SVIDEO_LUMA3 | 460 CX25840_SVIDEO_CHROMA4, 461 }, { 462 .type = CX23885_VMUX_COMPONENT, 463 .vmux = CX25840_VIN7_CH1 | 464 CX25840_VIN6_CH2 | 465 CX25840_VIN8_CH3 | 466 CX25840_COMPONENT_ON, 467 } }, 468 }, 469 [CX23885_BOARD_GOTVIEW_X5_3D_HYBRID] = { 470 .name = "GoTView X5 3D Hybrid", 471 .tuner_type = TUNER_XC5000, 472 .tuner_addr = 0x64, 473 .tuner_bus = 1, 474 .porta = CX23885_ANALOG_VIDEO, 475 .portb = CX23885_MPEG_DVB, 476 .input = {{ 477 .type = CX23885_VMUX_TELEVISION, 478 .vmux = CX25840_VIN2_CH1 | 479 CX25840_VIN5_CH2, 480 .gpio0 = 0x02, 481 }, { 482 .type = CX23885_VMUX_COMPOSITE1, 483 .vmux = CX23885_VMUX_COMPOSITE1, 484 }, { 485 .type = CX23885_VMUX_SVIDEO, 486 .vmux = CX25840_SVIDEO_LUMA3 | 487 CX25840_SVIDEO_CHROMA4, 488 } }, 489 }, 490 [CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF] = { 491 .ci_type = 2, 492 .name = "NetUP Dual DVB-T/C-CI RF", 493 .porta = CX23885_ANALOG_VIDEO, 494 .portb = CX23885_MPEG_DVB, 495 .portc = CX23885_MPEG_DVB, 496 .num_fds_portb = 2, 497 .num_fds_portc = 2, 498 .tuner_type = TUNER_XC5000, 499 .tuner_addr = 0x64, 500 .input = { { 501 .type = CX23885_VMUX_TELEVISION, 502 .vmux = CX25840_COMPOSITE1, 503 } }, 504 }, 505 [CX23885_BOARD_MPX885] = { 506 .name = "MPX-885", 507 .porta = CX23885_ANALOG_VIDEO, 508 .input = {{ 509 .type = CX23885_VMUX_COMPOSITE1, 510 .vmux = CX25840_COMPOSITE1, 511 .amux = CX25840_AUDIO6, 512 .gpio0 = 0, 513 }, { 514 .type = CX23885_VMUX_COMPOSITE2, 515 .vmux = CX25840_COMPOSITE2, 516 .amux = CX25840_AUDIO6, 517 .gpio0 = 0, 518 }, { 519 .type = CX23885_VMUX_COMPOSITE3, 520 .vmux = CX25840_COMPOSITE3, 521 .amux = CX25840_AUDIO7, 522 .gpio0 = 0, 523 }, { 524 .type = CX23885_VMUX_COMPOSITE4, 525 .vmux = CX25840_COMPOSITE4, 526 .amux = CX25840_AUDIO7, 527 .gpio0 = 0, 528 } }, 529 }, 530 [CX23885_BOARD_MYGICA_X8507] = { 531 .name = "Mygica X8502/X8507 ISDB-T", 532 .tuner_type = TUNER_XC5000, 533 .tuner_addr = 0x61, 534 .tuner_bus = 1, 535 .porta = CX23885_ANALOG_VIDEO, 536 .portb = CX23885_MPEG_DVB, 537 .input = { 538 { 539 .type = CX23885_VMUX_TELEVISION, 540 .vmux = CX25840_COMPOSITE2, 541 .amux = CX25840_AUDIO8, 542 }, 543 { 544 .type = CX23885_VMUX_COMPOSITE1, 545 .vmux = CX25840_COMPOSITE8, 546 .amux = CX25840_AUDIO7, 547 }, 548 { 549 .type = CX23885_VMUX_SVIDEO, 550 .vmux = CX25840_SVIDEO_LUMA3 | 551 CX25840_SVIDEO_CHROMA4, 552 .amux = CX25840_AUDIO7, 553 }, 554 { 555 .type = CX23885_VMUX_COMPONENT, 556 .vmux = CX25840_COMPONENT_ON | 557 CX25840_VIN1_CH1 | 558 CX25840_VIN6_CH2 | 559 CX25840_VIN7_CH3, 560 .amux = CX25840_AUDIO7, 561 }, 562 }, 563 }, 564 [CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL] = { 565 .name = "TerraTec Cinergy T PCIe Dual", 566 .portb = CX23885_MPEG_DVB, 567 .portc = CX23885_MPEG_DVB, 568 }, 569 [CX23885_BOARD_TEVII_S471] = { 570 .name = "TeVii S471", 571 .portb = CX23885_MPEG_DVB, 572 }, 573 [CX23885_BOARD_PROF_8000] = { 574 .name = "Prof Revolution DVB-S2 8000", 575 .portb = CX23885_MPEG_DVB, 576 }, 577 [CX23885_BOARD_HAUPPAUGE_HVR4400] = { 578 .name = "Hauppauge WinTV-HVR4400", 579 .portb = CX23885_MPEG_DVB, 580 }, 581 [CX23885_BOARD_AVERMEDIA_HC81R] = { 582 .name = "AVerTV Hybrid Express Slim HC81R", 583 .tuner_type = TUNER_XC2028, 584 .tuner_addr = 0x61, /* 0xc2 >> 1 */ 585 .tuner_bus = 1, 586 .porta = CX23885_ANALOG_VIDEO, 587 .input = {{ 588 .type = CX23885_VMUX_TELEVISION, 589 .vmux = CX25840_VIN2_CH1 | 590 CX25840_VIN5_CH2 | 591 CX25840_NONE0_CH3 | 592 CX25840_NONE1_CH3, 593 .amux = CX25840_AUDIO8, 594 }, { 595 .type = CX23885_VMUX_SVIDEO, 596 .vmux = CX25840_VIN8_CH1 | 597 CX25840_NONE_CH2 | 598 CX25840_VIN7_CH3 | 599 CX25840_SVIDEO_ON, 600 .amux = CX25840_AUDIO6, 601 }, { 602 .type = CX23885_VMUX_COMPONENT, 603 .vmux = CX25840_VIN1_CH1 | 604 CX25840_NONE_CH2 | 605 CX25840_NONE0_CH3 | 606 CX25840_NONE1_CH3, 607 .amux = CX25840_AUDIO6, 608 } }, 609 } 610 }; 611 const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards); 612 613 /* ------------------------------------------------------------------ */ 614 /* PCI subsystem IDs */ 615 616 struct cx23885_subid cx23885_subids[] = { 617 { 618 .subvendor = 0x0070, 619 .subdevice = 0x3400, 620 .card = CX23885_BOARD_UNKNOWN, 621 }, { 622 .subvendor = 0x0070, 623 .subdevice = 0x7600, 624 .card = CX23885_BOARD_HAUPPAUGE_HVR1800lp, 625 }, { 626 .subvendor = 0x0070, 627 .subdevice = 0x7800, 628 .card = CX23885_BOARD_HAUPPAUGE_HVR1800, 629 }, { 630 .subvendor = 0x0070, 631 .subdevice = 0x7801, 632 .card = CX23885_BOARD_HAUPPAUGE_HVR1800, 633 }, { 634 .subvendor = 0x0070, 635 .subdevice = 0x7809, 636 .card = CX23885_BOARD_HAUPPAUGE_HVR1800, 637 }, { 638 .subvendor = 0x0070, 639 .subdevice = 0x7911, 640 .card = CX23885_BOARD_HAUPPAUGE_HVR1250, 641 }, { 642 .subvendor = 0x18ac, 643 .subdevice = 0xd500, 644 .card = CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP, 645 }, { 646 .subvendor = 0x0070, 647 .subdevice = 0x7790, 648 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q, 649 }, { 650 .subvendor = 0x0070, 651 .subdevice = 0x7797, 652 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q, 653 }, { 654 .subvendor = 0x0070, 655 .subdevice = 0x7710, 656 .card = CX23885_BOARD_HAUPPAUGE_HVR1500, 657 }, { 658 .subvendor = 0x0070, 659 .subdevice = 0x7717, 660 .card = CX23885_BOARD_HAUPPAUGE_HVR1500, 661 }, { 662 .subvendor = 0x0070, 663 .subdevice = 0x71d1, 664 .card = CX23885_BOARD_HAUPPAUGE_HVR1200, 665 }, { 666 .subvendor = 0x0070, 667 .subdevice = 0x71d3, 668 .card = CX23885_BOARD_HAUPPAUGE_HVR1200, 669 }, { 670 .subvendor = 0x0070, 671 .subdevice = 0x8101, 672 .card = CX23885_BOARD_HAUPPAUGE_HVR1700, 673 }, { 674 .subvendor = 0x0070, 675 .subdevice = 0x8010, 676 .card = CX23885_BOARD_HAUPPAUGE_HVR1400, 677 }, { 678 .subvendor = 0x18ac, 679 .subdevice = 0xd618, 680 .card = CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP, 681 }, { 682 .subvendor = 0x18ac, 683 .subdevice = 0xdb78, 684 .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP, 685 }, { 686 .subvendor = 0x107d, 687 .subdevice = 0x6681, 688 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H, 689 }, { 690 .subvendor = 0x107d, 691 .subdevice = 0x6f39, 692 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000, 693 }, { 694 .subvendor = 0x185b, 695 .subdevice = 0xe800, 696 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E650F, 697 }, { 698 .subvendor = 0x6920, 699 .subdevice = 0x8888, 700 .card = CX23885_BOARD_TBS_6920, 701 }, { 702 .subvendor = 0xd470, 703 .subdevice = 0x9022, 704 .card = CX23885_BOARD_TEVII_S470, 705 }, { 706 .subvendor = 0x0001, 707 .subdevice = 0x2005, 708 .card = CX23885_BOARD_DVBWORLD_2005, 709 }, { 710 .subvendor = 0x1b55, 711 .subdevice = 0x2a2c, 712 .card = CX23885_BOARD_NETUP_DUAL_DVBS2_CI, 713 }, { 714 .subvendor = 0x0070, 715 .subdevice = 0x2211, 716 .card = CX23885_BOARD_HAUPPAUGE_HVR1270, 717 }, { 718 .subvendor = 0x0070, 719 .subdevice = 0x2215, 720 .card = CX23885_BOARD_HAUPPAUGE_HVR1275, 721 }, { 722 .subvendor = 0x0070, 723 .subdevice = 0x221d, 724 .card = CX23885_BOARD_HAUPPAUGE_HVR1275, 725 }, { 726 .subvendor = 0x0070, 727 .subdevice = 0x2251, 728 .card = CX23885_BOARD_HAUPPAUGE_HVR1255, 729 }, { 730 .subvendor = 0x0070, 731 .subdevice = 0x2259, 732 .card = CX23885_BOARD_HAUPPAUGE_HVR1255_22111, 733 }, { 734 .subvendor = 0x0070, 735 .subdevice = 0x2291, 736 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 737 }, { 738 .subvendor = 0x0070, 739 .subdevice = 0x2295, 740 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 741 }, { 742 .subvendor = 0x0070, 743 .subdevice = 0x2299, 744 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 745 }, { 746 .subvendor = 0x0070, 747 .subdevice = 0x229d, 748 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */ 749 }, { 750 .subvendor = 0x0070, 751 .subdevice = 0x22f0, 752 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 753 }, { 754 .subvendor = 0x0070, 755 .subdevice = 0x22f1, 756 .card = CX23885_BOARD_HAUPPAUGE_HVR1255, 757 }, { 758 .subvendor = 0x0070, 759 .subdevice = 0x22f2, 760 .card = CX23885_BOARD_HAUPPAUGE_HVR1275, 761 }, { 762 .subvendor = 0x0070, 763 .subdevice = 0x22f3, 764 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */ 765 }, { 766 .subvendor = 0x0070, 767 .subdevice = 0x22f4, 768 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 769 }, { 770 .subvendor = 0x0070, 771 .subdevice = 0x22f5, 772 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */ 773 }, { 774 .subvendor = 0x14f1, 775 .subdevice = 0x8651, 776 .card = CX23885_BOARD_MYGICA_X8506, 777 }, { 778 .subvendor = 0x14f1, 779 .subdevice = 0x8657, 780 .card = CX23885_BOARD_MAGICPRO_PROHDTVE2, 781 }, { 782 .subvendor = 0x0070, 783 .subdevice = 0x8541, 784 .card = CX23885_BOARD_HAUPPAUGE_HVR1850, 785 }, { 786 .subvendor = 0x1858, 787 .subdevice = 0xe800, 788 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E800, 789 }, { 790 .subvendor = 0x0070, 791 .subdevice = 0x8551, 792 .card = CX23885_BOARD_HAUPPAUGE_HVR1290, 793 }, { 794 .subvendor = 0x14f1, 795 .subdevice = 0x8578, 796 .card = CX23885_BOARD_MYGICA_X8558PRO, 797 }, { 798 .subvendor = 0x107d, 799 .subdevice = 0x6f22, 800 .card = CX23885_BOARD_LEADTEK_WINFAST_PXTV1200, 801 }, { 802 .subvendor = 0x5654, 803 .subdevice = 0x2390, 804 .card = CX23885_BOARD_GOTVIEW_X5_3D_HYBRID, 805 }, { 806 .subvendor = 0x1b55, 807 .subdevice = 0xe2e4, 808 .card = CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF, 809 }, { 810 .subvendor = 0x14f1, 811 .subdevice = 0x8502, 812 .card = CX23885_BOARD_MYGICA_X8507, 813 }, { 814 .subvendor = 0x153b, 815 .subdevice = 0x117e, 816 .card = CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL, 817 }, { 818 .subvendor = 0xd471, 819 .subdevice = 0x9022, 820 .card = CX23885_BOARD_TEVII_S471, 821 }, { 822 .subvendor = 0x8000, 823 .subdevice = 0x3034, 824 .card = CX23885_BOARD_PROF_8000, 825 }, { 826 .subvendor = 0x0070, 827 .subdevice = 0xc108, 828 .card = CX23885_BOARD_HAUPPAUGE_HVR4400, 829 }, { 830 .subvendor = 0x0070, 831 .subdevice = 0xc138, 832 .card = CX23885_BOARD_HAUPPAUGE_HVR4400, 833 }, { 834 .subvendor = 0x0070, 835 .subdevice = 0xc12a, 836 .card = CX23885_BOARD_HAUPPAUGE_HVR4400, 837 }, { 838 .subvendor = 0x0070, 839 .subdevice = 0xc1f8, 840 .card = CX23885_BOARD_HAUPPAUGE_HVR4400, 841 }, { 842 .subvendor = 0x1461, 843 .subdevice = 0xd939, 844 .card = CX23885_BOARD_AVERMEDIA_HC81R, 845 }, 846 }; 847 const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids); 848 849 void cx23885_card_list(struct cx23885_dev *dev) 850 { 851 int i; 852 853 if (0 == dev->pci->subsystem_vendor && 854 0 == dev->pci->subsystem_device) { 855 printk(KERN_INFO 856 "%s: Board has no valid PCIe Subsystem ID and can't\n" 857 "%s: be autodetected. Pass card=<n> insmod option\n" 858 "%s: to workaround that. Redirect complaints to the\n" 859 "%s: vendor of the TV card. Best regards,\n" 860 "%s: -- tux\n", 861 dev->name, dev->name, dev->name, dev->name, dev->name); 862 } else { 863 printk(KERN_INFO 864 "%s: Your board isn't known (yet) to the driver.\n" 865 "%s: Try to pick one of the existing card configs via\n" 866 "%s: card=<n> insmod option. Updating to the latest\n" 867 "%s: version might help as well.\n", 868 dev->name, dev->name, dev->name, dev->name); 869 } 870 printk(KERN_INFO "%s: Here is a list of valid choices for the card=<n> insmod option:\n", 871 dev->name); 872 for (i = 0; i < cx23885_bcount; i++) 873 printk(KERN_INFO "%s: card=%d -> %s\n", 874 dev->name, i, cx23885_boards[i].name); 875 } 876 877 static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data) 878 { 879 struct tveeprom tv; 880 881 tveeprom_hauppauge_analog(&dev->i2c_bus[0].i2c_client, &tv, 882 eeprom_data); 883 884 /* Make sure we support the board model */ 885 switch (tv.model) { 886 case 22001: 887 /* WinTV-HVR1270 (PCIe, Retail, half height) 888 * ATSC/QAM and basic analog, IR Blast */ 889 case 22009: 890 /* WinTV-HVR1210 (PCIe, Retail, half height) 891 * DVB-T and basic analog, IR Blast */ 892 case 22011: 893 /* WinTV-HVR1270 (PCIe, Retail, half height) 894 * ATSC/QAM and basic analog, IR Recv */ 895 case 22019: 896 /* WinTV-HVR1210 (PCIe, Retail, half height) 897 * DVB-T and basic analog, IR Recv */ 898 case 22021: 899 /* WinTV-HVR1275 (PCIe, Retail, half height) 900 * ATSC/QAM and basic analog, IR Recv */ 901 case 22029: 902 /* WinTV-HVR1210 (PCIe, Retail, half height) 903 * DVB-T and basic analog, IR Recv */ 904 case 22101: 905 /* WinTV-HVR1270 (PCIe, Retail, full height) 906 * ATSC/QAM and basic analog, IR Blast */ 907 case 22109: 908 /* WinTV-HVR1210 (PCIe, Retail, full height) 909 * DVB-T and basic analog, IR Blast */ 910 case 22111: 911 /* WinTV-HVR1270 (PCIe, Retail, full height) 912 * ATSC/QAM and basic analog, IR Recv */ 913 case 22119: 914 /* WinTV-HVR1210 (PCIe, Retail, full height) 915 * DVB-T and basic analog, IR Recv */ 916 case 22121: 917 /* WinTV-HVR1275 (PCIe, Retail, full height) 918 * ATSC/QAM and basic analog, IR Recv */ 919 case 22129: 920 /* WinTV-HVR1210 (PCIe, Retail, full height) 921 * DVB-T and basic analog, IR Recv */ 922 case 71009: 923 /* WinTV-HVR1200 (PCIe, Retail, full height) 924 * DVB-T and basic analog */ 925 case 71359: 926 /* WinTV-HVR1200 (PCIe, OEM, half height) 927 * DVB-T and basic analog */ 928 case 71439: 929 /* WinTV-HVR1200 (PCIe, OEM, half height) 930 * DVB-T and basic analog */ 931 case 71449: 932 /* WinTV-HVR1200 (PCIe, OEM, full height) 933 * DVB-T and basic analog */ 934 case 71939: 935 /* WinTV-HVR1200 (PCIe, OEM, half height) 936 * DVB-T and basic analog */ 937 case 71949: 938 /* WinTV-HVR1200 (PCIe, OEM, full height) 939 * DVB-T and basic analog */ 940 case 71959: 941 /* WinTV-HVR1200 (PCIe, OEM, full height) 942 * DVB-T and basic analog */ 943 case 71979: 944 /* WinTV-HVR1200 (PCIe, OEM, half height) 945 * DVB-T and basic analog */ 946 case 71999: 947 /* WinTV-HVR1200 (PCIe, OEM, full height) 948 * DVB-T and basic analog */ 949 case 76601: 950 /* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual 951 channel ATSC and MPEG2 HW Encoder */ 952 case 77001: 953 /* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC 954 and Basic analog */ 955 case 77011: 956 /* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC 957 and Basic analog */ 958 case 77041: 959 /* WinTV-HVR1500Q (Express Card, OEM, No IR, ATSC/QAM 960 and Basic analog */ 961 case 77051: 962 /* WinTV-HVR1500Q (Express Card, Retail, No IR, ATSC/QAM 963 and Basic analog */ 964 case 78011: 965 /* WinTV-HVR1800 (PCIe, Retail, 3.5mm in, IR, No FM, 966 Dual channel ATSC and MPEG2 HW Encoder */ 967 case 78501: 968 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM, 969 Dual channel ATSC and MPEG2 HW Encoder */ 970 case 78521: 971 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM, 972 Dual channel ATSC and MPEG2 HW Encoder */ 973 case 78531: 974 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, No FM, 975 Dual channel ATSC and MPEG2 HW Encoder */ 976 case 78631: 977 /* WinTV-HVR1800 (PCIe, OEM, No IR, No FM, 978 Dual channel ATSC and MPEG2 HW Encoder */ 979 case 79001: 980 /* WinTV-HVR1250 (PCIe, Retail, IR, full height, 981 ATSC and Basic analog */ 982 case 79101: 983 /* WinTV-HVR1250 (PCIe, Retail, IR, half height, 984 ATSC and Basic analog */ 985 case 79501: 986 /* WinTV-HVR1250 (PCIe, No IR, half height, 987 ATSC [at least] and Basic analog) */ 988 case 79561: 989 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height, 990 ATSC and Basic analog */ 991 case 79571: 992 /* WinTV-HVR1250 (PCIe, OEM, No IR, full height, 993 ATSC and Basic analog */ 994 case 79671: 995 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height, 996 ATSC and Basic analog */ 997 case 80019: 998 /* WinTV-HVR1400 (Express Card, Retail, IR, 999 * DVB-T and Basic analog */ 1000 case 81509: 1001 /* WinTV-HVR1700 (PCIe, OEM, No IR, half height) 1002 * DVB-T and MPEG2 HW Encoder */ 1003 case 81519: 1004 /* WinTV-HVR1700 (PCIe, OEM, No IR, full height) 1005 * DVB-T and MPEG2 HW Encoder */ 1006 break; 1007 case 85021: 1008 /* WinTV-HVR1850 (PCIe, Retail, 3.5mm in, IR, FM, 1009 Dual channel ATSC and MPEG2 HW Encoder */ 1010 break; 1011 case 85721: 1012 /* WinTV-HVR1290 (PCIe, OEM, RCA in, IR, 1013 Dual channel ATSC and Basic analog */ 1014 break; 1015 default: 1016 printk(KERN_WARNING "%s: warning: " 1017 "unknown hauppauge model #%d\n", 1018 dev->name, tv.model); 1019 break; 1020 } 1021 1022 printk(KERN_INFO "%s: hauppauge eeprom: model=%d\n", 1023 dev->name, tv.model); 1024 } 1025 1026 int cx23885_tuner_callback(void *priv, int component, int command, int arg) 1027 { 1028 struct cx23885_tsport *port = priv; 1029 struct cx23885_dev *dev = port->dev; 1030 u32 bitmask = 0; 1031 1032 if ((command == XC2028_RESET_CLK) || (command == XC2028_I2C_FLUSH)) 1033 return 0; 1034 1035 if (command != 0) { 1036 printk(KERN_ERR "%s(): Unknown command 0x%x.\n", 1037 __func__, command); 1038 return -EINVAL; 1039 } 1040 1041 switch (dev->board) { 1042 case CX23885_BOARD_HAUPPAUGE_HVR1400: 1043 case CX23885_BOARD_HAUPPAUGE_HVR1500: 1044 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 1045 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: 1046 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: 1047 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: 1048 case CX23885_BOARD_COMPRO_VIDEOMATE_E800: 1049 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200: 1050 /* Tuner Reset Command */ 1051 bitmask = 0x04; 1052 break; 1053 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP: 1054 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: 1055 /* Two identical tuners on two different i2c buses, 1056 * we need to reset the correct gpio. */ 1057 if (port->nr == 1) 1058 bitmask = 0x01; 1059 else if (port->nr == 2) 1060 bitmask = 0x04; 1061 break; 1062 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID: 1063 /* Tuner Reset Command */ 1064 bitmask = 0x02; 1065 break; 1066 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: 1067 altera_ci_tuner_reset(dev, port->nr); 1068 break; 1069 case CX23885_BOARD_AVERMEDIA_HC81R: 1070 /* XC3028L Reset Command */ 1071 bitmask = 1 << 2; 1072 break; 1073 } 1074 1075 if (bitmask) { 1076 /* Drive the tuner into reset and back out */ 1077 cx_clear(GP0_IO, bitmask); 1078 mdelay(200); 1079 cx_set(GP0_IO, bitmask); 1080 } 1081 1082 return 0; 1083 } 1084 1085 void cx23885_gpio_setup(struct cx23885_dev *dev) 1086 { 1087 switch (dev->board) { 1088 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1089 /* GPIO-0 cx24227 demodulator reset */ 1090 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */ 1091 break; 1092 case CX23885_BOARD_HAUPPAUGE_HVR1500: 1093 /* GPIO-0 cx24227 demodulator */ 1094 /* GPIO-2 xc3028 tuner */ 1095 1096 /* Put the parts into reset */ 1097 cx_set(GP0_IO, 0x00050000); 1098 cx_clear(GP0_IO, 0x00000005); 1099 msleep(5); 1100 1101 /* Bring the parts out of reset */ 1102 cx_set(GP0_IO, 0x00050005); 1103 break; 1104 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 1105 /* GPIO-0 cx24227 demodulator reset */ 1106 /* GPIO-2 xc5000 tuner reset */ 1107 cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */ 1108 break; 1109 case CX23885_BOARD_HAUPPAUGE_HVR1800: 1110 /* GPIO-0 656_CLK */ 1111 /* GPIO-1 656_D0 */ 1112 /* GPIO-2 8295A Reset */ 1113 /* GPIO-3-10 cx23417 data0-7 */ 1114 /* GPIO-11-14 cx23417 addr0-3 */ 1115 /* GPIO-15-18 cx23417 READY, CS, RD, WR */ 1116 /* GPIO-19 IR_RX */ 1117 1118 /* CX23417 GPIO's */ 1119 /* EIO15 Zilog Reset */ 1120 /* EIO14 S5H1409/CX24227 Reset */ 1121 mc417_gpio_enable(dev, GPIO_15 | GPIO_14, 1); 1122 1123 /* Put the demod into reset and protect the eeprom */ 1124 mc417_gpio_clear(dev, GPIO_15 | GPIO_14); 1125 mdelay(100); 1126 1127 /* Bring the demod and blaster out of reset */ 1128 mc417_gpio_set(dev, GPIO_15 | GPIO_14); 1129 mdelay(100); 1130 1131 /* Force the TDA8295A into reset and back */ 1132 cx23885_gpio_enable(dev, GPIO_2, 1); 1133 cx23885_gpio_set(dev, GPIO_2); 1134 mdelay(20); 1135 cx23885_gpio_clear(dev, GPIO_2); 1136 mdelay(20); 1137 cx23885_gpio_set(dev, GPIO_2); 1138 mdelay(20); 1139 break; 1140 case CX23885_BOARD_HAUPPAUGE_HVR1200: 1141 /* GPIO-0 tda10048 demodulator reset */ 1142 /* GPIO-2 tda18271 tuner reset */ 1143 1144 /* Put the parts into reset and back */ 1145 cx_set(GP0_IO, 0x00050000); 1146 mdelay(20); 1147 cx_clear(GP0_IO, 0x00000005); 1148 mdelay(20); 1149 cx_set(GP0_IO, 0x00050005); 1150 break; 1151 case CX23885_BOARD_HAUPPAUGE_HVR1700: 1152 /* GPIO-0 TDA10048 demodulator reset */ 1153 /* GPIO-2 TDA8295A Reset */ 1154 /* GPIO-3-10 cx23417 data0-7 */ 1155 /* GPIO-11-14 cx23417 addr0-3 */ 1156 /* GPIO-15-18 cx23417 READY, CS, RD, WR */ 1157 1158 /* The following GPIO's are on the interna AVCore (cx25840) */ 1159 /* GPIO-19 IR_RX */ 1160 /* GPIO-20 IR_TX 416/DVBT Select */ 1161 /* GPIO-21 IIS DAT */ 1162 /* GPIO-22 IIS WCLK */ 1163 /* GPIO-23 IIS BCLK */ 1164 1165 /* Put the parts into reset and back */ 1166 cx_set(GP0_IO, 0x00050000); 1167 mdelay(20); 1168 cx_clear(GP0_IO, 0x00000005); 1169 mdelay(20); 1170 cx_set(GP0_IO, 0x00050005); 1171 break; 1172 case CX23885_BOARD_HAUPPAUGE_HVR1400: 1173 /* GPIO-0 Dibcom7000p demodulator reset */ 1174 /* GPIO-2 xc3028L tuner reset */ 1175 /* GPIO-13 LED */ 1176 1177 /* Put the parts into reset and back */ 1178 cx_set(GP0_IO, 0x00050000); 1179 mdelay(20); 1180 cx_clear(GP0_IO, 0x00000005); 1181 mdelay(20); 1182 cx_set(GP0_IO, 0x00050005); 1183 break; 1184 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP: 1185 /* GPIO-0 xc5000 tuner reset i2c bus 0 */ 1186 /* GPIO-1 s5h1409 demod reset i2c bus 0 */ 1187 /* GPIO-2 xc5000 tuner reset i2c bus 1 */ 1188 /* GPIO-3 s5h1409 demod reset i2c bus 0 */ 1189 1190 /* Put the parts into reset and back */ 1191 cx_set(GP0_IO, 0x000f0000); 1192 mdelay(20); 1193 cx_clear(GP0_IO, 0x0000000f); 1194 mdelay(20); 1195 cx_set(GP0_IO, 0x000f000f); 1196 break; 1197 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: 1198 /* GPIO-0 portb xc3028 reset */ 1199 /* GPIO-1 portb zl10353 reset */ 1200 /* GPIO-2 portc xc3028 reset */ 1201 /* GPIO-3 portc zl10353 reset */ 1202 1203 /* Put the parts into reset and back */ 1204 cx_set(GP0_IO, 0x000f0000); 1205 mdelay(20); 1206 cx_clear(GP0_IO, 0x0000000f); 1207 mdelay(20); 1208 cx_set(GP0_IO, 0x000f000f); 1209 break; 1210 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: 1211 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: 1212 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: 1213 case CX23885_BOARD_COMPRO_VIDEOMATE_E800: 1214 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200: 1215 /* GPIO-2 xc3028 tuner reset */ 1216 1217 /* The following GPIO's are on the internal AVCore (cx25840) */ 1218 /* GPIO-? zl10353 demod reset */ 1219 1220 /* Put the parts into reset and back */ 1221 cx_set(GP0_IO, 0x00040000); 1222 mdelay(20); 1223 cx_clear(GP0_IO, 0x00000004); 1224 mdelay(20); 1225 cx_set(GP0_IO, 0x00040004); 1226 break; 1227 case CX23885_BOARD_TBS_6920: 1228 case CX23885_BOARD_PROF_8000: 1229 cx_write(MC417_CTL, 0x00000036); 1230 cx_write(MC417_OEN, 0x00001000); 1231 cx_set(MC417_RWD, 0x00000002); 1232 mdelay(200); 1233 cx_clear(MC417_RWD, 0x00000800); 1234 mdelay(200); 1235 cx_set(MC417_RWD, 0x00000800); 1236 mdelay(200); 1237 break; 1238 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 1239 /* GPIO-0 INTA from CiMax1 1240 GPIO-1 INTB from CiMax2 1241 GPIO-2 reset chips 1242 GPIO-3 to GPIO-10 data/addr for CA 1243 GPIO-11 ~CS0 to CiMax1 1244 GPIO-12 ~CS1 to CiMax2 1245 GPIO-13 ADL0 load LSB addr 1246 GPIO-14 ADL1 load MSB addr 1247 GPIO-15 ~RDY from CiMax 1248 GPIO-17 ~RD to CiMax 1249 GPIO-18 ~WR to CiMax 1250 */ 1251 cx_set(GP0_IO, 0x00040000); /* GPIO as out */ 1252 /* GPIO1 and GPIO2 as INTA and INTB from CiMaxes, reset low */ 1253 cx_clear(GP0_IO, 0x00030004); 1254 mdelay(100);/* reset delay */ 1255 cx_set(GP0_IO, 0x00040004); /* GPIO as out, reset high */ 1256 cx_write(MC417_CTL, 0x00000037);/* enable GPIO3-18 pins */ 1257 /* GPIO-15 IN as ~ACK, rest as OUT */ 1258 cx_write(MC417_OEN, 0x00001000); 1259 /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */ 1260 cx_write(MC417_RWD, 0x0000c300); 1261 /* enable irq */ 1262 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/ 1263 break; 1264 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1265 case CX23885_BOARD_HAUPPAUGE_HVR1275: 1266 case CX23885_BOARD_HAUPPAUGE_HVR1255: 1267 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 1268 case CX23885_BOARD_HAUPPAUGE_HVR1210: 1269 /* GPIO-5 RF Control: 0 = RF1 Terrestrial, 1 = RF2 Cable */ 1270 /* GPIO-6 I2C Gate which can isolate the demod from the bus */ 1271 /* GPIO-9 Demod reset */ 1272 1273 /* Put the parts into reset and back */ 1274 cx23885_gpio_enable(dev, GPIO_9 | GPIO_6 | GPIO_5, 1); 1275 cx23885_gpio_set(dev, GPIO_9 | GPIO_6 | GPIO_5); 1276 cx23885_gpio_clear(dev, GPIO_9); 1277 mdelay(20); 1278 cx23885_gpio_set(dev, GPIO_9); 1279 break; 1280 case CX23885_BOARD_MYGICA_X8506: 1281 case CX23885_BOARD_MAGICPRO_PROHDTVE2: 1282 case CX23885_BOARD_MYGICA_X8507: 1283 /* GPIO-0 (0)Analog / (1)Digital TV */ 1284 /* GPIO-1 reset XC5000 */ 1285 /* GPIO-2 demod reset */ 1286 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1 | GPIO_2, 1); 1287 cx23885_gpio_clear(dev, GPIO_1 | GPIO_2); 1288 mdelay(100); 1289 cx23885_gpio_set(dev, GPIO_0 | GPIO_1 | GPIO_2); 1290 mdelay(100); 1291 break; 1292 case CX23885_BOARD_MYGICA_X8558PRO: 1293 /* GPIO-0 reset first ATBM8830 */ 1294 /* GPIO-1 reset second ATBM8830 */ 1295 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1, 1); 1296 cx23885_gpio_clear(dev, GPIO_0 | GPIO_1); 1297 mdelay(100); 1298 cx23885_gpio_set(dev, GPIO_0 | GPIO_1); 1299 mdelay(100); 1300 break; 1301 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1302 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1303 /* GPIO-0 656_CLK */ 1304 /* GPIO-1 656_D0 */ 1305 /* GPIO-2 Wake# */ 1306 /* GPIO-3-10 cx23417 data0-7 */ 1307 /* GPIO-11-14 cx23417 addr0-3 */ 1308 /* GPIO-15-18 cx23417 READY, CS, RD, WR */ 1309 /* GPIO-19 IR_RX */ 1310 /* GPIO-20 C_IR_TX */ 1311 /* GPIO-21 I2S DAT */ 1312 /* GPIO-22 I2S WCLK */ 1313 /* GPIO-23 I2S BCLK */ 1314 /* ALT GPIO: EXP GPIO LATCH */ 1315 1316 /* CX23417 GPIO's */ 1317 /* GPIO-14 S5H1411/CX24228 Reset */ 1318 /* GPIO-13 EEPROM write protect */ 1319 mc417_gpio_enable(dev, GPIO_14 | GPIO_13, 1); 1320 1321 /* Put the demod into reset and protect the eeprom */ 1322 mc417_gpio_clear(dev, GPIO_14 | GPIO_13); 1323 mdelay(100); 1324 1325 /* Bring the demod out of reset */ 1326 mc417_gpio_set(dev, GPIO_14); 1327 mdelay(100); 1328 1329 /* CX24228 GPIO */ 1330 /* Connected to IF / Mux */ 1331 break; 1332 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID: 1333 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */ 1334 break; 1335 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: 1336 /* GPIO-0 ~INT in 1337 GPIO-1 TMS out 1338 GPIO-2 ~reset chips out 1339 GPIO-3 to GPIO-10 data/addr for CA in/out 1340 GPIO-11 ~CS out 1341 GPIO-12 ADDR out 1342 GPIO-13 ~WR out 1343 GPIO-14 ~RD out 1344 GPIO-15 ~RDY in 1345 GPIO-16 TCK out 1346 GPIO-17 TDO in 1347 GPIO-18 TDI out 1348 */ 1349 cx_set(GP0_IO, 0x00060000); /* GPIO-1,2 as out */ 1350 /* GPIO-0 as INT, reset & TMS low */ 1351 cx_clear(GP0_IO, 0x00010006); 1352 mdelay(100);/* reset delay */ 1353 cx_set(GP0_IO, 0x00000004); /* reset high */ 1354 cx_write(MC417_CTL, 0x00000037);/* enable GPIO-3..18 pins */ 1355 /* GPIO-17 is TDO in, GPIO-15 is ~RDY in, rest is out */ 1356 cx_write(MC417_OEN, 0x00005000); 1357 /* ~RD, ~WR high; ADDR low; ~CS high */ 1358 cx_write(MC417_RWD, 0x00000d00); 1359 /* enable irq */ 1360 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/ 1361 break; 1362 case CX23885_BOARD_HAUPPAUGE_HVR4400: 1363 /* GPIO-8 tda10071 demod reset */ 1364 1365 /* Put the parts into reset and back */ 1366 cx23885_gpio_enable(dev, GPIO_8, 1); 1367 cx23885_gpio_clear(dev, GPIO_8); 1368 mdelay(100); 1369 cx23885_gpio_set(dev, GPIO_8); 1370 mdelay(100); 1371 break; 1372 case CX23885_BOARD_AVERMEDIA_HC81R: 1373 cx_clear(MC417_CTL, 1); 1374 /* GPIO-0,1,2 setup direction as output */ 1375 cx_set(GP0_IO, 0x00070000); 1376 mdelay(10); 1377 /* AF9013 demod reset */ 1378 cx_set(GP0_IO, 0x00010001); 1379 mdelay(10); 1380 cx_clear(GP0_IO, 0x00010001); 1381 mdelay(10); 1382 cx_set(GP0_IO, 0x00010001); 1383 mdelay(10); 1384 /* demod tune? */ 1385 cx_clear(GP0_IO, 0x00030003); 1386 mdelay(10); 1387 cx_set(GP0_IO, 0x00020002); 1388 mdelay(10); 1389 cx_set(GP0_IO, 0x00010001); 1390 mdelay(10); 1391 cx_clear(GP0_IO, 0x00020002); 1392 /* XC3028L tuner reset */ 1393 cx_set(GP0_IO, 0x00040004); 1394 cx_clear(GP0_IO, 0x00040004); 1395 cx_set(GP0_IO, 0x00040004); 1396 mdelay(60); 1397 break; 1398 } 1399 } 1400 1401 int cx23885_ir_init(struct cx23885_dev *dev) 1402 { 1403 static struct v4l2_subdev_io_pin_config ir_rxtx_pin_cfg[] = { 1404 { 1405 .flags = V4L2_SUBDEV_IO_PIN_INPUT, 1406 .pin = CX23885_PIN_IR_RX_GPIO19, 1407 .function = CX23885_PAD_IR_RX, 1408 .value = 0, 1409 .strength = CX25840_PIN_DRIVE_MEDIUM, 1410 }, { 1411 .flags = V4L2_SUBDEV_IO_PIN_OUTPUT, 1412 .pin = CX23885_PIN_IR_TX_GPIO20, 1413 .function = CX23885_PAD_IR_TX, 1414 .value = 0, 1415 .strength = CX25840_PIN_DRIVE_MEDIUM, 1416 } 1417 }; 1418 const size_t ir_rxtx_pin_cfg_count = ARRAY_SIZE(ir_rxtx_pin_cfg); 1419 1420 static struct v4l2_subdev_io_pin_config ir_rx_pin_cfg[] = { 1421 { 1422 .flags = V4L2_SUBDEV_IO_PIN_INPUT, 1423 .pin = CX23885_PIN_IR_RX_GPIO19, 1424 .function = CX23885_PAD_IR_RX, 1425 .value = 0, 1426 .strength = CX25840_PIN_DRIVE_MEDIUM, 1427 } 1428 }; 1429 const size_t ir_rx_pin_cfg_count = ARRAY_SIZE(ir_rx_pin_cfg); 1430 1431 struct v4l2_subdev_ir_parameters params; 1432 int ret = 0; 1433 switch (dev->board) { 1434 case CX23885_BOARD_HAUPPAUGE_HVR1500: 1435 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 1436 case CX23885_BOARD_HAUPPAUGE_HVR1800: 1437 case CX23885_BOARD_HAUPPAUGE_HVR1200: 1438 case CX23885_BOARD_HAUPPAUGE_HVR1400: 1439 case CX23885_BOARD_HAUPPAUGE_HVR1275: 1440 case CX23885_BOARD_HAUPPAUGE_HVR1255: 1441 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 1442 case CX23885_BOARD_HAUPPAUGE_HVR1210: 1443 /* FIXME: Implement me */ 1444 break; 1445 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1446 ret = cx23888_ir_probe(dev); 1447 if (ret) 1448 break; 1449 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR); 1450 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config, 1451 ir_rx_pin_cfg_count, ir_rx_pin_cfg); 1452 break; 1453 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1454 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1455 ret = cx23888_ir_probe(dev); 1456 if (ret) 1457 break; 1458 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR); 1459 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config, 1460 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg); 1461 /* 1462 * For these boards we need to invert the Tx output via the 1463 * IR controller to have the LED off while idle 1464 */ 1465 v4l2_subdev_call(dev->sd_ir, ir, tx_g_parameters, ¶ms); 1466 params.enable = false; 1467 params.shutdown = false; 1468 params.invert_level = true; 1469 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, ¶ms); 1470 params.shutdown = true; 1471 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, ¶ms); 1472 break; 1473 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 1474 case CX23885_BOARD_TEVII_S470: 1475 case CX23885_BOARD_MYGICA_X8507: 1476 if (!enable_885_ir) 1477 break; 1478 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE); 1479 if (dev->sd_ir == NULL) { 1480 ret = -ENODEV; 1481 break; 1482 } 1483 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config, 1484 ir_rx_pin_cfg_count, ir_rx_pin_cfg); 1485 break; 1486 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1487 if (!enable_885_ir) 1488 break; 1489 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE); 1490 if (dev->sd_ir == NULL) { 1491 ret = -ENODEV; 1492 break; 1493 } 1494 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config, 1495 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg); 1496 break; 1497 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: 1498 request_module("ir-kbd-i2c"); 1499 break; 1500 } 1501 1502 return ret; 1503 } 1504 1505 void cx23885_ir_fini(struct cx23885_dev *dev) 1506 { 1507 switch (dev->board) { 1508 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1509 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1510 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1511 cx23885_irq_remove(dev, PCI_MSK_IR); 1512 cx23888_ir_remove(dev); 1513 dev->sd_ir = NULL; 1514 break; 1515 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 1516 case CX23885_BOARD_TEVII_S470: 1517 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1518 case CX23885_BOARD_MYGICA_X8507: 1519 cx23885_irq_remove(dev, PCI_MSK_AV_CORE); 1520 /* sd_ir is a duplicate pointer to the AV Core, just clear it */ 1521 dev->sd_ir = NULL; 1522 break; 1523 } 1524 } 1525 1526 static int netup_jtag_io(void *device, int tms, int tdi, int read_tdo) 1527 { 1528 int data; 1529 int tdo = 0; 1530 struct cx23885_dev *dev = (struct cx23885_dev *)device; 1531 /*TMS*/ 1532 data = ((cx_read(GP0_IO)) & (~0x00000002)); 1533 data |= (tms ? 0x00020002 : 0x00020000); 1534 cx_write(GP0_IO, data); 1535 1536 /*TDI*/ 1537 data = ((cx_read(MC417_RWD)) & (~0x0000a000)); 1538 data |= (tdi ? 0x00008000 : 0); 1539 cx_write(MC417_RWD, data); 1540 if (read_tdo) 1541 tdo = (data & 0x00004000) ? 1 : 0; /*TDO*/ 1542 1543 cx_write(MC417_RWD, data | 0x00002000); 1544 udelay(1); 1545 /*TCK*/ 1546 cx_write(MC417_RWD, data); 1547 1548 return tdo; 1549 } 1550 1551 void cx23885_ir_pci_int_enable(struct cx23885_dev *dev) 1552 { 1553 switch (dev->board) { 1554 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1555 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1556 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1557 if (dev->sd_ir) 1558 cx23885_irq_add_enable(dev, PCI_MSK_IR); 1559 break; 1560 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 1561 case CX23885_BOARD_TEVII_S470: 1562 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1563 case CX23885_BOARD_MYGICA_X8507: 1564 if (dev->sd_ir) 1565 cx23885_irq_add_enable(dev, PCI_MSK_AV_CORE); 1566 break; 1567 } 1568 } 1569 1570 void cx23885_card_setup(struct cx23885_dev *dev) 1571 { 1572 struct cx23885_tsport *ts1 = &dev->ts1; 1573 struct cx23885_tsport *ts2 = &dev->ts2; 1574 1575 static u8 eeprom[256]; 1576 1577 if (dev->i2c_bus[0].i2c_rc == 0) { 1578 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1; 1579 tveeprom_read(&dev->i2c_bus[0].i2c_client, 1580 eeprom, sizeof(eeprom)); 1581 } 1582 1583 switch (dev->board) { 1584 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1585 if (dev->i2c_bus[0].i2c_rc == 0) { 1586 if (eeprom[0x80] != 0x84) 1587 hauppauge_eeprom(dev, eeprom+0xc0); 1588 else 1589 hauppauge_eeprom(dev, eeprom+0x80); 1590 } 1591 break; 1592 case CX23885_BOARD_HAUPPAUGE_HVR1500: 1593 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 1594 case CX23885_BOARD_HAUPPAUGE_HVR1400: 1595 if (dev->i2c_bus[0].i2c_rc == 0) 1596 hauppauge_eeprom(dev, eeprom+0x80); 1597 break; 1598 case CX23885_BOARD_HAUPPAUGE_HVR1800: 1599 case CX23885_BOARD_HAUPPAUGE_HVR1800lp: 1600 case CX23885_BOARD_HAUPPAUGE_HVR1200: 1601 case CX23885_BOARD_HAUPPAUGE_HVR1700: 1602 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1603 case CX23885_BOARD_HAUPPAUGE_HVR1275: 1604 case CX23885_BOARD_HAUPPAUGE_HVR1255: 1605 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 1606 case CX23885_BOARD_HAUPPAUGE_HVR1210: 1607 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1608 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1609 case CX23885_BOARD_HAUPPAUGE_HVR4400: 1610 if (dev->i2c_bus[0].i2c_rc == 0) 1611 hauppauge_eeprom(dev, eeprom+0xc0); 1612 break; 1613 } 1614 1615 switch (dev->board) { 1616 case CX23885_BOARD_AVERMEDIA_HC81R: 1617 /* Defaults for VID B */ 1618 ts1->gen_ctrl_val = 0x4; /* Parallel */ 1619 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1620 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1621 /* Defaults for VID C */ 1622 /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */ 1623 ts2->gen_ctrl_val = 0x10e; 1624 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1625 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1626 break; 1627 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP: 1628 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: 1629 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1630 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1631 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1632 /* break omitted intentionally */ 1633 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP: 1634 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1635 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1636 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1637 break; 1638 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1639 case CX23885_BOARD_HAUPPAUGE_HVR1800: 1640 /* Defaults for VID B - Analog encoder */ 1641 /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */ 1642 ts1->gen_ctrl_val = 0x10e; 1643 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1644 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1645 1646 /* APB_TSVALERR_POL (active low)*/ 1647 ts1->vld_misc_val = 0x2000; 1648 ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc); 1649 cx_write(0x130184, 0xc); 1650 1651 /* Defaults for VID C */ 1652 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1653 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1654 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1655 break; 1656 case CX23885_BOARD_TBS_6920: 1657 ts1->gen_ctrl_val = 0x4; /* Parallel */ 1658 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1659 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1660 break; 1661 case CX23885_BOARD_TEVII_S470: 1662 case CX23885_BOARD_TEVII_S471: 1663 case CX23885_BOARD_DVBWORLD_2005: 1664 case CX23885_BOARD_PROF_8000: 1665 ts1->gen_ctrl_val = 0x5; /* Parallel */ 1666 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1667 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1668 break; 1669 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 1670 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: 1671 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 1672 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1673 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1674 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1675 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1676 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1677 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1678 break; 1679 case CX23885_BOARD_MYGICA_X8506: 1680 case CX23885_BOARD_MAGICPRO_PROHDTVE2: 1681 case CX23885_BOARD_MYGICA_X8507: 1682 ts1->gen_ctrl_val = 0x5; /* Parallel */ 1683 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1684 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1685 break; 1686 case CX23885_BOARD_MYGICA_X8558PRO: 1687 ts1->gen_ctrl_val = 0x5; /* Parallel */ 1688 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1689 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1690 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1691 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1692 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1693 break; 1694 case CX23885_BOARD_HAUPPAUGE_HVR4400: 1695 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1696 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1697 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1698 break; 1699 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1700 case CX23885_BOARD_HAUPPAUGE_HVR1500: 1701 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 1702 case CX23885_BOARD_HAUPPAUGE_HVR1800lp: 1703 case CX23885_BOARD_HAUPPAUGE_HVR1200: 1704 case CX23885_BOARD_HAUPPAUGE_HVR1700: 1705 case CX23885_BOARD_HAUPPAUGE_HVR1400: 1706 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: 1707 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: 1708 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: 1709 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1710 case CX23885_BOARD_HAUPPAUGE_HVR1275: 1711 case CX23885_BOARD_HAUPPAUGE_HVR1255: 1712 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 1713 case CX23885_BOARD_HAUPPAUGE_HVR1210: 1714 case CX23885_BOARD_COMPRO_VIDEOMATE_E800: 1715 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1716 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID: 1717 default: 1718 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1719 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1720 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1721 } 1722 1723 /* Certain boards support analog, or require the avcore to be 1724 * loaded, ensure this happens. 1725 */ 1726 switch (dev->board) { 1727 case CX23885_BOARD_TEVII_S470: 1728 /* Currently only enabled for the integrated IR controller */ 1729 if (!enable_885_ir) 1730 break; 1731 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1732 case CX23885_BOARD_HAUPPAUGE_HVR1800: 1733 case CX23885_BOARD_HAUPPAUGE_HVR1800lp: 1734 case CX23885_BOARD_HAUPPAUGE_HVR1700: 1735 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: 1736 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: 1737 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: 1738 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 1739 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: 1740 case CX23885_BOARD_COMPRO_VIDEOMATE_E800: 1741 case CX23885_BOARD_HAUPPAUGE_HVR1255: 1742 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: 1743 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1744 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1745 case CX23885_BOARD_MYGICA_X8506: 1746 case CX23885_BOARD_MAGICPRO_PROHDTVE2: 1747 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1748 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200: 1749 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID: 1750 case CX23885_BOARD_HAUPPAUGE_HVR1500: 1751 case CX23885_BOARD_MPX885: 1752 case CX23885_BOARD_MYGICA_X8507: 1753 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 1754 case CX23885_BOARD_AVERMEDIA_HC81R: 1755 dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev, 1756 &dev->i2c_bus[2].i2c_adap, 1757 "cx25840", 0x88 >> 1, NULL); 1758 if (dev->sd_cx25840) { 1759 dev->sd_cx25840->grp_id = CX23885_HW_AV_CORE; 1760 v4l2_subdev_call(dev->sd_cx25840, core, load_fw); 1761 } 1762 break; 1763 } 1764 1765 /* AUX-PLL 27MHz CLK */ 1766 switch (dev->board) { 1767 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 1768 netup_initialize(dev); 1769 break; 1770 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: { 1771 int ret; 1772 const struct firmware *fw; 1773 const char *filename = "dvb-netup-altera-01.fw"; 1774 char *action = "configure"; 1775 static struct netup_card_info cinfo; 1776 struct altera_config netup_config = { 1777 .dev = dev, 1778 .action = action, 1779 .jtag_io = netup_jtag_io, 1780 }; 1781 1782 netup_initialize(dev); 1783 1784 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo); 1785 if (netup_card_rev) 1786 cinfo.rev = netup_card_rev; 1787 1788 switch (cinfo.rev) { 1789 case 0x4: 1790 filename = "dvb-netup-altera-04.fw"; 1791 break; 1792 default: 1793 filename = "dvb-netup-altera-01.fw"; 1794 break; 1795 } 1796 printk(KERN_INFO "NetUP card rev=0x%x fw_filename=%s\n", 1797 cinfo.rev, filename); 1798 1799 ret = request_firmware(&fw, filename, &dev->pci->dev); 1800 if (ret != 0) 1801 printk(KERN_ERR "did not find the firmware file. (%s) " 1802 "Please see linux/Documentation/dvb/ for more details " 1803 "on firmware-problems.", filename); 1804 else 1805 altera_init(&netup_config, fw); 1806 1807 release_firmware(fw); 1808 break; 1809 } 1810 } 1811 } 1812 1813 /* ------------------------------------------------------------------ */ 1814