1 /* 2 * 3 * Support for a cx23417 mpeg encoder via cx23885 host port. 4 * 5 * (c) 2004 Jelle Foks <jelle@foks.us> 6 * (c) 2004 Gerd Knorr <kraxel@bytesex.org> 7 * (c) 2008 Steven Toth <stoth@linuxtv.org> 8 * - CX23885/7/8 support 9 * 10 * Includes parts from the ivtv driver <http://sourceforge.net/projects/ivtv/> 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 */ 22 23 #include "cx23885.h" 24 #include "cx23885-ioctl.h" 25 26 #include <linux/module.h> 27 #include <linux/moduleparam.h> 28 #include <linux/init.h> 29 #include <linux/fs.h> 30 #include <linux/delay.h> 31 #include <linux/device.h> 32 #include <linux/firmware.h> 33 #include <linux/slab.h> 34 #include <media/v4l2-common.h> 35 #include <media/v4l2-ioctl.h> 36 #include <media/drv-intf/cx2341x.h> 37 38 #define CX23885_FIRM_IMAGE_SIZE 376836 39 #define CX23885_FIRM_IMAGE_NAME "v4l-cx23885-enc.fw" 40 41 static unsigned int mpegbufs = 32; 42 module_param(mpegbufs, int, 0644); 43 MODULE_PARM_DESC(mpegbufs, "number of mpeg buffers, range 2-32"); 44 static unsigned int mpeglines = 32; 45 module_param(mpeglines, int, 0644); 46 MODULE_PARM_DESC(mpeglines, "number of lines in an MPEG buffer, range 2-32"); 47 static unsigned int mpeglinesize = 512; 48 module_param(mpeglinesize, int, 0644); 49 MODULE_PARM_DESC(mpeglinesize, 50 "number of bytes in each line of an MPEG buffer, range 512-1024"); 51 52 static unsigned int v4l_debug; 53 module_param(v4l_debug, int, 0644); 54 MODULE_PARM_DESC(v4l_debug, "enable V4L debug messages"); 55 56 #define dprintk(level, fmt, arg...)\ 57 do { if (v4l_debug >= level) \ 58 printk(KERN_DEBUG pr_fmt("%s: 417:" fmt), \ 59 __func__, ##arg); \ 60 } while (0) 61 62 static struct cx23885_tvnorm cx23885_tvnorms[] = { 63 { 64 .name = "NTSC-M", 65 .id = V4L2_STD_NTSC_M, 66 }, { 67 .name = "NTSC-JP", 68 .id = V4L2_STD_NTSC_M_JP, 69 }, { 70 .name = "PAL-BG", 71 .id = V4L2_STD_PAL_BG, 72 }, { 73 .name = "PAL-DK", 74 .id = V4L2_STD_PAL_DK, 75 }, { 76 .name = "PAL-I", 77 .id = V4L2_STD_PAL_I, 78 }, { 79 .name = "PAL-M", 80 .id = V4L2_STD_PAL_M, 81 }, { 82 .name = "PAL-N", 83 .id = V4L2_STD_PAL_N, 84 }, { 85 .name = "PAL-Nc", 86 .id = V4L2_STD_PAL_Nc, 87 }, { 88 .name = "PAL-60", 89 .id = V4L2_STD_PAL_60, 90 }, { 91 .name = "SECAM-L", 92 .id = V4L2_STD_SECAM_L, 93 }, { 94 .name = "SECAM-DK", 95 .id = V4L2_STD_SECAM_DK, 96 } 97 }; 98 99 /* ------------------------------------------------------------------ */ 100 enum cx23885_capture_type { 101 CX23885_MPEG_CAPTURE, 102 CX23885_RAW_CAPTURE, 103 CX23885_RAW_PASSTHRU_CAPTURE 104 }; 105 enum cx23885_capture_bits { 106 CX23885_RAW_BITS_NONE = 0x00, 107 CX23885_RAW_BITS_YUV_CAPTURE = 0x01, 108 CX23885_RAW_BITS_PCM_CAPTURE = 0x02, 109 CX23885_RAW_BITS_VBI_CAPTURE = 0x04, 110 CX23885_RAW_BITS_PASSTHRU_CAPTURE = 0x08, 111 CX23885_RAW_BITS_TO_HOST_CAPTURE = 0x10 112 }; 113 enum cx23885_capture_end { 114 CX23885_END_AT_GOP, /* stop at the end of gop, generate irq */ 115 CX23885_END_NOW, /* stop immediately, no irq */ 116 }; 117 enum cx23885_framerate { 118 CX23885_FRAMERATE_NTSC_30, /* NTSC: 30fps */ 119 CX23885_FRAMERATE_PAL_25 /* PAL: 25fps */ 120 }; 121 enum cx23885_stream_port { 122 CX23885_OUTPUT_PORT_MEMORY, 123 CX23885_OUTPUT_PORT_STREAMING, 124 CX23885_OUTPUT_PORT_SERIAL 125 }; 126 enum cx23885_data_xfer_status { 127 CX23885_MORE_BUFFERS_FOLLOW, 128 CX23885_LAST_BUFFER, 129 }; 130 enum cx23885_picture_mask { 131 CX23885_PICTURE_MASK_NONE, 132 CX23885_PICTURE_MASK_I_FRAMES, 133 CX23885_PICTURE_MASK_I_P_FRAMES = 0x3, 134 CX23885_PICTURE_MASK_ALL_FRAMES = 0x7, 135 }; 136 enum cx23885_vbi_mode_bits { 137 CX23885_VBI_BITS_SLICED, 138 CX23885_VBI_BITS_RAW, 139 }; 140 enum cx23885_vbi_insertion_bits { 141 CX23885_VBI_BITS_INSERT_IN_XTENSION_USR_DATA, 142 CX23885_VBI_BITS_INSERT_IN_PRIVATE_PACKETS = 0x1 << 1, 143 CX23885_VBI_BITS_SEPARATE_STREAM = 0x2 << 1, 144 CX23885_VBI_BITS_SEPARATE_STREAM_USR_DATA = 0x4 << 1, 145 CX23885_VBI_BITS_SEPARATE_STREAM_PRV_DATA = 0x5 << 1, 146 }; 147 enum cx23885_dma_unit { 148 CX23885_DMA_BYTES, 149 CX23885_DMA_FRAMES, 150 }; 151 enum cx23885_dma_transfer_status_bits { 152 CX23885_DMA_TRANSFER_BITS_DONE = 0x01, 153 CX23885_DMA_TRANSFER_BITS_ERROR = 0x04, 154 CX23885_DMA_TRANSFER_BITS_LL_ERROR = 0x10, 155 }; 156 enum cx23885_pause { 157 CX23885_PAUSE_ENCODING, 158 CX23885_RESUME_ENCODING, 159 }; 160 enum cx23885_copyright { 161 CX23885_COPYRIGHT_OFF, 162 CX23885_COPYRIGHT_ON, 163 }; 164 enum cx23885_notification_type { 165 CX23885_NOTIFICATION_REFRESH, 166 }; 167 enum cx23885_notification_status { 168 CX23885_NOTIFICATION_OFF, 169 CX23885_NOTIFICATION_ON, 170 }; 171 enum cx23885_notification_mailbox { 172 CX23885_NOTIFICATION_NO_MAILBOX = -1, 173 }; 174 enum cx23885_field1_lines { 175 CX23885_FIELD1_SAA7114 = 0x00EF, /* 239 */ 176 CX23885_FIELD1_SAA7115 = 0x00F0, /* 240 */ 177 CX23885_FIELD1_MICRONAS = 0x0105, /* 261 */ 178 }; 179 enum cx23885_field2_lines { 180 CX23885_FIELD2_SAA7114 = 0x00EF, /* 239 */ 181 CX23885_FIELD2_SAA7115 = 0x00F0, /* 240 */ 182 CX23885_FIELD2_MICRONAS = 0x0106, /* 262 */ 183 }; 184 enum cx23885_custom_data_type { 185 CX23885_CUSTOM_EXTENSION_USR_DATA, 186 CX23885_CUSTOM_PRIVATE_PACKET, 187 }; 188 enum cx23885_mute { 189 CX23885_UNMUTE, 190 CX23885_MUTE, 191 }; 192 enum cx23885_mute_video_mask { 193 CX23885_MUTE_VIDEO_V_MASK = 0x0000FF00, 194 CX23885_MUTE_VIDEO_U_MASK = 0x00FF0000, 195 CX23885_MUTE_VIDEO_Y_MASK = 0xFF000000, 196 }; 197 enum cx23885_mute_video_shift { 198 CX23885_MUTE_VIDEO_V_SHIFT = 8, 199 CX23885_MUTE_VIDEO_U_SHIFT = 16, 200 CX23885_MUTE_VIDEO_Y_SHIFT = 24, 201 }; 202 203 /* defines below are from ivtv-driver.h */ 204 #define IVTV_CMD_HW_BLOCKS_RST 0xFFFFFFFF 205 206 /* Firmware API commands */ 207 #define IVTV_API_STD_TIMEOUT 500 208 209 /* Registers */ 210 /* IVTV_REG_OFFSET */ 211 #define IVTV_REG_ENC_SDRAM_REFRESH (0x07F8) 212 #define IVTV_REG_ENC_SDRAM_PRECHARGE (0x07FC) 213 #define IVTV_REG_SPU (0x9050) 214 #define IVTV_REG_HW_BLOCKS (0x9054) 215 #define IVTV_REG_VPU (0x9058) 216 #define IVTV_REG_APU (0xA064) 217 218 /**** Bit definitions for MC417_RWD and MC417_OEN registers *** 219 bits 31-16 220 +-----------+ 221 | Reserved | 222 +-----------+ 223 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 224 +-------+-------+-------+-------+-------+-------+-------+-------+ 225 | MIWR# | MIRD# | MICS# |MIRDY# |MIADDR3|MIADDR2|MIADDR1|MIADDR0| 226 +-------+-------+-------+-------+-------+-------+-------+-------+ 227 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 228 +-------+-------+-------+-------+-------+-------+-------+-------+ 229 |MIDATA7|MIDATA6|MIDATA5|MIDATA4|MIDATA3|MIDATA2|MIDATA1|MIDATA0| 230 +-------+-------+-------+-------+-------+-------+-------+-------+ 231 ***/ 232 #define MC417_MIWR 0x8000 233 #define MC417_MIRD 0x4000 234 #define MC417_MICS 0x2000 235 #define MC417_MIRDY 0x1000 236 #define MC417_MIADDR 0x0F00 237 #define MC417_MIDATA 0x00FF 238 239 /* MIADDR* nibble definitions */ 240 #define MCI_MEMORY_DATA_BYTE0 0x000 241 #define MCI_MEMORY_DATA_BYTE1 0x100 242 #define MCI_MEMORY_DATA_BYTE2 0x200 243 #define MCI_MEMORY_DATA_BYTE3 0x300 244 #define MCI_MEMORY_ADDRESS_BYTE2 0x400 245 #define MCI_MEMORY_ADDRESS_BYTE1 0x500 246 #define MCI_MEMORY_ADDRESS_BYTE0 0x600 247 #define MCI_REGISTER_DATA_BYTE0 0x800 248 #define MCI_REGISTER_DATA_BYTE1 0x900 249 #define MCI_REGISTER_DATA_BYTE2 0xA00 250 #define MCI_REGISTER_DATA_BYTE3 0xB00 251 #define MCI_REGISTER_ADDRESS_BYTE0 0xC00 252 #define MCI_REGISTER_ADDRESS_BYTE1 0xD00 253 #define MCI_REGISTER_MODE 0xE00 254 255 /* Read and write modes */ 256 #define MCI_MODE_REGISTER_READ 0 257 #define MCI_MODE_REGISTER_WRITE 1 258 #define MCI_MODE_MEMORY_READ 0 259 #define MCI_MODE_MEMORY_WRITE 0x40 260 261 /*** Bit definitions for MC417_CTL register **** 262 bits 31-6 bits 5-4 bit 3 bits 2-1 Bit 0 263 +--------+-------------+--------+--------------+------------+ 264 |Reserved|MC417_SPD_CTL|Reserved|MC417_GPIO_SEL|UART_GPIO_EN| 265 +--------+-------------+--------+--------------+------------+ 266 ***/ 267 #define MC417_SPD_CTL(x) (((x) << 4) & 0x00000030) 268 #define MC417_GPIO_SEL(x) (((x) << 1) & 0x00000006) 269 #define MC417_UART_GPIO_EN 0x00000001 270 271 /* Values for speed control */ 272 #define MC417_SPD_CTL_SLOW 0x1 273 #define MC417_SPD_CTL_MEDIUM 0x0 274 #define MC417_SPD_CTL_FAST 0x3 /* b'1x, but we use b'11 */ 275 276 /* Values for GPIO select */ 277 #define MC417_GPIO_SEL_GPIO3 0x3 278 #define MC417_GPIO_SEL_GPIO2 0x2 279 #define MC417_GPIO_SEL_GPIO1 0x1 280 #define MC417_GPIO_SEL_GPIO0 0x0 281 282 void cx23885_mc417_init(struct cx23885_dev *dev) 283 { 284 u32 regval; 285 286 dprintk(2, "%s()\n", __func__); 287 288 /* Configure MC417_CTL register to defaults. */ 289 regval = MC417_SPD_CTL(MC417_SPD_CTL_FAST) | 290 MC417_GPIO_SEL(MC417_GPIO_SEL_GPIO3) | 291 MC417_UART_GPIO_EN; 292 cx_write(MC417_CTL, regval); 293 294 /* Configure MC417_OEN to defaults. */ 295 regval = MC417_MIRDY; 296 cx_write(MC417_OEN, regval); 297 298 /* Configure MC417_RWD to defaults. */ 299 regval = MC417_MIWR | MC417_MIRD | MC417_MICS; 300 cx_write(MC417_RWD, regval); 301 } 302 303 static int mc417_wait_ready(struct cx23885_dev *dev) 304 { 305 u32 mi_ready; 306 unsigned long timeout = jiffies + msecs_to_jiffies(1); 307 308 for (;;) { 309 mi_ready = cx_read(MC417_RWD) & MC417_MIRDY; 310 if (mi_ready != 0) 311 return 0; 312 if (time_after(jiffies, timeout)) 313 return -1; 314 udelay(1); 315 } 316 } 317 318 int mc417_register_write(struct cx23885_dev *dev, u16 address, u32 value) 319 { 320 u32 regval; 321 322 /* Enable MC417 GPIO outputs except for MC417_MIRDY, 323 * which is an input. 324 */ 325 cx_write(MC417_OEN, MC417_MIRDY); 326 327 /* Write data byte 0 */ 328 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0 | 329 (value & 0x000000FF); 330 cx_write(MC417_RWD, regval); 331 332 /* Transition CS/WR to effect write transaction across bus. */ 333 regval |= MC417_MICS | MC417_MIWR; 334 cx_write(MC417_RWD, regval); 335 336 /* Write data byte 1 */ 337 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1 | 338 ((value >> 8) & 0x000000FF); 339 cx_write(MC417_RWD, regval); 340 regval |= MC417_MICS | MC417_MIWR; 341 cx_write(MC417_RWD, regval); 342 343 /* Write data byte 2 */ 344 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2 | 345 ((value >> 16) & 0x000000FF); 346 cx_write(MC417_RWD, regval); 347 regval |= MC417_MICS | MC417_MIWR; 348 cx_write(MC417_RWD, regval); 349 350 /* Write data byte 3 */ 351 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3 | 352 ((value >> 24) & 0x000000FF); 353 cx_write(MC417_RWD, regval); 354 regval |= MC417_MICS | MC417_MIWR; 355 cx_write(MC417_RWD, regval); 356 357 /* Write address byte 0 */ 358 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE0 | 359 (address & 0xFF); 360 cx_write(MC417_RWD, regval); 361 regval |= MC417_MICS | MC417_MIWR; 362 cx_write(MC417_RWD, regval); 363 364 /* Write address byte 1 */ 365 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE1 | 366 ((address >> 8) & 0xFF); 367 cx_write(MC417_RWD, regval); 368 regval |= MC417_MICS | MC417_MIWR; 369 cx_write(MC417_RWD, regval); 370 371 /* Indicate that this is a write. */ 372 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_MODE | 373 MCI_MODE_REGISTER_WRITE; 374 cx_write(MC417_RWD, regval); 375 regval |= MC417_MICS | MC417_MIWR; 376 cx_write(MC417_RWD, regval); 377 378 /* Wait for the trans to complete (MC417_MIRDY asserted). */ 379 return mc417_wait_ready(dev); 380 } 381 382 int mc417_register_read(struct cx23885_dev *dev, u16 address, u32 *value) 383 { 384 int retval; 385 u32 regval; 386 u32 tempval; 387 u32 dataval; 388 389 /* Enable MC417 GPIO outputs except for MC417_MIRDY, 390 * which is an input. 391 */ 392 cx_write(MC417_OEN, MC417_MIRDY); 393 394 /* Write address byte 0 */ 395 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE0 | 396 ((address & 0x00FF)); 397 cx_write(MC417_RWD, regval); 398 regval |= MC417_MICS | MC417_MIWR; 399 cx_write(MC417_RWD, regval); 400 401 /* Write address byte 1 */ 402 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE1 | 403 ((address >> 8) & 0xFF); 404 cx_write(MC417_RWD, regval); 405 regval |= MC417_MICS | MC417_MIWR; 406 cx_write(MC417_RWD, regval); 407 408 /* Indicate that this is a register read. */ 409 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_MODE | 410 MCI_MODE_REGISTER_READ; 411 cx_write(MC417_RWD, regval); 412 regval |= MC417_MICS | MC417_MIWR; 413 cx_write(MC417_RWD, regval); 414 415 /* Wait for the trans to complete (MC417_MIRDY asserted). */ 416 retval = mc417_wait_ready(dev); 417 418 /* switch the DAT0-7 GPIO[10:3] to input mode */ 419 cx_write(MC417_OEN, MC417_MIRDY | MC417_MIDATA); 420 421 /* Read data byte 0 */ 422 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0; 423 cx_write(MC417_RWD, regval); 424 425 /* Transition RD to effect read transaction across bus. 426 * Transition 0x5000 -> 0x9000 correct (RD/RDY -> WR/RDY)? 427 * Should it be 0x9000 -> 0xF000 (also why is RDY being set, its 428 * input only...) 429 */ 430 regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0; 431 cx_write(MC417_RWD, regval); 432 433 /* Collect byte */ 434 tempval = cx_read(MC417_RWD); 435 dataval = tempval & 0x000000FF; 436 437 /* Bring CS and RD high. */ 438 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; 439 cx_write(MC417_RWD, regval); 440 441 /* Read data byte 1 */ 442 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1; 443 cx_write(MC417_RWD, regval); 444 regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1; 445 cx_write(MC417_RWD, regval); 446 tempval = cx_read(MC417_RWD); 447 dataval |= ((tempval & 0x000000FF) << 8); 448 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; 449 cx_write(MC417_RWD, regval); 450 451 /* Read data byte 2 */ 452 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2; 453 cx_write(MC417_RWD, regval); 454 regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2; 455 cx_write(MC417_RWD, regval); 456 tempval = cx_read(MC417_RWD); 457 dataval |= ((tempval & 0x000000FF) << 16); 458 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; 459 cx_write(MC417_RWD, regval); 460 461 /* Read data byte 3 */ 462 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3; 463 cx_write(MC417_RWD, regval); 464 regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3; 465 cx_write(MC417_RWD, regval); 466 tempval = cx_read(MC417_RWD); 467 dataval |= ((tempval & 0x000000FF) << 24); 468 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; 469 cx_write(MC417_RWD, regval); 470 471 *value = dataval; 472 473 return retval; 474 } 475 476 int mc417_memory_write(struct cx23885_dev *dev, u32 address, u32 value) 477 { 478 u32 regval; 479 480 /* Enable MC417 GPIO outputs except for MC417_MIRDY, 481 * which is an input. 482 */ 483 cx_write(MC417_OEN, MC417_MIRDY); 484 485 /* Write data byte 0 */ 486 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0 | 487 (value & 0x000000FF); 488 cx_write(MC417_RWD, regval); 489 490 /* Transition CS/WR to effect write transaction across bus. */ 491 regval |= MC417_MICS | MC417_MIWR; 492 cx_write(MC417_RWD, regval); 493 494 /* Write data byte 1 */ 495 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1 | 496 ((value >> 8) & 0x000000FF); 497 cx_write(MC417_RWD, regval); 498 regval |= MC417_MICS | MC417_MIWR; 499 cx_write(MC417_RWD, regval); 500 501 /* Write data byte 2 */ 502 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2 | 503 ((value >> 16) & 0x000000FF); 504 cx_write(MC417_RWD, regval); 505 regval |= MC417_MICS | MC417_MIWR; 506 cx_write(MC417_RWD, regval); 507 508 /* Write data byte 3 */ 509 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3 | 510 ((value >> 24) & 0x000000FF); 511 cx_write(MC417_RWD, regval); 512 regval |= MC417_MICS | MC417_MIWR; 513 cx_write(MC417_RWD, regval); 514 515 /* Write address byte 2 */ 516 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE2 | 517 MCI_MODE_MEMORY_WRITE | ((address >> 16) & 0x3F); 518 cx_write(MC417_RWD, regval); 519 regval |= MC417_MICS | MC417_MIWR; 520 cx_write(MC417_RWD, regval); 521 522 /* Write address byte 1 */ 523 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE1 | 524 ((address >> 8) & 0xFF); 525 cx_write(MC417_RWD, regval); 526 regval |= MC417_MICS | MC417_MIWR; 527 cx_write(MC417_RWD, regval); 528 529 /* Write address byte 0 */ 530 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE0 | 531 (address & 0xFF); 532 cx_write(MC417_RWD, regval); 533 regval |= MC417_MICS | MC417_MIWR; 534 cx_write(MC417_RWD, regval); 535 536 /* Wait for the trans to complete (MC417_MIRDY asserted). */ 537 return mc417_wait_ready(dev); 538 } 539 540 int mc417_memory_read(struct cx23885_dev *dev, u32 address, u32 *value) 541 { 542 int retval; 543 u32 regval; 544 u32 tempval; 545 u32 dataval; 546 547 /* Enable MC417 GPIO outputs except for MC417_MIRDY, 548 * which is an input. 549 */ 550 cx_write(MC417_OEN, MC417_MIRDY); 551 552 /* Write address byte 2 */ 553 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE2 | 554 MCI_MODE_MEMORY_READ | ((address >> 16) & 0x3F); 555 cx_write(MC417_RWD, regval); 556 regval |= MC417_MICS | MC417_MIWR; 557 cx_write(MC417_RWD, regval); 558 559 /* Write address byte 1 */ 560 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE1 | 561 ((address >> 8) & 0xFF); 562 cx_write(MC417_RWD, regval); 563 regval |= MC417_MICS | MC417_MIWR; 564 cx_write(MC417_RWD, regval); 565 566 /* Write address byte 0 */ 567 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE0 | 568 (address & 0xFF); 569 cx_write(MC417_RWD, regval); 570 regval |= MC417_MICS | MC417_MIWR; 571 cx_write(MC417_RWD, regval); 572 573 /* Wait for the trans to complete (MC417_MIRDY asserted). */ 574 retval = mc417_wait_ready(dev); 575 576 /* switch the DAT0-7 GPIO[10:3] to input mode */ 577 cx_write(MC417_OEN, MC417_MIRDY | MC417_MIDATA); 578 579 /* Read data byte 3 */ 580 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3; 581 cx_write(MC417_RWD, regval); 582 583 /* Transition RD to effect read transaction across bus. */ 584 regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3; 585 cx_write(MC417_RWD, regval); 586 587 /* Collect byte */ 588 tempval = cx_read(MC417_RWD); 589 dataval = ((tempval & 0x000000FF) << 24); 590 591 /* Bring CS and RD high. */ 592 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; 593 cx_write(MC417_RWD, regval); 594 595 /* Read data byte 2 */ 596 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2; 597 cx_write(MC417_RWD, regval); 598 regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2; 599 cx_write(MC417_RWD, regval); 600 tempval = cx_read(MC417_RWD); 601 dataval |= ((tempval & 0x000000FF) << 16); 602 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; 603 cx_write(MC417_RWD, regval); 604 605 /* Read data byte 1 */ 606 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1; 607 cx_write(MC417_RWD, regval); 608 regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1; 609 cx_write(MC417_RWD, regval); 610 tempval = cx_read(MC417_RWD); 611 dataval |= ((tempval & 0x000000FF) << 8); 612 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; 613 cx_write(MC417_RWD, regval); 614 615 /* Read data byte 0 */ 616 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0; 617 cx_write(MC417_RWD, regval); 618 regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0; 619 cx_write(MC417_RWD, regval); 620 tempval = cx_read(MC417_RWD); 621 dataval |= (tempval & 0x000000FF); 622 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; 623 cx_write(MC417_RWD, regval); 624 625 *value = dataval; 626 627 return retval; 628 } 629 630 void mc417_gpio_set(struct cx23885_dev *dev, u32 mask) 631 { 632 u32 val; 633 634 /* Set the gpio value */ 635 mc417_register_read(dev, 0x900C, &val); 636 val |= (mask & 0x000ffff); 637 mc417_register_write(dev, 0x900C, val); 638 } 639 640 void mc417_gpio_clear(struct cx23885_dev *dev, u32 mask) 641 { 642 u32 val; 643 644 /* Clear the gpio value */ 645 mc417_register_read(dev, 0x900C, &val); 646 val &= ~(mask & 0x0000ffff); 647 mc417_register_write(dev, 0x900C, val); 648 } 649 650 void mc417_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput) 651 { 652 u32 val; 653 654 /* Enable GPIO direction bits */ 655 mc417_register_read(dev, 0x9020, &val); 656 if (asoutput) 657 val |= (mask & 0x0000ffff); 658 else 659 val &= ~(mask & 0x0000ffff); 660 661 mc417_register_write(dev, 0x9020, val); 662 } 663 /* ------------------------------------------------------------------ */ 664 665 /* MPEG encoder API */ 666 static char *cmd_to_str(int cmd) 667 { 668 switch (cmd) { 669 case CX2341X_ENC_PING_FW: 670 return "PING_FW"; 671 case CX2341X_ENC_START_CAPTURE: 672 return "START_CAPTURE"; 673 case CX2341X_ENC_STOP_CAPTURE: 674 return "STOP_CAPTURE"; 675 case CX2341X_ENC_SET_AUDIO_ID: 676 return "SET_AUDIO_ID"; 677 case CX2341X_ENC_SET_VIDEO_ID: 678 return "SET_VIDEO_ID"; 679 case CX2341X_ENC_SET_PCR_ID: 680 return "SET_PCR_ID"; 681 case CX2341X_ENC_SET_FRAME_RATE: 682 return "SET_FRAME_RATE"; 683 case CX2341X_ENC_SET_FRAME_SIZE: 684 return "SET_FRAME_SIZE"; 685 case CX2341X_ENC_SET_BIT_RATE: 686 return "SET_BIT_RATE"; 687 case CX2341X_ENC_SET_GOP_PROPERTIES: 688 return "SET_GOP_PROPERTIES"; 689 case CX2341X_ENC_SET_ASPECT_RATIO: 690 return "SET_ASPECT_RATIO"; 691 case CX2341X_ENC_SET_DNR_FILTER_MODE: 692 return "SET_DNR_FILTER_MODE"; 693 case CX2341X_ENC_SET_DNR_FILTER_PROPS: 694 return "SET_DNR_FILTER_PROPS"; 695 case CX2341X_ENC_SET_CORING_LEVELS: 696 return "SET_CORING_LEVELS"; 697 case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE: 698 return "SET_SPATIAL_FILTER_TYPE"; 699 case CX2341X_ENC_SET_VBI_LINE: 700 return "SET_VBI_LINE"; 701 case CX2341X_ENC_SET_STREAM_TYPE: 702 return "SET_STREAM_TYPE"; 703 case CX2341X_ENC_SET_OUTPUT_PORT: 704 return "SET_OUTPUT_PORT"; 705 case CX2341X_ENC_SET_AUDIO_PROPERTIES: 706 return "SET_AUDIO_PROPERTIES"; 707 case CX2341X_ENC_HALT_FW: 708 return "HALT_FW"; 709 case CX2341X_ENC_GET_VERSION: 710 return "GET_VERSION"; 711 case CX2341X_ENC_SET_GOP_CLOSURE: 712 return "SET_GOP_CLOSURE"; 713 case CX2341X_ENC_GET_SEQ_END: 714 return "GET_SEQ_END"; 715 case CX2341X_ENC_SET_PGM_INDEX_INFO: 716 return "SET_PGM_INDEX_INFO"; 717 case CX2341X_ENC_SET_VBI_CONFIG: 718 return "SET_VBI_CONFIG"; 719 case CX2341X_ENC_SET_DMA_BLOCK_SIZE: 720 return "SET_DMA_BLOCK_SIZE"; 721 case CX2341X_ENC_GET_PREV_DMA_INFO_MB_10: 722 return "GET_PREV_DMA_INFO_MB_10"; 723 case CX2341X_ENC_GET_PREV_DMA_INFO_MB_9: 724 return "GET_PREV_DMA_INFO_MB_9"; 725 case CX2341X_ENC_SCHED_DMA_TO_HOST: 726 return "SCHED_DMA_TO_HOST"; 727 case CX2341X_ENC_INITIALIZE_INPUT: 728 return "INITIALIZE_INPUT"; 729 case CX2341X_ENC_SET_FRAME_DROP_RATE: 730 return "SET_FRAME_DROP_RATE"; 731 case CX2341X_ENC_PAUSE_ENCODER: 732 return "PAUSE_ENCODER"; 733 case CX2341X_ENC_REFRESH_INPUT: 734 return "REFRESH_INPUT"; 735 case CX2341X_ENC_SET_COPYRIGHT: 736 return "SET_COPYRIGHT"; 737 case CX2341X_ENC_SET_EVENT_NOTIFICATION: 738 return "SET_EVENT_NOTIFICATION"; 739 case CX2341X_ENC_SET_NUM_VSYNC_LINES: 740 return "SET_NUM_VSYNC_LINES"; 741 case CX2341X_ENC_SET_PLACEHOLDER: 742 return "SET_PLACEHOLDER"; 743 case CX2341X_ENC_MUTE_VIDEO: 744 return "MUTE_VIDEO"; 745 case CX2341X_ENC_MUTE_AUDIO: 746 return "MUTE_AUDIO"; 747 case CX2341X_ENC_MISC: 748 return "MISC"; 749 default: 750 return "UNKNOWN"; 751 } 752 } 753 754 static int cx23885_mbox_func(void *priv, 755 u32 command, 756 int in, 757 int out, 758 u32 data[CX2341X_MBOX_MAX_DATA]) 759 { 760 struct cx23885_dev *dev = priv; 761 unsigned long timeout; 762 u32 value, flag, retval = 0; 763 int i; 764 765 dprintk(3, "%s: command(0x%X) = %s\n", __func__, command, 766 cmd_to_str(command)); 767 768 /* this may not be 100% safe if we can't read any memory location 769 without side effects */ 770 mc417_memory_read(dev, dev->cx23417_mailbox - 4, &value); 771 if (value != 0x12345678) { 772 pr_err("Firmware and/or mailbox pointer not initialized or corrupted, signature = 0x%x, cmd = %s\n", 773 value, cmd_to_str(command)); 774 return -1; 775 } 776 777 /* This read looks at 32 bits, but flag is only 8 bits. 778 * Seems we also bail if CMD or TIMEOUT bytes are set??? 779 */ 780 mc417_memory_read(dev, dev->cx23417_mailbox, &flag); 781 if (flag) { 782 pr_err("ERROR: Mailbox appears to be in use (%x), cmd = %s\n", 783 flag, cmd_to_str(command)); 784 return -1; 785 } 786 787 flag |= 1; /* tell 'em we're working on it */ 788 mc417_memory_write(dev, dev->cx23417_mailbox, flag); 789 790 /* write command + args + fill remaining with zeros */ 791 /* command code */ 792 mc417_memory_write(dev, dev->cx23417_mailbox + 1, command); 793 mc417_memory_write(dev, dev->cx23417_mailbox + 3, 794 IVTV_API_STD_TIMEOUT); /* timeout */ 795 for (i = 0; i < in; i++) { 796 mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, data[i]); 797 dprintk(3, "API Input %d = %d\n", i, data[i]); 798 } 799 for (; i < CX2341X_MBOX_MAX_DATA; i++) 800 mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, 0); 801 802 flag |= 3; /* tell 'em we're done writing */ 803 mc417_memory_write(dev, dev->cx23417_mailbox, flag); 804 805 /* wait for firmware to handle the API command */ 806 timeout = jiffies + msecs_to_jiffies(10); 807 for (;;) { 808 mc417_memory_read(dev, dev->cx23417_mailbox, &flag); 809 if (0 != (flag & 4)) 810 break; 811 if (time_after(jiffies, timeout)) { 812 pr_err("ERROR: API Mailbox timeout\n"); 813 return -1; 814 } 815 udelay(10); 816 } 817 818 /* read output values */ 819 for (i = 0; i < out; i++) { 820 mc417_memory_read(dev, dev->cx23417_mailbox + 4 + i, data + i); 821 dprintk(3, "API Output %d = %d\n", i, data[i]); 822 } 823 824 mc417_memory_read(dev, dev->cx23417_mailbox + 2, &retval); 825 dprintk(3, "API result = %d\n", retval); 826 827 flag = 0; 828 mc417_memory_write(dev, dev->cx23417_mailbox, flag); 829 830 return retval; 831 } 832 833 /* We don't need to call the API often, so using just one 834 * mailbox will probably suffice 835 */ 836 static int cx23885_api_cmd(struct cx23885_dev *dev, 837 u32 command, 838 u32 inputcnt, 839 u32 outputcnt, 840 ...) 841 { 842 u32 data[CX2341X_MBOX_MAX_DATA]; 843 va_list vargs; 844 int i, err; 845 846 dprintk(3, "%s() cmds = 0x%08x\n", __func__, command); 847 848 va_start(vargs, outputcnt); 849 for (i = 0; i < inputcnt; i++) 850 data[i] = va_arg(vargs, int); 851 852 err = cx23885_mbox_func(dev, command, inputcnt, outputcnt, data); 853 for (i = 0; i < outputcnt; i++) { 854 int *vptr = va_arg(vargs, int *); 855 *vptr = data[i]; 856 } 857 va_end(vargs); 858 859 return err; 860 } 861 862 static int cx23885_api_func(void *priv, u32 cmd, int in, int out, u32 data[CX2341X_MBOX_MAX_DATA]) 863 { 864 return cx23885_mbox_func(priv, cmd, in, out, data); 865 } 866 867 static int cx23885_find_mailbox(struct cx23885_dev *dev) 868 { 869 u32 signature[4] = { 870 0x12345678, 0x34567812, 0x56781234, 0x78123456 871 }; 872 int signaturecnt = 0; 873 u32 value; 874 int i; 875 876 dprintk(2, "%s()\n", __func__); 877 878 for (i = 0; i < CX23885_FIRM_IMAGE_SIZE; i++) { 879 mc417_memory_read(dev, i, &value); 880 if (value == signature[signaturecnt]) 881 signaturecnt++; 882 else 883 signaturecnt = 0; 884 if (4 == signaturecnt) { 885 dprintk(1, "Mailbox signature found at 0x%x\n", i+1); 886 return i+1; 887 } 888 } 889 pr_err("Mailbox signature values not found!\n"); 890 return -1; 891 } 892 893 static int cx23885_load_firmware(struct cx23885_dev *dev) 894 { 895 static const unsigned char magic[8] = { 896 0xa7, 0x0d, 0x00, 0x00, 0x66, 0xbb, 0x55, 0xaa 897 }; 898 const struct firmware *firmware; 899 int i, retval = 0; 900 u32 value = 0; 901 u32 gpio_output = 0; 902 u32 gpio_value; 903 u32 checksum = 0; 904 u32 *dataptr; 905 906 dprintk(2, "%s()\n", __func__); 907 908 /* Save GPIO settings before reset of APU */ 909 retval |= mc417_memory_read(dev, 0x9020, &gpio_output); 910 retval |= mc417_memory_read(dev, 0x900C, &gpio_value); 911 912 retval = mc417_register_write(dev, 913 IVTV_REG_VPU, 0xFFFFFFED); 914 retval |= mc417_register_write(dev, 915 IVTV_REG_HW_BLOCKS, IVTV_CMD_HW_BLOCKS_RST); 916 retval |= mc417_register_write(dev, 917 IVTV_REG_ENC_SDRAM_REFRESH, 0x80000800); 918 retval |= mc417_register_write(dev, 919 IVTV_REG_ENC_SDRAM_PRECHARGE, 0x1A); 920 retval |= mc417_register_write(dev, 921 IVTV_REG_APU, 0); 922 923 if (retval != 0) { 924 pr_err("%s: Error with mc417_register_write\n", 925 __func__); 926 return -1; 927 } 928 929 retval = request_firmware(&firmware, CX23885_FIRM_IMAGE_NAME, 930 &dev->pci->dev); 931 932 if (retval != 0) { 933 pr_err("ERROR: Hotplug firmware request failed (%s).\n", 934 CX23885_FIRM_IMAGE_NAME); 935 pr_err("Please fix your hotplug setup, the board will not work without firmware loaded!\n"); 936 return -1; 937 } 938 939 if (firmware->size != CX23885_FIRM_IMAGE_SIZE) { 940 pr_err("ERROR: Firmware size mismatch (have %zu, expected %d)\n", 941 firmware->size, CX23885_FIRM_IMAGE_SIZE); 942 release_firmware(firmware); 943 return -1; 944 } 945 946 if (0 != memcmp(firmware->data, magic, 8)) { 947 pr_err("ERROR: Firmware magic mismatch, wrong file?\n"); 948 release_firmware(firmware); 949 return -1; 950 } 951 952 /* transfer to the chip */ 953 dprintk(2, "Loading firmware ...\n"); 954 dataptr = (u32 *)firmware->data; 955 for (i = 0; i < (firmware->size >> 2); i++) { 956 value = *dataptr; 957 checksum += ~value; 958 if (mc417_memory_write(dev, i, value) != 0) { 959 pr_err("ERROR: Loading firmware failed!\n"); 960 release_firmware(firmware); 961 return -1; 962 } 963 dataptr++; 964 } 965 966 /* read back to verify with the checksum */ 967 dprintk(1, "Verifying firmware ...\n"); 968 for (i--; i >= 0; i--) { 969 if (mc417_memory_read(dev, i, &value) != 0) { 970 pr_err("ERROR: Reading firmware failed!\n"); 971 release_firmware(firmware); 972 return -1; 973 } 974 checksum -= ~value; 975 } 976 if (checksum) { 977 pr_err("ERROR: Firmware load failed (checksum mismatch).\n"); 978 release_firmware(firmware); 979 return -1; 980 } 981 release_firmware(firmware); 982 dprintk(1, "Firmware upload successful.\n"); 983 984 retval |= mc417_register_write(dev, IVTV_REG_HW_BLOCKS, 985 IVTV_CMD_HW_BLOCKS_RST); 986 987 /* F/W power up disturbs the GPIOs, restore state */ 988 retval |= mc417_register_write(dev, 0x9020, gpio_output); 989 retval |= mc417_register_write(dev, 0x900C, gpio_value); 990 991 retval |= mc417_register_read(dev, IVTV_REG_VPU, &value); 992 retval |= mc417_register_write(dev, IVTV_REG_VPU, value & 0xFFFFFFE8); 993 994 /* Hardcoded GPIO's here */ 995 retval |= mc417_register_write(dev, 0x9020, 0x4000); 996 retval |= mc417_register_write(dev, 0x900C, 0x4000); 997 998 mc417_register_read(dev, 0x9020, &gpio_output); 999 mc417_register_read(dev, 0x900C, &gpio_value); 1000 1001 if (retval < 0) 1002 pr_err("%s: Error with mc417_register_write\n", 1003 __func__); 1004 return 0; 1005 } 1006 1007 void cx23885_417_check_encoder(struct cx23885_dev *dev) 1008 { 1009 u32 status, seq; 1010 1011 status = seq = 0; 1012 cx23885_api_cmd(dev, CX2341X_ENC_GET_SEQ_END, 0, 2, &status, &seq); 1013 dprintk(1, "%s() status = %d, seq = %d\n", __func__, status, seq); 1014 } 1015 1016 static void cx23885_codec_settings(struct cx23885_dev *dev) 1017 { 1018 dprintk(1, "%s()\n", __func__); 1019 1020 /* Dynamically change the height based on video standard */ 1021 if (dev->encodernorm.id & V4L2_STD_525_60) 1022 dev->ts1.height = 480; 1023 else 1024 dev->ts1.height = 576; 1025 1026 /* assign frame size */ 1027 cx23885_api_cmd(dev, CX2341X_ENC_SET_FRAME_SIZE, 2, 0, 1028 dev->ts1.height, dev->ts1.width); 1029 1030 dev->cxhdl.width = dev->ts1.width; 1031 dev->cxhdl.height = dev->ts1.height; 1032 dev->cxhdl.is_50hz = 1033 (dev->encodernorm.id & V4L2_STD_625_50) != 0; 1034 1035 cx2341x_handler_setup(&dev->cxhdl); 1036 1037 cx23885_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 3, 1); 1038 cx23885_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 4, 1); 1039 } 1040 1041 static int cx23885_initialize_codec(struct cx23885_dev *dev, int startencoder) 1042 { 1043 int version; 1044 int retval; 1045 u32 i, data[7]; 1046 1047 dprintk(1, "%s()\n", __func__); 1048 1049 retval = cx23885_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0); /* ping */ 1050 if (retval < 0) { 1051 dprintk(2, "%s() PING OK\n", __func__); 1052 retval = cx23885_load_firmware(dev); 1053 if (retval < 0) { 1054 pr_err("%s() f/w load failed\n", __func__); 1055 return retval; 1056 } 1057 retval = cx23885_find_mailbox(dev); 1058 if (retval < 0) { 1059 pr_err("%s() mailbox < 0, error\n", 1060 __func__); 1061 return -1; 1062 } 1063 dev->cx23417_mailbox = retval; 1064 retval = cx23885_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0); 1065 if (retval < 0) { 1066 pr_err("ERROR: cx23417 firmware ping failed!\n"); 1067 return -1; 1068 } 1069 retval = cx23885_api_cmd(dev, CX2341X_ENC_GET_VERSION, 0, 1, 1070 &version); 1071 if (retval < 0) { 1072 pr_err("ERROR: cx23417 firmware get encoder :version failed!\n"); 1073 return -1; 1074 } 1075 dprintk(1, "cx23417 firmware version is 0x%08x\n", version); 1076 msleep(200); 1077 } 1078 1079 cx23885_codec_settings(dev); 1080 msleep(60); 1081 1082 cx23885_api_cmd(dev, CX2341X_ENC_SET_NUM_VSYNC_LINES, 2, 0, 1083 CX23885_FIELD1_SAA7115, CX23885_FIELD2_SAA7115); 1084 cx23885_api_cmd(dev, CX2341X_ENC_SET_PLACEHOLDER, 12, 0, 1085 CX23885_CUSTOM_EXTENSION_USR_DATA, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1086 0, 0); 1087 1088 /* Setup to capture VBI */ 1089 data[0] = 0x0001BD00; 1090 data[1] = 1; /* frames per interrupt */ 1091 data[2] = 4; /* total bufs */ 1092 data[3] = 0x91559155; /* start codes */ 1093 data[4] = 0x206080C0; /* stop codes */ 1094 data[5] = 6; /* lines */ 1095 data[6] = 64; /* BPL */ 1096 1097 cx23885_api_cmd(dev, CX2341X_ENC_SET_VBI_CONFIG, 7, 0, data[0], data[1], 1098 data[2], data[3], data[4], data[5], data[6]); 1099 1100 for (i = 2; i <= 24; i++) { 1101 int valid; 1102 1103 valid = ((i >= 19) && (i <= 21)); 1104 cx23885_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0, i, 1105 valid, 0 , 0, 0); 1106 cx23885_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0, 1107 i | 0x80000000, valid, 0, 0, 0); 1108 } 1109 1110 cx23885_api_cmd(dev, CX2341X_ENC_MUTE_AUDIO, 1, 0, CX23885_UNMUTE); 1111 msleep(60); 1112 1113 /* initialize the video input */ 1114 cx23885_api_cmd(dev, CX2341X_ENC_INITIALIZE_INPUT, 0, 0); 1115 msleep(60); 1116 1117 /* Enable VIP style pixel invalidation so we work with scaled mode */ 1118 mc417_memory_write(dev, 2120, 0x00000080); 1119 1120 /* start capturing to the host interface */ 1121 if (startencoder) { 1122 cx23885_api_cmd(dev, CX2341X_ENC_START_CAPTURE, 2, 0, 1123 CX23885_MPEG_CAPTURE, CX23885_RAW_BITS_NONE); 1124 msleep(10); 1125 } 1126 1127 return 0; 1128 } 1129 1130 /* ------------------------------------------------------------------ */ 1131 1132 static int queue_setup(struct vb2_queue *q, 1133 unsigned int *num_buffers, unsigned int *num_planes, 1134 unsigned int sizes[], struct device *alloc_devs[]) 1135 { 1136 struct cx23885_dev *dev = q->drv_priv; 1137 1138 dev->ts1.ts_packet_size = mpeglinesize; 1139 dev->ts1.ts_packet_count = mpeglines; 1140 *num_planes = 1; 1141 sizes[0] = mpeglinesize * mpeglines; 1142 *num_buffers = mpegbufs; 1143 return 0; 1144 } 1145 1146 static int buffer_prepare(struct vb2_buffer *vb) 1147 { 1148 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 1149 struct cx23885_dev *dev = vb->vb2_queue->drv_priv; 1150 struct cx23885_buffer *buf = 1151 container_of(vbuf, struct cx23885_buffer, vb); 1152 1153 return cx23885_buf_prepare(buf, &dev->ts1); 1154 } 1155 1156 static void buffer_finish(struct vb2_buffer *vb) 1157 { 1158 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 1159 struct cx23885_dev *dev = vb->vb2_queue->drv_priv; 1160 struct cx23885_buffer *buf = container_of(vbuf, 1161 struct cx23885_buffer, vb); 1162 1163 cx23885_free_buffer(dev, buf); 1164 } 1165 1166 static void buffer_queue(struct vb2_buffer *vb) 1167 { 1168 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 1169 struct cx23885_dev *dev = vb->vb2_queue->drv_priv; 1170 struct cx23885_buffer *buf = container_of(vbuf, 1171 struct cx23885_buffer, vb); 1172 1173 cx23885_buf_queue(&dev->ts1, buf); 1174 } 1175 1176 static int cx23885_start_streaming(struct vb2_queue *q, unsigned int count) 1177 { 1178 struct cx23885_dev *dev = q->drv_priv; 1179 struct cx23885_dmaqueue *dmaq = &dev->ts1.mpegq; 1180 unsigned long flags; 1181 int ret; 1182 1183 ret = cx23885_initialize_codec(dev, 1); 1184 if (ret == 0) { 1185 struct cx23885_buffer *buf = list_entry(dmaq->active.next, 1186 struct cx23885_buffer, queue); 1187 1188 cx23885_start_dma(&dev->ts1, dmaq, buf); 1189 return 0; 1190 } 1191 spin_lock_irqsave(&dev->slock, flags); 1192 while (!list_empty(&dmaq->active)) { 1193 struct cx23885_buffer *buf = list_entry(dmaq->active.next, 1194 struct cx23885_buffer, queue); 1195 1196 list_del(&buf->queue); 1197 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED); 1198 } 1199 spin_unlock_irqrestore(&dev->slock, flags); 1200 return ret; 1201 } 1202 1203 static void cx23885_stop_streaming(struct vb2_queue *q) 1204 { 1205 struct cx23885_dev *dev = q->drv_priv; 1206 1207 /* stop mpeg capture */ 1208 cx23885_api_cmd(dev, CX2341X_ENC_STOP_CAPTURE, 3, 0, 1209 CX23885_END_NOW, CX23885_MPEG_CAPTURE, 1210 CX23885_RAW_BITS_NONE); 1211 1212 msleep(500); 1213 cx23885_417_check_encoder(dev); 1214 cx23885_cancel_buffers(&dev->ts1); 1215 } 1216 1217 static const struct vb2_ops cx23885_qops = { 1218 .queue_setup = queue_setup, 1219 .buf_prepare = buffer_prepare, 1220 .buf_finish = buffer_finish, 1221 .buf_queue = buffer_queue, 1222 .wait_prepare = vb2_ops_wait_prepare, 1223 .wait_finish = vb2_ops_wait_finish, 1224 .start_streaming = cx23885_start_streaming, 1225 .stop_streaming = cx23885_stop_streaming, 1226 }; 1227 1228 /* ------------------------------------------------------------------ */ 1229 1230 static int vidioc_g_std(struct file *file, void *priv, v4l2_std_id *id) 1231 { 1232 struct cx23885_dev *dev = video_drvdata(file); 1233 1234 *id = dev->tvnorm; 1235 return 0; 1236 } 1237 1238 static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id id) 1239 { 1240 struct cx23885_dev *dev = video_drvdata(file); 1241 unsigned int i; 1242 int ret; 1243 1244 for (i = 0; i < ARRAY_SIZE(cx23885_tvnorms); i++) 1245 if (id & cx23885_tvnorms[i].id) 1246 break; 1247 if (i == ARRAY_SIZE(cx23885_tvnorms)) 1248 return -EINVAL; 1249 1250 ret = cx23885_set_tvnorm(dev, id); 1251 if (!ret) 1252 dev->encodernorm = cx23885_tvnorms[i]; 1253 return ret; 1254 } 1255 1256 static int vidioc_enum_input(struct file *file, void *priv, 1257 struct v4l2_input *i) 1258 { 1259 struct cx23885_dev *dev = video_drvdata(file); 1260 dprintk(1, "%s()\n", __func__); 1261 return cx23885_enum_input(dev, i); 1262 } 1263 1264 static int vidioc_g_input(struct file *file, void *priv, unsigned int *i) 1265 { 1266 return cx23885_get_input(file, priv, i); 1267 } 1268 1269 static int vidioc_s_input(struct file *file, void *priv, unsigned int i) 1270 { 1271 return cx23885_set_input(file, priv, i); 1272 } 1273 1274 static int vidioc_g_tuner(struct file *file, void *priv, 1275 struct v4l2_tuner *t) 1276 { 1277 struct cx23885_dev *dev = video_drvdata(file); 1278 1279 if (dev->tuner_type == TUNER_ABSENT) 1280 return -EINVAL; 1281 if (0 != t->index) 1282 return -EINVAL; 1283 strscpy(t->name, "Television", sizeof(t->name)); 1284 call_all(dev, tuner, g_tuner, t); 1285 1286 dprintk(1, "VIDIOC_G_TUNER: tuner type %d\n", t->type); 1287 1288 return 0; 1289 } 1290 1291 static int vidioc_s_tuner(struct file *file, void *priv, 1292 const struct v4l2_tuner *t) 1293 { 1294 struct cx23885_dev *dev = video_drvdata(file); 1295 1296 if (dev->tuner_type == TUNER_ABSENT) 1297 return -EINVAL; 1298 1299 /* Update the A/V core */ 1300 call_all(dev, tuner, s_tuner, t); 1301 1302 return 0; 1303 } 1304 1305 static int vidioc_g_frequency(struct file *file, void *priv, 1306 struct v4l2_frequency *f) 1307 { 1308 struct cx23885_dev *dev = video_drvdata(file); 1309 1310 if (dev->tuner_type == TUNER_ABSENT) 1311 return -EINVAL; 1312 f->type = V4L2_TUNER_ANALOG_TV; 1313 f->frequency = dev->freq; 1314 1315 call_all(dev, tuner, g_frequency, f); 1316 1317 return 0; 1318 } 1319 1320 static int vidioc_s_frequency(struct file *file, void *priv, 1321 const struct v4l2_frequency *f) 1322 { 1323 return cx23885_set_frequency(file, priv, f); 1324 } 1325 1326 static int vidioc_querycap(struct file *file, void *priv, 1327 struct v4l2_capability *cap) 1328 { 1329 struct cx23885_dev *dev = video_drvdata(file); 1330 struct cx23885_tsport *tsport = &dev->ts1; 1331 1332 strscpy(cap->driver, dev->name, sizeof(cap->driver)); 1333 strscpy(cap->card, cx23885_boards[tsport->dev->board].name, 1334 sizeof(cap->card)); 1335 sprintf(cap->bus_info, "PCIe:%s", pci_name(dev->pci)); 1336 cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE | 1337 V4L2_CAP_STREAMING; 1338 if (dev->tuner_type != TUNER_ABSENT) 1339 cap->device_caps |= V4L2_CAP_TUNER; 1340 cap->capabilities = cap->device_caps | V4L2_CAP_VBI_CAPTURE | 1341 V4L2_CAP_AUDIO | V4L2_CAP_DEVICE_CAPS; 1342 1343 return 0; 1344 } 1345 1346 static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv, 1347 struct v4l2_fmtdesc *f) 1348 { 1349 if (f->index != 0) 1350 return -EINVAL; 1351 1352 strscpy(f->description, "MPEG", sizeof(f->description)); 1353 f->pixelformat = V4L2_PIX_FMT_MPEG; 1354 1355 return 0; 1356 } 1357 1358 static int vidioc_g_fmt_vid_cap(struct file *file, void *priv, 1359 struct v4l2_format *f) 1360 { 1361 struct cx23885_dev *dev = video_drvdata(file); 1362 1363 f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG; 1364 f->fmt.pix.bytesperline = 0; 1365 f->fmt.pix.sizeimage = 1366 dev->ts1.ts_packet_size * dev->ts1.ts_packet_count; 1367 f->fmt.pix.colorspace = 0; 1368 f->fmt.pix.width = dev->ts1.width; 1369 f->fmt.pix.height = dev->ts1.height; 1370 f->fmt.pix.field = V4L2_FIELD_INTERLACED; 1371 dprintk(1, "VIDIOC_G_FMT: w: %d, h: %d\n", 1372 dev->ts1.width, dev->ts1.height); 1373 return 0; 1374 } 1375 1376 static int vidioc_try_fmt_vid_cap(struct file *file, void *priv, 1377 struct v4l2_format *f) 1378 { 1379 struct cx23885_dev *dev = video_drvdata(file); 1380 1381 f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG; 1382 f->fmt.pix.bytesperline = 0; 1383 f->fmt.pix.sizeimage = 1384 dev->ts1.ts_packet_size * dev->ts1.ts_packet_count; 1385 f->fmt.pix.colorspace = 0; 1386 f->fmt.pix.field = V4L2_FIELD_INTERLACED; 1387 dprintk(1, "VIDIOC_TRY_FMT: w: %d, h: %d\n", 1388 dev->ts1.width, dev->ts1.height); 1389 return 0; 1390 } 1391 1392 static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, 1393 struct v4l2_format *f) 1394 { 1395 struct cx23885_dev *dev = video_drvdata(file); 1396 1397 f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG; 1398 f->fmt.pix.bytesperline = 0; 1399 f->fmt.pix.sizeimage = 1400 dev->ts1.ts_packet_size * dev->ts1.ts_packet_count; 1401 f->fmt.pix.colorspace = 0; 1402 f->fmt.pix.field = V4L2_FIELD_INTERLACED; 1403 dprintk(1, "VIDIOC_S_FMT: w: %d, h: %d, f: %d\n", 1404 f->fmt.pix.width, f->fmt.pix.height, f->fmt.pix.field); 1405 return 0; 1406 } 1407 1408 static int vidioc_log_status(struct file *file, void *priv) 1409 { 1410 struct cx23885_dev *dev = video_drvdata(file); 1411 char name[32 + 2]; 1412 1413 snprintf(name, sizeof(name), "%s/2", dev->name); 1414 call_all(dev, core, log_status); 1415 v4l2_ctrl_handler_log_status(&dev->cxhdl.hdl, name); 1416 return 0; 1417 } 1418 1419 static const struct v4l2_file_operations mpeg_fops = { 1420 .owner = THIS_MODULE, 1421 .open = v4l2_fh_open, 1422 .release = vb2_fop_release, 1423 .read = vb2_fop_read, 1424 .poll = vb2_fop_poll, 1425 .unlocked_ioctl = video_ioctl2, 1426 .mmap = vb2_fop_mmap, 1427 }; 1428 1429 static const struct v4l2_ioctl_ops mpeg_ioctl_ops = { 1430 .vidioc_g_std = vidioc_g_std, 1431 .vidioc_s_std = vidioc_s_std, 1432 .vidioc_enum_input = vidioc_enum_input, 1433 .vidioc_g_input = vidioc_g_input, 1434 .vidioc_s_input = vidioc_s_input, 1435 .vidioc_g_tuner = vidioc_g_tuner, 1436 .vidioc_s_tuner = vidioc_s_tuner, 1437 .vidioc_g_frequency = vidioc_g_frequency, 1438 .vidioc_s_frequency = vidioc_s_frequency, 1439 .vidioc_querycap = vidioc_querycap, 1440 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, 1441 .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, 1442 .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, 1443 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, 1444 .vidioc_reqbufs = vb2_ioctl_reqbufs, 1445 .vidioc_prepare_buf = vb2_ioctl_prepare_buf, 1446 .vidioc_querybuf = vb2_ioctl_querybuf, 1447 .vidioc_qbuf = vb2_ioctl_qbuf, 1448 .vidioc_dqbuf = vb2_ioctl_dqbuf, 1449 .vidioc_streamon = vb2_ioctl_streamon, 1450 .vidioc_streamoff = vb2_ioctl_streamoff, 1451 .vidioc_log_status = vidioc_log_status, 1452 #ifdef CONFIG_VIDEO_ADV_DEBUG 1453 .vidioc_g_chip_info = cx23885_g_chip_info, 1454 .vidioc_g_register = cx23885_g_register, 1455 .vidioc_s_register = cx23885_s_register, 1456 #endif 1457 }; 1458 1459 static struct video_device cx23885_mpeg_template = { 1460 .name = "cx23885", 1461 .fops = &mpeg_fops, 1462 .ioctl_ops = &mpeg_ioctl_ops, 1463 .tvnorms = CX23885_NORMS, 1464 }; 1465 1466 void cx23885_417_unregister(struct cx23885_dev *dev) 1467 { 1468 dprintk(1, "%s()\n", __func__); 1469 1470 if (dev->v4l_device) { 1471 if (video_is_registered(dev->v4l_device)) 1472 video_unregister_device(dev->v4l_device); 1473 else 1474 video_device_release(dev->v4l_device); 1475 v4l2_ctrl_handler_free(&dev->cxhdl.hdl); 1476 dev->v4l_device = NULL; 1477 } 1478 } 1479 1480 static struct video_device *cx23885_video_dev_alloc( 1481 struct cx23885_tsport *tsport, 1482 struct pci_dev *pci, 1483 struct video_device *template, 1484 char *type) 1485 { 1486 struct video_device *vfd; 1487 struct cx23885_dev *dev = tsport->dev; 1488 1489 dprintk(1, "%s()\n", __func__); 1490 1491 vfd = video_device_alloc(); 1492 if (NULL == vfd) 1493 return NULL; 1494 *vfd = *template; 1495 snprintf(vfd->name, sizeof(vfd->name), "%s (%s)", 1496 cx23885_boards[tsport->dev->board].name, type); 1497 vfd->v4l2_dev = &dev->v4l2_dev; 1498 vfd->release = video_device_release; 1499 return vfd; 1500 } 1501 1502 int cx23885_417_register(struct cx23885_dev *dev) 1503 { 1504 /* FIXME: Port1 hardcoded here */ 1505 int err = -ENODEV; 1506 struct cx23885_tsport *tsport = &dev->ts1; 1507 struct vb2_queue *q; 1508 1509 dprintk(1, "%s()\n", __func__); 1510 1511 if (cx23885_boards[dev->board].portb != CX23885_MPEG_ENCODER) 1512 return err; 1513 1514 /* Set default TV standard */ 1515 dev->encodernorm = cx23885_tvnorms[0]; 1516 1517 if (dev->encodernorm.id & V4L2_STD_525_60) 1518 tsport->height = 480; 1519 else 1520 tsport->height = 576; 1521 1522 tsport->width = 720; 1523 dev->cxhdl.port = CX2341X_PORT_SERIAL; 1524 err = cx2341x_handler_init(&dev->cxhdl, 50); 1525 if (err) 1526 return err; 1527 dev->cxhdl.priv = dev; 1528 dev->cxhdl.func = cx23885_api_func; 1529 cx2341x_handler_set_50hz(&dev->cxhdl, tsport->height == 576); 1530 v4l2_ctrl_add_handler(&dev->ctrl_handler, &dev->cxhdl.hdl, NULL, false); 1531 1532 /* Allocate and initialize V4L video device */ 1533 dev->v4l_device = cx23885_video_dev_alloc(tsport, 1534 dev->pci, &cx23885_mpeg_template, "mpeg"); 1535 q = &dev->vb2_mpegq; 1536 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 1537 q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ; 1538 q->gfp_flags = GFP_DMA32; 1539 q->min_buffers_needed = 2; 1540 q->drv_priv = dev; 1541 q->buf_struct_size = sizeof(struct cx23885_buffer); 1542 q->ops = &cx23885_qops; 1543 q->mem_ops = &vb2_dma_sg_memops; 1544 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; 1545 q->lock = &dev->lock; 1546 q->dev = &dev->pci->dev; 1547 1548 err = vb2_queue_init(q); 1549 if (err < 0) 1550 return err; 1551 video_set_drvdata(dev->v4l_device, dev); 1552 dev->v4l_device->lock = &dev->lock; 1553 dev->v4l_device->queue = q; 1554 err = video_register_device(dev->v4l_device, 1555 VFL_TYPE_GRABBER, -1); 1556 if (err < 0) { 1557 pr_info("%s: can't register mpeg device\n", dev->name); 1558 return err; 1559 } 1560 1561 pr_info("%s: registered device %s [mpeg]\n", 1562 dev->name, video_device_node_name(dev->v4l_device)); 1563 1564 /* ST: Configure the encoder paramaters, but don't begin 1565 * encoding, this resolves an issue where the first time the 1566 * encoder is started video can be choppy. 1567 */ 1568 cx23885_initialize_codec(dev, 0); 1569 1570 return 0; 1571 } 1572 1573 MODULE_FIRMWARE(CX23885_FIRM_IMAGE_NAME); 1574