1 /* 2 * altera-ci.c 3 * 4 * CI driver in conjunction with NetUp Dual DVB-T/C RF CI card 5 * 6 * Copyright (C) 2010,2011 NetUP Inc. 7 * Copyright (C) 2010,2011 Igor M. Liplianin <liplianin@netup.ru> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * 18 * GNU General Public License for more details. 19 */ 20 21 /* 22 * currently cx23885 GPIO's used. 23 * GPIO-0 ~INT in 24 * GPIO-1 TMS out 25 * GPIO-2 ~reset chips out 26 * GPIO-3 to GPIO-10 data/addr for CA in/out 27 * GPIO-11 ~CS out 28 * GPIO-12 AD_RG out 29 * GPIO-13 ~WR out 30 * GPIO-14 ~RD out 31 * GPIO-15 ~RDY in 32 * GPIO-16 TCK out 33 * GPIO-17 TDO in 34 * GPIO-18 TDI out 35 */ 36 /* 37 * Bit definitions for MC417_RWD and MC417_OEN registers 38 * bits 31-16 39 * +-----------+ 40 * | Reserved | 41 * +-----------+ 42 * bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 43 * +-------+-------+-------+-------+-------+-------+-------+-------+ 44 * | TDI | TDO | TCK | RDY# | #RD | #WR | AD_RG | #CS | 45 * +-------+-------+-------+-------+-------+-------+-------+-------+ 46 * bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 47 * +-------+-------+-------+-------+-------+-------+-------+-------+ 48 * | DATA7| DATA6| DATA5| DATA4| DATA3| DATA2| DATA1| DATA0| 49 * +-------+-------+-------+-------+-------+-------+-------+-------+ 50 */ 51 #include <dvb_demux.h> 52 #include <dvb_frontend.h> 53 #include "altera-ci.h" 54 #include "dvb_ca_en50221.h" 55 56 /* FPGA regs */ 57 #define NETUP_CI_INT_CTRL 0x00 58 #define NETUP_CI_BUSCTRL2 0x01 59 #define NETUP_CI_ADDR0 0x04 60 #define NETUP_CI_ADDR1 0x05 61 #define NETUP_CI_DATA 0x06 62 #define NETUP_CI_BUSCTRL 0x07 63 #define NETUP_CI_PID_ADDR0 0x08 64 #define NETUP_CI_PID_ADDR1 0x09 65 #define NETUP_CI_PID_DATA 0x0a 66 #define NETUP_CI_TSA_DIV 0x0c 67 #define NETUP_CI_TSB_DIV 0x0d 68 #define NETUP_CI_REVISION 0x0f 69 70 /* const for ci op */ 71 #define NETUP_CI_FLG_CTL 1 72 #define NETUP_CI_FLG_RD 1 73 #define NETUP_CI_FLG_AD 1 74 75 static unsigned int ci_dbg; 76 module_param(ci_dbg, int, 0644); 77 MODULE_PARM_DESC(ci_dbg, "Enable CI debugging"); 78 79 static unsigned int pid_dbg; 80 module_param(pid_dbg, int, 0644); 81 MODULE_PARM_DESC(pid_dbg, "Enable PID filtering debugging"); 82 83 MODULE_DESCRIPTION("altera FPGA CI module"); 84 MODULE_AUTHOR("Igor M. Liplianin <liplianin@netup.ru>"); 85 MODULE_LICENSE("GPL"); 86 87 #define ci_dbg_print(args...) \ 88 do { \ 89 if (ci_dbg) \ 90 printk(KERN_DEBUG args); \ 91 } while (0) 92 93 #define pid_dbg_print(args...) \ 94 do { \ 95 if (pid_dbg) \ 96 printk(KERN_DEBUG args); \ 97 } while (0) 98 99 struct altera_ci_state; 100 struct netup_hw_pid_filter; 101 102 struct fpga_internal { 103 void *dev; 104 struct mutex fpga_mutex;/* two CI's on the same fpga */ 105 struct netup_hw_pid_filter *pid_filt[2]; 106 struct altera_ci_state *state[2]; 107 struct work_struct work; 108 int (*fpga_rw) (void *dev, int flag, int data, int rw); 109 int cis_used; 110 int filts_used; 111 int strt_wrk; 112 }; 113 114 /* stores all private variables for communication with CI */ 115 struct altera_ci_state { 116 struct fpga_internal *internal; 117 struct dvb_ca_en50221 ca; 118 int status; 119 int nr; 120 }; 121 122 /* stores all private variables for hardware pid filtering */ 123 struct netup_hw_pid_filter { 124 struct fpga_internal *internal; 125 struct dvb_demux *demux; 126 /* save old functions */ 127 int (*start_feed)(struct dvb_demux_feed *feed); 128 int (*stop_feed)(struct dvb_demux_feed *feed); 129 130 int status; 131 int nr; 132 }; 133 134 /* internal params node */ 135 struct fpga_inode { 136 /* pointer for internal params, one for each pair of CI's */ 137 struct fpga_internal *internal; 138 struct fpga_inode *next_inode; 139 }; 140 141 /* first internal params */ 142 static struct fpga_inode *fpga_first_inode; 143 144 /* find chip by dev */ 145 static struct fpga_inode *find_inode(void *dev) 146 { 147 struct fpga_inode *temp_chip = fpga_first_inode; 148 149 if (temp_chip == NULL) 150 return temp_chip; 151 152 /* 153 Search for the last fpga CI chip or 154 find it by dev */ 155 while ((temp_chip != NULL) && 156 (temp_chip->internal->dev != dev)) 157 temp_chip = temp_chip->next_inode; 158 159 return temp_chip; 160 } 161 /* check demux */ 162 static struct fpga_internal *check_filter(struct fpga_internal *temp_int, 163 void *demux_dev, int filt_nr) 164 { 165 if (temp_int == NULL) 166 return NULL; 167 168 if ((temp_int->pid_filt[filt_nr]) == NULL) 169 return NULL; 170 171 if (temp_int->pid_filt[filt_nr]->demux == demux_dev) 172 return temp_int; 173 174 return NULL; 175 } 176 177 /* find chip by demux */ 178 static struct fpga_inode *find_dinode(void *demux_dev) 179 { 180 struct fpga_inode *temp_chip = fpga_first_inode; 181 struct fpga_internal *temp_int; 182 183 /* 184 * Search of the last fpga CI chip or 185 * find it by demux 186 */ 187 while (temp_chip != NULL) { 188 if (temp_chip->internal != NULL) { 189 temp_int = temp_chip->internal; 190 if (check_filter(temp_int, demux_dev, 0)) 191 break; 192 if (check_filter(temp_int, demux_dev, 1)) 193 break; 194 } 195 196 temp_chip = temp_chip->next_inode; 197 } 198 199 return temp_chip; 200 } 201 202 /* deallocating chip */ 203 static void remove_inode(struct fpga_internal *internal) 204 { 205 struct fpga_inode *prev_node = fpga_first_inode; 206 struct fpga_inode *del_node = find_inode(internal->dev); 207 208 if (del_node != NULL) { 209 if (del_node == fpga_first_inode) { 210 fpga_first_inode = del_node->next_inode; 211 } else { 212 while (prev_node->next_inode != del_node) 213 prev_node = prev_node->next_inode; 214 215 if (del_node->next_inode == NULL) 216 prev_node->next_inode = NULL; 217 else 218 prev_node->next_inode = 219 prev_node->next_inode->next_inode; 220 } 221 222 kfree(del_node); 223 } 224 } 225 226 /* allocating new chip */ 227 static struct fpga_inode *append_internal(struct fpga_internal *internal) 228 { 229 struct fpga_inode *new_node = fpga_first_inode; 230 231 if (new_node == NULL) { 232 new_node = kmalloc(sizeof(struct fpga_inode), GFP_KERNEL); 233 fpga_first_inode = new_node; 234 } else { 235 while (new_node->next_inode != NULL) 236 new_node = new_node->next_inode; 237 238 new_node->next_inode = 239 kmalloc(sizeof(struct fpga_inode), GFP_KERNEL); 240 if (new_node->next_inode != NULL) 241 new_node = new_node->next_inode; 242 else 243 new_node = NULL; 244 } 245 246 if (new_node != NULL) { 247 new_node->internal = internal; 248 new_node->next_inode = NULL; 249 } 250 251 return new_node; 252 } 253 254 static int netup_fpga_op_rw(struct fpga_internal *inter, int addr, 255 u8 val, u8 read) 256 { 257 inter->fpga_rw(inter->dev, NETUP_CI_FLG_AD, addr, 0); 258 return inter->fpga_rw(inter->dev, 0, val, read); 259 } 260 261 /* flag - mem/io, read - read/write */ 262 static int altera_ci_op_cam(struct dvb_ca_en50221 *en50221, int slot, 263 u8 flag, u8 read, int addr, u8 val) 264 { 265 266 struct altera_ci_state *state = en50221->data; 267 struct fpga_internal *inter = state->internal; 268 269 u8 store; 270 int mem = 0; 271 272 if (0 != slot) 273 return -EINVAL; 274 275 mutex_lock(&inter->fpga_mutex); 276 277 netup_fpga_op_rw(inter, NETUP_CI_ADDR0, ((addr << 1) & 0xfe), 0); 278 netup_fpga_op_rw(inter, NETUP_CI_ADDR1, ((addr >> 7) & 0x7f), 0); 279 store = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 0, NETUP_CI_FLG_RD); 280 281 store &= 0x0f; 282 store |= ((state->nr << 7) | (flag << 6)); 283 284 netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, store, 0); 285 mem = netup_fpga_op_rw(inter, NETUP_CI_DATA, val, read); 286 287 mutex_unlock(&inter->fpga_mutex); 288 289 ci_dbg_print("%s: %s: addr=[0x%02x], %s=%x\n", __func__, 290 (read) ? "read" : "write", addr, 291 (flag == NETUP_CI_FLG_CTL) ? "ctl" : "mem", 292 (read) ? mem : val); 293 294 return mem; 295 } 296 297 static int altera_ci_read_attribute_mem(struct dvb_ca_en50221 *en50221, 298 int slot, int addr) 299 { 300 return altera_ci_op_cam(en50221, slot, 0, NETUP_CI_FLG_RD, addr, 0); 301 } 302 303 static int altera_ci_write_attribute_mem(struct dvb_ca_en50221 *en50221, 304 int slot, int addr, u8 data) 305 { 306 return altera_ci_op_cam(en50221, slot, 0, 0, addr, data); 307 } 308 309 static int altera_ci_read_cam_ctl(struct dvb_ca_en50221 *en50221, 310 int slot, u8 addr) 311 { 312 return altera_ci_op_cam(en50221, slot, NETUP_CI_FLG_CTL, 313 NETUP_CI_FLG_RD, addr, 0); 314 } 315 316 static int altera_ci_write_cam_ctl(struct dvb_ca_en50221 *en50221, int slot, 317 u8 addr, u8 data) 318 { 319 return altera_ci_op_cam(en50221, slot, NETUP_CI_FLG_CTL, 0, addr, data); 320 } 321 322 static int altera_ci_slot_reset(struct dvb_ca_en50221 *en50221, int slot) 323 { 324 struct altera_ci_state *state = en50221->data; 325 struct fpga_internal *inter = state->internal; 326 /* reasonable timeout for CI reset is 10 seconds */ 327 unsigned long t_out = jiffies + msecs_to_jiffies(9999); 328 int ret; 329 330 ci_dbg_print("%s\n", __func__); 331 332 if (0 != slot) 333 return -EINVAL; 334 335 mutex_lock(&inter->fpga_mutex); 336 337 ret = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 0, NETUP_CI_FLG_RD); 338 netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 339 (ret & 0xcf) | (1 << (5 - state->nr)), 0); 340 341 mutex_unlock(&inter->fpga_mutex); 342 343 for (;;) { 344 mdelay(50); 345 346 mutex_lock(&inter->fpga_mutex); 347 348 ret = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 349 0, NETUP_CI_FLG_RD); 350 mutex_unlock(&inter->fpga_mutex); 351 352 if ((ret & (1 << (5 - state->nr))) == 0) 353 break; 354 if (time_after(jiffies, t_out)) 355 break; 356 } 357 358 359 ci_dbg_print("%s: %d msecs\n", __func__, 360 jiffies_to_msecs(jiffies + msecs_to_jiffies(9999) - t_out)); 361 362 return 0; 363 } 364 365 static int altera_ci_slot_shutdown(struct dvb_ca_en50221 *en50221, int slot) 366 { 367 /* not implemented */ 368 return 0; 369 } 370 371 static int altera_ci_slot_ts_ctl(struct dvb_ca_en50221 *en50221, int slot) 372 { 373 struct altera_ci_state *state = en50221->data; 374 struct fpga_internal *inter = state->internal; 375 int ret; 376 377 ci_dbg_print("%s\n", __func__); 378 379 if (0 != slot) 380 return -EINVAL; 381 382 mutex_lock(&inter->fpga_mutex); 383 384 ret = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 0, NETUP_CI_FLG_RD); 385 netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 386 (ret & 0x0f) | (1 << (3 - state->nr)), 0); 387 388 mutex_unlock(&inter->fpga_mutex); 389 390 return 0; 391 } 392 393 /* work handler */ 394 static void netup_read_ci_status(struct work_struct *work) 395 { 396 struct fpga_internal *inter = 397 container_of(work, struct fpga_internal, work); 398 int ret; 399 400 ci_dbg_print("%s\n", __func__); 401 402 mutex_lock(&inter->fpga_mutex); 403 /* ack' irq */ 404 ret = netup_fpga_op_rw(inter, NETUP_CI_INT_CTRL, 0, NETUP_CI_FLG_RD); 405 ret = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 0, NETUP_CI_FLG_RD); 406 407 mutex_unlock(&inter->fpga_mutex); 408 409 if (inter->state[1] != NULL) { 410 inter->state[1]->status = 411 ((ret & 1) == 0 ? 412 DVB_CA_EN50221_POLL_CAM_PRESENT | 413 DVB_CA_EN50221_POLL_CAM_READY : 0); 414 ci_dbg_print("%s: setting CI[1] status = 0x%x\n", 415 __func__, inter->state[1]->status); 416 } 417 418 if (inter->state[0] != NULL) { 419 inter->state[0]->status = 420 ((ret & 2) == 0 ? 421 DVB_CA_EN50221_POLL_CAM_PRESENT | 422 DVB_CA_EN50221_POLL_CAM_READY : 0); 423 ci_dbg_print("%s: setting CI[0] status = 0x%x\n", 424 __func__, inter->state[0]->status); 425 } 426 } 427 428 /* CI irq handler */ 429 int altera_ci_irq(void *dev) 430 { 431 struct fpga_inode *temp_int = NULL; 432 struct fpga_internal *inter = NULL; 433 434 ci_dbg_print("%s\n", __func__); 435 436 if (dev != NULL) { 437 temp_int = find_inode(dev); 438 if (temp_int != NULL) { 439 inter = temp_int->internal; 440 schedule_work(&inter->work); 441 } 442 } 443 444 return 1; 445 } 446 EXPORT_SYMBOL(altera_ci_irq); 447 448 static int altera_poll_ci_slot_status(struct dvb_ca_en50221 *en50221, 449 int slot, int open) 450 { 451 struct altera_ci_state *state = en50221->data; 452 453 if (0 != slot) 454 return -EINVAL; 455 456 return state->status; 457 } 458 459 static void altera_hw_filt_release(void *main_dev, int filt_nr) 460 { 461 struct fpga_inode *temp_int = find_inode(main_dev); 462 struct netup_hw_pid_filter *pid_filt = NULL; 463 464 ci_dbg_print("%s\n", __func__); 465 466 if (temp_int != NULL) { 467 pid_filt = temp_int->internal->pid_filt[filt_nr - 1]; 468 /* stored old feed controls */ 469 pid_filt->demux->start_feed = pid_filt->start_feed; 470 pid_filt->demux->stop_feed = pid_filt->stop_feed; 471 472 if (((--(temp_int->internal->filts_used)) <= 0) && 473 ((temp_int->internal->cis_used) <= 0)) { 474 475 ci_dbg_print("%s: Actually removing\n", __func__); 476 477 remove_inode(temp_int->internal); 478 kfree(pid_filt->internal); 479 } 480 481 kfree(pid_filt); 482 483 } 484 485 } 486 487 void altera_ci_release(void *dev, int ci_nr) 488 { 489 struct fpga_inode *temp_int = find_inode(dev); 490 struct altera_ci_state *state = NULL; 491 492 ci_dbg_print("%s\n", __func__); 493 494 if (temp_int != NULL) { 495 state = temp_int->internal->state[ci_nr - 1]; 496 altera_hw_filt_release(dev, ci_nr); 497 498 499 if (((temp_int->internal->filts_used) <= 0) && 500 ((--(temp_int->internal->cis_used)) <= 0)) { 501 502 ci_dbg_print("%s: Actually removing\n", __func__); 503 504 remove_inode(temp_int->internal); 505 kfree(state->internal); 506 } 507 508 if (state != NULL) { 509 if (state->ca.data != NULL) 510 dvb_ca_en50221_release(&state->ca); 511 512 kfree(state); 513 } 514 } 515 516 } 517 EXPORT_SYMBOL(altera_ci_release); 518 519 static void altera_pid_control(struct netup_hw_pid_filter *pid_filt, 520 u16 pid, int onoff) 521 { 522 struct fpga_internal *inter = pid_filt->internal; 523 u8 store = 0; 524 525 /* pid 0-0x1f always enabled, don't touch them */ 526 if ((pid == 0x2000) || (pid < 0x20)) 527 return; 528 529 mutex_lock(&inter->fpga_mutex); 530 531 netup_fpga_op_rw(inter, NETUP_CI_PID_ADDR0, (pid >> 3) & 0xff, 0); 532 netup_fpga_op_rw(inter, NETUP_CI_PID_ADDR1, 533 ((pid >> 11) & 0x03) | (pid_filt->nr << 2), 0); 534 535 store = netup_fpga_op_rw(inter, NETUP_CI_PID_DATA, 0, NETUP_CI_FLG_RD); 536 537 if (onoff)/* 0 - on, 1 - off */ 538 store |= (1 << (pid & 7)); 539 else 540 store &= ~(1 << (pid & 7)); 541 542 netup_fpga_op_rw(inter, NETUP_CI_PID_DATA, store, 0); 543 544 mutex_unlock(&inter->fpga_mutex); 545 546 pid_dbg_print("%s: (%d) set pid: %5d 0x%04x '%s'\n", __func__, 547 pid_filt->nr, pid, pid, onoff ? "off" : "on"); 548 } 549 550 static void altera_toggle_fullts_streaming(struct netup_hw_pid_filter *pid_filt, 551 int filt_nr, int onoff) 552 { 553 struct fpga_internal *inter = pid_filt->internal; 554 u8 store = 0; 555 int i; 556 557 pid_dbg_print("%s: pid_filt->nr[%d] now %s\n", __func__, pid_filt->nr, 558 onoff ? "off" : "on"); 559 560 if (onoff)/* 0 - on, 1 - off */ 561 store = 0xff;/* ignore pid */ 562 else 563 store = 0;/* enable pid */ 564 565 mutex_lock(&inter->fpga_mutex); 566 567 for (i = 0; i < 1024; i++) { 568 netup_fpga_op_rw(inter, NETUP_CI_PID_ADDR0, i & 0xff, 0); 569 570 netup_fpga_op_rw(inter, NETUP_CI_PID_ADDR1, 571 ((i >> 8) & 0x03) | (pid_filt->nr << 2), 0); 572 /* pid 0-0x1f always enabled */ 573 netup_fpga_op_rw(inter, NETUP_CI_PID_DATA, 574 (i > 3 ? store : 0), 0); 575 } 576 577 mutex_unlock(&inter->fpga_mutex); 578 } 579 580 static int altera_pid_feed_control(void *demux_dev, int filt_nr, 581 struct dvb_demux_feed *feed, int onoff) 582 { 583 struct fpga_inode *temp_int = find_dinode(demux_dev); 584 struct fpga_internal *inter = temp_int->internal; 585 struct netup_hw_pid_filter *pid_filt = inter->pid_filt[filt_nr - 1]; 586 587 altera_pid_control(pid_filt, feed->pid, onoff ? 0 : 1); 588 /* call old feed proc's */ 589 if (onoff) 590 pid_filt->start_feed(feed); 591 else 592 pid_filt->stop_feed(feed); 593 594 if (feed->pid == 0x2000) 595 altera_toggle_fullts_streaming(pid_filt, filt_nr, 596 onoff ? 0 : 1); 597 598 return 0; 599 } 600 601 static int altera_ci_start_feed(struct dvb_demux_feed *feed, int num) 602 { 603 altera_pid_feed_control(feed->demux, num, feed, 1); 604 605 return 0; 606 } 607 608 static int altera_ci_stop_feed(struct dvb_demux_feed *feed, int num) 609 { 610 altera_pid_feed_control(feed->demux, num, feed, 0); 611 612 return 0; 613 } 614 615 static int altera_ci_start_feed_1(struct dvb_demux_feed *feed) 616 { 617 return altera_ci_start_feed(feed, 1); 618 } 619 620 static int altera_ci_stop_feed_1(struct dvb_demux_feed *feed) 621 { 622 return altera_ci_stop_feed(feed, 1); 623 } 624 625 static int altera_ci_start_feed_2(struct dvb_demux_feed *feed) 626 { 627 return altera_ci_start_feed(feed, 2); 628 } 629 630 static int altera_ci_stop_feed_2(struct dvb_demux_feed *feed) 631 { 632 return altera_ci_stop_feed(feed, 2); 633 } 634 635 static int altera_hw_filt_init(struct altera_ci_config *config, int hw_filt_nr) 636 { 637 struct netup_hw_pid_filter *pid_filt = NULL; 638 struct fpga_inode *temp_int = find_inode(config->dev); 639 struct fpga_internal *inter = NULL; 640 int ret = 0; 641 642 pid_filt = kzalloc(sizeof(struct netup_hw_pid_filter), GFP_KERNEL); 643 644 ci_dbg_print("%s\n", __func__); 645 646 if (!pid_filt) { 647 ret = -ENOMEM; 648 goto err; 649 } 650 651 if (temp_int != NULL) { 652 inter = temp_int->internal; 653 (inter->filts_used)++; 654 ci_dbg_print("%s: Find Internal Structure!\n", __func__); 655 } else { 656 inter = kzalloc(sizeof(struct fpga_internal), GFP_KERNEL); 657 if (!inter) { 658 ret = -ENOMEM; 659 goto err; 660 } 661 662 temp_int = append_internal(inter); 663 inter->filts_used = 1; 664 inter->dev = config->dev; 665 inter->fpga_rw = config->fpga_rw; 666 mutex_init(&inter->fpga_mutex); 667 inter->strt_wrk = 1; 668 ci_dbg_print("%s: Create New Internal Structure!\n", __func__); 669 } 670 671 ci_dbg_print("%s: setting hw pid filter = %p for ci = %d\n", __func__, 672 pid_filt, hw_filt_nr - 1); 673 inter->pid_filt[hw_filt_nr - 1] = pid_filt; 674 pid_filt->demux = config->demux; 675 pid_filt->internal = inter; 676 pid_filt->nr = hw_filt_nr - 1; 677 /* store old feed controls */ 678 pid_filt->start_feed = config->demux->start_feed; 679 pid_filt->stop_feed = config->demux->stop_feed; 680 /* replace with new feed controls */ 681 if (hw_filt_nr == 1) { 682 pid_filt->demux->start_feed = altera_ci_start_feed_1; 683 pid_filt->demux->stop_feed = altera_ci_stop_feed_1; 684 } else if (hw_filt_nr == 2) { 685 pid_filt->demux->start_feed = altera_ci_start_feed_2; 686 pid_filt->demux->stop_feed = altera_ci_stop_feed_2; 687 } 688 689 altera_toggle_fullts_streaming(pid_filt, 0, 1); 690 691 return 0; 692 err: 693 ci_dbg_print("%s: Can't init hardware filter: Error %d\n", 694 __func__, ret); 695 696 kfree(pid_filt); 697 698 return ret; 699 } 700 701 int altera_ci_init(struct altera_ci_config *config, int ci_nr) 702 { 703 struct altera_ci_state *state; 704 struct fpga_inode *temp_int = find_inode(config->dev); 705 struct fpga_internal *inter = NULL; 706 int ret = 0; 707 u8 store = 0; 708 709 state = kzalloc(sizeof(struct altera_ci_state), GFP_KERNEL); 710 711 ci_dbg_print("%s\n", __func__); 712 713 if (!state) { 714 ret = -ENOMEM; 715 goto err; 716 } 717 718 if (temp_int != NULL) { 719 inter = temp_int->internal; 720 (inter->cis_used)++; 721 inter->fpga_rw = config->fpga_rw; 722 ci_dbg_print("%s: Find Internal Structure!\n", __func__); 723 } else { 724 inter = kzalloc(sizeof(struct fpga_internal), GFP_KERNEL); 725 if (!inter) { 726 ret = -ENOMEM; 727 goto err; 728 } 729 730 temp_int = append_internal(inter); 731 inter->cis_used = 1; 732 inter->dev = config->dev; 733 inter->fpga_rw = config->fpga_rw; 734 mutex_init(&inter->fpga_mutex); 735 inter->strt_wrk = 1; 736 ci_dbg_print("%s: Create New Internal Structure!\n", __func__); 737 } 738 739 ci_dbg_print("%s: setting state = %p for ci = %d\n", __func__, 740 state, ci_nr - 1); 741 state->internal = inter; 742 state->nr = ci_nr - 1; 743 744 state->ca.owner = THIS_MODULE; 745 state->ca.read_attribute_mem = altera_ci_read_attribute_mem; 746 state->ca.write_attribute_mem = altera_ci_write_attribute_mem; 747 state->ca.read_cam_control = altera_ci_read_cam_ctl; 748 state->ca.write_cam_control = altera_ci_write_cam_ctl; 749 state->ca.slot_reset = altera_ci_slot_reset; 750 state->ca.slot_shutdown = altera_ci_slot_shutdown; 751 state->ca.slot_ts_enable = altera_ci_slot_ts_ctl; 752 state->ca.poll_slot_status = altera_poll_ci_slot_status; 753 state->ca.data = state; 754 755 ret = dvb_ca_en50221_init(config->adapter, 756 &state->ca, 757 /* flags */ 0, 758 /* n_slots */ 1); 759 if (0 != ret) 760 goto err; 761 762 inter->state[ci_nr - 1] = state; 763 764 altera_hw_filt_init(config, ci_nr); 765 766 if (inter->strt_wrk) { 767 INIT_WORK(&inter->work, netup_read_ci_status); 768 inter->strt_wrk = 0; 769 } 770 771 ci_dbg_print("%s: CI initialized!\n", __func__); 772 773 mutex_lock(&inter->fpga_mutex); 774 775 /* Enable div */ 776 netup_fpga_op_rw(inter, NETUP_CI_TSA_DIV, 0x0, 0); 777 netup_fpga_op_rw(inter, NETUP_CI_TSB_DIV, 0x0, 0); 778 779 /* enable TS out */ 780 store = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, 0, NETUP_CI_FLG_RD); 781 store |= (3 << 4); 782 netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, store, 0); 783 784 ret = netup_fpga_op_rw(inter, NETUP_CI_REVISION, 0, NETUP_CI_FLG_RD); 785 /* enable irq */ 786 netup_fpga_op_rw(inter, NETUP_CI_INT_CTRL, 0x44, 0); 787 788 mutex_unlock(&inter->fpga_mutex); 789 790 ci_dbg_print("%s: NetUP CI Revision = 0x%x\n", __func__, ret); 791 792 schedule_work(&inter->work); 793 794 return 0; 795 err: 796 ci_dbg_print("%s: Cannot initialize CI: Error %d.\n", __func__, ret); 797 798 kfree(state); 799 800 return ret; 801 } 802 EXPORT_SYMBOL(altera_ci_init); 803 804 int altera_ci_tuner_reset(void *dev, int ci_nr) 805 { 806 struct fpga_inode *temp_int = find_inode(dev); 807 struct fpga_internal *inter = NULL; 808 u8 store; 809 810 ci_dbg_print("%s\n", __func__); 811 812 if (temp_int == NULL) 813 return -1; 814 815 if (temp_int->internal == NULL) 816 return -1; 817 818 inter = temp_int->internal; 819 820 mutex_lock(&inter->fpga_mutex); 821 822 store = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, 0, NETUP_CI_FLG_RD); 823 store &= ~(4 << (2 - ci_nr)); 824 netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, store, 0); 825 msleep(100); 826 store |= (4 << (2 - ci_nr)); 827 netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, store, 0); 828 829 mutex_unlock(&inter->fpga_mutex); 830 831 return 0; 832 } 833 EXPORT_SYMBOL(altera_ci_tuner_reset); 834