1 /* 2 * cx18 driver PCI memory mapped IO access routines 3 * 4 * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl> 5 * Copyright (C) 2008 Andy Walls <awalls@md.metrocast.net> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 20 * 02111-1307 USA 21 */ 22 23 #include "cx18-driver.h" 24 #include "cx18-io.h" 25 #include "cx18-irq.h" 26 27 void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count) 28 { 29 u8 __iomem *dst = addr; 30 u16 val2 = val | (val << 8); 31 u32 val4 = val2 | (val2 << 16); 32 33 /* Align writes on the CX23418's addresses */ 34 if ((count > 0) && ((unsigned long)dst & 1)) { 35 cx18_writeb(cx, (u8) val, dst); 36 count--; 37 dst++; 38 } 39 if ((count > 1) && ((unsigned long)dst & 2)) { 40 cx18_writew(cx, val2, dst); 41 count -= 2; 42 dst += 2; 43 } 44 while (count > 3) { 45 cx18_writel(cx, val4, dst); 46 count -= 4; 47 dst += 4; 48 } 49 if (count > 1) { 50 cx18_writew(cx, val2, dst); 51 count -= 2; 52 dst += 2; 53 } 54 if (count > 0) 55 cx18_writeb(cx, (u8) val, dst); 56 } 57 58 void cx18_sw1_irq_enable(struct cx18 *cx, u32 val) 59 { 60 cx18_write_reg_expect(cx, val, SW1_INT_STATUS, ~val, val); 61 cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) | val; 62 cx18_write_reg(cx, cx->sw1_irq_mask, SW1_INT_ENABLE_PCI); 63 } 64 65 void cx18_sw1_irq_disable(struct cx18 *cx, u32 val) 66 { 67 cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) & ~val; 68 cx18_write_reg(cx, cx->sw1_irq_mask, SW1_INT_ENABLE_PCI); 69 } 70 71 void cx18_sw2_irq_enable(struct cx18 *cx, u32 val) 72 { 73 cx18_write_reg_expect(cx, val, SW2_INT_STATUS, ~val, val); 74 cx->sw2_irq_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) | val; 75 cx18_write_reg(cx, cx->sw2_irq_mask, SW2_INT_ENABLE_PCI); 76 } 77 78 void cx18_sw2_irq_disable(struct cx18 *cx, u32 val) 79 { 80 cx->sw2_irq_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) & ~val; 81 cx18_write_reg(cx, cx->sw2_irq_mask, SW2_INT_ENABLE_PCI); 82 } 83 84 void cx18_sw2_irq_disable_cpu(struct cx18 *cx, u32 val) 85 { 86 u32 r; 87 r = cx18_read_reg(cx, SW2_INT_ENABLE_CPU); 88 cx18_write_reg(cx, r & ~val, SW2_INT_ENABLE_CPU); 89 } 90 91 void cx18_setup_page(struct cx18 *cx, u32 addr) 92 { 93 u32 val; 94 val = cx18_read_reg(cx, 0xD000F8); 95 val = (val & ~0x1f00) | ((addr >> 17) & 0x1f00); 96 cx18_write_reg(cx, val, 0xD000F8); 97 } 98