1b285192aSMauro Carvalho Chehab /* 2b285192aSMauro Carvalho Chehab * cx18 firmware functions 3b285192aSMauro Carvalho Chehab * 4b285192aSMauro Carvalho Chehab * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl> 5b285192aSMauro Carvalho Chehab * Copyright (C) 2008 Andy Walls <awalls@md.metrocast.net> 6b285192aSMauro Carvalho Chehab * 7b285192aSMauro Carvalho Chehab * This program is free software; you can redistribute it and/or modify 8b285192aSMauro Carvalho Chehab * it under the terms of the GNU General Public License as published by 9b285192aSMauro Carvalho Chehab * the Free Software Foundation; either version 2 of the License, or 10b285192aSMauro Carvalho Chehab * (at your option) any later version. 11b285192aSMauro Carvalho Chehab * 12b285192aSMauro Carvalho Chehab * This program is distributed in the hope that it will be useful, 13b285192aSMauro Carvalho Chehab * but WITHOUT ANY WARRANTY; without even the implied warranty of 14b285192aSMauro Carvalho Chehab * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15b285192aSMauro Carvalho Chehab * GNU General Public License for more details. 16b285192aSMauro Carvalho Chehab * 17b285192aSMauro Carvalho Chehab * You should have received a copy of the GNU General Public License 18b285192aSMauro Carvalho Chehab * along with this program; if not, write to the Free Software 19b285192aSMauro Carvalho Chehab * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 20b285192aSMauro Carvalho Chehab * 02111-1307 USA 21b285192aSMauro Carvalho Chehab */ 22b285192aSMauro Carvalho Chehab 23b285192aSMauro Carvalho Chehab #include "cx18-driver.h" 24b285192aSMauro Carvalho Chehab #include "cx18-io.h" 25b285192aSMauro Carvalho Chehab #include "cx18-scb.h" 26b285192aSMauro Carvalho Chehab #include "cx18-irq.h" 27b285192aSMauro Carvalho Chehab #include "cx18-firmware.h" 28b285192aSMauro Carvalho Chehab #include "cx18-cards.h" 29b285192aSMauro Carvalho Chehab #include <linux/firmware.h> 30b285192aSMauro Carvalho Chehab 31b285192aSMauro Carvalho Chehab #define CX18_PROC_SOFT_RESET 0xc70010 32b285192aSMauro Carvalho Chehab #define CX18_DDR_SOFT_RESET 0xc70014 33b285192aSMauro Carvalho Chehab #define CX18_CLOCK_SELECT1 0xc71000 34b285192aSMauro Carvalho Chehab #define CX18_CLOCK_SELECT2 0xc71004 35b285192aSMauro Carvalho Chehab #define CX18_HALF_CLOCK_SELECT1 0xc71008 36b285192aSMauro Carvalho Chehab #define CX18_HALF_CLOCK_SELECT2 0xc7100C 37b285192aSMauro Carvalho Chehab #define CX18_CLOCK_POLARITY1 0xc71010 38b285192aSMauro Carvalho Chehab #define CX18_CLOCK_POLARITY2 0xc71014 39b285192aSMauro Carvalho Chehab #define CX18_ADD_DELAY_ENABLE1 0xc71018 40b285192aSMauro Carvalho Chehab #define CX18_ADD_DELAY_ENABLE2 0xc7101C 41b285192aSMauro Carvalho Chehab #define CX18_CLOCK_ENABLE1 0xc71020 42b285192aSMauro Carvalho Chehab #define CX18_CLOCK_ENABLE2 0xc71024 43b285192aSMauro Carvalho Chehab 44b285192aSMauro Carvalho Chehab #define CX18_REG_BUS_TIMEOUT_EN 0xc72024 45b285192aSMauro Carvalho Chehab 46b285192aSMauro Carvalho Chehab #define CX18_FAST_CLOCK_PLL_INT 0xc78000 47b285192aSMauro Carvalho Chehab #define CX18_FAST_CLOCK_PLL_FRAC 0xc78004 48b285192aSMauro Carvalho Chehab #define CX18_FAST_CLOCK_PLL_POST 0xc78008 49b285192aSMauro Carvalho Chehab #define CX18_FAST_CLOCK_PLL_PRESCALE 0xc7800C 50b285192aSMauro Carvalho Chehab #define CX18_FAST_CLOCK_PLL_ADJUST_BANDWIDTH 0xc78010 51b285192aSMauro Carvalho Chehab 52b285192aSMauro Carvalho Chehab #define CX18_SLOW_CLOCK_PLL_INT 0xc78014 53b285192aSMauro Carvalho Chehab #define CX18_SLOW_CLOCK_PLL_FRAC 0xc78018 54b285192aSMauro Carvalho Chehab #define CX18_SLOW_CLOCK_PLL_POST 0xc7801C 55b285192aSMauro Carvalho Chehab #define CX18_MPEG_CLOCK_PLL_INT 0xc78040 56b285192aSMauro Carvalho Chehab #define CX18_MPEG_CLOCK_PLL_FRAC 0xc78044 57b285192aSMauro Carvalho Chehab #define CX18_MPEG_CLOCK_PLL_POST 0xc78048 58b285192aSMauro Carvalho Chehab #define CX18_PLL_POWER_DOWN 0xc78088 59b285192aSMauro Carvalho Chehab #define CX18_SW1_INT_STATUS 0xc73104 60b285192aSMauro Carvalho Chehab #define CX18_SW1_INT_ENABLE_PCI 0xc7311C 61b285192aSMauro Carvalho Chehab #define CX18_SW2_INT_SET 0xc73140 62b285192aSMauro Carvalho Chehab #define CX18_SW2_INT_STATUS 0xc73144 63b285192aSMauro Carvalho Chehab #define CX18_ADEC_CONTROL 0xc78120 64b285192aSMauro Carvalho Chehab 65b285192aSMauro Carvalho Chehab #define CX18_DDR_REQUEST_ENABLE 0xc80000 66b285192aSMauro Carvalho Chehab #define CX18_DDR_CHIP_CONFIG 0xc80004 67b285192aSMauro Carvalho Chehab #define CX18_DDR_REFRESH 0xc80008 68b285192aSMauro Carvalho Chehab #define CX18_DDR_TIMING1 0xc8000C 69b285192aSMauro Carvalho Chehab #define CX18_DDR_TIMING2 0xc80010 70b285192aSMauro Carvalho Chehab #define CX18_DDR_POWER_REG 0xc8001C 71b285192aSMauro Carvalho Chehab 72b285192aSMauro Carvalho Chehab #define CX18_DDR_TUNE_LANE 0xc80048 73b285192aSMauro Carvalho Chehab #define CX18_DDR_INITIAL_EMRS 0xc80054 74b285192aSMauro Carvalho Chehab #define CX18_DDR_MB_PER_ROW_7 0xc8009C 75b285192aSMauro Carvalho Chehab #define CX18_DDR_BASE_63_ADDR 0xc804FC 76b285192aSMauro Carvalho Chehab 77b285192aSMauro Carvalho Chehab #define CX18_WMB_CLIENT02 0xc90108 78b285192aSMauro Carvalho Chehab #define CX18_WMB_CLIENT05 0xc90114 79b285192aSMauro Carvalho Chehab #define CX18_WMB_CLIENT06 0xc90118 80b285192aSMauro Carvalho Chehab #define CX18_WMB_CLIENT07 0xc9011C 81b285192aSMauro Carvalho Chehab #define CX18_WMB_CLIENT08 0xc90120 82b285192aSMauro Carvalho Chehab #define CX18_WMB_CLIENT09 0xc90124 83b285192aSMauro Carvalho Chehab #define CX18_WMB_CLIENT10 0xc90128 84b285192aSMauro Carvalho Chehab #define CX18_WMB_CLIENT11 0xc9012C 85b285192aSMauro Carvalho Chehab #define CX18_WMB_CLIENT12 0xc90130 86b285192aSMauro Carvalho Chehab #define CX18_WMB_CLIENT13 0xc90134 87b285192aSMauro Carvalho Chehab #define CX18_WMB_CLIENT14 0xc90138 88b285192aSMauro Carvalho Chehab 89b285192aSMauro Carvalho Chehab #define CX18_DSP0_INTERRUPT_MASK 0xd0004C 90b285192aSMauro Carvalho Chehab 91b285192aSMauro Carvalho Chehab #define APU_ROM_SYNC1 0x6D676553 /* "mgeS" */ 92b285192aSMauro Carvalho Chehab #define APU_ROM_SYNC2 0x72646548 /* "rdeH" */ 93b285192aSMauro Carvalho Chehab 94b285192aSMauro Carvalho Chehab struct cx18_apu_rom_seghdr { 95b285192aSMauro Carvalho Chehab u32 sync1; 96b285192aSMauro Carvalho Chehab u32 sync2; 97b285192aSMauro Carvalho Chehab u32 addr; 98b285192aSMauro Carvalho Chehab u32 size; 99b285192aSMauro Carvalho Chehab }; 100b285192aSMauro Carvalho Chehab 101b285192aSMauro Carvalho Chehab static int load_cpu_fw_direct(const char *fn, u8 __iomem *mem, struct cx18 *cx) 102b285192aSMauro Carvalho Chehab { 103b285192aSMauro Carvalho Chehab const struct firmware *fw = NULL; 104b285192aSMauro Carvalho Chehab int i, j; 105b285192aSMauro Carvalho Chehab unsigned size; 106b285192aSMauro Carvalho Chehab u32 __iomem *dst = (u32 __iomem *)mem; 107b285192aSMauro Carvalho Chehab const u32 *src; 108b285192aSMauro Carvalho Chehab 109b285192aSMauro Carvalho Chehab if (request_firmware(&fw, fn, &cx->pci_dev->dev)) { 110b285192aSMauro Carvalho Chehab CX18_ERR("Unable to open firmware %s\n", fn); 111b285192aSMauro Carvalho Chehab CX18_ERR("Did you put the firmware in the hotplug firmware directory?\n"); 112b285192aSMauro Carvalho Chehab return -ENOMEM; 113b285192aSMauro Carvalho Chehab } 114b285192aSMauro Carvalho Chehab 115b285192aSMauro Carvalho Chehab src = (const u32 *)fw->data; 116b285192aSMauro Carvalho Chehab 117b285192aSMauro Carvalho Chehab for (i = 0; i < fw->size; i += 4096) { 118b285192aSMauro Carvalho Chehab cx18_setup_page(cx, i); 119b285192aSMauro Carvalho Chehab for (j = i; j < fw->size && j < i + 4096; j += 4) { 120b285192aSMauro Carvalho Chehab /* no need for endianness conversion on the ppc */ 121b285192aSMauro Carvalho Chehab cx18_raw_writel(cx, *src, dst); 122b285192aSMauro Carvalho Chehab if (cx18_raw_readl(cx, dst) != *src) { 123b285192aSMauro Carvalho Chehab CX18_ERR("Mismatch at offset %x\n", i); 124b285192aSMauro Carvalho Chehab release_firmware(fw); 125b285192aSMauro Carvalho Chehab cx18_setup_page(cx, 0); 126b285192aSMauro Carvalho Chehab return -EIO; 127b285192aSMauro Carvalho Chehab } 128b285192aSMauro Carvalho Chehab dst++; 129b285192aSMauro Carvalho Chehab src++; 130b285192aSMauro Carvalho Chehab } 131b285192aSMauro Carvalho Chehab } 132b285192aSMauro Carvalho Chehab if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags)) 133339f06c5SMauro Carvalho Chehab CX18_INFO("loaded %s firmware (%zu bytes)\n", fn, fw->size); 134b285192aSMauro Carvalho Chehab size = fw->size; 135b285192aSMauro Carvalho Chehab release_firmware(fw); 136b285192aSMauro Carvalho Chehab cx18_setup_page(cx, SCB_OFFSET); 137b285192aSMauro Carvalho Chehab return size; 138b285192aSMauro Carvalho Chehab } 139b285192aSMauro Carvalho Chehab 140b285192aSMauro Carvalho Chehab static int load_apu_fw_direct(const char *fn, u8 __iomem *dst, struct cx18 *cx, 141b285192aSMauro Carvalho Chehab u32 *entry_addr) 142b285192aSMauro Carvalho Chehab { 143b285192aSMauro Carvalho Chehab const struct firmware *fw = NULL; 144b285192aSMauro Carvalho Chehab int i, j; 145b285192aSMauro Carvalho Chehab unsigned size; 146b285192aSMauro Carvalho Chehab const u32 *src; 147b285192aSMauro Carvalho Chehab struct cx18_apu_rom_seghdr seghdr; 148b285192aSMauro Carvalho Chehab const u8 *vers; 149b285192aSMauro Carvalho Chehab u32 offset = 0; 150b285192aSMauro Carvalho Chehab u32 apu_version = 0; 151b285192aSMauro Carvalho Chehab int sz; 152b285192aSMauro Carvalho Chehab 153b285192aSMauro Carvalho Chehab if (request_firmware(&fw, fn, &cx->pci_dev->dev)) { 154b285192aSMauro Carvalho Chehab CX18_ERR("unable to open firmware %s\n", fn); 155b285192aSMauro Carvalho Chehab CX18_ERR("did you put the firmware in the hotplug firmware directory?\n"); 156b285192aSMauro Carvalho Chehab cx18_setup_page(cx, 0); 157b285192aSMauro Carvalho Chehab return -ENOMEM; 158b285192aSMauro Carvalho Chehab } 159b285192aSMauro Carvalho Chehab 160b285192aSMauro Carvalho Chehab *entry_addr = 0; 161b285192aSMauro Carvalho Chehab src = (const u32 *)fw->data; 162b285192aSMauro Carvalho Chehab vers = fw->data + sizeof(seghdr); 163b285192aSMauro Carvalho Chehab sz = fw->size; 164b285192aSMauro Carvalho Chehab 165b285192aSMauro Carvalho Chehab apu_version = (vers[0] << 24) | (vers[4] << 16) | vers[32]; 166b285192aSMauro Carvalho Chehab while (offset + sizeof(seghdr) < fw->size) { 16739fd4460SHans Verkuil const __le32 *shptr = (__force __le32 *)src + offset / 4; 168b285192aSMauro Carvalho Chehab 169b285192aSMauro Carvalho Chehab seghdr.sync1 = le32_to_cpu(shptr[0]); 170b285192aSMauro Carvalho Chehab seghdr.sync2 = le32_to_cpu(shptr[1]); 171b285192aSMauro Carvalho Chehab seghdr.addr = le32_to_cpu(shptr[2]); 172b285192aSMauro Carvalho Chehab seghdr.size = le32_to_cpu(shptr[3]); 173b285192aSMauro Carvalho Chehab 174b285192aSMauro Carvalho Chehab offset += sizeof(seghdr); 175b285192aSMauro Carvalho Chehab if (seghdr.sync1 != APU_ROM_SYNC1 || 176b285192aSMauro Carvalho Chehab seghdr.sync2 != APU_ROM_SYNC2) { 177b285192aSMauro Carvalho Chehab offset += seghdr.size; 178b285192aSMauro Carvalho Chehab continue; 179b285192aSMauro Carvalho Chehab } 180b285192aSMauro Carvalho Chehab CX18_DEBUG_INFO("load segment %x-%x\n", seghdr.addr, 181b285192aSMauro Carvalho Chehab seghdr.addr + seghdr.size - 1); 182b285192aSMauro Carvalho Chehab if (*entry_addr == 0) 183b285192aSMauro Carvalho Chehab *entry_addr = seghdr.addr; 184b285192aSMauro Carvalho Chehab if (offset + seghdr.size > sz) 185b285192aSMauro Carvalho Chehab break; 186b285192aSMauro Carvalho Chehab for (i = 0; i < seghdr.size; i += 4096) { 187b285192aSMauro Carvalho Chehab cx18_setup_page(cx, seghdr.addr + i); 188b285192aSMauro Carvalho Chehab for (j = i; j < seghdr.size && j < i + 4096; j += 4) { 189b285192aSMauro Carvalho Chehab /* no need for endianness conversion on the ppc */ 190b285192aSMauro Carvalho Chehab cx18_raw_writel(cx, src[(offset + j) / 4], 191b285192aSMauro Carvalho Chehab dst + seghdr.addr + j); 192b285192aSMauro Carvalho Chehab if (cx18_raw_readl(cx, dst + seghdr.addr + j) 193b285192aSMauro Carvalho Chehab != src[(offset + j) / 4]) { 194b285192aSMauro Carvalho Chehab CX18_ERR("Mismatch at offset %x\n", 195b285192aSMauro Carvalho Chehab offset + j); 196b285192aSMauro Carvalho Chehab release_firmware(fw); 197b285192aSMauro Carvalho Chehab cx18_setup_page(cx, 0); 198b285192aSMauro Carvalho Chehab return -EIO; 199b285192aSMauro Carvalho Chehab } 200b285192aSMauro Carvalho Chehab } 201b285192aSMauro Carvalho Chehab } 202b285192aSMauro Carvalho Chehab offset += seghdr.size; 203b285192aSMauro Carvalho Chehab } 204b285192aSMauro Carvalho Chehab if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags)) 205339f06c5SMauro Carvalho Chehab CX18_INFO("loaded %s firmware V%08x (%zu bytes)\n", 206b285192aSMauro Carvalho Chehab fn, apu_version, fw->size); 207b285192aSMauro Carvalho Chehab size = fw->size; 208b285192aSMauro Carvalho Chehab release_firmware(fw); 209b285192aSMauro Carvalho Chehab cx18_setup_page(cx, 0); 210b285192aSMauro Carvalho Chehab return size; 211b285192aSMauro Carvalho Chehab } 212b285192aSMauro Carvalho Chehab 213b285192aSMauro Carvalho Chehab void cx18_halt_firmware(struct cx18 *cx) 214b285192aSMauro Carvalho Chehab { 215b285192aSMauro Carvalho Chehab CX18_DEBUG_INFO("Preparing for firmware halt.\n"); 216b285192aSMauro Carvalho Chehab cx18_write_reg_expect(cx, 0x000F000F, CX18_PROC_SOFT_RESET, 217b285192aSMauro Carvalho Chehab 0x0000000F, 0x000F000F); 218b285192aSMauro Carvalho Chehab cx18_write_reg_expect(cx, 0x00020002, CX18_ADEC_CONTROL, 219b285192aSMauro Carvalho Chehab 0x00000002, 0x00020002); 220b285192aSMauro Carvalho Chehab } 221b285192aSMauro Carvalho Chehab 222b285192aSMauro Carvalho Chehab void cx18_init_power(struct cx18 *cx, int lowpwr) 223b285192aSMauro Carvalho Chehab { 224b285192aSMauro Carvalho Chehab /* power-down Spare and AOM PLLs */ 225b285192aSMauro Carvalho Chehab /* power-up fast, slow and mpeg PLLs */ 226b285192aSMauro Carvalho Chehab cx18_write_reg(cx, 0x00000008, CX18_PLL_POWER_DOWN); 227b285192aSMauro Carvalho Chehab 228b285192aSMauro Carvalho Chehab /* ADEC out of sleep */ 229b285192aSMauro Carvalho Chehab cx18_write_reg_expect(cx, 0x00020000, CX18_ADEC_CONTROL, 230b285192aSMauro Carvalho Chehab 0x00000000, 0x00020002); 231b285192aSMauro Carvalho Chehab 232b285192aSMauro Carvalho Chehab /* 233b285192aSMauro Carvalho Chehab * The PLL parameters are based on the external crystal frequency that 234b285192aSMauro Carvalho Chehab * would ideally be: 235b285192aSMauro Carvalho Chehab * 236b285192aSMauro Carvalho Chehab * NTSC Color subcarrier freq * 8 = 237b285192aSMauro Carvalho Chehab * 4.5 MHz/286 * 455/2 * 8 = 28.63636363... MHz 238b285192aSMauro Carvalho Chehab * 239b285192aSMauro Carvalho Chehab * The accidents of history and rationale that explain from where this 240b285192aSMauro Carvalho Chehab * combination of magic numbers originate can be found in: 241b285192aSMauro Carvalho Chehab * 242b285192aSMauro Carvalho Chehab * [1] Abrahams, I. C., "Choice of Chrominance Subcarrier Frequency in 243b285192aSMauro Carvalho Chehab * the NTSC Standards", Proceedings of the I-R-E, January 1954, pp 79-80 244b285192aSMauro Carvalho Chehab * 245b285192aSMauro Carvalho Chehab * [2] Abrahams, I. C., "The 'Frequency Interleaving' Principle in the 246b285192aSMauro Carvalho Chehab * NTSC Standards", Proceedings of the I-R-E, January 1954, pp 81-83 247b285192aSMauro Carvalho Chehab * 248b285192aSMauro Carvalho Chehab * As Mike Bradley has rightly pointed out, it's not the exact crystal 249b285192aSMauro Carvalho Chehab * frequency that matters, only that all parts of the driver and 250b285192aSMauro Carvalho Chehab * firmware are using the same value (close to the ideal value). 251b285192aSMauro Carvalho Chehab * 252b285192aSMauro Carvalho Chehab * Since I have a strong suspicion that, if the firmware ever assumes a 253b285192aSMauro Carvalho Chehab * crystal value at all, it will assume 28.636360 MHz, the crystal 254b285192aSMauro Carvalho Chehab * freq used in calculations in this driver will be: 255b285192aSMauro Carvalho Chehab * 256b285192aSMauro Carvalho Chehab * xtal_freq = 28.636360 MHz 257b285192aSMauro Carvalho Chehab * 258b285192aSMauro Carvalho Chehab * an error of less than 0.13 ppm which is way, way better than any off 259b285192aSMauro Carvalho Chehab * the shelf crystal will have for accuracy anyway. 260b285192aSMauro Carvalho Chehab * 261b285192aSMauro Carvalho Chehab * Below I aim to run the PLLs' VCOs near 400 MHz to minimze errors. 262b285192aSMauro Carvalho Chehab * 263b285192aSMauro Carvalho Chehab * Many thanks to Jeff Campbell and Mike Bradley for their extensive 264b285192aSMauro Carvalho Chehab * investigation, experimentation, testing, and suggested solutions of 265b285192aSMauro Carvalho Chehab * of audio/video sync problems with SVideo and CVBS captures. 266b285192aSMauro Carvalho Chehab */ 267b285192aSMauro Carvalho Chehab 268b285192aSMauro Carvalho Chehab /* the fast clock is at 200/245 MHz */ 269b285192aSMauro Carvalho Chehab /* 1 * xtal_freq * 0x0d.f7df9b8 / 2 = 200 MHz: 400 MHz pre post-divide*/ 270b285192aSMauro Carvalho Chehab /* 1 * xtal_freq * 0x11.1c71eb8 / 2 = 245 MHz: 490 MHz pre post-divide*/ 271b285192aSMauro Carvalho Chehab cx18_write_reg(cx, lowpwr ? 0xD : 0x11, CX18_FAST_CLOCK_PLL_INT); 272b285192aSMauro Carvalho Chehab cx18_write_reg(cx, lowpwr ? 0x1EFBF37 : 0x038E3D7, 273b285192aSMauro Carvalho Chehab CX18_FAST_CLOCK_PLL_FRAC); 274b285192aSMauro Carvalho Chehab 275b285192aSMauro Carvalho Chehab cx18_write_reg(cx, 2, CX18_FAST_CLOCK_PLL_POST); 276b285192aSMauro Carvalho Chehab cx18_write_reg(cx, 1, CX18_FAST_CLOCK_PLL_PRESCALE); 277b285192aSMauro Carvalho Chehab cx18_write_reg(cx, 4, CX18_FAST_CLOCK_PLL_ADJUST_BANDWIDTH); 278b285192aSMauro Carvalho Chehab 279b285192aSMauro Carvalho Chehab /* set slow clock to 125/120 MHz */ 280b285192aSMauro Carvalho Chehab /* xtal_freq * 0x0d.1861a20 / 3 = 125 MHz: 375 MHz before post-divide */ 281b285192aSMauro Carvalho Chehab /* xtal_freq * 0x0c.92493f8 / 3 = 120 MHz: 360 MHz before post-divide */ 282b285192aSMauro Carvalho Chehab cx18_write_reg(cx, lowpwr ? 0xD : 0xC, CX18_SLOW_CLOCK_PLL_INT); 283b285192aSMauro Carvalho Chehab cx18_write_reg(cx, lowpwr ? 0x30C344 : 0x124927F, 284b285192aSMauro Carvalho Chehab CX18_SLOW_CLOCK_PLL_FRAC); 285b285192aSMauro Carvalho Chehab cx18_write_reg(cx, 3, CX18_SLOW_CLOCK_PLL_POST); 286b285192aSMauro Carvalho Chehab 287b285192aSMauro Carvalho Chehab /* mpeg clock pll 54MHz */ 288b285192aSMauro Carvalho Chehab /* xtal_freq * 0xf.15f17f0 / 8 = 54 MHz: 432 MHz before post-divide */ 289b285192aSMauro Carvalho Chehab cx18_write_reg(cx, 0xF, CX18_MPEG_CLOCK_PLL_INT); 290b285192aSMauro Carvalho Chehab cx18_write_reg(cx, 0x2BE2FE, CX18_MPEG_CLOCK_PLL_FRAC); 291b285192aSMauro Carvalho Chehab cx18_write_reg(cx, 8, CX18_MPEG_CLOCK_PLL_POST); 292b285192aSMauro Carvalho Chehab 293b285192aSMauro Carvalho Chehab /* Defaults */ 294b285192aSMauro Carvalho Chehab /* APU = SC or SC/2 = 125/62.5 */ 295b285192aSMauro Carvalho Chehab /* EPU = SC = 125 */ 296b285192aSMauro Carvalho Chehab /* DDR = FC = 180 */ 297b285192aSMauro Carvalho Chehab /* ENC = SC = 125 */ 298b285192aSMauro Carvalho Chehab /* AI1 = SC = 125 */ 299b285192aSMauro Carvalho Chehab /* VIM2 = disabled */ 300b285192aSMauro Carvalho Chehab /* PCI = FC/2 = 90 */ 301b285192aSMauro Carvalho Chehab /* AI2 = disabled */ 302b285192aSMauro Carvalho Chehab /* DEMUX = disabled */ 303b285192aSMauro Carvalho Chehab /* AO = SC/2 = 62.5 */ 304b285192aSMauro Carvalho Chehab /* SER = 54MHz */ 305b285192aSMauro Carvalho Chehab /* VFC = disabled */ 306b285192aSMauro Carvalho Chehab /* USB = disabled */ 307b285192aSMauro Carvalho Chehab 308b285192aSMauro Carvalho Chehab if (lowpwr) { 309b285192aSMauro Carvalho Chehab cx18_write_reg_expect(cx, 0xFFFF0020, CX18_CLOCK_SELECT1, 310b285192aSMauro Carvalho Chehab 0x00000020, 0xFFFFFFFF); 311b285192aSMauro Carvalho Chehab cx18_write_reg_expect(cx, 0xFFFF0004, CX18_CLOCK_SELECT2, 312b285192aSMauro Carvalho Chehab 0x00000004, 0xFFFFFFFF); 313b285192aSMauro Carvalho Chehab } else { 314b285192aSMauro Carvalho Chehab /* This doesn't explicitly set every clock select */ 315b285192aSMauro Carvalho Chehab cx18_write_reg_expect(cx, 0x00060004, CX18_CLOCK_SELECT1, 316b285192aSMauro Carvalho Chehab 0x00000004, 0x00060006); 317b285192aSMauro Carvalho Chehab cx18_write_reg_expect(cx, 0x00060006, CX18_CLOCK_SELECT2, 318b285192aSMauro Carvalho Chehab 0x00000006, 0x00060006); 319b285192aSMauro Carvalho Chehab } 320b285192aSMauro Carvalho Chehab 321b285192aSMauro Carvalho Chehab cx18_write_reg_expect(cx, 0xFFFF0002, CX18_HALF_CLOCK_SELECT1, 322b285192aSMauro Carvalho Chehab 0x00000002, 0xFFFFFFFF); 323b285192aSMauro Carvalho Chehab cx18_write_reg_expect(cx, 0xFFFF0104, CX18_HALF_CLOCK_SELECT2, 324b285192aSMauro Carvalho Chehab 0x00000104, 0xFFFFFFFF); 325b285192aSMauro Carvalho Chehab cx18_write_reg_expect(cx, 0xFFFF9026, CX18_CLOCK_ENABLE1, 326b285192aSMauro Carvalho Chehab 0x00009026, 0xFFFFFFFF); 327b285192aSMauro Carvalho Chehab cx18_write_reg_expect(cx, 0xFFFF3105, CX18_CLOCK_ENABLE2, 328b285192aSMauro Carvalho Chehab 0x00003105, 0xFFFFFFFF); 329b285192aSMauro Carvalho Chehab } 330b285192aSMauro Carvalho Chehab 331b285192aSMauro Carvalho Chehab void cx18_init_memory(struct cx18 *cx) 332b285192aSMauro Carvalho Chehab { 333b285192aSMauro Carvalho Chehab cx18_msleep_timeout(10, 0); 334b285192aSMauro Carvalho Chehab cx18_write_reg_expect(cx, 0x00010000, CX18_DDR_SOFT_RESET, 335b285192aSMauro Carvalho Chehab 0x00000000, 0x00010001); 336b285192aSMauro Carvalho Chehab cx18_msleep_timeout(10, 0); 337b285192aSMauro Carvalho Chehab 338b285192aSMauro Carvalho Chehab cx18_write_reg(cx, cx->card->ddr.chip_config, CX18_DDR_CHIP_CONFIG); 339b285192aSMauro Carvalho Chehab 340b285192aSMauro Carvalho Chehab cx18_msleep_timeout(10, 0); 341b285192aSMauro Carvalho Chehab 342b285192aSMauro Carvalho Chehab cx18_write_reg(cx, cx->card->ddr.refresh, CX18_DDR_REFRESH); 343b285192aSMauro Carvalho Chehab cx18_write_reg(cx, cx->card->ddr.timing1, CX18_DDR_TIMING1); 344b285192aSMauro Carvalho Chehab cx18_write_reg(cx, cx->card->ddr.timing2, CX18_DDR_TIMING2); 345b285192aSMauro Carvalho Chehab 346b285192aSMauro Carvalho Chehab cx18_msleep_timeout(10, 0); 347b285192aSMauro Carvalho Chehab 348b285192aSMauro Carvalho Chehab /* Initialize DQS pad time */ 349b285192aSMauro Carvalho Chehab cx18_write_reg(cx, cx->card->ddr.tune_lane, CX18_DDR_TUNE_LANE); 350b285192aSMauro Carvalho Chehab cx18_write_reg(cx, cx->card->ddr.initial_emrs, CX18_DDR_INITIAL_EMRS); 351b285192aSMauro Carvalho Chehab 352b285192aSMauro Carvalho Chehab cx18_msleep_timeout(10, 0); 353b285192aSMauro Carvalho Chehab 354b285192aSMauro Carvalho Chehab cx18_write_reg_expect(cx, 0x00020000, CX18_DDR_SOFT_RESET, 355b285192aSMauro Carvalho Chehab 0x00000000, 0x00020002); 356b285192aSMauro Carvalho Chehab cx18_msleep_timeout(10, 0); 357b285192aSMauro Carvalho Chehab 358b285192aSMauro Carvalho Chehab /* use power-down mode when idle */ 359b285192aSMauro Carvalho Chehab cx18_write_reg(cx, 0x00000010, CX18_DDR_POWER_REG); 360b285192aSMauro Carvalho Chehab 361b285192aSMauro Carvalho Chehab cx18_write_reg_expect(cx, 0x00010001, CX18_REG_BUS_TIMEOUT_EN, 362b285192aSMauro Carvalho Chehab 0x00000001, 0x00010001); 363b285192aSMauro Carvalho Chehab 364b285192aSMauro Carvalho Chehab cx18_write_reg(cx, 0x48, CX18_DDR_MB_PER_ROW_7); 365b285192aSMauro Carvalho Chehab cx18_write_reg(cx, 0xE0000, CX18_DDR_BASE_63_ADDR); 366b285192aSMauro Carvalho Chehab 367b285192aSMauro Carvalho Chehab cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT02); /* AO */ 368b285192aSMauro Carvalho Chehab cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT09); /* AI2 */ 369b285192aSMauro Carvalho Chehab cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT05); /* VIM1 */ 370b285192aSMauro Carvalho Chehab cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT06); /* AI1 */ 371b285192aSMauro Carvalho Chehab cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT07); /* 3D comb */ 372b285192aSMauro Carvalho Chehab cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT10); /* ME */ 373b285192aSMauro Carvalho Chehab cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT12); /* ENC */ 374b285192aSMauro Carvalho Chehab cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT13); /* PK */ 375b285192aSMauro Carvalho Chehab cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT11); /* RC */ 376b285192aSMauro Carvalho Chehab cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT14); /* AVO */ 377b285192aSMauro Carvalho Chehab } 378b285192aSMauro Carvalho Chehab 379b285192aSMauro Carvalho Chehab #define CX18_CPU_FIRMWARE "v4l-cx23418-cpu.fw" 380b285192aSMauro Carvalho Chehab #define CX18_APU_FIRMWARE "v4l-cx23418-apu.fw" 381b285192aSMauro Carvalho Chehab 382b285192aSMauro Carvalho Chehab int cx18_firmware_init(struct cx18 *cx) 383b285192aSMauro Carvalho Chehab { 384b285192aSMauro Carvalho Chehab u32 fw_entry_addr; 385b285192aSMauro Carvalho Chehab int sz, retries; 386b285192aSMauro Carvalho Chehab u32 api_args[MAX_MB_ARGUMENTS]; 387b285192aSMauro Carvalho Chehab 388b285192aSMauro Carvalho Chehab /* Allow chip to control CLKRUN */ 389b285192aSMauro Carvalho Chehab cx18_write_reg(cx, 0x5, CX18_DSP0_INTERRUPT_MASK); 390b285192aSMauro Carvalho Chehab 391b285192aSMauro Carvalho Chehab /* Stop the firmware */ 392b285192aSMauro Carvalho Chehab cx18_write_reg_expect(cx, 0x000F000F, CX18_PROC_SOFT_RESET, 393b285192aSMauro Carvalho Chehab 0x0000000F, 0x000F000F); 394b285192aSMauro Carvalho Chehab 395b285192aSMauro Carvalho Chehab cx18_msleep_timeout(1, 0); 396b285192aSMauro Carvalho Chehab 397b285192aSMauro Carvalho Chehab /* If the CPU is still running */ 398b285192aSMauro Carvalho Chehab if ((cx18_read_reg(cx, CX18_PROC_SOFT_RESET) & 8) == 0) { 399b285192aSMauro Carvalho Chehab CX18_ERR("%s: couldn't stop CPU to load firmware\n", __func__); 400b285192aSMauro Carvalho Chehab return -EIO; 401b285192aSMauro Carvalho Chehab } 402b285192aSMauro Carvalho Chehab 403b285192aSMauro Carvalho Chehab cx18_sw1_irq_enable(cx, IRQ_CPU_TO_EPU | IRQ_APU_TO_EPU); 404b285192aSMauro Carvalho Chehab cx18_sw2_irq_enable(cx, IRQ_CPU_TO_EPU_ACK | IRQ_APU_TO_EPU_ACK); 405b285192aSMauro Carvalho Chehab 406b285192aSMauro Carvalho Chehab sz = load_cpu_fw_direct(CX18_CPU_FIRMWARE, cx->enc_mem, cx); 407b285192aSMauro Carvalho Chehab if (sz <= 0) 408b285192aSMauro Carvalho Chehab return sz; 409b285192aSMauro Carvalho Chehab 410b285192aSMauro Carvalho Chehab /* The SCB & IPC area *must* be correct before starting the firmwares */ 411b285192aSMauro Carvalho Chehab cx18_init_scb(cx); 412b285192aSMauro Carvalho Chehab 413b285192aSMauro Carvalho Chehab fw_entry_addr = 0; 414b285192aSMauro Carvalho Chehab sz = load_apu_fw_direct(CX18_APU_FIRMWARE, cx->enc_mem, cx, 415b285192aSMauro Carvalho Chehab &fw_entry_addr); 416b285192aSMauro Carvalho Chehab if (sz <= 0) 417b285192aSMauro Carvalho Chehab return sz; 418b285192aSMauro Carvalho Chehab 419b285192aSMauro Carvalho Chehab /* Start the CPU. The CPU will take care of the APU for us. */ 420b285192aSMauro Carvalho Chehab cx18_write_reg_expect(cx, 0x00080000, CX18_PROC_SOFT_RESET, 421b285192aSMauro Carvalho Chehab 0x00000000, 0x00080008); 422b285192aSMauro Carvalho Chehab 423b285192aSMauro Carvalho Chehab /* Wait up to 500 ms for the APU to come out of reset */ 424b285192aSMauro Carvalho Chehab for (retries = 0; 425b285192aSMauro Carvalho Chehab retries < 50 && (cx18_read_reg(cx, CX18_PROC_SOFT_RESET) & 1) == 1; 426b285192aSMauro Carvalho Chehab retries++) 427b285192aSMauro Carvalho Chehab cx18_msleep_timeout(10, 0); 428b285192aSMauro Carvalho Chehab 429b285192aSMauro Carvalho Chehab cx18_msleep_timeout(200, 0); 430b285192aSMauro Carvalho Chehab 431b285192aSMauro Carvalho Chehab if (retries == 50 && 432b285192aSMauro Carvalho Chehab (cx18_read_reg(cx, CX18_PROC_SOFT_RESET) & 1) == 1) { 433b285192aSMauro Carvalho Chehab CX18_ERR("Could not start the CPU\n"); 434b285192aSMauro Carvalho Chehab return -EIO; 435b285192aSMauro Carvalho Chehab } 436b285192aSMauro Carvalho Chehab 437b285192aSMauro Carvalho Chehab /* 438b285192aSMauro Carvalho Chehab * The CPU had once before set up to receive an interrupt for it's 439b285192aSMauro Carvalho Chehab * outgoing IRQ_CPU_TO_EPU_ACK to us. If it ever does this, we get an 440b285192aSMauro Carvalho Chehab * interrupt when it sends us an ack, but by the time we process it, 441b285192aSMauro Carvalho Chehab * that flag in the SW2 status register has been cleared by the CPU 442b285192aSMauro Carvalho Chehab * firmware. We'll prevent that not so useful condition from happening 443b285192aSMauro Carvalho Chehab * by clearing the CPU's interrupt enables for Ack IRQ's we want to 444b285192aSMauro Carvalho Chehab * process. 445b285192aSMauro Carvalho Chehab */ 446b285192aSMauro Carvalho Chehab cx18_sw2_irq_disable_cpu(cx, IRQ_CPU_TO_EPU_ACK | IRQ_APU_TO_EPU_ACK); 447b285192aSMauro Carvalho Chehab 448b285192aSMauro Carvalho Chehab /* Try a benign command to see if the CPU is alive and well */ 449b285192aSMauro Carvalho Chehab sz = cx18_vapi_result(cx, api_args, CX18_CPU_DEBUG_PEEK32, 1, 0); 450b285192aSMauro Carvalho Chehab if (sz < 0) 451b285192aSMauro Carvalho Chehab return sz; 452b285192aSMauro Carvalho Chehab 453b285192aSMauro Carvalho Chehab /* initialize GPIO */ 454b285192aSMauro Carvalho Chehab cx18_write_reg_expect(cx, 0x14001400, 0xc78110, 0x00001400, 0x14001400); 455b285192aSMauro Carvalho Chehab return 0; 456b285192aSMauro Carvalho Chehab } 457b285192aSMauro Carvalho Chehab 458b285192aSMauro Carvalho Chehab MODULE_FIRMWARE(CX18_CPU_FIRMWARE); 459b285192aSMauro Carvalho Chehab MODULE_FIRMWARE(CX18_APU_FIRMWARE); 460