1 /* 2 * cx18 ADEC firmware functions 3 * 4 * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl> 5 * Copyright (C) 2008 Andy Walls <awalls@md.metrocast.net> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 2 10 * of the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 20 * 02110-1301, USA. 21 */ 22 23 #include "cx18-driver.h" 24 #include "cx18-io.h" 25 #include <linux/firmware.h> 26 27 #define CX18_AUDIO_ENABLE 0xc72014 28 #define CX18_AI1_MUX_MASK 0x30 29 #define CX18_AI1_MUX_I2S1 0x00 30 #define CX18_AI1_MUX_I2S2 0x10 31 #define CX18_AI1_MUX_843_I2S 0x20 32 #define CX18_AI1_MUX_INVALID 0x30 33 34 #define FWFILE "v4l-cx23418-dig.fw" 35 36 static int cx18_av_verifyfw(struct cx18 *cx, const struct firmware *fw) 37 { 38 struct v4l2_subdev *sd = &cx->av_state.sd; 39 int ret = 0; 40 const u8 *data; 41 u32 size; 42 int addr; 43 u32 expected, dl_control; 44 45 /* Ensure we put the 8051 in reset and enable firmware upload mode */ 46 dl_control = cx18_av_read4(cx, CXADEC_DL_CTL); 47 do { 48 dl_control &= 0x00ffffff; 49 dl_control |= 0x0f000000; 50 cx18_av_write4_noretry(cx, CXADEC_DL_CTL, dl_control); 51 dl_control = cx18_av_read4(cx, CXADEC_DL_CTL); 52 } while ((dl_control & 0xff000000) != 0x0f000000); 53 54 /* Read and auto increment until at address 0x0000 */ 55 while (dl_control & 0x3fff) 56 dl_control = cx18_av_read4(cx, CXADEC_DL_CTL); 57 58 data = fw->data; 59 size = fw->size; 60 for (addr = 0; addr < size; addr++) { 61 dl_control &= 0xffff3fff; /* ignore top 2 bits of address */ 62 expected = 0x0f000000 | ((u32)data[addr] << 16) | addr; 63 if (expected != dl_control) { 64 CX18_ERR_DEV(sd, "verification of %s firmware load failed: expected %#010x got %#010x\n", 65 FWFILE, expected, dl_control); 66 ret = -EIO; 67 break; 68 } 69 dl_control = cx18_av_read4(cx, CXADEC_DL_CTL); 70 } 71 if (ret == 0) 72 CX18_INFO_DEV(sd, "verified load of %s firmware (%d bytes)\n", 73 FWFILE, size); 74 return ret; 75 } 76 77 int cx18_av_loadfw(struct cx18 *cx) 78 { 79 struct v4l2_subdev *sd = &cx->av_state.sd; 80 const struct firmware *fw = NULL; 81 u32 size; 82 u32 u, v; 83 const u8 *ptr; 84 int i; 85 int retries1 = 0; 86 87 if (request_firmware(&fw, FWFILE, &cx->pci_dev->dev) != 0) { 88 CX18_ERR_DEV(sd, "unable to open firmware %s\n", FWFILE); 89 return -EINVAL; 90 } 91 92 /* The firmware load often has byte errors, so allow for several 93 retries, both at byte level and at the firmware load level. */ 94 while (retries1 < 5) { 95 cx18_av_write4_expect(cx, CXADEC_CHIP_CTRL, 0x00010000, 96 0x00008430, 0xffffffff); /* cx25843 */ 97 cx18_av_write_expect(cx, CXADEC_STD_DET_CTL, 0xf6, 0xf6, 0xff); 98 99 /* Reset the Mako core, Register is alias of CXADEC_CHIP_CTRL */ 100 cx18_av_write4_expect(cx, 0x8100, 0x00010000, 101 0x00008430, 0xffffffff); /* cx25843 */ 102 103 /* Put the 8051 in reset and enable firmware upload */ 104 cx18_av_write4_noretry(cx, CXADEC_DL_CTL, 0x0F000000); 105 106 ptr = fw->data; 107 size = fw->size; 108 109 for (i = 0; i < size; i++) { 110 u32 dl_control = 0x0F000000 | i | ((u32)ptr[i] << 16); 111 u32 value = 0; 112 int retries2; 113 int unrec_err = 0; 114 115 for (retries2 = 0; retries2 < CX18_MAX_MMIO_WR_RETRIES; 116 retries2++) { 117 cx18_av_write4_noretry(cx, CXADEC_DL_CTL, 118 dl_control); 119 udelay(10); 120 value = cx18_av_read4(cx, CXADEC_DL_CTL); 121 if (value == dl_control) 122 break; 123 /* Check if we can correct the byte by changing 124 the address. We can only write the lower 125 address byte of the address. */ 126 if ((value & 0x3F00) != (dl_control & 0x3F00)) { 127 unrec_err = 1; 128 break; 129 } 130 } 131 if (unrec_err || retries2 >= CX18_MAX_MMIO_WR_RETRIES) 132 break; 133 } 134 if (i == size) 135 break; 136 retries1++; 137 } 138 if (retries1 >= 5) { 139 CX18_ERR_DEV(sd, "unable to load firmware %s\n", FWFILE); 140 release_firmware(fw); 141 return -EIO; 142 } 143 144 cx18_av_write4_expect(cx, CXADEC_DL_CTL, 145 0x03000000 | fw->size, 0x03000000, 0x13000000); 146 147 CX18_INFO_DEV(sd, "loaded %s firmware (%d bytes)\n", FWFILE, size); 148 149 if (cx18_av_verifyfw(cx, fw) == 0) 150 cx18_av_write4_expect(cx, CXADEC_DL_CTL, 151 0x13000000 | fw->size, 0x13000000, 0x13000000); 152 153 /* Output to the 416 */ 154 cx18_av_and_or4(cx, CXADEC_PIN_CTRL1, ~0, 0x78000); 155 156 /* Audio input control 1 set to Sony mode */ 157 /* Audio output input 2 is 0 for slave operation input */ 158 /* 0xC4000914[5]: 0 = left sample on WS=0, 1 = left sample on WS=1 */ 159 /* 0xC4000914[7]: 0 = Philips mode, 1 = Sony mode (1st SCK rising edge 160 after WS transition for first bit of audio word. */ 161 cx18_av_write4(cx, CXADEC_I2S_IN_CTL, 0x000000A0); 162 163 /* Audio output control 1 is set to Sony mode */ 164 /* Audio output control 2 is set to 1 for master mode */ 165 /* 0xC4000918[5]: 0 = left sample on WS=0, 1 = left sample on WS=1 */ 166 /* 0xC4000918[7]: 0 = Philips mode, 1 = Sony mode (1st SCK rising edge 167 after WS transition for first bit of audio word. */ 168 /* 0xC4000918[8]: 0 = slave operation, 1 = master (SCK_OUT and WS_OUT 169 are generated) */ 170 cx18_av_write4(cx, CXADEC_I2S_OUT_CTL, 0x000001A0); 171 172 /* set alt I2s master clock to /0x16 and enable alt divider i2s 173 passthrough */ 174 cx18_av_write4(cx, CXADEC_PIN_CFG3, 0x5600B687); 175 176 cx18_av_write4_expect(cx, CXADEC_STD_DET_CTL, 0x000000F6, 0x000000F6, 177 0x3F00FFFF); 178 /* CxDevWrReg(CXADEC_STD_DET_CTL, 0x000000FF); */ 179 180 /* Set bit 0 in register 0x9CC to signify that this is MiniMe. */ 181 /* Register 0x09CC is defined by the Merlin firmware, and doesn't 182 have a name in the spec. */ 183 cx18_av_write4(cx, 0x09CC, 1); 184 185 v = cx18_read_reg(cx, CX18_AUDIO_ENABLE); 186 /* If bit 11 is 1, clear bit 10 */ 187 if (v & 0x800) 188 cx18_write_reg_expect(cx, v & 0xFFFFFBFF, CX18_AUDIO_ENABLE, 189 0, 0x400); 190 191 /* Toggle the AI1 MUX */ 192 v = cx18_read_reg(cx, CX18_AUDIO_ENABLE); 193 u = v & CX18_AI1_MUX_MASK; 194 v &= ~CX18_AI1_MUX_MASK; 195 if (u == CX18_AI1_MUX_843_I2S || u == CX18_AI1_MUX_INVALID) { 196 /* Switch to I2S1 */ 197 v |= CX18_AI1_MUX_I2S1; 198 cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE, 199 v, CX18_AI1_MUX_MASK); 200 /* Switch back to the A/V decoder core I2S output */ 201 v = (v & ~CX18_AI1_MUX_MASK) | CX18_AI1_MUX_843_I2S; 202 } else { 203 /* Switch to the A/V decoder core I2S output */ 204 v |= CX18_AI1_MUX_843_I2S; 205 cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE, 206 v, CX18_AI1_MUX_MASK); 207 /* Switch back to I2S1 or I2S2 */ 208 v = (v & ~CX18_AI1_MUX_MASK) | u; 209 } 210 cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE, 211 v, CX18_AI1_MUX_MASK); 212 213 /* Enable WW auto audio standard detection */ 214 v = cx18_av_read4(cx, CXADEC_STD_DET_CTL); 215 v |= 0xFF; /* Auto by default */ 216 v |= 0x400; /* Stereo by default */ 217 v |= 0x14000000; 218 cx18_av_write4_expect(cx, CXADEC_STD_DET_CTL, v, v, 0x3F00FFFF); 219 220 release_firmware(fw); 221 return 0; 222 } 223 224 MODULE_FIRMWARE(FWFILE); 225