1 /*
2  *  cx18 ADEC header
3  *
4  *  Derived from cx25840-core.h
5  *
6  *  Copyright (C) 2007  Hans Verkuil <hverkuil@xs4all.nl>
7  *  Copyright (C) 2008  Andy Walls <awalls@md.metrocast.net>
8  *
9  *  This program is free software; you can redistribute it and/or
10  *  modify it under the terms of the GNU General Public License
11  *  as published by the Free Software Foundation; either version 2
12  *  of the License, or (at your option) any later version.
13  *
14  *  This program is distributed in the hope that it will be useful,
15  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
16  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  *  GNU General Public License for more details.
18  */
19 
20 #ifndef _CX18_AV_CORE_H_
21 #define _CX18_AV_CORE_H_
22 
23 #include <media/v4l2-device.h>
24 #include <media/v4l2-ctrls.h>
25 
26 struct cx18;
27 
28 enum cx18_av_video_input {
29 	/* Composite video inputs In1-In8 */
30 	CX18_AV_COMPOSITE1 = 1,
31 	CX18_AV_COMPOSITE2,
32 	CX18_AV_COMPOSITE3,
33 	CX18_AV_COMPOSITE4,
34 	CX18_AV_COMPOSITE5,
35 	CX18_AV_COMPOSITE6,
36 	CX18_AV_COMPOSITE7,
37 	CX18_AV_COMPOSITE8,
38 
39 	/* S-Video inputs consist of one luma input (In1-In8) ORed with one
40 	   chroma input (In5-In8) */
41 	CX18_AV_SVIDEO_LUMA1 = 0x10,
42 	CX18_AV_SVIDEO_LUMA2 = 0x20,
43 	CX18_AV_SVIDEO_LUMA3 = 0x30,
44 	CX18_AV_SVIDEO_LUMA4 = 0x40,
45 	CX18_AV_SVIDEO_LUMA5 = 0x50,
46 	CX18_AV_SVIDEO_LUMA6 = 0x60,
47 	CX18_AV_SVIDEO_LUMA7 = 0x70,
48 	CX18_AV_SVIDEO_LUMA8 = 0x80,
49 	CX18_AV_SVIDEO_CHROMA4 = 0x400,
50 	CX18_AV_SVIDEO_CHROMA5 = 0x500,
51 	CX18_AV_SVIDEO_CHROMA6 = 0x600,
52 	CX18_AV_SVIDEO_CHROMA7 = 0x700,
53 	CX18_AV_SVIDEO_CHROMA8 = 0x800,
54 
55 	/* S-Video aliases for common luma/chroma combinations */
56 	CX18_AV_SVIDEO1 = 0x510,
57 	CX18_AV_SVIDEO2 = 0x620,
58 	CX18_AV_SVIDEO3 = 0x730,
59 	CX18_AV_SVIDEO4 = 0x840,
60 
61 	/* Component Video inputs consist of one luma input (In1-In8) ORed
62 	   with a red chroma (In4-In6) and blue chroma input (In7-In8) */
63 	CX18_AV_COMPONENT_LUMA1 = 0x1000,
64 	CX18_AV_COMPONENT_LUMA2 = 0x2000,
65 	CX18_AV_COMPONENT_LUMA3 = 0x3000,
66 	CX18_AV_COMPONENT_LUMA4 = 0x4000,
67 	CX18_AV_COMPONENT_LUMA5 = 0x5000,
68 	CX18_AV_COMPONENT_LUMA6 = 0x6000,
69 	CX18_AV_COMPONENT_LUMA7 = 0x7000,
70 	CX18_AV_COMPONENT_LUMA8 = 0x8000,
71 	CX18_AV_COMPONENT_R_CHROMA4 = 0x40000,
72 	CX18_AV_COMPONENT_R_CHROMA5 = 0x50000,
73 	CX18_AV_COMPONENT_R_CHROMA6 = 0x60000,
74 	CX18_AV_COMPONENT_B_CHROMA7 = 0x700000,
75 	CX18_AV_COMPONENT_B_CHROMA8 = 0x800000,
76 
77 	/* Component Video aliases for common combinations */
78 	CX18_AV_COMPONENT1 = 0x861000,
79 };
80 
81 enum cx18_av_audio_input {
82 	/* Audio inputs: serial or In4-In8 */
83 	CX18_AV_AUDIO_SERIAL1,
84 	CX18_AV_AUDIO_SERIAL2,
85 	CX18_AV_AUDIO4 = 4,
86 	CX18_AV_AUDIO5,
87 	CX18_AV_AUDIO6,
88 	CX18_AV_AUDIO7,
89 	CX18_AV_AUDIO8,
90 };
91 
92 struct cx18_av_state {
93 	struct v4l2_subdev sd;
94 	struct v4l2_ctrl_handler hdl;
95 	struct v4l2_ctrl *volume;
96 	int radio;
97 	v4l2_std_id std;
98 	enum cx18_av_video_input vid_input;
99 	enum cx18_av_audio_input aud_input;
100 	u32 audclk_freq;
101 	int audmode;
102 	u32 rev;
103 	int is_initialized;
104 
105 	/*
106 	 * The VBI slicer starts operating and counting lines, beginning at
107 	 * slicer line count of 1, at D lines after the deassertion of VRESET.
108 	 * This staring field line, S, is 6 (& 319) or 10 (& 273) for 625 or 525
109 	 * line systems respectively.  Sliced ancillary data captured on VBI
110 	 * slicer line M is inserted after the VBI slicer is done with line M,
111 	 * when VBI slicer line count is N = M+1.  Thus when the VBI slicer
112 	 * reports a VBI slicer line number with ancillary data, the IDID0 byte
113 	 * indicates VBI slicer line N.  The actual field line that the captured
114 	 * data comes from is
115 	 *
116 	 * L = M+(S+D-1) = N-1+(S+D-1) = N + (S+D-2).
117 	 *
118 	 * L is the line in the field, not frame, from which the VBI data came.
119 	 * N is the line reported by the slicer in the ancillary data.
120 	 * D is the slicer_line_delay value programmed into register 0x47f.
121 	 * S is 6 for 625 line systems or 10 for 525 line systems
122 	 * (S+D-2) is the slicer_line_offset used to convert slicer reported
123 	 * line counts to actual field lines.
124 	 */
125 	int slicer_line_delay;
126 	int slicer_line_offset;
127 };
128 
129 
130 /* Registers */
131 #define CXADEC_CHIP_TYPE_TIGER     0x837
132 #define CXADEC_CHIP_TYPE_MAKO      0x843
133 
134 #define CXADEC_HOST_REG1           0x000
135 #define CXADEC_HOST_REG2           0x001
136 
137 #define CXADEC_CHIP_CTRL           0x100
138 #define CXADEC_AFE_CTRL            0x104
139 #define CXADEC_PLL_CTRL1           0x108
140 #define CXADEC_VID_PLL_FRAC        0x10C
141 #define CXADEC_AUX_PLL_FRAC        0x110
142 #define CXADEC_PIN_CTRL1           0x114
143 #define CXADEC_PIN_CTRL2           0x118
144 #define CXADEC_PIN_CFG1            0x11C
145 #define CXADEC_PIN_CFG2            0x120
146 
147 #define CXADEC_PIN_CFG3            0x124
148 #define CXADEC_I2S_MCLK            0x127
149 
150 #define CXADEC_AUD_LOCK1           0x128
151 #define CXADEC_AUD_LOCK2           0x12C
152 #define CXADEC_POWER_CTRL          0x130
153 #define CXADEC_AFE_DIAG_CTRL1      0x134
154 #define CXADEC_AFE_DIAG_CTRL2      0x138
155 #define CXADEC_AFE_DIAG_CTRL3      0x13C
156 #define CXADEC_PLL_DIAG_CTRL       0x140
157 #define CXADEC_TEST_CTRL1          0x144
158 #define CXADEC_TEST_CTRL2          0x148
159 #define CXADEC_BIST_STAT           0x14C
160 #define CXADEC_DLL1_DIAG_CTRL      0x158
161 #define CXADEC_DLL2_DIAG_CTRL      0x15C
162 
163 /* IR registers */
164 #define CXADEC_IR_CTRL_REG         0x200
165 #define CXADEC_IR_TXCLK_REG        0x204
166 #define CXADEC_IR_RXCLK_REG        0x208
167 #define CXADEC_IR_CDUTY_REG        0x20C
168 #define CXADEC_IR_STAT_REG         0x210
169 #define CXADEC_IR_IRQEN_REG        0x214
170 #define CXADEC_IR_FILTER_REG       0x218
171 #define CXADEC_IR_FIFO_REG         0x21C
172 
173 /* Video Registers */
174 #define CXADEC_MODE_CTRL           0x400
175 #define CXADEC_OUT_CTRL1           0x404
176 #define CXADEC_OUT_CTRL2           0x408
177 #define CXADEC_GEN_STAT            0x40C
178 #define CXADEC_INT_STAT_MASK       0x410
179 #define CXADEC_LUMA_CTRL           0x414
180 
181 #define CXADEC_BRIGHTNESS_CTRL_BYTE 0x414
182 #define CXADEC_CONTRAST_CTRL_BYTE  0x415
183 #define CXADEC_LUMA_CTRL_BYTE_3    0x416
184 
185 #define CXADEC_HSCALE_CTRL         0x418
186 #define CXADEC_VSCALE_CTRL         0x41C
187 
188 #define CXADEC_CHROMA_CTRL         0x420
189 
190 #define CXADEC_USAT_CTRL_BYTE      0x420
191 #define CXADEC_VSAT_CTRL_BYTE      0x421
192 #define CXADEC_HUE_CTRL_BYTE       0x422
193 
194 #define CXADEC_VBI_LINE_CTRL1      0x424
195 #define CXADEC_VBI_LINE_CTRL2      0x428
196 #define CXADEC_VBI_LINE_CTRL3      0x42C
197 #define CXADEC_VBI_LINE_CTRL4      0x430
198 #define CXADEC_VBI_LINE_CTRL5      0x434
199 #define CXADEC_VBI_FC_CFG          0x438
200 #define CXADEC_VBI_MISC_CFG1       0x43C
201 #define CXADEC_VBI_MISC_CFG2       0x440
202 #define CXADEC_VBI_PAY1            0x444
203 #define CXADEC_VBI_PAY2            0x448
204 #define CXADEC_VBI_CUST1_CFG1      0x44C
205 #define CXADEC_VBI_CUST1_CFG2      0x450
206 #define CXADEC_VBI_CUST1_CFG3      0x454
207 #define CXADEC_VBI_CUST2_CFG1      0x458
208 #define CXADEC_VBI_CUST2_CFG2      0x45C
209 #define CXADEC_VBI_CUST2_CFG3      0x460
210 #define CXADEC_VBI_CUST3_CFG1      0x464
211 #define CXADEC_VBI_CUST3_CFG2      0x468
212 #define CXADEC_VBI_CUST3_CFG3      0x46C
213 #define CXADEC_HORIZ_TIM_CTRL      0x470
214 #define CXADEC_VERT_TIM_CTRL       0x474
215 #define CXADEC_SRC_COMB_CFG        0x478
216 #define CXADEC_CHROMA_VBIOFF_CFG   0x47C
217 #define CXADEC_FIELD_COUNT         0x480
218 #define CXADEC_MISC_TIM_CTRL       0x484
219 #define CXADEC_DFE_CTRL1           0x488
220 #define CXADEC_DFE_CTRL2           0x48C
221 #define CXADEC_DFE_CTRL3           0x490
222 #define CXADEC_PLL_CTRL2           0x494
223 #define CXADEC_HTL_CTRL            0x498
224 #define CXADEC_COMB_CTRL           0x49C
225 #define CXADEC_CRUSH_CTRL          0x4A0
226 #define CXADEC_SOFT_RST_CTRL       0x4A4
227 #define CXADEC_MV_DT_CTRL2         0x4A8
228 #define CXADEC_MV_DT_CTRL3         0x4AC
229 #define CXADEC_MISC_DIAG_CTRL      0x4B8
230 
231 #define CXADEC_DL_CTL              0x800
232 #define CXADEC_DL_CTL_ADDRESS_LOW  0x800   /* Byte 1 in DL_CTL */
233 #define CXADEC_DL_CTL_ADDRESS_HIGH 0x801   /* Byte 2 in DL_CTL */
234 #define CXADEC_DL_CTL_DATA         0x802   /* Byte 3 in DL_CTL */
235 #define CXADEC_DL_CTL_CONTROL      0x803   /* Byte 4 in DL_CTL */
236 
237 #define CXADEC_STD_DET_STATUS      0x804
238 
239 #define CXADEC_STD_DET_CTL         0x808
240 #define CXADEC_STD_DET_CTL_AUD_CTL   0x808 /* Byte 1 in STD_DET_CTL */
241 #define CXADEC_STD_DET_CTL_PREF_MODE 0x809 /* Byte 2 in STD_DET_CTL */
242 
243 #define CXADEC_DW8051_INT          0x80C
244 #define CXADEC_GENERAL_CTL         0x810
245 #define CXADEC_AAGC_CTL            0x814
246 #define CXADEC_IF_SRC_CTL          0x818
247 #define CXADEC_ANLOG_DEMOD_CTL     0x81C
248 #define CXADEC_ROT_FREQ_CTL        0x820
249 #define CXADEC_FM1_CTL             0x824
250 #define CXADEC_PDF_CTL             0x828
251 #define CXADEC_DFT1_CTL1           0x82C
252 #define CXADEC_DFT1_CTL2           0x830
253 #define CXADEC_DFT_STATUS          0x834
254 #define CXADEC_DFT2_CTL1           0x838
255 #define CXADEC_DFT2_CTL2           0x83C
256 #define CXADEC_DFT2_STATUS         0x840
257 #define CXADEC_DFT3_CTL1           0x844
258 #define CXADEC_DFT3_CTL2           0x848
259 #define CXADEC_DFT3_STATUS         0x84C
260 #define CXADEC_DFT4_CTL1           0x850
261 #define CXADEC_DFT4_CTL2           0x854
262 #define CXADEC_DFT4_STATUS         0x858
263 #define CXADEC_AM_MTS_DET          0x85C
264 #define CXADEC_ANALOG_MUX_CTL      0x860
265 #define CXADEC_DIG_PLL_CTL1        0x864
266 #define CXADEC_DIG_PLL_CTL2        0x868
267 #define CXADEC_DIG_PLL_CTL3        0x86C
268 #define CXADEC_DIG_PLL_CTL4        0x870
269 #define CXADEC_DIG_PLL_CTL5        0x874
270 #define CXADEC_DEEMPH_GAIN_CTL     0x878
271 #define CXADEC_DEEMPH_COEF1        0x87C
272 #define CXADEC_DEEMPH_COEF2        0x880
273 #define CXADEC_DBX1_CTL1           0x884
274 #define CXADEC_DBX1_CTL2           0x888
275 #define CXADEC_DBX1_STATUS         0x88C
276 #define CXADEC_DBX2_CTL1           0x890
277 #define CXADEC_DBX2_CTL2           0x894
278 #define CXADEC_DBX2_STATUS         0x898
279 #define CXADEC_AM_FM_DIFF          0x89C
280 
281 /* NICAM registers go here */
282 #define CXADEC_NICAM_STATUS        0x8C8
283 #define CXADEC_DEMATRIX_CTL        0x8CC
284 
285 #define CXADEC_PATH1_CTL1          0x8D0
286 #define CXADEC_PATH1_VOL_CTL       0x8D4
287 #define CXADEC_PATH1_EQ_CTL        0x8D8
288 #define CXADEC_PATH1_SC_CTL        0x8DC
289 
290 #define CXADEC_PATH2_CTL1          0x8E0
291 #define CXADEC_PATH2_VOL_CTL       0x8E4
292 #define CXADEC_PATH2_EQ_CTL        0x8E8
293 #define CXADEC_PATH2_SC_CTL        0x8EC
294 
295 #define CXADEC_SRC_CTL             0x8F0
296 #define CXADEC_SRC_LF_COEF         0x8F4
297 #define CXADEC_SRC1_CTL            0x8F8
298 #define CXADEC_SRC2_CTL            0x8FC
299 #define CXADEC_SRC3_CTL            0x900
300 #define CXADEC_SRC4_CTL            0x904
301 #define CXADEC_SRC5_CTL            0x908
302 #define CXADEC_SRC6_CTL            0x90C
303 
304 #define CXADEC_BASEBAND_OUT_SEL    0x910
305 #define CXADEC_I2S_IN_CTL          0x914
306 #define CXADEC_I2S_OUT_CTL         0x918
307 #define CXADEC_AC97_CTL            0x91C
308 #define CXADEC_QAM_PDF             0x920
309 #define CXADEC_QAM_CONST_DEC       0x924
310 #define CXADEC_QAM_ROTATOR_FREQ    0x948
311 
312 /* Bit definitions / settings used in Mako Audio */
313 #define CXADEC_PREF_MODE_MONO_LANGA        0
314 #define CXADEC_PREF_MODE_MONO_LANGB        1
315 #define CXADEC_PREF_MODE_MONO_LANGC        2
316 #define CXADEC_PREF_MODE_FALLBACK          3
317 #define CXADEC_PREF_MODE_STEREO            4
318 #define CXADEC_PREF_MODE_DUAL_LANG_AC      5
319 #define CXADEC_PREF_MODE_DUAL_LANG_BC      6
320 #define CXADEC_PREF_MODE_DUAL_LANG_AB      7
321 
322 
323 #define CXADEC_DETECT_STEREO               1
324 #define CXADEC_DETECT_DUAL                 2
325 #define CXADEC_DETECT_TRI                  4
326 #define CXADEC_DETECT_SAP                  0x10
327 #define CXADEC_DETECT_NO_SIGNAL            0xFF
328 
329 #define CXADEC_SELECT_AUDIO_STANDARD_BG    0xF0  /* NICAM BG and A2 BG */
330 #define CXADEC_SELECT_AUDIO_STANDARD_DK1   0xF1  /* NICAM DK and A2 DK */
331 #define CXADEC_SELECT_AUDIO_STANDARD_DK2   0xF2
332 #define CXADEC_SELECT_AUDIO_STANDARD_DK3   0xF3
333 #define CXADEC_SELECT_AUDIO_STANDARD_I     0xF4  /* NICAM I and A1 */
334 #define CXADEC_SELECT_AUDIO_STANDARD_L     0xF5  /* NICAM L and System L AM */
335 #define CXADEC_SELECT_AUDIO_STANDARD_BTSC  0xF6
336 #define CXADEC_SELECT_AUDIO_STANDARD_EIAJ  0xF7
337 #define CXADEC_SELECT_AUDIO_STANDARD_A2_M  0xF8  /* A2 M */
338 #define CXADEC_SELECT_AUDIO_STANDARD_FM    0xF9  /* FM radio */
339 #define CXADEC_SELECT_AUDIO_STANDARD_AUTO  0xFF  /* Auto detect */
340 
341 static inline struct cx18_av_state *to_cx18_av_state(struct v4l2_subdev *sd)
342 {
343 	return container_of(sd, struct cx18_av_state, sd);
344 }
345 
346 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
347 {
348 	return &container_of(ctrl->handler, struct cx18_av_state, hdl)->sd;
349 }
350 
351 /* ----------------------------------------------------------------------- */
352 /* cx18_av-core.c							   */
353 int cx18_av_write(struct cx18 *cx, u16 addr, u8 value);
354 int cx18_av_write4(struct cx18 *cx, u16 addr, u32 value);
355 int cx18_av_write4_noretry(struct cx18 *cx, u16 addr, u32 value);
356 int cx18_av_write_expect(struct cx18 *cx, u16 addr, u8 value, u8 eval, u8 mask);
357 int cx18_av_write4_expect(struct cx18 *cx, u16 addr, u32 value, u32 eval,
358 			  u32 mask);
359 u8 cx18_av_read(struct cx18 *cx, u16 addr);
360 u32 cx18_av_read4(struct cx18 *cx, u16 addr);
361 int cx18_av_and_or(struct cx18 *cx, u16 addr, unsigned mask, u8 value);
362 int cx18_av_and_or4(struct cx18 *cx, u16 addr, u32 mask, u32 value);
363 void cx18_av_std_setup(struct cx18 *cx);
364 
365 int cx18_av_probe(struct cx18 *cx);
366 
367 /* ----------------------------------------------------------------------- */
368 /* cx18_av-firmware.c                                                      */
369 int cx18_av_loadfw(struct cx18 *cx);
370 
371 /* ----------------------------------------------------------------------- */
372 /* cx18_av-audio.c                                                         */
373 int cx18_av_s_clock_freq(struct v4l2_subdev *sd, u32 freq);
374 void cx18_av_audio_set_path(struct cx18 *cx);
375 extern const struct v4l2_ctrl_ops cx18_av_audio_ctrl_ops;
376 
377 /* ----------------------------------------------------------------------- */
378 /* cx18_av-vbi.c                                                           */
379 int cx18_av_decode_vbi_line(struct v4l2_subdev *sd,
380 			   struct v4l2_decode_vbi_line *vbi);
381 int cx18_av_s_raw_fmt(struct v4l2_subdev *sd, struct v4l2_vbi_format *fmt);
382 int cx18_av_g_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *fmt);
383 int cx18_av_s_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *fmt);
384 
385 #endif
386