1 /* 2 * cx18 ADEC header 3 * 4 * Derived from cx25840-core.h 5 * 6 * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl> 7 * Copyright (C) 2008 Andy Walls <awalls@md.metrocast.net> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 2 12 * of the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 22 * 02110-1301, USA. 23 */ 24 25 #ifndef _CX18_AV_CORE_H_ 26 #define _CX18_AV_CORE_H_ 27 28 #include <media/v4l2-device.h> 29 #include <media/v4l2-ctrls.h> 30 31 struct cx18; 32 33 enum cx18_av_video_input { 34 /* Composite video inputs In1-In8 */ 35 CX18_AV_COMPOSITE1 = 1, 36 CX18_AV_COMPOSITE2, 37 CX18_AV_COMPOSITE3, 38 CX18_AV_COMPOSITE4, 39 CX18_AV_COMPOSITE5, 40 CX18_AV_COMPOSITE6, 41 CX18_AV_COMPOSITE7, 42 CX18_AV_COMPOSITE8, 43 44 /* S-Video inputs consist of one luma input (In1-In8) ORed with one 45 chroma input (In5-In8) */ 46 CX18_AV_SVIDEO_LUMA1 = 0x10, 47 CX18_AV_SVIDEO_LUMA2 = 0x20, 48 CX18_AV_SVIDEO_LUMA3 = 0x30, 49 CX18_AV_SVIDEO_LUMA4 = 0x40, 50 CX18_AV_SVIDEO_LUMA5 = 0x50, 51 CX18_AV_SVIDEO_LUMA6 = 0x60, 52 CX18_AV_SVIDEO_LUMA7 = 0x70, 53 CX18_AV_SVIDEO_LUMA8 = 0x80, 54 CX18_AV_SVIDEO_CHROMA4 = 0x400, 55 CX18_AV_SVIDEO_CHROMA5 = 0x500, 56 CX18_AV_SVIDEO_CHROMA6 = 0x600, 57 CX18_AV_SVIDEO_CHROMA7 = 0x700, 58 CX18_AV_SVIDEO_CHROMA8 = 0x800, 59 60 /* S-Video aliases for common luma/chroma combinations */ 61 CX18_AV_SVIDEO1 = 0x510, 62 CX18_AV_SVIDEO2 = 0x620, 63 CX18_AV_SVIDEO3 = 0x730, 64 CX18_AV_SVIDEO4 = 0x840, 65 66 /* Component Video inputs consist of one luma input (In1-In8) ORed 67 with a red chroma (In4-In6) and blue chroma input (In7-In8) */ 68 CX18_AV_COMPONENT_LUMA1 = 0x1000, 69 CX18_AV_COMPONENT_LUMA2 = 0x2000, 70 CX18_AV_COMPONENT_LUMA3 = 0x3000, 71 CX18_AV_COMPONENT_LUMA4 = 0x4000, 72 CX18_AV_COMPONENT_LUMA5 = 0x5000, 73 CX18_AV_COMPONENT_LUMA6 = 0x6000, 74 CX18_AV_COMPONENT_LUMA7 = 0x7000, 75 CX18_AV_COMPONENT_LUMA8 = 0x8000, 76 CX18_AV_COMPONENT_R_CHROMA4 = 0x40000, 77 CX18_AV_COMPONENT_R_CHROMA5 = 0x50000, 78 CX18_AV_COMPONENT_R_CHROMA6 = 0x60000, 79 CX18_AV_COMPONENT_B_CHROMA7 = 0x700000, 80 CX18_AV_COMPONENT_B_CHROMA8 = 0x800000, 81 82 /* Component Video aliases for common combinations */ 83 CX18_AV_COMPONENT1 = 0x861000, 84 }; 85 86 enum cx18_av_audio_input { 87 /* Audio inputs: serial or In4-In8 */ 88 CX18_AV_AUDIO_SERIAL1, 89 CX18_AV_AUDIO_SERIAL2, 90 CX18_AV_AUDIO4 = 4, 91 CX18_AV_AUDIO5, 92 CX18_AV_AUDIO6, 93 CX18_AV_AUDIO7, 94 CX18_AV_AUDIO8, 95 }; 96 97 struct cx18_av_state { 98 struct v4l2_subdev sd; 99 struct v4l2_ctrl_handler hdl; 100 struct v4l2_ctrl *volume; 101 int radio; 102 v4l2_std_id std; 103 enum cx18_av_video_input vid_input; 104 enum cx18_av_audio_input aud_input; 105 u32 audclk_freq; 106 int audmode; 107 u32 id; 108 u32 rev; 109 int is_initialized; 110 111 /* 112 * The VBI slicer starts operating and counting lines, beginning at 113 * slicer line count of 1, at D lines after the deassertion of VRESET. 114 * This staring field line, S, is 6 (& 319) or 10 (& 273) for 625 or 525 115 * line systems respectively. Sliced ancillary data captured on VBI 116 * slicer line M is inserted after the VBI slicer is done with line M, 117 * when VBI slicer line count is N = M+1. Thus when the VBI slicer 118 * reports a VBI slicer line number with ancillary data, the IDID0 byte 119 * indicates VBI slicer line N. The actual field line that the captured 120 * data comes from is 121 * 122 * L = M+(S+D-1) = N-1+(S+D-1) = N + (S+D-2). 123 * 124 * L is the line in the field, not frame, from which the VBI data came. 125 * N is the line reported by the slicer in the ancillary data. 126 * D is the slicer_line_delay value programmed into register 0x47f. 127 * S is 6 for 625 line systems or 10 for 525 line systems 128 * (S+D-2) is the slicer_line_offset used to convert slicer reported 129 * line counts to actual field lines. 130 */ 131 int slicer_line_delay; 132 int slicer_line_offset; 133 }; 134 135 136 /* Registers */ 137 #define CXADEC_CHIP_TYPE_TIGER 0x837 138 #define CXADEC_CHIP_TYPE_MAKO 0x843 139 140 #define CXADEC_HOST_REG1 0x000 141 #define CXADEC_HOST_REG2 0x001 142 143 #define CXADEC_CHIP_CTRL 0x100 144 #define CXADEC_AFE_CTRL 0x104 145 #define CXADEC_PLL_CTRL1 0x108 146 #define CXADEC_VID_PLL_FRAC 0x10C 147 #define CXADEC_AUX_PLL_FRAC 0x110 148 #define CXADEC_PIN_CTRL1 0x114 149 #define CXADEC_PIN_CTRL2 0x118 150 #define CXADEC_PIN_CFG1 0x11C 151 #define CXADEC_PIN_CFG2 0x120 152 153 #define CXADEC_PIN_CFG3 0x124 154 #define CXADEC_I2S_MCLK 0x127 155 156 #define CXADEC_AUD_LOCK1 0x128 157 #define CXADEC_AUD_LOCK2 0x12C 158 #define CXADEC_POWER_CTRL 0x130 159 #define CXADEC_AFE_DIAG_CTRL1 0x134 160 #define CXADEC_AFE_DIAG_CTRL2 0x138 161 #define CXADEC_AFE_DIAG_CTRL3 0x13C 162 #define CXADEC_PLL_DIAG_CTRL 0x140 163 #define CXADEC_TEST_CTRL1 0x144 164 #define CXADEC_TEST_CTRL2 0x148 165 #define CXADEC_BIST_STAT 0x14C 166 #define CXADEC_DLL1_DIAG_CTRL 0x158 167 #define CXADEC_DLL2_DIAG_CTRL 0x15C 168 169 /* IR registers */ 170 #define CXADEC_IR_CTRL_REG 0x200 171 #define CXADEC_IR_TXCLK_REG 0x204 172 #define CXADEC_IR_RXCLK_REG 0x208 173 #define CXADEC_IR_CDUTY_REG 0x20C 174 #define CXADEC_IR_STAT_REG 0x210 175 #define CXADEC_IR_IRQEN_REG 0x214 176 #define CXADEC_IR_FILTER_REG 0x218 177 #define CXADEC_IR_FIFO_REG 0x21C 178 179 /* Video Registers */ 180 #define CXADEC_MODE_CTRL 0x400 181 #define CXADEC_OUT_CTRL1 0x404 182 #define CXADEC_OUT_CTRL2 0x408 183 #define CXADEC_GEN_STAT 0x40C 184 #define CXADEC_INT_STAT_MASK 0x410 185 #define CXADEC_LUMA_CTRL 0x414 186 187 #define CXADEC_BRIGHTNESS_CTRL_BYTE 0x414 188 #define CXADEC_CONTRAST_CTRL_BYTE 0x415 189 #define CXADEC_LUMA_CTRL_BYTE_3 0x416 190 191 #define CXADEC_HSCALE_CTRL 0x418 192 #define CXADEC_VSCALE_CTRL 0x41C 193 194 #define CXADEC_CHROMA_CTRL 0x420 195 196 #define CXADEC_USAT_CTRL_BYTE 0x420 197 #define CXADEC_VSAT_CTRL_BYTE 0x421 198 #define CXADEC_HUE_CTRL_BYTE 0x422 199 200 #define CXADEC_VBI_LINE_CTRL1 0x424 201 #define CXADEC_VBI_LINE_CTRL2 0x428 202 #define CXADEC_VBI_LINE_CTRL3 0x42C 203 #define CXADEC_VBI_LINE_CTRL4 0x430 204 #define CXADEC_VBI_LINE_CTRL5 0x434 205 #define CXADEC_VBI_FC_CFG 0x438 206 #define CXADEC_VBI_MISC_CFG1 0x43C 207 #define CXADEC_VBI_MISC_CFG2 0x440 208 #define CXADEC_VBI_PAY1 0x444 209 #define CXADEC_VBI_PAY2 0x448 210 #define CXADEC_VBI_CUST1_CFG1 0x44C 211 #define CXADEC_VBI_CUST1_CFG2 0x450 212 #define CXADEC_VBI_CUST1_CFG3 0x454 213 #define CXADEC_VBI_CUST2_CFG1 0x458 214 #define CXADEC_VBI_CUST2_CFG2 0x45C 215 #define CXADEC_VBI_CUST2_CFG3 0x460 216 #define CXADEC_VBI_CUST3_CFG1 0x464 217 #define CXADEC_VBI_CUST3_CFG2 0x468 218 #define CXADEC_VBI_CUST3_CFG3 0x46C 219 #define CXADEC_HORIZ_TIM_CTRL 0x470 220 #define CXADEC_VERT_TIM_CTRL 0x474 221 #define CXADEC_SRC_COMB_CFG 0x478 222 #define CXADEC_CHROMA_VBIOFF_CFG 0x47C 223 #define CXADEC_FIELD_COUNT 0x480 224 #define CXADEC_MISC_TIM_CTRL 0x484 225 #define CXADEC_DFE_CTRL1 0x488 226 #define CXADEC_DFE_CTRL2 0x48C 227 #define CXADEC_DFE_CTRL3 0x490 228 #define CXADEC_PLL_CTRL2 0x494 229 #define CXADEC_HTL_CTRL 0x498 230 #define CXADEC_COMB_CTRL 0x49C 231 #define CXADEC_CRUSH_CTRL 0x4A0 232 #define CXADEC_SOFT_RST_CTRL 0x4A4 233 #define CXADEC_MV_DT_CTRL2 0x4A8 234 #define CXADEC_MV_DT_CTRL3 0x4AC 235 #define CXADEC_MISC_DIAG_CTRL 0x4B8 236 237 #define CXADEC_DL_CTL 0x800 238 #define CXADEC_DL_CTL_ADDRESS_LOW 0x800 /* Byte 1 in DL_CTL */ 239 #define CXADEC_DL_CTL_ADDRESS_HIGH 0x801 /* Byte 2 in DL_CTL */ 240 #define CXADEC_DL_CTL_DATA 0x802 /* Byte 3 in DL_CTL */ 241 #define CXADEC_DL_CTL_CONTROL 0x803 /* Byte 4 in DL_CTL */ 242 243 #define CXADEC_STD_DET_STATUS 0x804 244 245 #define CXADEC_STD_DET_CTL 0x808 246 #define CXADEC_STD_DET_CTL_AUD_CTL 0x808 /* Byte 1 in STD_DET_CTL */ 247 #define CXADEC_STD_DET_CTL_PREF_MODE 0x809 /* Byte 2 in STD_DET_CTL */ 248 249 #define CXADEC_DW8051_INT 0x80C 250 #define CXADEC_GENERAL_CTL 0x810 251 #define CXADEC_AAGC_CTL 0x814 252 #define CXADEC_IF_SRC_CTL 0x818 253 #define CXADEC_ANLOG_DEMOD_CTL 0x81C 254 #define CXADEC_ROT_FREQ_CTL 0x820 255 #define CXADEC_FM1_CTL 0x824 256 #define CXADEC_PDF_CTL 0x828 257 #define CXADEC_DFT1_CTL1 0x82C 258 #define CXADEC_DFT1_CTL2 0x830 259 #define CXADEC_DFT_STATUS 0x834 260 #define CXADEC_DFT2_CTL1 0x838 261 #define CXADEC_DFT2_CTL2 0x83C 262 #define CXADEC_DFT2_STATUS 0x840 263 #define CXADEC_DFT3_CTL1 0x844 264 #define CXADEC_DFT3_CTL2 0x848 265 #define CXADEC_DFT3_STATUS 0x84C 266 #define CXADEC_DFT4_CTL1 0x850 267 #define CXADEC_DFT4_CTL2 0x854 268 #define CXADEC_DFT4_STATUS 0x858 269 #define CXADEC_AM_MTS_DET 0x85C 270 #define CXADEC_ANALOG_MUX_CTL 0x860 271 #define CXADEC_DIG_PLL_CTL1 0x864 272 #define CXADEC_DIG_PLL_CTL2 0x868 273 #define CXADEC_DIG_PLL_CTL3 0x86C 274 #define CXADEC_DIG_PLL_CTL4 0x870 275 #define CXADEC_DIG_PLL_CTL5 0x874 276 #define CXADEC_DEEMPH_GAIN_CTL 0x878 277 #define CXADEC_DEEMPH_COEF1 0x87C 278 #define CXADEC_DEEMPH_COEF2 0x880 279 #define CXADEC_DBX1_CTL1 0x884 280 #define CXADEC_DBX1_CTL2 0x888 281 #define CXADEC_DBX1_STATUS 0x88C 282 #define CXADEC_DBX2_CTL1 0x890 283 #define CXADEC_DBX2_CTL2 0x894 284 #define CXADEC_DBX2_STATUS 0x898 285 #define CXADEC_AM_FM_DIFF 0x89C 286 287 /* NICAM registers go here */ 288 #define CXADEC_NICAM_STATUS 0x8C8 289 #define CXADEC_DEMATRIX_CTL 0x8CC 290 291 #define CXADEC_PATH1_CTL1 0x8D0 292 #define CXADEC_PATH1_VOL_CTL 0x8D4 293 #define CXADEC_PATH1_EQ_CTL 0x8D8 294 #define CXADEC_PATH1_SC_CTL 0x8DC 295 296 #define CXADEC_PATH2_CTL1 0x8E0 297 #define CXADEC_PATH2_VOL_CTL 0x8E4 298 #define CXADEC_PATH2_EQ_CTL 0x8E8 299 #define CXADEC_PATH2_SC_CTL 0x8EC 300 301 #define CXADEC_SRC_CTL 0x8F0 302 #define CXADEC_SRC_LF_COEF 0x8F4 303 #define CXADEC_SRC1_CTL 0x8F8 304 #define CXADEC_SRC2_CTL 0x8FC 305 #define CXADEC_SRC3_CTL 0x900 306 #define CXADEC_SRC4_CTL 0x904 307 #define CXADEC_SRC5_CTL 0x908 308 #define CXADEC_SRC6_CTL 0x90C 309 310 #define CXADEC_BASEBAND_OUT_SEL 0x910 311 #define CXADEC_I2S_IN_CTL 0x914 312 #define CXADEC_I2S_OUT_CTL 0x918 313 #define CXADEC_AC97_CTL 0x91C 314 #define CXADEC_QAM_PDF 0x920 315 #define CXADEC_QAM_CONST_DEC 0x924 316 #define CXADEC_QAM_ROTATOR_FREQ 0x948 317 318 /* Bit definitions / settings used in Mako Audio */ 319 #define CXADEC_PREF_MODE_MONO_LANGA 0 320 #define CXADEC_PREF_MODE_MONO_LANGB 1 321 #define CXADEC_PREF_MODE_MONO_LANGC 2 322 #define CXADEC_PREF_MODE_FALLBACK 3 323 #define CXADEC_PREF_MODE_STEREO 4 324 #define CXADEC_PREF_MODE_DUAL_LANG_AC 5 325 #define CXADEC_PREF_MODE_DUAL_LANG_BC 6 326 #define CXADEC_PREF_MODE_DUAL_LANG_AB 7 327 328 329 #define CXADEC_DETECT_STEREO 1 330 #define CXADEC_DETECT_DUAL 2 331 #define CXADEC_DETECT_TRI 4 332 #define CXADEC_DETECT_SAP 0x10 333 #define CXADEC_DETECT_NO_SIGNAL 0xFF 334 335 #define CXADEC_SELECT_AUDIO_STANDARD_BG 0xF0 /* NICAM BG and A2 BG */ 336 #define CXADEC_SELECT_AUDIO_STANDARD_DK1 0xF1 /* NICAM DK and A2 DK */ 337 #define CXADEC_SELECT_AUDIO_STANDARD_DK2 0xF2 338 #define CXADEC_SELECT_AUDIO_STANDARD_DK3 0xF3 339 #define CXADEC_SELECT_AUDIO_STANDARD_I 0xF4 /* NICAM I and A1 */ 340 #define CXADEC_SELECT_AUDIO_STANDARD_L 0xF5 /* NICAM L and System L AM */ 341 #define CXADEC_SELECT_AUDIO_STANDARD_BTSC 0xF6 342 #define CXADEC_SELECT_AUDIO_STANDARD_EIAJ 0xF7 343 #define CXADEC_SELECT_AUDIO_STANDARD_A2_M 0xF8 /* A2 M */ 344 #define CXADEC_SELECT_AUDIO_STANDARD_FM 0xF9 /* FM radio */ 345 #define CXADEC_SELECT_AUDIO_STANDARD_AUTO 0xFF /* Auto detect */ 346 347 static inline struct cx18_av_state *to_cx18_av_state(struct v4l2_subdev *sd) 348 { 349 return container_of(sd, struct cx18_av_state, sd); 350 } 351 352 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) 353 { 354 return &container_of(ctrl->handler, struct cx18_av_state, hdl)->sd; 355 } 356 357 /* ----------------------------------------------------------------------- */ 358 /* cx18_av-core.c */ 359 int cx18_av_write(struct cx18 *cx, u16 addr, u8 value); 360 int cx18_av_write4(struct cx18 *cx, u16 addr, u32 value); 361 int cx18_av_write4_noretry(struct cx18 *cx, u16 addr, u32 value); 362 int cx18_av_write_expect(struct cx18 *cx, u16 addr, u8 value, u8 eval, u8 mask); 363 int cx18_av_write4_expect(struct cx18 *cx, u16 addr, u32 value, u32 eval, 364 u32 mask); 365 u8 cx18_av_read(struct cx18 *cx, u16 addr); 366 u32 cx18_av_read4(struct cx18 *cx, u16 addr); 367 int cx18_av_and_or(struct cx18 *cx, u16 addr, unsigned mask, u8 value); 368 int cx18_av_and_or4(struct cx18 *cx, u16 addr, u32 mask, u32 value); 369 void cx18_av_std_setup(struct cx18 *cx); 370 371 int cx18_av_probe(struct cx18 *cx); 372 373 /* ----------------------------------------------------------------------- */ 374 /* cx18_av-firmware.c */ 375 int cx18_av_loadfw(struct cx18 *cx); 376 377 /* ----------------------------------------------------------------------- */ 378 /* cx18_av-audio.c */ 379 int cx18_av_s_clock_freq(struct v4l2_subdev *sd, u32 freq); 380 void cx18_av_audio_set_path(struct cx18 *cx); 381 extern const struct v4l2_ctrl_ops cx18_av_audio_ctrl_ops; 382 383 /* ----------------------------------------------------------------------- */ 384 /* cx18_av-vbi.c */ 385 int cx18_av_decode_vbi_line(struct v4l2_subdev *sd, 386 struct v4l2_decode_vbi_line *vbi); 387 int cx18_av_s_raw_fmt(struct v4l2_subdev *sd, struct v4l2_vbi_format *fmt); 388 int cx18_av_g_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *fmt); 389 int cx18_av_s_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *fmt); 390 391 #endif 392