1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  *  cx18 ADEC audio functions
4  *
5  *  Derived from cx25840-core.c
6  *
7  *  Copyright (C) 2007  Hans Verkuil <hverkuil@xs4all.nl>
8  *  Copyright (C) 2008  Andy Walls <awalls@md.metrocast.net>
9  */
10 
11 #include "cx18-driver.h"
12 #include "cx18-io.h"
13 #include "cx18-cards.h"
14 
15 int cx18_av_write(struct cx18 *cx, u16 addr, u8 value)
16 {
17 	u32 reg = 0xc40000 + (addr & ~3);
18 	u32 mask = 0xff;
19 	int shift = (addr & 3) * 8;
20 	u32 x = cx18_read_reg(cx, reg);
21 
22 	x = (x & ~(mask << shift)) | ((u32)value << shift);
23 	cx18_write_reg(cx, x, reg);
24 	return 0;
25 }
26 
27 int cx18_av_write_expect(struct cx18 *cx, u16 addr, u8 value, u8 eval, u8 mask)
28 {
29 	u32 reg = 0xc40000 + (addr & ~3);
30 	int shift = (addr & 3) * 8;
31 	u32 x = cx18_read_reg(cx, reg);
32 
33 	x = (x & ~((u32)0xff << shift)) | ((u32)value << shift);
34 	cx18_write_reg_expect(cx, x, reg,
35 				((u32)eval << shift), ((u32)mask << shift));
36 	return 0;
37 }
38 
39 int cx18_av_write4(struct cx18 *cx, u16 addr, u32 value)
40 {
41 	cx18_write_reg(cx, value, 0xc40000 + addr);
42 	return 0;
43 }
44 
45 int
46 cx18_av_write4_expect(struct cx18 *cx, u16 addr, u32 value, u32 eval, u32 mask)
47 {
48 	cx18_write_reg_expect(cx, value, 0xc40000 + addr, eval, mask);
49 	return 0;
50 }
51 
52 int cx18_av_write4_noretry(struct cx18 *cx, u16 addr, u32 value)
53 {
54 	cx18_write_reg_noretry(cx, value, 0xc40000 + addr);
55 	return 0;
56 }
57 
58 u8 cx18_av_read(struct cx18 *cx, u16 addr)
59 {
60 	u32 x = cx18_read_reg(cx, 0xc40000 + (addr & ~3));
61 	int shift = (addr & 3) * 8;
62 
63 	return (x >> shift) & 0xff;
64 }
65 
66 u32 cx18_av_read4(struct cx18 *cx, u16 addr)
67 {
68 	return cx18_read_reg(cx, 0xc40000 + addr);
69 }
70 
71 int cx18_av_and_or(struct cx18 *cx, u16 addr, unsigned and_mask,
72 		   u8 or_value)
73 {
74 	return cx18_av_write(cx, addr,
75 			     (cx18_av_read(cx, addr) & and_mask) |
76 			     or_value);
77 }
78 
79 int cx18_av_and_or4(struct cx18 *cx, u16 addr, u32 and_mask,
80 		   u32 or_value)
81 {
82 	return cx18_av_write4(cx, addr,
83 			     (cx18_av_read4(cx, addr) & and_mask) |
84 			     or_value);
85 }
86 
87 static void cx18_av_init(struct cx18 *cx)
88 {
89 	/*
90 	 * The crystal freq used in calculations in this driver will be
91 	 * 28.636360 MHz.
92 	 * Aim to run the PLLs' VCOs near 400 MHz to minimize errors.
93 	 */
94 
95 	/*
96 	 * VDCLK  Integer = 0x0f, Post Divider = 0x04
97 	 * AIMCLK Integer = 0x0e, Post Divider = 0x16
98 	 */
99 	cx18_av_write4(cx, CXADEC_PLL_CTRL1, 0x160e040f);
100 
101 	/* VDCLK Fraction = 0x2be2fe */
102 	/* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz before post divide */
103 	cx18_av_write4(cx, CXADEC_VID_PLL_FRAC, 0x002be2fe);
104 
105 	/* AIMCLK Fraction = 0x05227ad */
106 	/* xtal * 0xe.2913d68/0x16 = 48000 * 384: 406 MHz pre post-div*/
107 	cx18_av_write4(cx, CXADEC_AUX_PLL_FRAC, 0x005227ad);
108 
109 	/* SA_MCLK_SEL=1, SA_MCLK_DIV=0x16 */
110 	cx18_av_write(cx, CXADEC_I2S_MCLK, 0x56);
111 }
112 
113 static void cx18_av_initialize(struct v4l2_subdev *sd)
114 {
115 	struct cx18_av_state *state = to_cx18_av_state(sd);
116 	struct cx18 *cx = v4l2_get_subdevdata(sd);
117 	int default_volume;
118 	u32 v;
119 
120 	cx18_av_loadfw(cx);
121 	/* Stop 8051 code execution */
122 	cx18_av_write4_expect(cx, CXADEC_DL_CTL, 0x03000000,
123 						 0x03000000, 0x13000000);
124 
125 	/* initialize the PLL by toggling sleep bit */
126 	v = cx18_av_read4(cx, CXADEC_HOST_REG1);
127 	/* enable sleep mode - register appears to be read only... */
128 	cx18_av_write4_expect(cx, CXADEC_HOST_REG1, v | 1, v, 0xfffe);
129 	/* disable sleep mode */
130 	cx18_av_write4_expect(cx, CXADEC_HOST_REG1, v & 0xfffe,
131 						    v & 0xfffe, 0xffff);
132 
133 	/* initialize DLLs */
134 	v = cx18_av_read4(cx, CXADEC_DLL1_DIAG_CTRL) & 0xE1FFFEFF;
135 	/* disable FLD */
136 	cx18_av_write4(cx, CXADEC_DLL1_DIAG_CTRL, v);
137 	/* enable FLD */
138 	cx18_av_write4(cx, CXADEC_DLL1_DIAG_CTRL, v | 0x10000100);
139 
140 	v = cx18_av_read4(cx, CXADEC_DLL2_DIAG_CTRL) & 0xE1FFFEFF;
141 	/* disable FLD */
142 	cx18_av_write4(cx, CXADEC_DLL2_DIAG_CTRL, v);
143 	/* enable FLD */
144 	cx18_av_write4(cx, CXADEC_DLL2_DIAG_CTRL, v | 0x06000100);
145 
146 	/* set analog bias currents. Set Vreg to 1.20V. */
147 	cx18_av_write4(cx, CXADEC_AFE_DIAG_CTRL1, 0x000A1802);
148 
149 	v = cx18_av_read4(cx, CXADEC_AFE_DIAG_CTRL3) | 1;
150 	/* enable TUNE_FIL_RST */
151 	cx18_av_write4_expect(cx, CXADEC_AFE_DIAG_CTRL3, v, v, 0x03009F0F);
152 	/* disable TUNE_FIL_RST */
153 	cx18_av_write4_expect(cx, CXADEC_AFE_DIAG_CTRL3,
154 			      v & 0xFFFFFFFE, v & 0xFFFFFFFE, 0x03009F0F);
155 
156 	/* enable 656 output */
157 	cx18_av_and_or4(cx, CXADEC_PIN_CTRL1, ~0, 0x040C00);
158 
159 	/* video output drive strength */
160 	cx18_av_and_or4(cx, CXADEC_PIN_CTRL2, ~0, 0x2);
161 
162 	/* reset video */
163 	cx18_av_write4(cx, CXADEC_SOFT_RST_CTRL, 0x8000);
164 	cx18_av_write4(cx, CXADEC_SOFT_RST_CTRL, 0);
165 
166 	/*
167 	 * Disable Video Auto-config of the Analog Front End and Video PLL.
168 	 *
169 	 * Since we only use BT.656 pixel mode, which works for both 525 and 625
170 	 * line systems, it's just easier for us to set registers
171 	 * 0x102 (CXADEC_CHIP_CTRL), 0x104-0x106 (CXADEC_AFE_CTRL),
172 	 * 0x108-0x109 (CXADEC_PLL_CTRL1), and 0x10c-0x10f (CXADEC_VID_PLL_FRAC)
173 	 * ourselves, than to run around cleaning up after the auto-config.
174 	 *
175 	 * (Note: my CX23418 chip doesn't seem to let the ACFG_DIS bit
176 	 * get set to 1, but OTOH, it doesn't seem to do AFE and VID PLL
177 	 * autoconfig either.)
178 	 *
179 	 * As a default, also turn off Dual mode for ADC2 and set ADC2 to CH3.
180 	 */
181 	cx18_av_and_or4(cx, CXADEC_CHIP_CTRL, 0xFFFBFFFF, 0x00120000);
182 
183 	/* Setup the Video and and Aux/Audio PLLs */
184 	cx18_av_init(cx);
185 
186 	/* set video to auto-detect */
187 	/* Clear bits 11-12 to enable slow locking mode.  Set autodetect mode */
188 	/* set the comb notch = 1 */
189 	cx18_av_and_or4(cx, CXADEC_MODE_CTRL, 0xFFF7E7F0, 0x02040800);
190 
191 	/* Enable wtw_en in CRUSH_CTRL (Set bit 22) */
192 	/* Enable maj_sel in CRUSH_CTRL (Set bit 20) */
193 	cx18_av_and_or4(cx, CXADEC_CRUSH_CTRL, ~0, 0x00500000);
194 
195 	/* Set VGA_TRACK_RANGE to 0x20 */
196 	cx18_av_and_or4(cx, CXADEC_DFE_CTRL2, 0xFFFF00FF, 0x00002000);
197 
198 	/*
199 	 * Initial VBI setup
200 	 * VIP-1.1, 10 bit mode, enable Raw, disable sliced,
201 	 * don't clamp raw samples when codes are in use, 1 byte user D-words,
202 	 * IDID0 has line #, RP code V bit transition on VBLANK, data during
203 	 * blanking intervals
204 	 */
205 	cx18_av_write4(cx, CXADEC_OUT_CTRL1, 0x4013252e);
206 
207 	/* Set the video input.
208 	   The setting in MODE_CTRL gets lost when we do the above setup */
209 	/* EncSetSignalStd(dwDevNum, pEnc->dwSigStd); */
210 	/* EncSetVideoInput(dwDevNum, pEnc->VidIndSelection); */
211 
212 	/*
213 	 * Analog Front End (AFE)
214 	 * Default to luma on ch1/ADC1, chroma on ch2/ADC2, SIF on ch3/ADC2
215 	 *  bypass_ch[1-3]     use filter
216 	 *  droop_comp_ch[1-3] disable
217 	 *  clamp_en_ch[1-3]   disable
218 	 *  aud_in_sel         ADC2
219 	 *  luma_in_sel        ADC1
220 	 *  chroma_in_sel      ADC2
221 	 *  clamp_sel_ch[2-3]  midcode
222 	 *  clamp_sel_ch1      video decoder
223 	 *  vga_sel_ch3        audio decoder
224 	 *  vga_sel_ch[1-2]    video decoder
225 	 *  half_bw_ch[1-3]    disable
226 	 *  +12db_ch[1-3]      disable
227 	 */
228 	cx18_av_and_or4(cx, CXADEC_AFE_CTRL, 0xFF000000, 0x00005D00);
229 
230 /*	if(dwEnable && dw3DCombAvailable) { */
231 /*		CxDevWrReg(CXADEC_SRC_COMB_CFG, 0x7728021F); */
232 /*    } else { */
233 /*		CxDevWrReg(CXADEC_SRC_COMB_CFG, 0x6628021F); */
234 /*    } */
235 	cx18_av_write4(cx, CXADEC_SRC_COMB_CFG, 0x6628021F);
236 	default_volume = cx18_av_read(cx, 0x8d4);
237 	/*
238 	 * Enforce the legacy volume scale mapping limits to avoid
239 	 * -ERANGE errors when initializing the volume control
240 	 */
241 	if (default_volume > 228) {
242 		/* Bottom out at -96 dB, v4l2 vol range 0x2e00-0x2fff */
243 		default_volume = 228;
244 		cx18_av_write(cx, 0x8d4, 228);
245 	} else if (default_volume < 20) {
246 		/* Top out at + 8 dB, v4l2 vol range 0xfe00-0xffff */
247 		default_volume = 20;
248 		cx18_av_write(cx, 0x8d4, 20);
249 	}
250 	default_volume = (((228 - default_volume) >> 1) + 23) << 9;
251 	state->volume->cur.val = state->volume->default_value = default_volume;
252 	v4l2_ctrl_handler_setup(&state->hdl);
253 }
254 
255 static int cx18_av_reset(struct v4l2_subdev *sd, u32 val)
256 {
257 	cx18_av_initialize(sd);
258 	return 0;
259 }
260 
261 static int cx18_av_load_fw(struct v4l2_subdev *sd)
262 {
263 	struct cx18_av_state *state = to_cx18_av_state(sd);
264 
265 	if (!state->is_initialized) {
266 		/* initialize on first use */
267 		state->is_initialized = 1;
268 		cx18_av_initialize(sd);
269 	}
270 	return 0;
271 }
272 
273 void cx18_av_std_setup(struct cx18 *cx)
274 {
275 	struct cx18_av_state *state = &cx->av_state;
276 	struct v4l2_subdev *sd = &state->sd;
277 	v4l2_std_id std = state->std;
278 
279 	/*
280 	 * Video ADC crystal clock to pixel clock SRC decimation ratio
281 	 * 28.636360 MHz/13.5 Mpps * 256 = 0x21f.07b
282 	 */
283 	const int src_decimation = 0x21f;
284 
285 	int hblank, hactive, burst, vblank, vactive, sc;
286 	int vblank656;
287 	int luma_lpf, uv_lpf, comb;
288 	u32 pll_int, pll_frac, pll_post;
289 
290 	/* datasheet startup, step 8d */
291 	if (std & ~V4L2_STD_NTSC)
292 		cx18_av_write(cx, 0x49f, 0x11);
293 	else
294 		cx18_av_write(cx, 0x49f, 0x14);
295 
296 	/*
297 	 * Note: At the end of a field, there are 3 sets of half line duration
298 	 * (double horizontal rate) pulses:
299 	 *
300 	 * 5 (625) or 6 (525) half-lines to blank for the vertical retrace
301 	 * 5 (625) or 6 (525) vertical sync pulses of half line duration
302 	 * 5 (625) or 6 (525) half-lines of equalization pulses
303 	 */
304 	if (std & V4L2_STD_625_50) {
305 		/*
306 		 * The following relationships of half line counts should hold:
307 		 * 625 = vblank656 + vactive
308 		 * 10 = vblank656 - vblank = vsync pulses + equalization pulses
309 		 *
310 		 * vblank656: half lines after line 625/mid-313 of blanked video
311 		 * vblank:    half lines, after line 5/317, of blanked video
312 		 * vactive:   half lines of active video +
313 		 *		5 half lines after the end of active video
314 		 *
315 		 * As far as I can tell:
316 		 * vblank656 starts counting from the falling edge of the first
317 		 *	vsync pulse (start of line 1 or mid-313)
318 		 * vblank starts counting from the after the 5 vsync pulses and
319 		 *	5 or 4 equalization pulses (start of line 6 or 318)
320 		 *
321 		 * For 625 line systems the driver will extract VBI information
322 		 * from lines 6-23 and lines 318-335 (but the slicer can only
323 		 * handle 17 lines, not the 18 in the vblank region).
324 		 * In addition, we need vblank656 and vblank to be one whole
325 		 * line longer, to cover line 24 and 336, so the SAV/EAV RP
326 		 * codes get generated such that the encoder can actually
327 		 * extract line 23 & 335 (WSS).  We'll lose 1 line in each field
328 		 * at the top of the screen.
329 		 *
330 		 * It appears the 5 half lines that happen after active
331 		 * video must be included in vactive (579 instead of 574),
332 		 * otherwise the colors get badly displayed in various regions
333 		 * of the screen.  I guess the chroma comb filter gets confused
334 		 * without them (at least when a PVR-350 is the PAL source).
335 		 */
336 		vblank656 = 48; /* lines  1 -  24  &  313 - 336 */
337 		vblank = 38;    /* lines  6 -  24  &  318 - 336 */
338 		vactive = 579;  /* lines 24 - 313  &  337 - 626 */
339 
340 		/*
341 		 * For a 13.5 Mpps clock and 15,625 Hz line rate, a line is
342 		 * is 864 pixels = 720 active + 144 blanking.  ITU-R BT.601
343 		 * specifies 12 luma clock periods or ~ 0.9 * 13.5 Mpps after
344 		 * the end of active video to start a horizontal line, so that
345 		 * leaves 132 pixels of hblank to ignore.
346 		 */
347 		hblank = 132;
348 		hactive = 720;
349 
350 		/*
351 		 * Burst gate delay (for 625 line systems)
352 		 * Hsync leading edge to color burst rise = 5.6 us
353 		 * Color burst width = 2.25 us
354 		 * Gate width = 4 pixel clocks
355 		 * (5.6 us + 2.25/2 us) * 13.5 Mpps + 4/2 clocks = 92.79 clocks
356 		 */
357 		burst = 93;
358 		luma_lpf = 2;
359 		if (std & V4L2_STD_PAL) {
360 			uv_lpf = 1;
361 			comb = 0x20;
362 			/* sc = 4433618.75 * src_decimation/28636360 * 2^13 */
363 			sc = 688700;
364 		} else if (std == V4L2_STD_PAL_Nc) {
365 			uv_lpf = 1;
366 			comb = 0x20;
367 			/* sc = 3582056.25 * src_decimation/28636360 * 2^13 */
368 			sc = 556422;
369 		} else { /* SECAM */
370 			uv_lpf = 0;
371 			comb = 0;
372 			/* (fr + fb)/2 = (4406260 + 4250000)/2 = 4328130 */
373 			/* sc = 4328130 * src_decimation/28636360 * 2^13 */
374 			sc = 672314;
375 		}
376 	} else {
377 		/*
378 		 * The following relationships of half line counts should hold:
379 		 * 525 = prevsync + vblank656 + vactive
380 		 * 12 = vblank656 - vblank = vsync pulses + equalization pulses
381 		 *
382 		 * prevsync:  6 half-lines before the vsync pulses
383 		 * vblank656: half lines, after line 3/mid-266, of blanked video
384 		 * vblank:    half lines, after line 9/272, of blanked video
385 		 * vactive:   half lines of active video
386 		 *
387 		 * As far as I can tell:
388 		 * vblank656 starts counting from the falling edge of the first
389 		 *	vsync pulse (start of line 4 or mid-266)
390 		 * vblank starts counting from the after the 6 vsync pulses and
391 		 *	6 or 5 equalization pulses (start of line 10 or 272)
392 		 *
393 		 * For 525 line systems the driver will extract VBI information
394 		 * from lines 10-21 and lines 273-284.
395 		 */
396 		vblank656 = 38; /* lines  4 -  22  &  266 - 284 */
397 		vblank = 26;	/* lines 10 -  22  &  272 - 284 */
398 		vactive = 481;  /* lines 23 - 263  &  285 - 525 */
399 
400 		/*
401 		 * For a 13.5 Mpps clock and 15,734.26 Hz line rate, a line is
402 		 * is 858 pixels = 720 active + 138 blanking.  The Hsync leading
403 		 * edge should happen 1.2 us * 13.5 Mpps ~= 16 pixels after the
404 		 * end of active video, leaving 122 pixels of hblank to ignore
405 		 * before active video starts.
406 		 */
407 		hactive = 720;
408 		hblank = 122;
409 		luma_lpf = 1;
410 		uv_lpf = 1;
411 
412 		/*
413 		 * Burst gate delay (for 525 line systems)
414 		 * Hsync leading edge to color burst rise = 5.3 us
415 		 * Color burst width = 2.5 us
416 		 * Gate width = 4 pixel clocks
417 		 * (5.3 us + 2.5/2 us) * 13.5 Mpps + 4/2 clocks = 90.425 clocks
418 		 */
419 		if (std == V4L2_STD_PAL_60) {
420 			burst = 90;
421 			luma_lpf = 2;
422 			comb = 0x20;
423 			/* sc = 4433618.75 * src_decimation/28636360 * 2^13 */
424 			sc = 688700;
425 		} else if (std == V4L2_STD_PAL_M) {
426 			/* The 97 needs to be verified against PAL-M timings */
427 			burst = 97;
428 			comb = 0x20;
429 			/* sc = 3575611.49 * src_decimation/28636360 * 2^13 */
430 			sc = 555421;
431 		} else {
432 			burst = 90;
433 			comb = 0x66;
434 			/* sc = 3579545.45.. * src_decimation/28636360 * 2^13 */
435 			sc = 556032;
436 		}
437 	}
438 
439 	/* DEBUG: Displays configured PLL frequency */
440 	pll_int = cx18_av_read(cx, 0x108);
441 	pll_frac = cx18_av_read4(cx, 0x10c) & 0x1ffffff;
442 	pll_post = cx18_av_read(cx, 0x109);
443 	CX18_DEBUG_INFO_DEV(sd, "PLL regs = int: %u, frac: %u, post: %u\n",
444 			    pll_int, pll_frac, pll_post);
445 
446 	if (pll_post) {
447 		int fsc, pll;
448 		u64 tmp;
449 
450 		pll = (28636360L * ((((u64)pll_int) << 25) + pll_frac)) >> 25;
451 		pll /= pll_post;
452 		CX18_DEBUG_INFO_DEV(sd, "Video PLL = %d.%06d MHz\n",
453 				    pll / 1000000, pll % 1000000);
454 		CX18_DEBUG_INFO_DEV(sd, "Pixel rate = %d.%06d Mpixel/sec\n",
455 				    pll / 8000000, (pll / 8) % 1000000);
456 
457 		CX18_DEBUG_INFO_DEV(sd, "ADC XTAL/pixel clock decimation ratio = %d.%03d\n",
458 				    src_decimation / 256,
459 				    ((src_decimation % 256) * 1000) / 256);
460 
461 		tmp = 28636360 * (u64) sc;
462 		do_div(tmp, src_decimation);
463 		fsc = tmp >> 13;
464 		CX18_DEBUG_INFO_DEV(sd,
465 				    "Chroma sub-carrier initial freq = %d.%06d MHz\n",
466 				    fsc / 1000000, fsc % 1000000);
467 
468 		CX18_DEBUG_INFO_DEV(sd,
469 				    "hblank %i, hactive %i, vblank %i, vactive %i, vblank656 %i, src_dec %i, burst 0x%02x, luma_lpf %i, uv_lpf %i, comb 0x%02x, sc 0x%06x\n",
470 				    hblank, hactive, vblank, vactive, vblank656,
471 				    src_decimation, burst, luma_lpf, uv_lpf,
472 				    comb, sc);
473 	}
474 
475 	/* Sets horizontal blanking delay and active lines */
476 	cx18_av_write(cx, 0x470, hblank);
477 	cx18_av_write(cx, 0x471,
478 		      (((hblank >> 8) & 0x3) | (hactive << 4)) & 0xff);
479 	cx18_av_write(cx, 0x472, hactive >> 4);
480 
481 	/* Sets burst gate delay */
482 	cx18_av_write(cx, 0x473, burst);
483 
484 	/* Sets vertical blanking delay and active duration */
485 	cx18_av_write(cx, 0x474, vblank);
486 	cx18_av_write(cx, 0x475,
487 		      (((vblank >> 8) & 0x3) | (vactive << 4)) & 0xff);
488 	cx18_av_write(cx, 0x476, vactive >> 4);
489 	cx18_av_write(cx, 0x477, vblank656);
490 
491 	/* Sets src decimation rate */
492 	cx18_av_write(cx, 0x478, src_decimation & 0xff);
493 	cx18_av_write(cx, 0x479, (src_decimation >> 8) & 0xff);
494 
495 	/* Sets Luma and UV Low pass filters */
496 	cx18_av_write(cx, 0x47a, luma_lpf << 6 | ((uv_lpf << 4) & 0x30));
497 
498 	/* Enables comb filters */
499 	cx18_av_write(cx, 0x47b, comb);
500 
501 	/* Sets SC Step*/
502 	cx18_av_write(cx, 0x47c, sc);
503 	cx18_av_write(cx, 0x47d, (sc >> 8) & 0xff);
504 	cx18_av_write(cx, 0x47e, (sc >> 16) & 0xff);
505 
506 	if (std & V4L2_STD_625_50) {
507 		state->slicer_line_delay = 1;
508 		state->slicer_line_offset = (6 + state->slicer_line_delay - 2);
509 	} else {
510 		state->slicer_line_delay = 0;
511 		state->slicer_line_offset = (10 + state->slicer_line_delay - 2);
512 	}
513 	cx18_av_write(cx, 0x47f, state->slicer_line_delay);
514 }
515 
516 static void input_change(struct cx18 *cx)
517 {
518 	struct cx18_av_state *state = &cx->av_state;
519 	v4l2_std_id std = state->std;
520 	u8 v;
521 
522 	/* Follow step 8c and 8d of section 3.16 in the cx18_av datasheet */
523 	cx18_av_write(cx, 0x49f, (std & V4L2_STD_NTSC) ? 0x14 : 0x11);
524 	cx18_av_and_or(cx, 0x401, ~0x60, 0);
525 	cx18_av_and_or(cx, 0x401, ~0x60, 0x60);
526 
527 	if (std & V4L2_STD_525_60) {
528 		if (std == V4L2_STD_NTSC_M_JP) {
529 			/* Japan uses EIAJ audio standard */
530 			cx18_av_write_expect(cx, 0x808, 0xf7, 0xf7, 0xff);
531 			cx18_av_write_expect(cx, 0x80b, 0x02, 0x02, 0x3f);
532 		} else if (std == V4L2_STD_NTSC_M_KR) {
533 			/* South Korea uses A2 audio standard */
534 			cx18_av_write_expect(cx, 0x808, 0xf8, 0xf8, 0xff);
535 			cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f);
536 		} else {
537 			/* Others use the BTSC audio standard */
538 			cx18_av_write_expect(cx, 0x808, 0xf6, 0xf6, 0xff);
539 			cx18_av_write_expect(cx, 0x80b, 0x01, 0x01, 0x3f);
540 		}
541 	} else if (std & V4L2_STD_PAL) {
542 		/* Follow tuner change procedure for PAL */
543 		cx18_av_write_expect(cx, 0x808, 0xff, 0xff, 0xff);
544 		cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f);
545 	} else if (std & V4L2_STD_SECAM) {
546 		/* Select autodetect for SECAM */
547 		cx18_av_write_expect(cx, 0x808, 0xff, 0xff, 0xff);
548 		cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f);
549 	}
550 
551 	v = cx18_av_read(cx, 0x803);
552 	if (v & 0x10) {
553 		/* restart audio decoder microcontroller */
554 		v &= ~0x10;
555 		cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
556 		v |= 0x10;
557 		cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
558 	}
559 }
560 
561 static int cx18_av_s_frequency(struct v4l2_subdev *sd,
562 			       const struct v4l2_frequency *freq)
563 {
564 	struct cx18 *cx = v4l2_get_subdevdata(sd);
565 	input_change(cx);
566 	return 0;
567 }
568 
569 static int set_input(struct cx18 *cx, enum cx18_av_video_input vid_input,
570 					enum cx18_av_audio_input aud_input)
571 {
572 	struct cx18_av_state *state = &cx->av_state;
573 	struct v4l2_subdev *sd = &state->sd;
574 
575 	enum analog_signal_type {
576 		NONE, CVBS, Y, C, SIF, Pb, Pr
577 	} ch[3] = {NONE, NONE, NONE};
578 
579 	u8 afe_mux_cfg;
580 	u8 adc2_cfg;
581 	u8 input_mode;
582 	u32 afe_cfg;
583 	int i;
584 
585 	CX18_DEBUG_INFO_DEV(sd, "decoder set video input %d, audio input %d\n",
586 			    vid_input, aud_input);
587 
588 	if (vid_input >= CX18_AV_COMPOSITE1 &&
589 	    vid_input <= CX18_AV_COMPOSITE8) {
590 		afe_mux_cfg = 0xf0 + (vid_input - CX18_AV_COMPOSITE1);
591 		ch[0] = CVBS;
592 		input_mode = 0x0;
593 	} else if (vid_input >= CX18_AV_COMPONENT_LUMA1) {
594 		int luma = vid_input & 0xf000;
595 		int r_chroma = vid_input & 0xf0000;
596 		int b_chroma = vid_input & 0xf00000;
597 
598 		if ((vid_input & ~0xfff000) ||
599 		    luma < CX18_AV_COMPONENT_LUMA1 ||
600 		    luma > CX18_AV_COMPONENT_LUMA8 ||
601 		    r_chroma < CX18_AV_COMPONENT_R_CHROMA4 ||
602 		    r_chroma > CX18_AV_COMPONENT_R_CHROMA6 ||
603 		    b_chroma < CX18_AV_COMPONENT_B_CHROMA7 ||
604 		    b_chroma > CX18_AV_COMPONENT_B_CHROMA8) {
605 			CX18_ERR_DEV(sd, "0x%06x is not a valid video input!\n",
606 				     vid_input);
607 			return -EINVAL;
608 		}
609 		afe_mux_cfg = (luma - CX18_AV_COMPONENT_LUMA1) >> 12;
610 		ch[0] = Y;
611 		afe_mux_cfg |= (r_chroma - CX18_AV_COMPONENT_R_CHROMA4) >> 12;
612 		ch[1] = Pr;
613 		afe_mux_cfg |= (b_chroma - CX18_AV_COMPONENT_B_CHROMA7) >> 14;
614 		ch[2] = Pb;
615 		input_mode = 0x6;
616 	} else {
617 		int luma = vid_input & 0xf0;
618 		int chroma = vid_input & 0xf00;
619 
620 		if ((vid_input & ~0xff0) ||
621 		    luma < CX18_AV_SVIDEO_LUMA1 ||
622 		    luma > CX18_AV_SVIDEO_LUMA8 ||
623 		    chroma < CX18_AV_SVIDEO_CHROMA4 ||
624 		    chroma > CX18_AV_SVIDEO_CHROMA8) {
625 			CX18_ERR_DEV(sd, "0x%06x is not a valid video input!\n",
626 				     vid_input);
627 			return -EINVAL;
628 		}
629 		afe_mux_cfg = 0xf0 + ((luma - CX18_AV_SVIDEO_LUMA1) >> 4);
630 		ch[0] = Y;
631 		if (chroma >= CX18_AV_SVIDEO_CHROMA7) {
632 			afe_mux_cfg &= 0x3f;
633 			afe_mux_cfg |= (chroma - CX18_AV_SVIDEO_CHROMA7) >> 2;
634 			ch[2] = C;
635 		} else {
636 			afe_mux_cfg &= 0xcf;
637 			afe_mux_cfg |= (chroma - CX18_AV_SVIDEO_CHROMA4) >> 4;
638 			ch[1] = C;
639 		}
640 		input_mode = 0x2;
641 	}
642 
643 	switch (aud_input) {
644 	case CX18_AV_AUDIO_SERIAL1:
645 	case CX18_AV_AUDIO_SERIAL2:
646 		/* do nothing, use serial audio input */
647 		break;
648 	case CX18_AV_AUDIO4:
649 		afe_mux_cfg &= ~0x30;
650 		ch[1] = SIF;
651 		break;
652 	case CX18_AV_AUDIO5:
653 		afe_mux_cfg = (afe_mux_cfg & ~0x30) | 0x10;
654 		ch[1] = SIF;
655 		break;
656 	case CX18_AV_AUDIO6:
657 		afe_mux_cfg = (afe_mux_cfg & ~0x30) | 0x20;
658 		ch[1] = SIF;
659 		break;
660 	case CX18_AV_AUDIO7:
661 		afe_mux_cfg &= ~0xc0;
662 		ch[2] = SIF;
663 		break;
664 	case CX18_AV_AUDIO8:
665 		afe_mux_cfg = (afe_mux_cfg & ~0xc0) | 0x40;
666 		ch[2] = SIF;
667 		break;
668 
669 	default:
670 		CX18_ERR_DEV(sd, "0x%04x is not a valid audio input!\n",
671 			     aud_input);
672 		return -EINVAL;
673 	}
674 
675 	/* Set up analog front end multiplexers */
676 	cx18_av_write_expect(cx, 0x103, afe_mux_cfg, afe_mux_cfg, 0xf7);
677 	/* Set INPUT_MODE to Composite, S-Video, or Component */
678 	cx18_av_and_or(cx, 0x401, ~0x6, input_mode);
679 
680 	/* Set CH_SEL_ADC2 to 1 if input comes from CH3 */
681 	adc2_cfg = cx18_av_read(cx, 0x102);
682 	if (ch[2] == NONE)
683 		adc2_cfg &= ~0x2; /* No sig on CH3, set ADC2 to CH2 for input */
684 	else
685 		adc2_cfg |= 0x2;  /* Signal on CH3, set ADC2 to CH3 for input */
686 
687 	/* Set DUAL_MODE_ADC2 to 1 if input comes from both CH2 and CH3 */
688 	if (ch[1] != NONE && ch[2] != NONE)
689 		adc2_cfg |= 0x4; /* Set dual mode */
690 	else
691 		adc2_cfg &= ~0x4; /* Clear dual mode */
692 	cx18_av_write_expect(cx, 0x102, adc2_cfg, adc2_cfg, 0x17);
693 
694 	/* Configure the analog front end */
695 	afe_cfg = cx18_av_read4(cx, CXADEC_AFE_CTRL);
696 	afe_cfg &= 0xff000000;
697 	afe_cfg |= 0x00005000; /* CHROMA_IN, AUD_IN: ADC2; LUMA_IN: ADC1 */
698 	if (ch[1] != NONE && ch[2] != NONE)
699 		afe_cfg |= 0x00000030; /* half_bw_ch[2-3] since in dual mode */
700 
701 	for (i = 0; i < 3; i++) {
702 		switch (ch[i]) {
703 		default:
704 		case NONE:
705 			/* CLAMP_SEL = Fixed to midcode clamp level */
706 			afe_cfg |= (0x00000200 << i);
707 			break;
708 		case CVBS:
709 		case Y:
710 			if (i > 0)
711 				afe_cfg |= 0x00002000; /* LUMA_IN_SEL: ADC2 */
712 			break;
713 		case C:
714 		case Pb:
715 		case Pr:
716 			/* CLAMP_SEL = Fixed to midcode clamp level */
717 			afe_cfg |= (0x00000200 << i);
718 			if (i == 0 && ch[i] == C)
719 				afe_cfg &= ~0x00001000; /* CHROMA_IN_SEL ADC1 */
720 			break;
721 		case SIF:
722 			/*
723 			 * VGA_GAIN_SEL = Audio Decoder
724 			 * CLAMP_SEL = Fixed to midcode clamp level
725 			 */
726 			afe_cfg |= (0x00000240 << i);
727 			if (i == 0)
728 				afe_cfg &= ~0x00004000; /* AUD_IN_SEL ADC1 */
729 			break;
730 		}
731 	}
732 
733 	cx18_av_write4(cx, CXADEC_AFE_CTRL, afe_cfg);
734 
735 	state->vid_input = vid_input;
736 	state->aud_input = aud_input;
737 	cx18_av_audio_set_path(cx);
738 	input_change(cx);
739 	return 0;
740 }
741 
742 static int cx18_av_s_video_routing(struct v4l2_subdev *sd,
743 				   u32 input, u32 output, u32 config)
744 {
745 	struct cx18_av_state *state = to_cx18_av_state(sd);
746 	struct cx18 *cx = v4l2_get_subdevdata(sd);
747 	return set_input(cx, input, state->aud_input);
748 }
749 
750 static int cx18_av_s_audio_routing(struct v4l2_subdev *sd,
751 				   u32 input, u32 output, u32 config)
752 {
753 	struct cx18_av_state *state = to_cx18_av_state(sd);
754 	struct cx18 *cx = v4l2_get_subdevdata(sd);
755 	return set_input(cx, state->vid_input, input);
756 }
757 
758 static int cx18_av_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
759 {
760 	struct cx18_av_state *state = to_cx18_av_state(sd);
761 	struct cx18 *cx = v4l2_get_subdevdata(sd);
762 	u8 vpres;
763 	u8 mode;
764 	int val = 0;
765 
766 	if (state->radio)
767 		return 0;
768 
769 	vpres = cx18_av_read(cx, 0x40e) & 0x20;
770 	vt->signal = vpres ? 0xffff : 0x0;
771 
772 	vt->capability |=
773 		    V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_LANG1 |
774 		    V4L2_TUNER_CAP_LANG2 | V4L2_TUNER_CAP_SAP;
775 
776 	mode = cx18_av_read(cx, 0x804);
777 
778 	/* get rxsubchans and audmode */
779 	if ((mode & 0xf) == 1)
780 		val |= V4L2_TUNER_SUB_STEREO;
781 	else
782 		val |= V4L2_TUNER_SUB_MONO;
783 
784 	if (mode == 2 || mode == 4)
785 		val = V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
786 
787 	if (mode & 0x10)
788 		val |= V4L2_TUNER_SUB_SAP;
789 
790 	vt->rxsubchans = val;
791 	vt->audmode = state->audmode;
792 	return 0;
793 }
794 
795 static int cx18_av_s_tuner(struct v4l2_subdev *sd, const struct v4l2_tuner *vt)
796 {
797 	struct cx18_av_state *state = to_cx18_av_state(sd);
798 	struct cx18 *cx = v4l2_get_subdevdata(sd);
799 	u8 v;
800 
801 	if (state->radio)
802 		return 0;
803 
804 	v = cx18_av_read(cx, 0x809);
805 	v &= ~0xf;
806 
807 	switch (vt->audmode) {
808 	case V4L2_TUNER_MODE_MONO:
809 		/* mono      -> mono
810 		   stereo    -> mono
811 		   bilingual -> lang1 */
812 		break;
813 	case V4L2_TUNER_MODE_STEREO:
814 	case V4L2_TUNER_MODE_LANG1:
815 		/* mono      -> mono
816 		   stereo    -> stereo
817 		   bilingual -> lang1 */
818 		v |= 0x4;
819 		break;
820 	case V4L2_TUNER_MODE_LANG1_LANG2:
821 		/* mono      -> mono
822 		   stereo    -> stereo
823 		   bilingual -> lang1/lang2 */
824 		v |= 0x7;
825 		break;
826 	case V4L2_TUNER_MODE_LANG2:
827 		/* mono      -> mono
828 		   stereo    -> stereo
829 		   bilingual -> lang2 */
830 		v |= 0x1;
831 		break;
832 	default:
833 		return -EINVAL;
834 	}
835 	cx18_av_write_expect(cx, 0x809, v, v, 0xff);
836 	state->audmode = vt->audmode;
837 	return 0;
838 }
839 
840 static int cx18_av_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
841 {
842 	struct cx18_av_state *state = to_cx18_av_state(sd);
843 	struct cx18 *cx = v4l2_get_subdevdata(sd);
844 
845 	u8 fmt = 0;	/* zero is autodetect */
846 	u8 pal_m = 0;
847 
848 	if (state->radio == 0 && state->std == norm)
849 		return 0;
850 
851 	state->radio = 0;
852 	state->std = norm;
853 
854 	/* First tests should be against specific std */
855 	if (state->std == V4L2_STD_NTSC_M_JP) {
856 		fmt = 0x2;
857 	} else if (state->std == V4L2_STD_NTSC_443) {
858 		fmt = 0x3;
859 	} else if (state->std == V4L2_STD_PAL_M) {
860 		pal_m = 1;
861 		fmt = 0x5;
862 	} else if (state->std == V4L2_STD_PAL_N) {
863 		fmt = 0x6;
864 	} else if (state->std == V4L2_STD_PAL_Nc) {
865 		fmt = 0x7;
866 	} else if (state->std == V4L2_STD_PAL_60) {
867 		fmt = 0x8;
868 	} else {
869 		/* Then, test against generic ones */
870 		if (state->std & V4L2_STD_NTSC)
871 			fmt = 0x1;
872 		else if (state->std & V4L2_STD_PAL)
873 			fmt = 0x4;
874 		else if (state->std & V4L2_STD_SECAM)
875 			fmt = 0xc;
876 	}
877 
878 	CX18_DEBUG_INFO_DEV(sd, "changing video std to fmt %i\n", fmt);
879 
880 	/* Follow step 9 of section 3.16 in the cx18_av datasheet.
881 	   Without this PAL may display a vertical ghosting effect.
882 	   This happens for example with the Yuan MPC622. */
883 	if (fmt >= 4 && fmt < 8) {
884 		/* Set format to NTSC-M */
885 		cx18_av_and_or(cx, 0x400, ~0xf, 1);
886 		/* Turn off LCOMB */
887 		cx18_av_and_or(cx, 0x47b, ~6, 0);
888 	}
889 	cx18_av_and_or(cx, 0x400, ~0x2f, fmt | 0x20);
890 	cx18_av_and_or(cx, 0x403, ~0x3, pal_m);
891 	cx18_av_std_setup(cx);
892 	input_change(cx);
893 	return 0;
894 }
895 
896 static int cx18_av_s_radio(struct v4l2_subdev *sd)
897 {
898 	struct cx18_av_state *state = to_cx18_av_state(sd);
899 	state->radio = 1;
900 	return 0;
901 }
902 
903 static int cx18_av_s_ctrl(struct v4l2_ctrl *ctrl)
904 {
905 	struct v4l2_subdev *sd = to_sd(ctrl);
906 	struct cx18 *cx = v4l2_get_subdevdata(sd);
907 
908 	switch (ctrl->id) {
909 	case V4L2_CID_BRIGHTNESS:
910 		cx18_av_write(cx, 0x414, ctrl->val - 128);
911 		break;
912 
913 	case V4L2_CID_CONTRAST:
914 		cx18_av_write(cx, 0x415, ctrl->val << 1);
915 		break;
916 
917 	case V4L2_CID_SATURATION:
918 		cx18_av_write(cx, 0x420, ctrl->val << 1);
919 		cx18_av_write(cx, 0x421, ctrl->val << 1);
920 		break;
921 
922 	case V4L2_CID_HUE:
923 		cx18_av_write(cx, 0x422, ctrl->val);
924 		break;
925 
926 	default:
927 		return -EINVAL;
928 	}
929 	return 0;
930 }
931 
932 static int cx18_av_set_fmt(struct v4l2_subdev *sd,
933 		struct v4l2_subdev_pad_config *cfg,
934 		struct v4l2_subdev_format *format)
935 {
936 	struct v4l2_mbus_framefmt *fmt = &format->format;
937 	struct cx18_av_state *state = to_cx18_av_state(sd);
938 	struct cx18 *cx = v4l2_get_subdevdata(sd);
939 	int HSC, VSC, Vsrc, Hsrc, filter, Vlines;
940 	int is_50Hz = !(state->std & V4L2_STD_525_60);
941 
942 	if (format->pad || fmt->code != MEDIA_BUS_FMT_FIXED)
943 		return -EINVAL;
944 
945 	fmt->field = V4L2_FIELD_INTERLACED;
946 	fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
947 
948 	Vsrc = (cx18_av_read(cx, 0x476) & 0x3f) << 4;
949 	Vsrc |= (cx18_av_read(cx, 0x475) & 0xf0) >> 4;
950 
951 	Hsrc = (cx18_av_read(cx, 0x472) & 0x3f) << 4;
952 	Hsrc |= (cx18_av_read(cx, 0x471) & 0xf0) >> 4;
953 
954 	/*
955 	 * This adjustment reflects the excess of vactive, set in
956 	 * cx18_av_std_setup(), above standard values:
957 	 *
958 	 * 480 + 1 for 60 Hz systems
959 	 * 576 + 3 for 50 Hz systems
960 	 */
961 	Vlines = fmt->height + (is_50Hz ? 3 : 1);
962 
963 	/*
964 	 * Invalid height and width scaling requests are:
965 	 * 1. width less than 1/16 of the source width
966 	 * 2. width greater than the source width
967 	 * 3. height less than 1/8 of the source height
968 	 * 4. height greater than the source height
969 	 */
970 	if ((fmt->width * 16 < Hsrc) || (Hsrc < fmt->width) ||
971 	    (Vlines * 8 < Vsrc) || (Vsrc < Vlines)) {
972 		CX18_ERR_DEV(sd, "%dx%d is not a valid size!\n",
973 			     fmt->width, fmt->height);
974 		return -ERANGE;
975 	}
976 
977 	if (format->which == V4L2_SUBDEV_FORMAT_TRY)
978 		return 0;
979 
980 	HSC = (Hsrc * (1 << 20)) / fmt->width - (1 << 20);
981 	VSC = (1 << 16) - (Vsrc * (1 << 9) / Vlines - (1 << 9));
982 	VSC &= 0x1fff;
983 
984 	if (fmt->width >= 385)
985 		filter = 0;
986 	else if (fmt->width > 192)
987 		filter = 1;
988 	else if (fmt->width > 96)
989 		filter = 2;
990 	else
991 		filter = 3;
992 
993 	CX18_DEBUG_INFO_DEV(sd,
994 			    "decoder set size %dx%d -> scale  %ux%u\n",
995 			    fmt->width, fmt->height, HSC, VSC);
996 
997 	/* HSCALE=HSC */
998 	cx18_av_write(cx, 0x418, HSC & 0xff);
999 	cx18_av_write(cx, 0x419, (HSC >> 8) & 0xff);
1000 	cx18_av_write(cx, 0x41a, HSC >> 16);
1001 	/* VSCALE=VSC */
1002 	cx18_av_write(cx, 0x41c, VSC & 0xff);
1003 	cx18_av_write(cx, 0x41d, VSC >> 8);
1004 	/* VS_INTRLACE=1 VFILT=filter */
1005 	cx18_av_write(cx, 0x41e, 0x8 | filter);
1006 	return 0;
1007 }
1008 
1009 static int cx18_av_s_stream(struct v4l2_subdev *sd, int enable)
1010 {
1011 	struct cx18 *cx = v4l2_get_subdevdata(sd);
1012 
1013 	CX18_DEBUG_INFO_DEV(sd, "%s output\n", enable ? "enable" : "disable");
1014 	if (enable) {
1015 		cx18_av_write(cx, 0x115, 0x8c);
1016 		cx18_av_write(cx, 0x116, 0x07);
1017 	} else {
1018 		cx18_av_write(cx, 0x115, 0x00);
1019 		cx18_av_write(cx, 0x116, 0x00);
1020 	}
1021 	return 0;
1022 }
1023 
1024 static void log_video_status(struct cx18 *cx)
1025 {
1026 	static const char *const fmt_strs[] = {
1027 		"0x0",
1028 		"NTSC-M", "NTSC-J", "NTSC-4.43",
1029 		"PAL-BDGHI", "PAL-M", "PAL-N", "PAL-Nc", "PAL-60",
1030 		"0x9", "0xA", "0xB",
1031 		"SECAM",
1032 		"0xD", "0xE", "0xF"
1033 	};
1034 
1035 	struct cx18_av_state *state = &cx->av_state;
1036 	struct v4l2_subdev *sd = &state->sd;
1037 	u8 vidfmt_sel = cx18_av_read(cx, 0x400) & 0xf;
1038 	u8 gen_stat1 = cx18_av_read(cx, 0x40d);
1039 	u8 gen_stat2 = cx18_av_read(cx, 0x40e);
1040 	int vid_input = state->vid_input;
1041 
1042 	CX18_INFO_DEV(sd, "Video signal:              %spresent\n",
1043 		      (gen_stat2 & 0x20) ? "" : "not ");
1044 	CX18_INFO_DEV(sd, "Detected format:           %s\n",
1045 		      fmt_strs[gen_stat1 & 0xf]);
1046 
1047 	CX18_INFO_DEV(sd, "Specified standard:        %s\n",
1048 		      vidfmt_sel ? fmt_strs[vidfmt_sel]
1049 				 : "automatic detection");
1050 
1051 	if (vid_input >= CX18_AV_COMPOSITE1 &&
1052 	    vid_input <= CX18_AV_COMPOSITE8) {
1053 		CX18_INFO_DEV(sd, "Specified video input:     Composite %d\n",
1054 			      vid_input - CX18_AV_COMPOSITE1 + 1);
1055 	} else {
1056 		CX18_INFO_DEV(sd, "Specified video input:     S-Video (Luma In%d, Chroma In%d)\n",
1057 			      (vid_input & 0xf0) >> 4,
1058 			      (vid_input & 0xf00) >> 8);
1059 	}
1060 
1061 	CX18_INFO_DEV(sd, "Specified audioclock freq: %d Hz\n",
1062 		      state->audclk_freq);
1063 }
1064 
1065 static void log_audio_status(struct cx18 *cx)
1066 {
1067 	struct cx18_av_state *state = &cx->av_state;
1068 	struct v4l2_subdev *sd = &state->sd;
1069 	u8 download_ctl = cx18_av_read(cx, 0x803);
1070 	u8 mod_det_stat0 = cx18_av_read(cx, 0x804);
1071 	u8 mod_det_stat1 = cx18_av_read(cx, 0x805);
1072 	u8 audio_config = cx18_av_read(cx, 0x808);
1073 	u8 pref_mode = cx18_av_read(cx, 0x809);
1074 	u8 afc0 = cx18_av_read(cx, 0x80b);
1075 	u8 mute_ctl = cx18_av_read(cx, 0x8d3);
1076 	int aud_input = state->aud_input;
1077 	char *p;
1078 
1079 	switch (mod_det_stat0) {
1080 	case 0x00: p = "mono"; break;
1081 	case 0x01: p = "stereo"; break;
1082 	case 0x02: p = "dual"; break;
1083 	case 0x04: p = "tri"; break;
1084 	case 0x10: p = "mono with SAP"; break;
1085 	case 0x11: p = "stereo with SAP"; break;
1086 	case 0x12: p = "dual with SAP"; break;
1087 	case 0x14: p = "tri with SAP"; break;
1088 	case 0xfe: p = "forced mode"; break;
1089 	default: p = "not defined"; break;
1090 	}
1091 	CX18_INFO_DEV(sd, "Detected audio mode:       %s\n", p);
1092 
1093 	switch (mod_det_stat1) {
1094 	case 0x00: p = "not defined"; break;
1095 	case 0x01: p = "EIAJ"; break;
1096 	case 0x02: p = "A2-M"; break;
1097 	case 0x03: p = "A2-BG"; break;
1098 	case 0x04: p = "A2-DK1"; break;
1099 	case 0x05: p = "A2-DK2"; break;
1100 	case 0x06: p = "A2-DK3"; break;
1101 	case 0x07: p = "A1 (6.0 MHz FM Mono)"; break;
1102 	case 0x08: p = "AM-L"; break;
1103 	case 0x09: p = "NICAM-BG"; break;
1104 	case 0x0a: p = "NICAM-DK"; break;
1105 	case 0x0b: p = "NICAM-I"; break;
1106 	case 0x0c: p = "NICAM-L"; break;
1107 	case 0x0d: p = "BTSC/EIAJ/A2-M Mono (4.5 MHz FMMono)"; break;
1108 	case 0x0e: p = "IF FM Radio"; break;
1109 	case 0x0f: p = "BTSC"; break;
1110 	case 0x10: p = "detected chrominance"; break;
1111 	case 0xfd: p = "unknown audio standard"; break;
1112 	case 0xfe: p = "forced audio standard"; break;
1113 	case 0xff: p = "no detected audio standard"; break;
1114 	default: p = "not defined"; break;
1115 	}
1116 	CX18_INFO_DEV(sd, "Detected audio standard:   %s\n", p);
1117 	CX18_INFO_DEV(sd, "Audio muted:               %s\n",
1118 		      (mute_ctl & 0x2) ? "yes" : "no");
1119 	CX18_INFO_DEV(sd, "Audio microcontroller:     %s\n",
1120 		      (download_ctl & 0x10) ? "running" : "stopped");
1121 
1122 	switch (audio_config >> 4) {
1123 	case 0x00: p = "undefined"; break;
1124 	case 0x01: p = "BTSC"; break;
1125 	case 0x02: p = "EIAJ"; break;
1126 	case 0x03: p = "A2-M"; break;
1127 	case 0x04: p = "A2-BG"; break;
1128 	case 0x05: p = "A2-DK1"; break;
1129 	case 0x06: p = "A2-DK2"; break;
1130 	case 0x07: p = "A2-DK3"; break;
1131 	case 0x08: p = "A1 (6.0 MHz FM Mono)"; break;
1132 	case 0x09: p = "AM-L"; break;
1133 	case 0x0a: p = "NICAM-BG"; break;
1134 	case 0x0b: p = "NICAM-DK"; break;
1135 	case 0x0c: p = "NICAM-I"; break;
1136 	case 0x0d: p = "NICAM-L"; break;
1137 	case 0x0e: p = "FM radio"; break;
1138 	case 0x0f: p = "automatic detection"; break;
1139 	default: p = "undefined"; break;
1140 	}
1141 	CX18_INFO_DEV(sd, "Configured audio standard: %s\n", p);
1142 
1143 	if ((audio_config >> 4) < 0xF) {
1144 		switch (audio_config & 0xF) {
1145 		case 0x00: p = "MONO1 (LANGUAGE A/Mono L+R channel for BTSC, EIAJ, A2)"; break;
1146 		case 0x01: p = "MONO2 (LANGUAGE B)"; break;
1147 		case 0x02: p = "MONO3 (STEREO forced MONO)"; break;
1148 		case 0x03: p = "MONO4 (NICAM ANALOG-Language C/Analog Fallback)"; break;
1149 		case 0x04: p = "STEREO"; break;
1150 		case 0x05: p = "DUAL1 (AC)"; break;
1151 		case 0x06: p = "DUAL2 (BC)"; break;
1152 		case 0x07: p = "DUAL3 (AB)"; break;
1153 		default: p = "undefined";
1154 		}
1155 		CX18_INFO_DEV(sd, "Configured audio mode:     %s\n", p);
1156 	} else {
1157 		switch (audio_config & 0xF) {
1158 		case 0x00: p = "BG"; break;
1159 		case 0x01: p = "DK1"; break;
1160 		case 0x02: p = "DK2"; break;
1161 		case 0x03: p = "DK3"; break;
1162 		case 0x04: p = "I"; break;
1163 		case 0x05: p = "L"; break;
1164 		case 0x06: p = "BTSC"; break;
1165 		case 0x07: p = "EIAJ"; break;
1166 		case 0x08: p = "A2-M"; break;
1167 		case 0x09: p = "FM Radio (4.5 MHz)"; break;
1168 		case 0x0a: p = "FM Radio (5.5 MHz)"; break;
1169 		case 0x0b: p = "S-Video"; break;
1170 		case 0x0f: p = "automatic standard and mode detection"; break;
1171 		default: p = "undefined"; break;
1172 		}
1173 		CX18_INFO_DEV(sd, "Configured audio system:   %s\n", p);
1174 	}
1175 
1176 	if (aud_input)
1177 		CX18_INFO_DEV(sd, "Specified audio input:     Tuner (In%d)\n",
1178 			      aud_input);
1179 	else
1180 		CX18_INFO_DEV(sd, "Specified audio input:     External\n");
1181 
1182 	switch (pref_mode & 0xf) {
1183 	case 0: p = "mono/language A"; break;
1184 	case 1: p = "language B"; break;
1185 	case 2: p = "language C"; break;
1186 	case 3: p = "analog fallback"; break;
1187 	case 4: p = "stereo"; break;
1188 	case 5: p = "language AC"; break;
1189 	case 6: p = "language BC"; break;
1190 	case 7: p = "language AB"; break;
1191 	default: p = "undefined"; break;
1192 	}
1193 	CX18_INFO_DEV(sd, "Preferred audio mode:      %s\n", p);
1194 
1195 	if ((audio_config & 0xf) == 0xf) {
1196 		switch ((afc0 >> 3) & 0x1) {
1197 		case 0: p = "system DK"; break;
1198 		case 1: p = "system L"; break;
1199 		}
1200 		CX18_INFO_DEV(sd, "Selected 65 MHz format:    %s\n", p);
1201 
1202 		switch (afc0 & 0x7) {
1203 		case 0: p = "Chroma"; break;
1204 		case 1: p = "BTSC"; break;
1205 		case 2: p = "EIAJ"; break;
1206 		case 3: p = "A2-M"; break;
1207 		case 4: p = "autodetect"; break;
1208 		default: p = "undefined"; break;
1209 		}
1210 		CX18_INFO_DEV(sd, "Selected 45 MHz format:    %s\n", p);
1211 	}
1212 }
1213 
1214 static int cx18_av_log_status(struct v4l2_subdev *sd)
1215 {
1216 	struct cx18 *cx = v4l2_get_subdevdata(sd);
1217 	log_video_status(cx);
1218 	log_audio_status(cx);
1219 	return 0;
1220 }
1221 
1222 #ifdef CONFIG_VIDEO_ADV_DEBUG
1223 static int cx18_av_g_register(struct v4l2_subdev *sd,
1224 			      struct v4l2_dbg_register *reg)
1225 {
1226 	struct cx18 *cx = v4l2_get_subdevdata(sd);
1227 
1228 	if ((reg->reg & 0x3) != 0)
1229 		return -EINVAL;
1230 	reg->size = 4;
1231 	reg->val = cx18_av_read4(cx, reg->reg & 0x00000ffc);
1232 	return 0;
1233 }
1234 
1235 static int cx18_av_s_register(struct v4l2_subdev *sd,
1236 			      const struct v4l2_dbg_register *reg)
1237 {
1238 	struct cx18 *cx = v4l2_get_subdevdata(sd);
1239 
1240 	if ((reg->reg & 0x3) != 0)
1241 		return -EINVAL;
1242 	cx18_av_write4(cx, reg->reg & 0x00000ffc, reg->val);
1243 	return 0;
1244 }
1245 #endif
1246 
1247 static const struct v4l2_ctrl_ops cx18_av_ctrl_ops = {
1248 	.s_ctrl = cx18_av_s_ctrl,
1249 };
1250 
1251 static const struct v4l2_subdev_core_ops cx18_av_general_ops = {
1252 	.log_status = cx18_av_log_status,
1253 	.load_fw = cx18_av_load_fw,
1254 	.reset = cx18_av_reset,
1255 #ifdef CONFIG_VIDEO_ADV_DEBUG
1256 	.g_register = cx18_av_g_register,
1257 	.s_register = cx18_av_s_register,
1258 #endif
1259 };
1260 
1261 static const struct v4l2_subdev_tuner_ops cx18_av_tuner_ops = {
1262 	.s_radio = cx18_av_s_radio,
1263 	.s_frequency = cx18_av_s_frequency,
1264 	.g_tuner = cx18_av_g_tuner,
1265 	.s_tuner = cx18_av_s_tuner,
1266 };
1267 
1268 static const struct v4l2_subdev_audio_ops cx18_av_audio_ops = {
1269 	.s_clock_freq = cx18_av_s_clock_freq,
1270 	.s_routing = cx18_av_s_audio_routing,
1271 };
1272 
1273 static const struct v4l2_subdev_video_ops cx18_av_video_ops = {
1274 	.s_std = cx18_av_s_std,
1275 	.s_routing = cx18_av_s_video_routing,
1276 	.s_stream = cx18_av_s_stream,
1277 };
1278 
1279 static const struct v4l2_subdev_vbi_ops cx18_av_vbi_ops = {
1280 	.decode_vbi_line = cx18_av_decode_vbi_line,
1281 	.g_sliced_fmt = cx18_av_g_sliced_fmt,
1282 	.s_sliced_fmt = cx18_av_s_sliced_fmt,
1283 	.s_raw_fmt = cx18_av_s_raw_fmt,
1284 };
1285 
1286 static const struct v4l2_subdev_pad_ops cx18_av_pad_ops = {
1287 	.set_fmt = cx18_av_set_fmt,
1288 };
1289 
1290 static const struct v4l2_subdev_ops cx18_av_ops = {
1291 	.core = &cx18_av_general_ops,
1292 	.tuner = &cx18_av_tuner_ops,
1293 	.audio = &cx18_av_audio_ops,
1294 	.video = &cx18_av_video_ops,
1295 	.vbi = &cx18_av_vbi_ops,
1296 	.pad = &cx18_av_pad_ops,
1297 };
1298 
1299 int cx18_av_probe(struct cx18 *cx)
1300 {
1301 	struct cx18_av_state *state = &cx->av_state;
1302 	struct v4l2_subdev *sd;
1303 	int err;
1304 
1305 	state->rev = cx18_av_read4(cx, CXADEC_CHIP_CTRL) & 0xffff;
1306 
1307 	state->vid_input = CX18_AV_COMPOSITE7;
1308 	state->aud_input = CX18_AV_AUDIO8;
1309 	state->audclk_freq = 48000;
1310 	state->audmode = V4L2_TUNER_MODE_LANG1;
1311 	state->slicer_line_delay = 0;
1312 	state->slicer_line_offset = (10 + state->slicer_line_delay - 2);
1313 
1314 	sd = &state->sd;
1315 	v4l2_subdev_init(sd, &cx18_av_ops);
1316 	v4l2_set_subdevdata(sd, cx);
1317 	snprintf(sd->name, sizeof(sd->name),
1318 		 "%s %03x", cx->v4l2_dev.name, (state->rev >> 4));
1319 	sd->grp_id = CX18_HW_418_AV;
1320 	v4l2_ctrl_handler_init(&state->hdl, 9);
1321 	v4l2_ctrl_new_std(&state->hdl, &cx18_av_ctrl_ops,
1322 			V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
1323 	v4l2_ctrl_new_std(&state->hdl, &cx18_av_ctrl_ops,
1324 			V4L2_CID_CONTRAST, 0, 127, 1, 64);
1325 	v4l2_ctrl_new_std(&state->hdl, &cx18_av_ctrl_ops,
1326 			V4L2_CID_SATURATION, 0, 127, 1, 64);
1327 	v4l2_ctrl_new_std(&state->hdl, &cx18_av_ctrl_ops,
1328 			V4L2_CID_HUE, -128, 127, 1, 0);
1329 
1330 	state->volume = v4l2_ctrl_new_std(&state->hdl,
1331 			&cx18_av_audio_ctrl_ops, V4L2_CID_AUDIO_VOLUME,
1332 			0, 65535, 65535 / 100, 0);
1333 	v4l2_ctrl_new_std(&state->hdl,
1334 			&cx18_av_audio_ctrl_ops, V4L2_CID_AUDIO_MUTE,
1335 			0, 1, 1, 0);
1336 	v4l2_ctrl_new_std(&state->hdl, &cx18_av_audio_ctrl_ops,
1337 			V4L2_CID_AUDIO_BALANCE,
1338 			0, 65535, 65535 / 100, 32768);
1339 	v4l2_ctrl_new_std(&state->hdl, &cx18_av_audio_ctrl_ops,
1340 			V4L2_CID_AUDIO_BASS,
1341 			0, 65535, 65535 / 100, 32768);
1342 	v4l2_ctrl_new_std(&state->hdl, &cx18_av_audio_ctrl_ops,
1343 			V4L2_CID_AUDIO_TREBLE,
1344 			0, 65535, 65535 / 100, 32768);
1345 	sd->ctrl_handler = &state->hdl;
1346 	if (state->hdl.error) {
1347 		int err = state->hdl.error;
1348 
1349 		v4l2_ctrl_handler_free(&state->hdl);
1350 		return err;
1351 	}
1352 	err = v4l2_device_register_subdev(&cx->v4l2_dev, sd);
1353 	if (err)
1354 		v4l2_ctrl_handler_free(&state->hdl);
1355 	else
1356 		cx18_av_init(cx);
1357 	return err;
1358 }
1359