16884db3cSHans Verkuil /* SPDX-License-Identifier: GPL-2.0-only */ 285756a06SHans Verkuil /* 385756a06SHans Verkuil * Copyright 2014-2015 Cisco Systems, Inc. and/or its affiliates. 485756a06SHans Verkuil * All rights reserved. 585756a06SHans Verkuil */ 685756a06SHans Verkuil 785756a06SHans Verkuil #ifndef M00460_EVCNT_MEMMAP_PACKAGE_H 885756a06SHans Verkuil #define M00460_EVCNT_MEMMAP_PACKAGE_H 985756a06SHans Verkuil 1085756a06SHans Verkuil /******************************************************************* 1185756a06SHans Verkuil * Register Block 1285756a06SHans Verkuil * M00460_EVCNT_MEMMAP_PACKAGE_VHD_REGMAP 1385756a06SHans Verkuil *******************************************************************/ 1485756a06SHans Verkuil struct m00460_evcnt_regmap { 1585756a06SHans Verkuil uint32_t control; /* Reg 0x0000, Default=0x0 */ 1685756a06SHans Verkuil uint32_t count; /* Reg 0x0004 */ 1785756a06SHans Verkuil }; 1885756a06SHans Verkuil 1985756a06SHans Verkuil #define M00460_EVCNT_REG_CONTROL_OFST 0 2085756a06SHans Verkuil #define M00460_EVCNT_REG_COUNT_OFST 4 2185756a06SHans Verkuil 2285756a06SHans Verkuil /******************************************************************* 2385756a06SHans Verkuil * Bit Mask for register 2485756a06SHans Verkuil * M00460_EVCNT_MEMMAP_PACKAGE_VHD_BITMAP 2585756a06SHans Verkuil *******************************************************************/ 2685756a06SHans Verkuil /* control [1:0] */ 2785756a06SHans Verkuil #define M00460_CONTROL_BITMAP_ENABLE_OFST (0) 2885756a06SHans Verkuil #define M00460_CONTROL_BITMAP_ENABLE_MSK (0x1 << M00460_CONTROL_BITMAP_ENABLE_OFST) 2985756a06SHans Verkuil #define M00460_CONTROL_BITMAP_CLEAR_OFST (1) 3085756a06SHans Verkuil #define M00460_CONTROL_BITMAP_CLEAR_MSK (0x1 << M00460_CONTROL_BITMAP_CLEAR_OFST) 3185756a06SHans Verkuil 3285756a06SHans Verkuil #endif /*M00460_EVCNT_MEMMAP_PACKAGE_H*/ 33