1 /* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics 2 * Digitizer with Horizontal PLL registers 3 * 4 * Copyright (C) 2009 Texas Instruments Inc 5 * Author: Santiago Nunez-Corrales <santiago.nunez@ridgerun.com> 6 * 7 * This code is partially based upon the TVP5150 driver 8 * written by Mauro Carvalho Chehab (mchehab@infradead.org), 9 * the TVP514x driver written by Vaibhav Hiremath <hvaibhav@ti.com> 10 * and the TVP7002 driver in the TI LSP 2.10.00.14 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 */ 22 23 /* Naming conventions 24 * ------------------ 25 * 26 * FDBK: Feedback 27 * DIV: Divider 28 * CTL: Control 29 * SEL: Select 30 * IN: Input 31 * OUT: Output 32 * R: Red 33 * G: Green 34 * B: Blue 35 * OFF: Offset 36 * THRS: Threshold 37 * DGTL: Digital 38 * LVL: Level 39 * PWR: Power 40 * MVIS: Macrovision 41 * W: Width 42 * H: Height 43 * ALGN: Alignment 44 * CLK: Clocks 45 * TOL: Tolerance 46 * BWTH: Bandwidth 47 * COEF: Coefficient 48 * STAT: Status 49 * AUTO: Automatic 50 * FLD: Field 51 * L: Line 52 */ 53 54 #define TVP7002_CHIP_REV 0x00 55 #define TVP7002_HPLL_FDBK_DIV_MSBS 0x01 56 #define TVP7002_HPLL_FDBK_DIV_LSBS 0x02 57 #define TVP7002_HPLL_CRTL 0x03 58 #define TVP7002_HPLL_PHASE_SEL 0x04 59 #define TVP7002_CLAMP_START 0x05 60 #define TVP7002_CLAMP_W 0x06 61 #define TVP7002_HSYNC_OUT_W 0x07 62 #define TVP7002_B_FINE_GAIN 0x08 63 #define TVP7002_G_FINE_GAIN 0x09 64 #define TVP7002_R_FINE_GAIN 0x0a 65 #define TVP7002_B_FINE_OFF_MSBS 0x0b 66 #define TVP7002_G_FINE_OFF_MSBS 0x0c 67 #define TVP7002_R_FINE_OFF_MSBS 0x0d 68 #define TVP7002_SYNC_CTL_1 0x0e 69 #define TVP7002_HPLL_AND_CLAMP_CTL 0x0f 70 #define TVP7002_SYNC_ON_G_THRS 0x10 71 #define TVP7002_SYNC_SEPARATOR_THRS 0x11 72 #define TVP7002_HPLL_PRE_COAST 0x12 73 #define TVP7002_HPLL_POST_COAST 0x13 74 #define TVP7002_SYNC_DETECT_STAT 0x14 75 #define TVP7002_OUT_FORMATTER 0x15 76 #define TVP7002_MISC_CTL_1 0x16 77 #define TVP7002_MISC_CTL_2 0x17 78 #define TVP7002_MISC_CTL_3 0x18 79 #define TVP7002_IN_MUX_SEL_1 0x19 80 #define TVP7002_IN_MUX_SEL_2 0x1a 81 #define TVP7002_B_AND_G_COARSE_GAIN 0x1b 82 #define TVP7002_R_COARSE_GAIN 0x1c 83 #define TVP7002_FINE_OFF_LSBS 0x1d 84 #define TVP7002_B_COARSE_OFF 0x1e 85 #define TVP7002_G_COARSE_OFF 0x1f 86 #define TVP7002_R_COARSE_OFF 0x20 87 #define TVP7002_HSOUT_OUT_START 0x21 88 #define TVP7002_MISC_CTL_4 0x22 89 #define TVP7002_B_DGTL_ALC_OUT_LSBS 0x23 90 #define TVP7002_G_DGTL_ALC_OUT_LSBS 0x24 91 #define TVP7002_R_DGTL_ALC_OUT_LSBS 0x25 92 #define TVP7002_AUTO_LVL_CTL_ENABLE 0x26 93 #define TVP7002_DGTL_ALC_OUT_MSBS 0x27 94 #define TVP7002_AUTO_LVL_CTL_FILTER 0x28 95 /* Reserved 0x29*/ 96 #define TVP7002_FINE_CLAMP_CTL 0x2a 97 #define TVP7002_PWR_CTL 0x2b 98 #define TVP7002_ADC_SETUP 0x2c 99 #define TVP7002_COARSE_CLAMP_CTL 0x2d 100 #define TVP7002_SOG_CLAMP 0x2e 101 #define TVP7002_RGB_COARSE_CLAMP_CTL 0x2f 102 #define TVP7002_SOG_COARSE_CLAMP_CTL 0x30 103 #define TVP7002_ALC_PLACEMENT 0x31 104 /* Reserved 0x32 */ 105 /* Reserved 0x33 */ 106 #define TVP7002_MVIS_STRIPPER_W 0x34 107 #define TVP7002_VSYNC_ALGN 0x35 108 #define TVP7002_SYNC_BYPASS 0x36 109 #define TVP7002_L_FRAME_STAT_LSBS 0x37 110 #define TVP7002_L_FRAME_STAT_MSBS 0x38 111 #define TVP7002_CLK_L_STAT_LSBS 0x39 112 #define TVP7002_CLK_L_STAT_MSBS 0x3a 113 #define TVP7002_HSYNC_W 0x3b 114 #define TVP7002_VSYNC_W 0x3c 115 #define TVP7002_L_LENGTH_TOL 0x3d 116 /* Reserved 0x3e */ 117 #define TVP7002_VIDEO_BWTH_CTL 0x3f 118 #define TVP7002_AVID_START_PIXEL_LSBS 0x40 119 #define TVP7002_AVID_START_PIXEL_MSBS 0x41 120 #define TVP7002_AVID_STOP_PIXEL_LSBS 0x42 121 #define TVP7002_AVID_STOP_PIXEL_MSBS 0x43 122 #define TVP7002_VBLK_F_0_START_L_OFF 0x44 123 #define TVP7002_VBLK_F_1_START_L_OFF 0x45 124 #define TVP7002_VBLK_F_0_DURATION 0x46 125 #define TVP7002_VBLK_F_1_DURATION 0x47 126 #define TVP7002_FBIT_F_0_START_L_OFF 0x48 127 #define TVP7002_FBIT_F_1_START_L_OFF 0x49 128 #define TVP7002_YUV_Y_G_COEF_LSBS 0x4a 129 #define TVP7002_YUV_Y_G_COEF_MSBS 0x4b 130 #define TVP7002_YUV_Y_B_COEF_LSBS 0x4c 131 #define TVP7002_YUV_Y_B_COEF_MSBS 0x4d 132 #define TVP7002_YUV_Y_R_COEF_LSBS 0x4e 133 #define TVP7002_YUV_Y_R_COEF_MSBS 0x4f 134 #define TVP7002_YUV_U_G_COEF_LSBS 0x50 135 #define TVP7002_YUV_U_G_COEF_MSBS 0x51 136 #define TVP7002_YUV_U_B_COEF_LSBS 0x52 137 #define TVP7002_YUV_U_B_COEF_MSBS 0x53 138 #define TVP7002_YUV_U_R_COEF_LSBS 0x54 139 #define TVP7002_YUV_U_R_COEF_MSBS 0x55 140 #define TVP7002_YUV_V_G_COEF_LSBS 0x56 141 #define TVP7002_YUV_V_G_COEF_MSBS 0x57 142 #define TVP7002_YUV_V_B_COEF_LSBS 0x58 143 #define TVP7002_YUV_V_B_COEF_MSBS 0x59 144 #define TVP7002_YUV_V_R_COEF_LSBS 0x5a 145 #define TVP7002_YUV_V_R_COEF_MSBS 0x5b 146 147