1 /* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics 2 * Digitizer with Horizontal PLL registers 3 * 4 * Copyright (C) 2009 Texas Instruments Inc 5 * Author: Santiago Nunez-Corrales <santiago.nunez@ridgerun.com> 6 * 7 * This code is partially based upon the TVP5150 driver 8 * written by Mauro Carvalho Chehab (mchehab@infradead.org), 9 * the TVP514x driver written by Vaibhav Hiremath <hvaibhav@ti.com> 10 * and the TVP7002 driver in the TI LSP 2.10.00.14. Revisions by 11 * Muralidharan Karicheri and Snehaprabha Narnakaje (TI). 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation; either version 2 of the License, or 16 * (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 26 */ 27 #include <linux/delay.h> 28 #include <linux/i2c.h> 29 #include <linux/slab.h> 30 #include <linux/videodev2.h> 31 #include <linux/module.h> 32 #include <linux/of.h> 33 #include <linux/of_graph.h> 34 #include <linux/v4l2-dv-timings.h> 35 #include <media/i2c/tvp7002.h> 36 #include <media/v4l2-async.h> 37 #include <media/v4l2-device.h> 38 #include <media/v4l2-common.h> 39 #include <media/v4l2-ctrls.h> 40 #include <media/v4l2-of.h> 41 42 #include "tvp7002_reg.h" 43 44 MODULE_DESCRIPTION("TI TVP7002 Video and Graphics Digitizer driver"); 45 MODULE_AUTHOR("Santiago Nunez-Corrales <santiago.nunez@ridgerun.com>"); 46 MODULE_LICENSE("GPL"); 47 48 /* I2C retry attempts */ 49 #define I2C_RETRY_COUNT (5) 50 51 /* End of registers */ 52 #define TVP7002_EOR 0x5c 53 54 /* Read write definition for registers */ 55 #define TVP7002_READ 0 56 #define TVP7002_WRITE 1 57 #define TVP7002_RESERVED 2 58 59 /* Interlaced vs progressive mask and shift */ 60 #define TVP7002_IP_SHIFT 5 61 #define TVP7002_INPR_MASK (0x01 << TVP7002_IP_SHIFT) 62 63 /* Shift for CPL and LPF registers */ 64 #define TVP7002_CL_SHIFT 8 65 #define TVP7002_CL_MASK 0x0f 66 67 /* Debug functions */ 68 static bool debug; 69 module_param(debug, bool, 0644); 70 MODULE_PARM_DESC(debug, "Debug level (0-2)"); 71 72 /* Structure for register values */ 73 struct i2c_reg_value { 74 u8 reg; 75 u8 value; 76 u8 type; 77 }; 78 79 /* 80 * Register default values (according to tvp7002 datasheet) 81 * In the case of read-only registers, the value (0xff) is 82 * never written. R/W functionality is controlled by the 83 * writable bit in the register struct definition. 84 */ 85 static const struct i2c_reg_value tvp7002_init_default[] = { 86 { TVP7002_CHIP_REV, 0xff, TVP7002_READ }, 87 { TVP7002_HPLL_FDBK_DIV_MSBS, 0x67, TVP7002_WRITE }, 88 { TVP7002_HPLL_FDBK_DIV_LSBS, 0x20, TVP7002_WRITE }, 89 { TVP7002_HPLL_CRTL, 0xa0, TVP7002_WRITE }, 90 { TVP7002_HPLL_PHASE_SEL, 0x80, TVP7002_WRITE }, 91 { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE }, 92 { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE }, 93 { TVP7002_HSYNC_OUT_W, 0x60, TVP7002_WRITE }, 94 { TVP7002_B_FINE_GAIN, 0x00, TVP7002_WRITE }, 95 { TVP7002_G_FINE_GAIN, 0x00, TVP7002_WRITE }, 96 { TVP7002_R_FINE_GAIN, 0x00, TVP7002_WRITE }, 97 { TVP7002_B_FINE_OFF_MSBS, 0x80, TVP7002_WRITE }, 98 { TVP7002_G_FINE_OFF_MSBS, 0x80, TVP7002_WRITE }, 99 { TVP7002_R_FINE_OFF_MSBS, 0x80, TVP7002_WRITE }, 100 { TVP7002_SYNC_CTL_1, 0x20, TVP7002_WRITE }, 101 { TVP7002_HPLL_AND_CLAMP_CTL, 0x2e, TVP7002_WRITE }, 102 { TVP7002_SYNC_ON_G_THRS, 0x5d, TVP7002_WRITE }, 103 { TVP7002_SYNC_SEPARATOR_THRS, 0x47, TVP7002_WRITE }, 104 { TVP7002_HPLL_PRE_COAST, 0x00, TVP7002_WRITE }, 105 { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE }, 106 { TVP7002_SYNC_DETECT_STAT, 0xff, TVP7002_READ }, 107 { TVP7002_OUT_FORMATTER, 0x47, TVP7002_WRITE }, 108 { TVP7002_MISC_CTL_1, 0x01, TVP7002_WRITE }, 109 { TVP7002_MISC_CTL_2, 0x00, TVP7002_WRITE }, 110 { TVP7002_MISC_CTL_3, 0x01, TVP7002_WRITE }, 111 { TVP7002_IN_MUX_SEL_1, 0x00, TVP7002_WRITE }, 112 { TVP7002_IN_MUX_SEL_2, 0x67, TVP7002_WRITE }, 113 { TVP7002_B_AND_G_COARSE_GAIN, 0x77, TVP7002_WRITE }, 114 { TVP7002_R_COARSE_GAIN, 0x07, TVP7002_WRITE }, 115 { TVP7002_FINE_OFF_LSBS, 0x00, TVP7002_WRITE }, 116 { TVP7002_B_COARSE_OFF, 0x10, TVP7002_WRITE }, 117 { TVP7002_G_COARSE_OFF, 0x10, TVP7002_WRITE }, 118 { TVP7002_R_COARSE_OFF, 0x10, TVP7002_WRITE }, 119 { TVP7002_HSOUT_OUT_START, 0x08, TVP7002_WRITE }, 120 { TVP7002_MISC_CTL_4, 0x00, TVP7002_WRITE }, 121 { TVP7002_B_DGTL_ALC_OUT_LSBS, 0xff, TVP7002_READ }, 122 { TVP7002_G_DGTL_ALC_OUT_LSBS, 0xff, TVP7002_READ }, 123 { TVP7002_R_DGTL_ALC_OUT_LSBS, 0xff, TVP7002_READ }, 124 { TVP7002_AUTO_LVL_CTL_ENABLE, 0x80, TVP7002_WRITE }, 125 { TVP7002_DGTL_ALC_OUT_MSBS, 0xff, TVP7002_READ }, 126 { TVP7002_AUTO_LVL_CTL_FILTER, 0x53, TVP7002_WRITE }, 127 { 0x29, 0x08, TVP7002_RESERVED }, 128 { TVP7002_FINE_CLAMP_CTL, 0x07, TVP7002_WRITE }, 129 /* PWR_CTL is controlled only by the probe and reset functions */ 130 { TVP7002_PWR_CTL, 0x00, TVP7002_RESERVED }, 131 { TVP7002_ADC_SETUP, 0x50, TVP7002_WRITE }, 132 { TVP7002_COARSE_CLAMP_CTL, 0x00, TVP7002_WRITE }, 133 { TVP7002_SOG_CLAMP, 0x80, TVP7002_WRITE }, 134 { TVP7002_RGB_COARSE_CLAMP_CTL, 0x8c, TVP7002_WRITE }, 135 { TVP7002_SOG_COARSE_CLAMP_CTL, 0x04, TVP7002_WRITE }, 136 { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE }, 137 { 0x32, 0x18, TVP7002_RESERVED }, 138 { 0x33, 0x60, TVP7002_RESERVED }, 139 { TVP7002_MVIS_STRIPPER_W, 0xff, TVP7002_RESERVED }, 140 { TVP7002_VSYNC_ALGN, 0x10, TVP7002_WRITE }, 141 { TVP7002_SYNC_BYPASS, 0x00, TVP7002_WRITE }, 142 { TVP7002_L_FRAME_STAT_LSBS, 0xff, TVP7002_READ }, 143 { TVP7002_L_FRAME_STAT_MSBS, 0xff, TVP7002_READ }, 144 { TVP7002_CLK_L_STAT_LSBS, 0xff, TVP7002_READ }, 145 { TVP7002_CLK_L_STAT_MSBS, 0xff, TVP7002_READ }, 146 { TVP7002_HSYNC_W, 0xff, TVP7002_READ }, 147 { TVP7002_VSYNC_W, 0xff, TVP7002_READ }, 148 { TVP7002_L_LENGTH_TOL, 0x03, TVP7002_WRITE }, 149 { 0x3e, 0x60, TVP7002_RESERVED }, 150 { TVP7002_VIDEO_BWTH_CTL, 0x01, TVP7002_WRITE }, 151 { TVP7002_AVID_START_PIXEL_LSBS, 0x01, TVP7002_WRITE }, 152 { TVP7002_AVID_START_PIXEL_MSBS, 0x2c, TVP7002_WRITE }, 153 { TVP7002_AVID_STOP_PIXEL_LSBS, 0x06, TVP7002_WRITE }, 154 { TVP7002_AVID_STOP_PIXEL_MSBS, 0x2c, TVP7002_WRITE }, 155 { TVP7002_VBLK_F_0_START_L_OFF, 0x05, TVP7002_WRITE }, 156 { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE }, 157 { TVP7002_VBLK_F_0_DURATION, 0x1e, TVP7002_WRITE }, 158 { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE }, 159 { TVP7002_FBIT_F_0_START_L_OFF, 0x00, TVP7002_WRITE }, 160 { TVP7002_FBIT_F_1_START_L_OFF, 0x00, TVP7002_WRITE }, 161 { TVP7002_YUV_Y_G_COEF_LSBS, 0xe3, TVP7002_WRITE }, 162 { TVP7002_YUV_Y_G_COEF_MSBS, 0x16, TVP7002_WRITE }, 163 { TVP7002_YUV_Y_B_COEF_LSBS, 0x4f, TVP7002_WRITE }, 164 { TVP7002_YUV_Y_B_COEF_MSBS, 0x02, TVP7002_WRITE }, 165 { TVP7002_YUV_Y_R_COEF_LSBS, 0xce, TVP7002_WRITE }, 166 { TVP7002_YUV_Y_R_COEF_MSBS, 0x06, TVP7002_WRITE }, 167 { TVP7002_YUV_U_G_COEF_LSBS, 0xab, TVP7002_WRITE }, 168 { TVP7002_YUV_U_G_COEF_MSBS, 0xf3, TVP7002_WRITE }, 169 { TVP7002_YUV_U_B_COEF_LSBS, 0x00, TVP7002_WRITE }, 170 { TVP7002_YUV_U_B_COEF_MSBS, 0x10, TVP7002_WRITE }, 171 { TVP7002_YUV_U_R_COEF_LSBS, 0x55, TVP7002_WRITE }, 172 { TVP7002_YUV_U_R_COEF_MSBS, 0xfc, TVP7002_WRITE }, 173 { TVP7002_YUV_V_G_COEF_LSBS, 0x78, TVP7002_WRITE }, 174 { TVP7002_YUV_V_G_COEF_MSBS, 0xf1, TVP7002_WRITE }, 175 { TVP7002_YUV_V_B_COEF_LSBS, 0x88, TVP7002_WRITE }, 176 { TVP7002_YUV_V_B_COEF_MSBS, 0xfe, TVP7002_WRITE }, 177 { TVP7002_YUV_V_R_COEF_LSBS, 0x00, TVP7002_WRITE }, 178 { TVP7002_YUV_V_R_COEF_MSBS, 0x10, TVP7002_WRITE }, 179 /* This signals end of register values */ 180 { TVP7002_EOR, 0xff, TVP7002_RESERVED } 181 }; 182 183 /* Register parameters for 480P */ 184 static const struct i2c_reg_value tvp7002_parms_480P[] = { 185 { TVP7002_HPLL_FDBK_DIV_MSBS, 0x35, TVP7002_WRITE }, 186 { TVP7002_HPLL_FDBK_DIV_LSBS, 0xa0, TVP7002_WRITE }, 187 { TVP7002_HPLL_CRTL, 0x02, TVP7002_WRITE }, 188 { TVP7002_AVID_START_PIXEL_LSBS, 0x91, TVP7002_WRITE }, 189 { TVP7002_AVID_START_PIXEL_MSBS, 0x00, TVP7002_WRITE }, 190 { TVP7002_AVID_STOP_PIXEL_LSBS, 0x0B, TVP7002_WRITE }, 191 { TVP7002_AVID_STOP_PIXEL_MSBS, 0x00, TVP7002_WRITE }, 192 { TVP7002_VBLK_F_0_START_L_OFF, 0x03, TVP7002_WRITE }, 193 { TVP7002_VBLK_F_1_START_L_OFF, 0x01, TVP7002_WRITE }, 194 { TVP7002_VBLK_F_0_DURATION, 0x13, TVP7002_WRITE }, 195 { TVP7002_VBLK_F_1_DURATION, 0x13, TVP7002_WRITE }, 196 { TVP7002_ALC_PLACEMENT, 0x18, TVP7002_WRITE }, 197 { TVP7002_CLAMP_START, 0x06, TVP7002_WRITE }, 198 { TVP7002_CLAMP_W, 0x10, TVP7002_WRITE }, 199 { TVP7002_HPLL_PRE_COAST, 0x03, TVP7002_WRITE }, 200 { TVP7002_HPLL_POST_COAST, 0x03, TVP7002_WRITE }, 201 { TVP7002_EOR, 0xff, TVP7002_RESERVED } 202 }; 203 204 /* Register parameters for 576P */ 205 static const struct i2c_reg_value tvp7002_parms_576P[] = { 206 { TVP7002_HPLL_FDBK_DIV_MSBS, 0x36, TVP7002_WRITE }, 207 { TVP7002_HPLL_FDBK_DIV_LSBS, 0x00, TVP7002_WRITE }, 208 { TVP7002_HPLL_CRTL, 0x18, TVP7002_WRITE }, 209 { TVP7002_AVID_START_PIXEL_LSBS, 0x9B, TVP7002_WRITE }, 210 { TVP7002_AVID_START_PIXEL_MSBS, 0x00, TVP7002_WRITE }, 211 { TVP7002_AVID_STOP_PIXEL_LSBS, 0x0F, TVP7002_WRITE }, 212 { TVP7002_AVID_STOP_PIXEL_MSBS, 0x00, TVP7002_WRITE }, 213 { TVP7002_VBLK_F_0_START_L_OFF, 0x00, TVP7002_WRITE }, 214 { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE }, 215 { TVP7002_VBLK_F_0_DURATION, 0x2D, TVP7002_WRITE }, 216 { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE }, 217 { TVP7002_ALC_PLACEMENT, 0x18, TVP7002_WRITE }, 218 { TVP7002_CLAMP_START, 0x06, TVP7002_WRITE }, 219 { TVP7002_CLAMP_W, 0x10, TVP7002_WRITE }, 220 { TVP7002_HPLL_PRE_COAST, 0x03, TVP7002_WRITE }, 221 { TVP7002_HPLL_POST_COAST, 0x03, TVP7002_WRITE }, 222 { TVP7002_EOR, 0xff, TVP7002_RESERVED } 223 }; 224 225 /* Register parameters for 1080I60 */ 226 static const struct i2c_reg_value tvp7002_parms_1080I60[] = { 227 { TVP7002_HPLL_FDBK_DIV_MSBS, 0x89, TVP7002_WRITE }, 228 { TVP7002_HPLL_FDBK_DIV_LSBS, 0x80, TVP7002_WRITE }, 229 { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE }, 230 { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE }, 231 { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE }, 232 { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE }, 233 { TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE }, 234 { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE }, 235 { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE }, 236 { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE }, 237 { TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE }, 238 { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE }, 239 { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE }, 240 { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE }, 241 { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE }, 242 { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE }, 243 { TVP7002_EOR, 0xff, TVP7002_RESERVED } 244 }; 245 246 /* Register parameters for 1080P60 */ 247 static const struct i2c_reg_value tvp7002_parms_1080P60[] = { 248 { TVP7002_HPLL_FDBK_DIV_MSBS, 0x89, TVP7002_WRITE }, 249 { TVP7002_HPLL_FDBK_DIV_LSBS, 0x80, TVP7002_WRITE }, 250 { TVP7002_HPLL_CRTL, 0xE0, TVP7002_WRITE }, 251 { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE }, 252 { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE }, 253 { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE }, 254 { TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE }, 255 { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE }, 256 { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE }, 257 { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE }, 258 { TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE }, 259 { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE }, 260 { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE }, 261 { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE }, 262 { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE }, 263 { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE }, 264 { TVP7002_EOR, 0xff, TVP7002_RESERVED } 265 }; 266 267 /* Register parameters for 1080I50 */ 268 static const struct i2c_reg_value tvp7002_parms_1080I50[] = { 269 { TVP7002_HPLL_FDBK_DIV_MSBS, 0xa5, TVP7002_WRITE }, 270 { TVP7002_HPLL_FDBK_DIV_LSBS, 0x00, TVP7002_WRITE }, 271 { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE }, 272 { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE }, 273 { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE }, 274 { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE }, 275 { TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE }, 276 { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE }, 277 { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE }, 278 { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE }, 279 { TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE }, 280 { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE }, 281 { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE }, 282 { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE }, 283 { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE }, 284 { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE }, 285 { TVP7002_EOR, 0xff, TVP7002_RESERVED } 286 }; 287 288 /* Register parameters for 720P60 */ 289 static const struct i2c_reg_value tvp7002_parms_720P60[] = { 290 { TVP7002_HPLL_FDBK_DIV_MSBS, 0x67, TVP7002_WRITE }, 291 { TVP7002_HPLL_FDBK_DIV_LSBS, 0x20, TVP7002_WRITE }, 292 { TVP7002_HPLL_CRTL, 0xa0, TVP7002_WRITE }, 293 { TVP7002_AVID_START_PIXEL_LSBS, 0x47, TVP7002_WRITE }, 294 { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE }, 295 { TVP7002_AVID_STOP_PIXEL_LSBS, 0x4B, TVP7002_WRITE }, 296 { TVP7002_AVID_STOP_PIXEL_MSBS, 0x06, TVP7002_WRITE }, 297 { TVP7002_VBLK_F_0_START_L_OFF, 0x05, TVP7002_WRITE }, 298 { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE }, 299 { TVP7002_VBLK_F_0_DURATION, 0x2D, TVP7002_WRITE }, 300 { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE }, 301 { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE }, 302 { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE }, 303 { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE }, 304 { TVP7002_HPLL_PRE_COAST, 0x00, TVP7002_WRITE }, 305 { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE }, 306 { TVP7002_EOR, 0xff, TVP7002_RESERVED } 307 }; 308 309 /* Register parameters for 720P50 */ 310 static const struct i2c_reg_value tvp7002_parms_720P50[] = { 311 { TVP7002_HPLL_FDBK_DIV_MSBS, 0x7b, TVP7002_WRITE }, 312 { TVP7002_HPLL_FDBK_DIV_LSBS, 0xc0, TVP7002_WRITE }, 313 { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE }, 314 { TVP7002_AVID_START_PIXEL_LSBS, 0x47, TVP7002_WRITE }, 315 { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE }, 316 { TVP7002_AVID_STOP_PIXEL_LSBS, 0x4B, TVP7002_WRITE }, 317 { TVP7002_AVID_STOP_PIXEL_MSBS, 0x06, TVP7002_WRITE }, 318 { TVP7002_VBLK_F_0_START_L_OFF, 0x05, TVP7002_WRITE }, 319 { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE }, 320 { TVP7002_VBLK_F_0_DURATION, 0x2D, TVP7002_WRITE }, 321 { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE }, 322 { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE }, 323 { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE }, 324 { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE }, 325 { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE }, 326 { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE }, 327 { TVP7002_EOR, 0xff, TVP7002_RESERVED } 328 }; 329 330 /* Timings definition for handling device operation */ 331 struct tvp7002_timings_definition { 332 struct v4l2_dv_timings timings; 333 const struct i2c_reg_value *p_settings; 334 enum v4l2_colorspace color_space; 335 enum v4l2_field scanmode; 336 u16 progressive; 337 u16 lines_per_frame; 338 u16 cpl_min; 339 u16 cpl_max; 340 }; 341 342 /* Struct list for digital video timings */ 343 static const struct tvp7002_timings_definition tvp7002_timings[] = { 344 { 345 V4L2_DV_BT_CEA_1280X720P60, 346 tvp7002_parms_720P60, 347 V4L2_COLORSPACE_REC709, 348 V4L2_FIELD_NONE, 349 1, 350 0x2EE, 351 135, 352 153 353 }, 354 { 355 V4L2_DV_BT_CEA_1920X1080I60, 356 tvp7002_parms_1080I60, 357 V4L2_COLORSPACE_REC709, 358 V4L2_FIELD_INTERLACED, 359 0, 360 0x465, 361 181, 362 205 363 }, 364 { 365 V4L2_DV_BT_CEA_1920X1080I50, 366 tvp7002_parms_1080I50, 367 V4L2_COLORSPACE_REC709, 368 V4L2_FIELD_INTERLACED, 369 0, 370 0x465, 371 217, 372 245 373 }, 374 { 375 V4L2_DV_BT_CEA_1280X720P50, 376 tvp7002_parms_720P50, 377 V4L2_COLORSPACE_REC709, 378 V4L2_FIELD_NONE, 379 1, 380 0x2EE, 381 163, 382 183 383 }, 384 { 385 V4L2_DV_BT_CEA_1920X1080P60, 386 tvp7002_parms_1080P60, 387 V4L2_COLORSPACE_REC709, 388 V4L2_FIELD_NONE, 389 1, 390 0x465, 391 90, 392 102 393 }, 394 { 395 V4L2_DV_BT_CEA_720X480P59_94, 396 tvp7002_parms_480P, 397 V4L2_COLORSPACE_SMPTE170M, 398 V4L2_FIELD_NONE, 399 1, 400 0x20D, 401 0xffff, 402 0xffff 403 }, 404 { 405 V4L2_DV_BT_CEA_720X576P50, 406 tvp7002_parms_576P, 407 V4L2_COLORSPACE_SMPTE170M, 408 V4L2_FIELD_NONE, 409 1, 410 0x271, 411 0xffff, 412 0xffff 413 } 414 }; 415 416 #define NUM_TIMINGS ARRAY_SIZE(tvp7002_timings) 417 418 /* Device definition */ 419 struct tvp7002 { 420 struct v4l2_subdev sd; 421 struct v4l2_ctrl_handler hdl; 422 const struct tvp7002_config *pdata; 423 424 int ver; 425 int streaming; 426 427 const struct tvp7002_timings_definition *current_timings; 428 struct media_pad pad; 429 }; 430 431 /* 432 * to_tvp7002 - Obtain device handler TVP7002 433 * @sd: ptr to v4l2_subdev struct 434 * 435 * Returns device handler tvp7002. 436 */ 437 static inline struct tvp7002 *to_tvp7002(struct v4l2_subdev *sd) 438 { 439 return container_of(sd, struct tvp7002, sd); 440 } 441 442 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) 443 { 444 return &container_of(ctrl->handler, struct tvp7002, hdl)->sd; 445 } 446 447 /* 448 * tvp7002_read - Read a value from a register in an TVP7002 449 * @sd: ptr to v4l2_subdev struct 450 * @addr: TVP7002 register address 451 * @dst: pointer to 8-bit destination 452 * 453 * Returns value read if successful, or non-zero (-1) otherwise. 454 */ 455 static int tvp7002_read(struct v4l2_subdev *sd, u8 addr, u8 *dst) 456 { 457 struct i2c_client *c = v4l2_get_subdevdata(sd); 458 int retry; 459 int error; 460 461 for (retry = 0; retry < I2C_RETRY_COUNT; retry++) { 462 error = i2c_smbus_read_byte_data(c, addr); 463 464 if (error >= 0) { 465 *dst = (u8)error; 466 return 0; 467 } 468 469 msleep_interruptible(10); 470 } 471 v4l2_err(sd, "TVP7002 read error %d\n", error); 472 return error; 473 } 474 475 /* 476 * tvp7002_read_err() - Read a register value with error code 477 * @sd: pointer to standard V4L2 sub-device structure 478 * @reg: destination register 479 * @val: value to be read 480 * @err: pointer to error value 481 * 482 * Read a value in a register and save error value in pointer. 483 * Also update the register table if successful 484 */ 485 static inline void tvp7002_read_err(struct v4l2_subdev *sd, u8 reg, 486 u8 *dst, int *err) 487 { 488 if (!*err) 489 *err = tvp7002_read(sd, reg, dst); 490 } 491 492 /* 493 * tvp7002_write() - Write a value to a register in TVP7002 494 * @sd: ptr to v4l2_subdev struct 495 * @addr: TVP7002 register address 496 * @value: value to be written to the register 497 * 498 * Write a value to a register in an TVP7002 decoder device. 499 * Returns zero if successful, or non-zero otherwise. 500 */ 501 static int tvp7002_write(struct v4l2_subdev *sd, u8 addr, u8 value) 502 { 503 struct i2c_client *c; 504 int retry; 505 int error; 506 507 c = v4l2_get_subdevdata(sd); 508 509 for (retry = 0; retry < I2C_RETRY_COUNT; retry++) { 510 error = i2c_smbus_write_byte_data(c, addr, value); 511 512 if (error >= 0) 513 return 0; 514 515 v4l2_warn(sd, "Write: retry ... %d\n", retry); 516 msleep_interruptible(10); 517 } 518 v4l2_err(sd, "TVP7002 write error %d\n", error); 519 return error; 520 } 521 522 /* 523 * tvp7002_write_err() - Write a register value with error code 524 * @sd: pointer to standard V4L2 sub-device structure 525 * @reg: destination register 526 * @val: value to be written 527 * @err: pointer to error value 528 * 529 * Write a value in a register and save error value in pointer. 530 * Also update the register table if successful 531 */ 532 static inline void tvp7002_write_err(struct v4l2_subdev *sd, u8 reg, 533 u8 val, int *err) 534 { 535 if (!*err) 536 *err = tvp7002_write(sd, reg, val); 537 } 538 539 /* 540 * tvp7002_write_inittab() - Write initialization values 541 * @sd: ptr to v4l2_subdev struct 542 * @regs: ptr to i2c_reg_value struct 543 * 544 * Write initialization values. 545 * Returns zero or -EINVAL if read operation fails. 546 */ 547 static int tvp7002_write_inittab(struct v4l2_subdev *sd, 548 const struct i2c_reg_value *regs) 549 { 550 int error = 0; 551 552 /* Initialize the first (defined) registers */ 553 while (TVP7002_EOR != regs->reg) { 554 if (TVP7002_WRITE == regs->type) 555 tvp7002_write_err(sd, regs->reg, regs->value, &error); 556 regs++; 557 } 558 559 return error; 560 } 561 562 static int tvp7002_s_dv_timings(struct v4l2_subdev *sd, 563 struct v4l2_dv_timings *dv_timings) 564 { 565 struct tvp7002 *device = to_tvp7002(sd); 566 const struct v4l2_bt_timings *bt = &dv_timings->bt; 567 int i; 568 569 if (dv_timings->type != V4L2_DV_BT_656_1120) 570 return -EINVAL; 571 for (i = 0; i < NUM_TIMINGS; i++) { 572 const struct v4l2_bt_timings *t = &tvp7002_timings[i].timings.bt; 573 574 if (!memcmp(bt, t, &bt->standards - &bt->width)) { 575 device->current_timings = &tvp7002_timings[i]; 576 return tvp7002_write_inittab(sd, tvp7002_timings[i].p_settings); 577 } 578 } 579 return -EINVAL; 580 } 581 582 static int tvp7002_g_dv_timings(struct v4l2_subdev *sd, 583 struct v4l2_dv_timings *dv_timings) 584 { 585 struct tvp7002 *device = to_tvp7002(sd); 586 587 *dv_timings = device->current_timings->timings; 588 return 0; 589 } 590 591 /* 592 * tvp7002_s_ctrl() - Set a control 593 * @ctrl: ptr to v4l2_ctrl struct 594 * 595 * Set a control in TVP7002 decoder device. 596 * Returns zero when successful or -EINVAL if register access fails. 597 */ 598 static int tvp7002_s_ctrl(struct v4l2_ctrl *ctrl) 599 { 600 struct v4l2_subdev *sd = to_sd(ctrl); 601 int error = 0; 602 603 switch (ctrl->id) { 604 case V4L2_CID_GAIN: 605 tvp7002_write_err(sd, TVP7002_R_FINE_GAIN, ctrl->val, &error); 606 tvp7002_write_err(sd, TVP7002_G_FINE_GAIN, ctrl->val, &error); 607 tvp7002_write_err(sd, TVP7002_B_FINE_GAIN, ctrl->val, &error); 608 return error; 609 } 610 return -EINVAL; 611 } 612 613 /* 614 * tvp7002_query_dv() - query DV timings 615 * @sd: pointer to standard V4L2 sub-device structure 616 * @index: index into the tvp7002_timings array 617 * 618 * Returns the current DV timings detected by TVP7002. If no active input is 619 * detected, returns -EINVAL 620 */ 621 static int tvp7002_query_dv(struct v4l2_subdev *sd, int *index) 622 { 623 const struct tvp7002_timings_definition *timings = tvp7002_timings; 624 u8 progressive; 625 u32 lpfr; 626 u32 cpln; 627 int error = 0; 628 u8 lpf_lsb; 629 u8 lpf_msb; 630 u8 cpl_lsb; 631 u8 cpl_msb; 632 633 /* Return invalid index if no active input is detected */ 634 *index = NUM_TIMINGS; 635 636 /* Read standards from device registers */ 637 tvp7002_read_err(sd, TVP7002_L_FRAME_STAT_LSBS, &lpf_lsb, &error); 638 tvp7002_read_err(sd, TVP7002_L_FRAME_STAT_MSBS, &lpf_msb, &error); 639 640 if (error < 0) 641 return error; 642 643 tvp7002_read_err(sd, TVP7002_CLK_L_STAT_LSBS, &cpl_lsb, &error); 644 tvp7002_read_err(sd, TVP7002_CLK_L_STAT_MSBS, &cpl_msb, &error); 645 646 if (error < 0) 647 return error; 648 649 /* Get lines per frame, clocks per line and interlaced/progresive */ 650 lpfr = lpf_lsb | ((TVP7002_CL_MASK & lpf_msb) << TVP7002_CL_SHIFT); 651 cpln = cpl_lsb | ((TVP7002_CL_MASK & cpl_msb) << TVP7002_CL_SHIFT); 652 progressive = (lpf_msb & TVP7002_INPR_MASK) >> TVP7002_IP_SHIFT; 653 654 /* Do checking of video modes */ 655 for (*index = 0; *index < NUM_TIMINGS; (*index)++, timings++) 656 if (lpfr == timings->lines_per_frame && 657 progressive == timings->progressive) { 658 if (timings->cpl_min == 0xffff) 659 break; 660 if (cpln >= timings->cpl_min && cpln <= timings->cpl_max) 661 break; 662 } 663 664 if (*index == NUM_TIMINGS) { 665 v4l2_dbg(1, debug, sd, "detection failed: lpf = %x, cpl = %x\n", 666 lpfr, cpln); 667 return -ENOLINK; 668 } 669 670 /* Update lines per frame and clocks per line info */ 671 v4l2_dbg(1, debug, sd, "detected timings: %d\n", *index); 672 return 0; 673 } 674 675 static int tvp7002_query_dv_timings(struct v4l2_subdev *sd, 676 struct v4l2_dv_timings *timings) 677 { 678 int index; 679 int err = tvp7002_query_dv(sd, &index); 680 681 if (err) 682 return err; 683 *timings = tvp7002_timings[index].timings; 684 return 0; 685 } 686 687 #ifdef CONFIG_VIDEO_ADV_DEBUG 688 /* 689 * tvp7002_g_register() - Get the value of a register 690 * @sd: ptr to v4l2_subdev struct 691 * @reg: ptr to v4l2_dbg_register struct 692 * 693 * Get the value of a TVP7002 decoder device register. 694 * Returns zero when successful, -EINVAL if register read fails or 695 * access to I2C client fails. 696 */ 697 static int tvp7002_g_register(struct v4l2_subdev *sd, 698 struct v4l2_dbg_register *reg) 699 { 700 u8 val; 701 int ret; 702 703 ret = tvp7002_read(sd, reg->reg & 0xff, &val); 704 reg->val = val; 705 reg->size = 1; 706 return ret; 707 } 708 709 /* 710 * tvp7002_s_register() - set a control 711 * @sd: ptr to v4l2_subdev struct 712 * @reg: ptr to v4l2_dbg_register struct 713 * 714 * Get the value of a TVP7002 decoder device register. 715 * Returns zero when successful, -EINVAL if register read fails. 716 */ 717 static int tvp7002_s_register(struct v4l2_subdev *sd, 718 const struct v4l2_dbg_register *reg) 719 { 720 return tvp7002_write(sd, reg->reg & 0xff, reg->val & 0xff); 721 } 722 #endif 723 724 /* 725 * tvp7002_s_stream() - V4L2 decoder i/f handler for s_stream 726 * @sd: pointer to standard V4L2 sub-device structure 727 * @enable: streaming enable or disable 728 * 729 * Sets streaming to enable or disable, if possible. 730 */ 731 static int tvp7002_s_stream(struct v4l2_subdev *sd, int enable) 732 { 733 struct tvp7002 *device = to_tvp7002(sd); 734 int error; 735 736 if (device->streaming == enable) 737 return 0; 738 739 /* low impedance: on, high impedance: off */ 740 error = tvp7002_write(sd, TVP7002_MISC_CTL_2, enable ? 0x00 : 0x03); 741 if (error) { 742 v4l2_dbg(1, debug, sd, "Fail to set streaming\n"); 743 return error; 744 } 745 746 device->streaming = enable; 747 return 0; 748 } 749 750 /* 751 * tvp7002_log_status() - Print information about register settings 752 * @sd: ptr to v4l2_subdev struct 753 * 754 * Log register values of a TVP7002 decoder device. 755 * Returns zero or -EINVAL if read operation fails. 756 */ 757 static int tvp7002_log_status(struct v4l2_subdev *sd) 758 { 759 struct tvp7002 *device = to_tvp7002(sd); 760 const struct v4l2_bt_timings *bt; 761 int detected; 762 763 /* Find my current timings */ 764 tvp7002_query_dv(sd, &detected); 765 766 bt = &device->current_timings->timings.bt; 767 v4l2_info(sd, "Selected DV Timings: %ux%u\n", bt->width, bt->height); 768 if (detected == NUM_TIMINGS) { 769 v4l2_info(sd, "Detected DV Timings: None\n"); 770 } else { 771 bt = &tvp7002_timings[detected].timings.bt; 772 v4l2_info(sd, "Detected DV Timings: %ux%u\n", 773 bt->width, bt->height); 774 } 775 v4l2_info(sd, "Streaming enabled: %s\n", 776 device->streaming ? "yes" : "no"); 777 778 /* Print the current value of the gain control */ 779 v4l2_ctrl_handler_log_status(&device->hdl, sd->name); 780 781 return 0; 782 } 783 784 static int tvp7002_enum_dv_timings(struct v4l2_subdev *sd, 785 struct v4l2_enum_dv_timings *timings) 786 { 787 if (timings->pad != 0) 788 return -EINVAL; 789 790 /* Check requested format index is within range */ 791 if (timings->index >= NUM_TIMINGS) 792 return -EINVAL; 793 794 timings->timings = tvp7002_timings[timings->index].timings; 795 return 0; 796 } 797 798 static const struct v4l2_ctrl_ops tvp7002_ctrl_ops = { 799 .s_ctrl = tvp7002_s_ctrl, 800 }; 801 802 /* 803 * tvp7002_enum_mbus_code() - Enum supported digital video format on pad 804 * @sd: pointer to standard V4L2 sub-device structure 805 * @cfg: pad configuration 806 * @code: pointer to subdev enum mbus code struct 807 * 808 * Enumerate supported digital video formats for pad. 809 */ 810 static int 811 tvp7002_enum_mbus_code(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg, 812 struct v4l2_subdev_mbus_code_enum *code) 813 { 814 /* Check requested format index is within range */ 815 if (code->index != 0) 816 return -EINVAL; 817 818 code->code = MEDIA_BUS_FMT_YUYV10_1X20; 819 820 return 0; 821 } 822 823 /* 824 * tvp7002_get_pad_format() - get video format on pad 825 * @sd: pointer to standard V4L2 sub-device structure 826 * @cfg: pad configuration 827 * @fmt: pointer to subdev format struct 828 * 829 * get video format for pad. 830 */ 831 static int 832 tvp7002_get_pad_format(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg, 833 struct v4l2_subdev_format *fmt) 834 { 835 struct tvp7002 *tvp7002 = to_tvp7002(sd); 836 837 fmt->format.code = MEDIA_BUS_FMT_YUYV10_1X20; 838 fmt->format.width = tvp7002->current_timings->timings.bt.width; 839 fmt->format.height = tvp7002->current_timings->timings.bt.height; 840 fmt->format.field = tvp7002->current_timings->scanmode; 841 fmt->format.colorspace = tvp7002->current_timings->color_space; 842 843 return 0; 844 } 845 846 /* 847 * tvp7002_set_pad_format() - set video format on pad 848 * @sd: pointer to standard V4L2 sub-device structure 849 * @cfg: pad configuration 850 * @fmt: pointer to subdev format struct 851 * 852 * set video format for pad. 853 */ 854 static int 855 tvp7002_set_pad_format(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg, 856 struct v4l2_subdev_format *fmt) 857 { 858 return tvp7002_get_pad_format(sd, cfg, fmt); 859 } 860 861 /* V4L2 core operation handlers */ 862 static const struct v4l2_subdev_core_ops tvp7002_core_ops = { 863 .log_status = tvp7002_log_status, 864 #ifdef CONFIG_VIDEO_ADV_DEBUG 865 .g_register = tvp7002_g_register, 866 .s_register = tvp7002_s_register, 867 #endif 868 }; 869 870 /* Specific video subsystem operation handlers */ 871 static const struct v4l2_subdev_video_ops tvp7002_video_ops = { 872 .g_dv_timings = tvp7002_g_dv_timings, 873 .s_dv_timings = tvp7002_s_dv_timings, 874 .query_dv_timings = tvp7002_query_dv_timings, 875 .s_stream = tvp7002_s_stream, 876 }; 877 878 /* media pad related operation handlers */ 879 static const struct v4l2_subdev_pad_ops tvp7002_pad_ops = { 880 .enum_mbus_code = tvp7002_enum_mbus_code, 881 .get_fmt = tvp7002_get_pad_format, 882 .set_fmt = tvp7002_set_pad_format, 883 .enum_dv_timings = tvp7002_enum_dv_timings, 884 }; 885 886 /* V4L2 top level operation handlers */ 887 static const struct v4l2_subdev_ops tvp7002_ops = { 888 .core = &tvp7002_core_ops, 889 .video = &tvp7002_video_ops, 890 .pad = &tvp7002_pad_ops, 891 }; 892 893 static struct tvp7002_config * 894 tvp7002_get_pdata(struct i2c_client *client) 895 { 896 struct v4l2_of_endpoint bus_cfg; 897 struct tvp7002_config *pdata = NULL; 898 struct device_node *endpoint; 899 unsigned int flags; 900 901 if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node) 902 return client->dev.platform_data; 903 904 endpoint = of_graph_get_next_endpoint(client->dev.of_node, NULL); 905 if (!endpoint) 906 return NULL; 907 908 if (v4l2_of_parse_endpoint(endpoint, &bus_cfg)) 909 goto done; 910 911 pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL); 912 if (!pdata) 913 goto done; 914 915 flags = bus_cfg.bus.parallel.flags; 916 917 if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) 918 pdata->hs_polarity = 1; 919 920 if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) 921 pdata->vs_polarity = 1; 922 923 if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING) 924 pdata->clk_polarity = 1; 925 926 if (flags & V4L2_MBUS_FIELD_EVEN_HIGH) 927 pdata->fid_polarity = 1; 928 929 if (flags & V4L2_MBUS_VIDEO_SOG_ACTIVE_HIGH) 930 pdata->sog_polarity = 1; 931 932 done: 933 of_node_put(endpoint); 934 return pdata; 935 } 936 937 /* 938 * tvp7002_probe - Probe a TVP7002 device 939 * @c: ptr to i2c_client struct 940 * @id: ptr to i2c_device_id struct 941 * 942 * Initialize the TVP7002 device 943 * Returns zero when successful, -EINVAL if register read fails or 944 * -EIO if i2c access is not available. 945 */ 946 static int tvp7002_probe(struct i2c_client *c, const struct i2c_device_id *id) 947 { 948 struct tvp7002_config *pdata = tvp7002_get_pdata(c); 949 struct v4l2_subdev *sd; 950 struct tvp7002 *device; 951 struct v4l2_dv_timings timings; 952 int polarity_a; 953 int polarity_b; 954 u8 revision; 955 int error; 956 957 if (pdata == NULL) { 958 dev_err(&c->dev, "No platform data\n"); 959 return -EINVAL; 960 } 961 962 /* Check if the adapter supports the needed features */ 963 if (!i2c_check_functionality(c->adapter, 964 I2C_FUNC_SMBUS_READ_BYTE | I2C_FUNC_SMBUS_WRITE_BYTE_DATA)) 965 return -EIO; 966 967 device = devm_kzalloc(&c->dev, sizeof(struct tvp7002), GFP_KERNEL); 968 969 if (!device) 970 return -ENOMEM; 971 972 sd = &device->sd; 973 device->pdata = pdata; 974 device->current_timings = tvp7002_timings; 975 976 /* Tell v4l2 the device is ready */ 977 v4l2_i2c_subdev_init(sd, c, &tvp7002_ops); 978 v4l_info(c, "tvp7002 found @ 0x%02x (%s)\n", 979 c->addr, c->adapter->name); 980 981 error = tvp7002_read(sd, TVP7002_CHIP_REV, &revision); 982 if (error < 0) 983 return error; 984 985 /* Get revision number */ 986 v4l2_info(sd, "Rev. %02x detected.\n", revision); 987 if (revision != 0x02) 988 v4l2_info(sd, "Unknown revision detected.\n"); 989 990 /* Initializes TVP7002 to its default values */ 991 error = tvp7002_write_inittab(sd, tvp7002_init_default); 992 993 if (error < 0) 994 return error; 995 996 /* Set polarity information after registers have been set */ 997 polarity_a = 0x20 | device->pdata->hs_polarity << 5 998 | device->pdata->vs_polarity << 2; 999 error = tvp7002_write(sd, TVP7002_SYNC_CTL_1, polarity_a); 1000 if (error < 0) 1001 return error; 1002 1003 polarity_b = 0x01 | device->pdata->fid_polarity << 2 1004 | device->pdata->sog_polarity << 1 1005 | device->pdata->clk_polarity; 1006 error = tvp7002_write(sd, TVP7002_MISC_CTL_3, polarity_b); 1007 if (error < 0) 1008 return error; 1009 1010 /* Set registers according to default video mode */ 1011 timings = device->current_timings->timings; 1012 error = tvp7002_s_dv_timings(sd, &timings); 1013 1014 #if defined(CONFIG_MEDIA_CONTROLLER) 1015 device->pad.flags = MEDIA_PAD_FL_SOURCE; 1016 device->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1017 device->sd.entity.flags |= MEDIA_ENT_F_ATV_DECODER; 1018 1019 error = media_entity_pads_init(&device->sd.entity, 1, &device->pad); 1020 if (error < 0) 1021 return error; 1022 #endif 1023 1024 v4l2_ctrl_handler_init(&device->hdl, 1); 1025 v4l2_ctrl_new_std(&device->hdl, &tvp7002_ctrl_ops, 1026 V4L2_CID_GAIN, 0, 255, 1, 0); 1027 sd->ctrl_handler = &device->hdl; 1028 if (device->hdl.error) { 1029 error = device->hdl.error; 1030 goto error; 1031 } 1032 v4l2_ctrl_handler_setup(&device->hdl); 1033 1034 error = v4l2_async_register_subdev(&device->sd); 1035 if (error) 1036 goto error; 1037 1038 return 0; 1039 1040 error: 1041 v4l2_ctrl_handler_free(&device->hdl); 1042 #if defined(CONFIG_MEDIA_CONTROLLER) 1043 media_entity_cleanup(&device->sd.entity); 1044 #endif 1045 return error; 1046 } 1047 1048 /* 1049 * tvp7002_remove - Remove TVP7002 device support 1050 * @c: ptr to i2c_client struct 1051 * 1052 * Reset the TVP7002 device 1053 * Returns zero. 1054 */ 1055 static int tvp7002_remove(struct i2c_client *c) 1056 { 1057 struct v4l2_subdev *sd = i2c_get_clientdata(c); 1058 struct tvp7002 *device = to_tvp7002(sd); 1059 1060 v4l2_dbg(1, debug, sd, "Removing tvp7002 adapter" 1061 "on address 0x%x\n", c->addr); 1062 v4l2_async_unregister_subdev(&device->sd); 1063 #if defined(CONFIG_MEDIA_CONTROLLER) 1064 media_entity_cleanup(&device->sd.entity); 1065 #endif 1066 v4l2_ctrl_handler_free(&device->hdl); 1067 return 0; 1068 } 1069 1070 /* I2C Device ID table */ 1071 static const struct i2c_device_id tvp7002_id[] = { 1072 { "tvp7002", 0 }, 1073 { } 1074 }; 1075 MODULE_DEVICE_TABLE(i2c, tvp7002_id); 1076 1077 #if IS_ENABLED(CONFIG_OF) 1078 static const struct of_device_id tvp7002_of_match[] = { 1079 { .compatible = "ti,tvp7002", }, 1080 { /* sentinel */ }, 1081 }; 1082 MODULE_DEVICE_TABLE(of, tvp7002_of_match); 1083 #endif 1084 1085 /* I2C driver data */ 1086 static struct i2c_driver tvp7002_driver = { 1087 .driver = { 1088 .of_match_table = of_match_ptr(tvp7002_of_match), 1089 .owner = THIS_MODULE, 1090 .name = TVP7002_MODULE_NAME, 1091 }, 1092 .probe = tvp7002_probe, 1093 .remove = tvp7002_remove, 1094 .id_table = tvp7002_id, 1095 }; 1096 1097 module_i2c_driver(tvp7002_driver); 1098