1 /* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics 2 * Digitizer with Horizontal PLL registers 3 * 4 * Copyright (C) 2009 Texas Instruments Inc 5 * Author: Santiago Nunez-Corrales <santiago.nunez@ridgerun.com> 6 * 7 * This code is partially based upon the TVP5150 driver 8 * written by Mauro Carvalho Chehab (mchehab@infradead.org), 9 * the TVP514x driver written by Vaibhav Hiremath <hvaibhav@ti.com> 10 * and the TVP7002 driver in the TI LSP 2.10.00.14. Revisions by 11 * Muralidharan Karicheri and Snehaprabha Narnakaje (TI). 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation; either version 2 of the License, or 16 * (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 26 */ 27 #include <linux/delay.h> 28 #include <linux/i2c.h> 29 #include <linux/slab.h> 30 #include <linux/videodev2.h> 31 #include <linux/module.h> 32 #include <linux/of.h> 33 #include <linux/v4l2-dv-timings.h> 34 #include <media/tvp7002.h> 35 #include <media/v4l2-async.h> 36 #include <media/v4l2-device.h> 37 #include <media/v4l2-common.h> 38 #include <media/v4l2-ctrls.h> 39 #include <media/v4l2-of.h> 40 41 #include "tvp7002_reg.h" 42 43 MODULE_DESCRIPTION("TI TVP7002 Video and Graphics Digitizer driver"); 44 MODULE_AUTHOR("Santiago Nunez-Corrales <santiago.nunez@ridgerun.com>"); 45 MODULE_LICENSE("GPL"); 46 47 /* I2C retry attempts */ 48 #define I2C_RETRY_COUNT (5) 49 50 /* End of registers */ 51 #define TVP7002_EOR 0x5c 52 53 /* Read write definition for registers */ 54 #define TVP7002_READ 0 55 #define TVP7002_WRITE 1 56 #define TVP7002_RESERVED 2 57 58 /* Interlaced vs progressive mask and shift */ 59 #define TVP7002_IP_SHIFT 5 60 #define TVP7002_INPR_MASK (0x01 << TVP7002_IP_SHIFT) 61 62 /* Shift for CPL and LPF registers */ 63 #define TVP7002_CL_SHIFT 8 64 #define TVP7002_CL_MASK 0x0f 65 66 /* Debug functions */ 67 static bool debug; 68 module_param(debug, bool, 0644); 69 MODULE_PARM_DESC(debug, "Debug level (0-2)"); 70 71 /* Structure for register values */ 72 struct i2c_reg_value { 73 u8 reg; 74 u8 value; 75 u8 type; 76 }; 77 78 /* 79 * Register default values (according to tvp7002 datasheet) 80 * In the case of read-only registers, the value (0xff) is 81 * never written. R/W functionality is controlled by the 82 * writable bit in the register struct definition. 83 */ 84 static const struct i2c_reg_value tvp7002_init_default[] = { 85 { TVP7002_CHIP_REV, 0xff, TVP7002_READ }, 86 { TVP7002_HPLL_FDBK_DIV_MSBS, 0x67, TVP7002_WRITE }, 87 { TVP7002_HPLL_FDBK_DIV_LSBS, 0x20, TVP7002_WRITE }, 88 { TVP7002_HPLL_CRTL, 0xa0, TVP7002_WRITE }, 89 { TVP7002_HPLL_PHASE_SEL, 0x80, TVP7002_WRITE }, 90 { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE }, 91 { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE }, 92 { TVP7002_HSYNC_OUT_W, 0x60, TVP7002_WRITE }, 93 { TVP7002_B_FINE_GAIN, 0x00, TVP7002_WRITE }, 94 { TVP7002_G_FINE_GAIN, 0x00, TVP7002_WRITE }, 95 { TVP7002_R_FINE_GAIN, 0x00, TVP7002_WRITE }, 96 { TVP7002_B_FINE_OFF_MSBS, 0x80, TVP7002_WRITE }, 97 { TVP7002_G_FINE_OFF_MSBS, 0x80, TVP7002_WRITE }, 98 { TVP7002_R_FINE_OFF_MSBS, 0x80, TVP7002_WRITE }, 99 { TVP7002_SYNC_CTL_1, 0x20, TVP7002_WRITE }, 100 { TVP7002_HPLL_AND_CLAMP_CTL, 0x2e, TVP7002_WRITE }, 101 { TVP7002_SYNC_ON_G_THRS, 0x5d, TVP7002_WRITE }, 102 { TVP7002_SYNC_SEPARATOR_THRS, 0x47, TVP7002_WRITE }, 103 { TVP7002_HPLL_PRE_COAST, 0x00, TVP7002_WRITE }, 104 { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE }, 105 { TVP7002_SYNC_DETECT_STAT, 0xff, TVP7002_READ }, 106 { TVP7002_OUT_FORMATTER, 0x47, TVP7002_WRITE }, 107 { TVP7002_MISC_CTL_1, 0x01, TVP7002_WRITE }, 108 { TVP7002_MISC_CTL_2, 0x00, TVP7002_WRITE }, 109 { TVP7002_MISC_CTL_3, 0x01, TVP7002_WRITE }, 110 { TVP7002_IN_MUX_SEL_1, 0x00, TVP7002_WRITE }, 111 { TVP7002_IN_MUX_SEL_2, 0x67, TVP7002_WRITE }, 112 { TVP7002_B_AND_G_COARSE_GAIN, 0x77, TVP7002_WRITE }, 113 { TVP7002_R_COARSE_GAIN, 0x07, TVP7002_WRITE }, 114 { TVP7002_FINE_OFF_LSBS, 0x00, TVP7002_WRITE }, 115 { TVP7002_B_COARSE_OFF, 0x10, TVP7002_WRITE }, 116 { TVP7002_G_COARSE_OFF, 0x10, TVP7002_WRITE }, 117 { TVP7002_R_COARSE_OFF, 0x10, TVP7002_WRITE }, 118 { TVP7002_HSOUT_OUT_START, 0x08, TVP7002_WRITE }, 119 { TVP7002_MISC_CTL_4, 0x00, TVP7002_WRITE }, 120 { TVP7002_B_DGTL_ALC_OUT_LSBS, 0xff, TVP7002_READ }, 121 { TVP7002_G_DGTL_ALC_OUT_LSBS, 0xff, TVP7002_READ }, 122 { TVP7002_R_DGTL_ALC_OUT_LSBS, 0xff, TVP7002_READ }, 123 { TVP7002_AUTO_LVL_CTL_ENABLE, 0x80, TVP7002_WRITE }, 124 { TVP7002_DGTL_ALC_OUT_MSBS, 0xff, TVP7002_READ }, 125 { TVP7002_AUTO_LVL_CTL_FILTER, 0x53, TVP7002_WRITE }, 126 { 0x29, 0x08, TVP7002_RESERVED }, 127 { TVP7002_FINE_CLAMP_CTL, 0x07, TVP7002_WRITE }, 128 /* PWR_CTL is controlled only by the probe and reset functions */ 129 { TVP7002_PWR_CTL, 0x00, TVP7002_RESERVED }, 130 { TVP7002_ADC_SETUP, 0x50, TVP7002_WRITE }, 131 { TVP7002_COARSE_CLAMP_CTL, 0x00, TVP7002_WRITE }, 132 { TVP7002_SOG_CLAMP, 0x80, TVP7002_WRITE }, 133 { TVP7002_RGB_COARSE_CLAMP_CTL, 0x8c, TVP7002_WRITE }, 134 { TVP7002_SOG_COARSE_CLAMP_CTL, 0x04, TVP7002_WRITE }, 135 { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE }, 136 { 0x32, 0x18, TVP7002_RESERVED }, 137 { 0x33, 0x60, TVP7002_RESERVED }, 138 { TVP7002_MVIS_STRIPPER_W, 0xff, TVP7002_RESERVED }, 139 { TVP7002_VSYNC_ALGN, 0x10, TVP7002_WRITE }, 140 { TVP7002_SYNC_BYPASS, 0x00, TVP7002_WRITE }, 141 { TVP7002_L_FRAME_STAT_LSBS, 0xff, TVP7002_READ }, 142 { TVP7002_L_FRAME_STAT_MSBS, 0xff, TVP7002_READ }, 143 { TVP7002_CLK_L_STAT_LSBS, 0xff, TVP7002_READ }, 144 { TVP7002_CLK_L_STAT_MSBS, 0xff, TVP7002_READ }, 145 { TVP7002_HSYNC_W, 0xff, TVP7002_READ }, 146 { TVP7002_VSYNC_W, 0xff, TVP7002_READ }, 147 { TVP7002_L_LENGTH_TOL, 0x03, TVP7002_WRITE }, 148 { 0x3e, 0x60, TVP7002_RESERVED }, 149 { TVP7002_VIDEO_BWTH_CTL, 0x01, TVP7002_WRITE }, 150 { TVP7002_AVID_START_PIXEL_LSBS, 0x01, TVP7002_WRITE }, 151 { TVP7002_AVID_START_PIXEL_MSBS, 0x2c, TVP7002_WRITE }, 152 { TVP7002_AVID_STOP_PIXEL_LSBS, 0x06, TVP7002_WRITE }, 153 { TVP7002_AVID_STOP_PIXEL_MSBS, 0x2c, TVP7002_WRITE }, 154 { TVP7002_VBLK_F_0_START_L_OFF, 0x05, TVP7002_WRITE }, 155 { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE }, 156 { TVP7002_VBLK_F_0_DURATION, 0x1e, TVP7002_WRITE }, 157 { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE }, 158 { TVP7002_FBIT_F_0_START_L_OFF, 0x00, TVP7002_WRITE }, 159 { TVP7002_FBIT_F_1_START_L_OFF, 0x00, TVP7002_WRITE }, 160 { TVP7002_YUV_Y_G_COEF_LSBS, 0xe3, TVP7002_WRITE }, 161 { TVP7002_YUV_Y_G_COEF_MSBS, 0x16, TVP7002_WRITE }, 162 { TVP7002_YUV_Y_B_COEF_LSBS, 0x4f, TVP7002_WRITE }, 163 { TVP7002_YUV_Y_B_COEF_MSBS, 0x02, TVP7002_WRITE }, 164 { TVP7002_YUV_Y_R_COEF_LSBS, 0xce, TVP7002_WRITE }, 165 { TVP7002_YUV_Y_R_COEF_MSBS, 0x06, TVP7002_WRITE }, 166 { TVP7002_YUV_U_G_COEF_LSBS, 0xab, TVP7002_WRITE }, 167 { TVP7002_YUV_U_G_COEF_MSBS, 0xf3, TVP7002_WRITE }, 168 { TVP7002_YUV_U_B_COEF_LSBS, 0x00, TVP7002_WRITE }, 169 { TVP7002_YUV_U_B_COEF_MSBS, 0x10, TVP7002_WRITE }, 170 { TVP7002_YUV_U_R_COEF_LSBS, 0x55, TVP7002_WRITE }, 171 { TVP7002_YUV_U_R_COEF_MSBS, 0xfc, TVP7002_WRITE }, 172 { TVP7002_YUV_V_G_COEF_LSBS, 0x78, TVP7002_WRITE }, 173 { TVP7002_YUV_V_G_COEF_MSBS, 0xf1, TVP7002_WRITE }, 174 { TVP7002_YUV_V_B_COEF_LSBS, 0x88, TVP7002_WRITE }, 175 { TVP7002_YUV_V_B_COEF_MSBS, 0xfe, TVP7002_WRITE }, 176 { TVP7002_YUV_V_R_COEF_LSBS, 0x00, TVP7002_WRITE }, 177 { TVP7002_YUV_V_R_COEF_MSBS, 0x10, TVP7002_WRITE }, 178 /* This signals end of register values */ 179 { TVP7002_EOR, 0xff, TVP7002_RESERVED } 180 }; 181 182 /* Register parameters for 480P */ 183 static const struct i2c_reg_value tvp7002_parms_480P[] = { 184 { TVP7002_HPLL_FDBK_DIV_MSBS, 0x35, TVP7002_WRITE }, 185 { TVP7002_HPLL_FDBK_DIV_LSBS, 0xa0, TVP7002_WRITE }, 186 { TVP7002_HPLL_CRTL, 0x02, TVP7002_WRITE }, 187 { TVP7002_AVID_START_PIXEL_LSBS, 0x91, TVP7002_WRITE }, 188 { TVP7002_AVID_START_PIXEL_MSBS, 0x00, TVP7002_WRITE }, 189 { TVP7002_AVID_STOP_PIXEL_LSBS, 0x0B, TVP7002_WRITE }, 190 { TVP7002_AVID_STOP_PIXEL_MSBS, 0x00, TVP7002_WRITE }, 191 { TVP7002_VBLK_F_0_START_L_OFF, 0x03, TVP7002_WRITE }, 192 { TVP7002_VBLK_F_1_START_L_OFF, 0x01, TVP7002_WRITE }, 193 { TVP7002_VBLK_F_0_DURATION, 0x13, TVP7002_WRITE }, 194 { TVP7002_VBLK_F_1_DURATION, 0x13, TVP7002_WRITE }, 195 { TVP7002_ALC_PLACEMENT, 0x18, TVP7002_WRITE }, 196 { TVP7002_CLAMP_START, 0x06, TVP7002_WRITE }, 197 { TVP7002_CLAMP_W, 0x10, TVP7002_WRITE }, 198 { TVP7002_HPLL_PRE_COAST, 0x03, TVP7002_WRITE }, 199 { TVP7002_HPLL_POST_COAST, 0x03, TVP7002_WRITE }, 200 { TVP7002_EOR, 0xff, TVP7002_RESERVED } 201 }; 202 203 /* Register parameters for 576P */ 204 static const struct i2c_reg_value tvp7002_parms_576P[] = { 205 { TVP7002_HPLL_FDBK_DIV_MSBS, 0x36, TVP7002_WRITE }, 206 { TVP7002_HPLL_FDBK_DIV_LSBS, 0x00, TVP7002_WRITE }, 207 { TVP7002_HPLL_CRTL, 0x18, TVP7002_WRITE }, 208 { TVP7002_AVID_START_PIXEL_LSBS, 0x9B, TVP7002_WRITE }, 209 { TVP7002_AVID_START_PIXEL_MSBS, 0x00, TVP7002_WRITE }, 210 { TVP7002_AVID_STOP_PIXEL_LSBS, 0x0F, TVP7002_WRITE }, 211 { TVP7002_AVID_STOP_PIXEL_MSBS, 0x00, TVP7002_WRITE }, 212 { TVP7002_VBLK_F_0_START_L_OFF, 0x00, TVP7002_WRITE }, 213 { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE }, 214 { TVP7002_VBLK_F_0_DURATION, 0x2D, TVP7002_WRITE }, 215 { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE }, 216 { TVP7002_ALC_PLACEMENT, 0x18, TVP7002_WRITE }, 217 { TVP7002_CLAMP_START, 0x06, TVP7002_WRITE }, 218 { TVP7002_CLAMP_W, 0x10, TVP7002_WRITE }, 219 { TVP7002_HPLL_PRE_COAST, 0x03, TVP7002_WRITE }, 220 { TVP7002_HPLL_POST_COAST, 0x03, TVP7002_WRITE }, 221 { TVP7002_EOR, 0xff, TVP7002_RESERVED } 222 }; 223 224 /* Register parameters for 1080I60 */ 225 static const struct i2c_reg_value tvp7002_parms_1080I60[] = { 226 { TVP7002_HPLL_FDBK_DIV_MSBS, 0x89, TVP7002_WRITE }, 227 { TVP7002_HPLL_FDBK_DIV_LSBS, 0x80, TVP7002_WRITE }, 228 { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE }, 229 { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE }, 230 { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE }, 231 { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE }, 232 { TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE }, 233 { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE }, 234 { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE }, 235 { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE }, 236 { TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE }, 237 { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE }, 238 { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE }, 239 { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE }, 240 { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE }, 241 { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE }, 242 { TVP7002_EOR, 0xff, TVP7002_RESERVED } 243 }; 244 245 /* Register parameters for 1080P60 */ 246 static const struct i2c_reg_value tvp7002_parms_1080P60[] = { 247 { TVP7002_HPLL_FDBK_DIV_MSBS, 0x89, TVP7002_WRITE }, 248 { TVP7002_HPLL_FDBK_DIV_LSBS, 0x80, TVP7002_WRITE }, 249 { TVP7002_HPLL_CRTL, 0xE0, TVP7002_WRITE }, 250 { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE }, 251 { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE }, 252 { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE }, 253 { TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE }, 254 { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE }, 255 { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE }, 256 { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE }, 257 { TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE }, 258 { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE }, 259 { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE }, 260 { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE }, 261 { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE }, 262 { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE }, 263 { TVP7002_EOR, 0xff, TVP7002_RESERVED } 264 }; 265 266 /* Register parameters for 1080I50 */ 267 static const struct i2c_reg_value tvp7002_parms_1080I50[] = { 268 { TVP7002_HPLL_FDBK_DIV_MSBS, 0xa5, TVP7002_WRITE }, 269 { TVP7002_HPLL_FDBK_DIV_LSBS, 0x00, TVP7002_WRITE }, 270 { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE }, 271 { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE }, 272 { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE }, 273 { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE }, 274 { TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE }, 275 { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE }, 276 { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE }, 277 { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE }, 278 { TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE }, 279 { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE }, 280 { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE }, 281 { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE }, 282 { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE }, 283 { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE }, 284 { TVP7002_EOR, 0xff, TVP7002_RESERVED } 285 }; 286 287 /* Register parameters for 720P60 */ 288 static const struct i2c_reg_value tvp7002_parms_720P60[] = { 289 { TVP7002_HPLL_FDBK_DIV_MSBS, 0x67, TVP7002_WRITE }, 290 { TVP7002_HPLL_FDBK_DIV_LSBS, 0x20, TVP7002_WRITE }, 291 { TVP7002_HPLL_CRTL, 0xa0, TVP7002_WRITE }, 292 { TVP7002_AVID_START_PIXEL_LSBS, 0x47, TVP7002_WRITE }, 293 { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE }, 294 { TVP7002_AVID_STOP_PIXEL_LSBS, 0x4B, TVP7002_WRITE }, 295 { TVP7002_AVID_STOP_PIXEL_MSBS, 0x06, TVP7002_WRITE }, 296 { TVP7002_VBLK_F_0_START_L_OFF, 0x05, TVP7002_WRITE }, 297 { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE }, 298 { TVP7002_VBLK_F_0_DURATION, 0x2D, TVP7002_WRITE }, 299 { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE }, 300 { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE }, 301 { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE }, 302 { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE }, 303 { TVP7002_HPLL_PRE_COAST, 0x00, TVP7002_WRITE }, 304 { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE }, 305 { TVP7002_EOR, 0xff, TVP7002_RESERVED } 306 }; 307 308 /* Register parameters for 720P50 */ 309 static const struct i2c_reg_value tvp7002_parms_720P50[] = { 310 { TVP7002_HPLL_FDBK_DIV_MSBS, 0x7b, TVP7002_WRITE }, 311 { TVP7002_HPLL_FDBK_DIV_LSBS, 0xc0, TVP7002_WRITE }, 312 { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE }, 313 { TVP7002_AVID_START_PIXEL_LSBS, 0x47, TVP7002_WRITE }, 314 { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE }, 315 { TVP7002_AVID_STOP_PIXEL_LSBS, 0x4B, TVP7002_WRITE }, 316 { TVP7002_AVID_STOP_PIXEL_MSBS, 0x06, TVP7002_WRITE }, 317 { TVP7002_VBLK_F_0_START_L_OFF, 0x05, TVP7002_WRITE }, 318 { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE }, 319 { TVP7002_VBLK_F_0_DURATION, 0x2D, TVP7002_WRITE }, 320 { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE }, 321 { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE }, 322 { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE }, 323 { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE }, 324 { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE }, 325 { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE }, 326 { TVP7002_EOR, 0xff, TVP7002_RESERVED } 327 }; 328 329 /* Timings definition for handling device operation */ 330 struct tvp7002_timings_definition { 331 struct v4l2_dv_timings timings; 332 const struct i2c_reg_value *p_settings; 333 enum v4l2_colorspace color_space; 334 enum v4l2_field scanmode; 335 u16 progressive; 336 u16 lines_per_frame; 337 u16 cpl_min; 338 u16 cpl_max; 339 }; 340 341 /* Struct list for digital video timings */ 342 static const struct tvp7002_timings_definition tvp7002_timings[] = { 343 { 344 V4L2_DV_BT_CEA_1280X720P60, 345 tvp7002_parms_720P60, 346 V4L2_COLORSPACE_REC709, 347 V4L2_FIELD_NONE, 348 1, 349 0x2EE, 350 135, 351 153 352 }, 353 { 354 V4L2_DV_BT_CEA_1920X1080I60, 355 tvp7002_parms_1080I60, 356 V4L2_COLORSPACE_REC709, 357 V4L2_FIELD_INTERLACED, 358 0, 359 0x465, 360 181, 361 205 362 }, 363 { 364 V4L2_DV_BT_CEA_1920X1080I50, 365 tvp7002_parms_1080I50, 366 V4L2_COLORSPACE_REC709, 367 V4L2_FIELD_INTERLACED, 368 0, 369 0x465, 370 217, 371 245 372 }, 373 { 374 V4L2_DV_BT_CEA_1280X720P50, 375 tvp7002_parms_720P50, 376 V4L2_COLORSPACE_REC709, 377 V4L2_FIELD_NONE, 378 1, 379 0x2EE, 380 163, 381 183 382 }, 383 { 384 V4L2_DV_BT_CEA_1920X1080P60, 385 tvp7002_parms_1080P60, 386 V4L2_COLORSPACE_REC709, 387 V4L2_FIELD_NONE, 388 1, 389 0x465, 390 90, 391 102 392 }, 393 { 394 V4L2_DV_BT_CEA_720X480P59_94, 395 tvp7002_parms_480P, 396 V4L2_COLORSPACE_SMPTE170M, 397 V4L2_FIELD_NONE, 398 1, 399 0x20D, 400 0xffff, 401 0xffff 402 }, 403 { 404 V4L2_DV_BT_CEA_720X576P50, 405 tvp7002_parms_576P, 406 V4L2_COLORSPACE_SMPTE170M, 407 V4L2_FIELD_NONE, 408 1, 409 0x271, 410 0xffff, 411 0xffff 412 } 413 }; 414 415 #define NUM_TIMINGS ARRAY_SIZE(tvp7002_timings) 416 417 /* Device definition */ 418 struct tvp7002 { 419 struct v4l2_subdev sd; 420 struct v4l2_ctrl_handler hdl; 421 const struct tvp7002_config *pdata; 422 423 int ver; 424 int streaming; 425 426 const struct tvp7002_timings_definition *current_timings; 427 struct media_pad pad; 428 }; 429 430 /* 431 * to_tvp7002 - Obtain device handler TVP7002 432 * @sd: ptr to v4l2_subdev struct 433 * 434 * Returns device handler tvp7002. 435 */ 436 static inline struct tvp7002 *to_tvp7002(struct v4l2_subdev *sd) 437 { 438 return container_of(sd, struct tvp7002, sd); 439 } 440 441 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) 442 { 443 return &container_of(ctrl->handler, struct tvp7002, hdl)->sd; 444 } 445 446 /* 447 * tvp7002_read - Read a value from a register in an TVP7002 448 * @sd: ptr to v4l2_subdev struct 449 * @addr: TVP7002 register address 450 * @dst: pointer to 8-bit destination 451 * 452 * Returns value read if successful, or non-zero (-1) otherwise. 453 */ 454 static int tvp7002_read(struct v4l2_subdev *sd, u8 addr, u8 *dst) 455 { 456 struct i2c_client *c = v4l2_get_subdevdata(sd); 457 int retry; 458 int error; 459 460 for (retry = 0; retry < I2C_RETRY_COUNT; retry++) { 461 error = i2c_smbus_read_byte_data(c, addr); 462 463 if (error >= 0) { 464 *dst = (u8)error; 465 return 0; 466 } 467 468 msleep_interruptible(10); 469 } 470 v4l2_err(sd, "TVP7002 read error %d\n", error); 471 return error; 472 } 473 474 /* 475 * tvp7002_read_err() - Read a register value with error code 476 * @sd: pointer to standard V4L2 sub-device structure 477 * @reg: destination register 478 * @val: value to be read 479 * @err: pointer to error value 480 * 481 * Read a value in a register and save error value in pointer. 482 * Also update the register table if successful 483 */ 484 static inline void tvp7002_read_err(struct v4l2_subdev *sd, u8 reg, 485 u8 *dst, int *err) 486 { 487 if (!*err) 488 *err = tvp7002_read(sd, reg, dst); 489 } 490 491 /* 492 * tvp7002_write() - Write a value to a register in TVP7002 493 * @sd: ptr to v4l2_subdev struct 494 * @addr: TVP7002 register address 495 * @value: value to be written to the register 496 * 497 * Write a value to a register in an TVP7002 decoder device. 498 * Returns zero if successful, or non-zero otherwise. 499 */ 500 static int tvp7002_write(struct v4l2_subdev *sd, u8 addr, u8 value) 501 { 502 struct i2c_client *c; 503 int retry; 504 int error; 505 506 c = v4l2_get_subdevdata(sd); 507 508 for (retry = 0; retry < I2C_RETRY_COUNT; retry++) { 509 error = i2c_smbus_write_byte_data(c, addr, value); 510 511 if (error >= 0) 512 return 0; 513 514 v4l2_warn(sd, "Write: retry ... %d\n", retry); 515 msleep_interruptible(10); 516 } 517 v4l2_err(sd, "TVP7002 write error %d\n", error); 518 return error; 519 } 520 521 /* 522 * tvp7002_write_err() - Write a register value with error code 523 * @sd: pointer to standard V4L2 sub-device structure 524 * @reg: destination register 525 * @val: value to be written 526 * @err: pointer to error value 527 * 528 * Write a value in a register and save error value in pointer. 529 * Also update the register table if successful 530 */ 531 static inline void tvp7002_write_err(struct v4l2_subdev *sd, u8 reg, 532 u8 val, int *err) 533 { 534 if (!*err) 535 *err = tvp7002_write(sd, reg, val); 536 } 537 538 /* 539 * tvp7002_write_inittab() - Write initialization values 540 * @sd: ptr to v4l2_subdev struct 541 * @regs: ptr to i2c_reg_value struct 542 * 543 * Write initialization values. 544 * Returns zero or -EINVAL if read operation fails. 545 */ 546 static int tvp7002_write_inittab(struct v4l2_subdev *sd, 547 const struct i2c_reg_value *regs) 548 { 549 int error = 0; 550 551 /* Initialize the first (defined) registers */ 552 while (TVP7002_EOR != regs->reg) { 553 if (TVP7002_WRITE == regs->type) 554 tvp7002_write_err(sd, regs->reg, regs->value, &error); 555 regs++; 556 } 557 558 return error; 559 } 560 561 static int tvp7002_s_dv_timings(struct v4l2_subdev *sd, 562 struct v4l2_dv_timings *dv_timings) 563 { 564 struct tvp7002 *device = to_tvp7002(sd); 565 const struct v4l2_bt_timings *bt = &dv_timings->bt; 566 int i; 567 568 if (dv_timings->type != V4L2_DV_BT_656_1120) 569 return -EINVAL; 570 for (i = 0; i < NUM_TIMINGS; i++) { 571 const struct v4l2_bt_timings *t = &tvp7002_timings[i].timings.bt; 572 573 if (!memcmp(bt, t, &bt->standards - &bt->width)) { 574 device->current_timings = &tvp7002_timings[i]; 575 return tvp7002_write_inittab(sd, tvp7002_timings[i].p_settings); 576 } 577 } 578 return -EINVAL; 579 } 580 581 static int tvp7002_g_dv_timings(struct v4l2_subdev *sd, 582 struct v4l2_dv_timings *dv_timings) 583 { 584 struct tvp7002 *device = to_tvp7002(sd); 585 586 *dv_timings = device->current_timings->timings; 587 return 0; 588 } 589 590 /* 591 * tvp7002_s_ctrl() - Set a control 592 * @ctrl: ptr to v4l2_ctrl struct 593 * 594 * Set a control in TVP7002 decoder device. 595 * Returns zero when successful or -EINVAL if register access fails. 596 */ 597 static int tvp7002_s_ctrl(struct v4l2_ctrl *ctrl) 598 { 599 struct v4l2_subdev *sd = to_sd(ctrl); 600 int error = 0; 601 602 switch (ctrl->id) { 603 case V4L2_CID_GAIN: 604 tvp7002_write_err(sd, TVP7002_R_FINE_GAIN, ctrl->val, &error); 605 tvp7002_write_err(sd, TVP7002_G_FINE_GAIN, ctrl->val, &error); 606 tvp7002_write_err(sd, TVP7002_B_FINE_GAIN, ctrl->val, &error); 607 return error; 608 } 609 return -EINVAL; 610 } 611 612 /* 613 * tvp7002_mbus_fmt() - V4L2 decoder interface handler for try/s/g_mbus_fmt 614 * @sd: pointer to standard V4L2 sub-device structure 615 * @f: pointer to mediabus format structure 616 * 617 * Negotiate the image capture size and mediabus format. 618 * There is only one possible format, so this single function works for 619 * get, set and try. 620 */ 621 static int tvp7002_mbus_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *f) 622 { 623 struct tvp7002 *device = to_tvp7002(sd); 624 const struct v4l2_bt_timings *bt = &device->current_timings->timings.bt; 625 626 f->width = bt->width; 627 f->height = bt->height; 628 f->code = V4L2_MBUS_FMT_YUYV10_1X20; 629 f->field = device->current_timings->scanmode; 630 f->colorspace = device->current_timings->color_space; 631 632 v4l2_dbg(1, debug, sd, "MBUS_FMT: Width - %d, Height - %d", 633 f->width, f->height); 634 return 0; 635 } 636 637 /* 638 * tvp7002_query_dv() - query DV timings 639 * @sd: pointer to standard V4L2 sub-device structure 640 * @index: index into the tvp7002_timings array 641 * 642 * Returns the current DV timings detected by TVP7002. If no active input is 643 * detected, returns -EINVAL 644 */ 645 static int tvp7002_query_dv(struct v4l2_subdev *sd, int *index) 646 { 647 const struct tvp7002_timings_definition *timings = tvp7002_timings; 648 u8 progressive; 649 u32 lpfr; 650 u32 cpln; 651 int error = 0; 652 u8 lpf_lsb; 653 u8 lpf_msb; 654 u8 cpl_lsb; 655 u8 cpl_msb; 656 657 /* Return invalid index if no active input is detected */ 658 *index = NUM_TIMINGS; 659 660 /* Read standards from device registers */ 661 tvp7002_read_err(sd, TVP7002_L_FRAME_STAT_LSBS, &lpf_lsb, &error); 662 tvp7002_read_err(sd, TVP7002_L_FRAME_STAT_MSBS, &lpf_msb, &error); 663 664 if (error < 0) 665 return error; 666 667 tvp7002_read_err(sd, TVP7002_CLK_L_STAT_LSBS, &cpl_lsb, &error); 668 tvp7002_read_err(sd, TVP7002_CLK_L_STAT_MSBS, &cpl_msb, &error); 669 670 if (error < 0) 671 return error; 672 673 /* Get lines per frame, clocks per line and interlaced/progresive */ 674 lpfr = lpf_lsb | ((TVP7002_CL_MASK & lpf_msb) << TVP7002_CL_SHIFT); 675 cpln = cpl_lsb | ((TVP7002_CL_MASK & cpl_msb) << TVP7002_CL_SHIFT); 676 progressive = (lpf_msb & TVP7002_INPR_MASK) >> TVP7002_IP_SHIFT; 677 678 /* Do checking of video modes */ 679 for (*index = 0; *index < NUM_TIMINGS; (*index)++, timings++) 680 if (lpfr == timings->lines_per_frame && 681 progressive == timings->progressive) { 682 if (timings->cpl_min == 0xffff) 683 break; 684 if (cpln >= timings->cpl_min && cpln <= timings->cpl_max) 685 break; 686 } 687 688 if (*index == NUM_TIMINGS) { 689 v4l2_dbg(1, debug, sd, "detection failed: lpf = %x, cpl = %x\n", 690 lpfr, cpln); 691 return -ENOLINK; 692 } 693 694 /* Update lines per frame and clocks per line info */ 695 v4l2_dbg(1, debug, sd, "detected timings: %d\n", *index); 696 return 0; 697 } 698 699 static int tvp7002_query_dv_timings(struct v4l2_subdev *sd, 700 struct v4l2_dv_timings *timings) 701 { 702 int index; 703 int err = tvp7002_query_dv(sd, &index); 704 705 if (err) 706 return err; 707 *timings = tvp7002_timings[index].timings; 708 return 0; 709 } 710 711 #ifdef CONFIG_VIDEO_ADV_DEBUG 712 /* 713 * tvp7002_g_register() - Get the value of a register 714 * @sd: ptr to v4l2_subdev struct 715 * @reg: ptr to v4l2_dbg_register struct 716 * 717 * Get the value of a TVP7002 decoder device register. 718 * Returns zero when successful, -EINVAL if register read fails or 719 * access to I2C client fails. 720 */ 721 static int tvp7002_g_register(struct v4l2_subdev *sd, 722 struct v4l2_dbg_register *reg) 723 { 724 u8 val; 725 int ret; 726 727 ret = tvp7002_read(sd, reg->reg & 0xff, &val); 728 reg->val = val; 729 reg->size = 1; 730 return ret; 731 } 732 733 /* 734 * tvp7002_s_register() - set a control 735 * @sd: ptr to v4l2_subdev struct 736 * @reg: ptr to v4l2_dbg_register struct 737 * 738 * Get the value of a TVP7002 decoder device register. 739 * Returns zero when successful, -EINVAL if register read fails. 740 */ 741 static int tvp7002_s_register(struct v4l2_subdev *sd, 742 const struct v4l2_dbg_register *reg) 743 { 744 return tvp7002_write(sd, reg->reg & 0xff, reg->val & 0xff); 745 } 746 #endif 747 748 /* 749 * tvp7002_enum_mbus_fmt() - Enum supported mediabus formats 750 * @sd: pointer to standard V4L2 sub-device structure 751 * @index: format index 752 * @code: pointer to mediabus format 753 * 754 * Enumerate supported mediabus formats. 755 */ 756 757 static int tvp7002_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned index, 758 enum v4l2_mbus_pixelcode *code) 759 { 760 /* Check requested format index is within range */ 761 if (index) 762 return -EINVAL; 763 *code = V4L2_MBUS_FMT_YUYV10_1X20; 764 return 0; 765 } 766 767 /* 768 * tvp7002_s_stream() - V4L2 decoder i/f handler for s_stream 769 * @sd: pointer to standard V4L2 sub-device structure 770 * @enable: streaming enable or disable 771 * 772 * Sets streaming to enable or disable, if possible. 773 */ 774 static int tvp7002_s_stream(struct v4l2_subdev *sd, int enable) 775 { 776 struct tvp7002 *device = to_tvp7002(sd); 777 int error = 0; 778 779 if (device->streaming == enable) 780 return 0; 781 782 if (enable) { 783 /* Set output state on (low impedance means stream on) */ 784 error = tvp7002_write(sd, TVP7002_MISC_CTL_2, 0x00); 785 device->streaming = enable; 786 } else { 787 /* Set output state off (high impedance means stream off) */ 788 error = tvp7002_write(sd, TVP7002_MISC_CTL_2, 0x03); 789 if (error) 790 v4l2_dbg(1, debug, sd, "Unable to stop streaming\n"); 791 792 device->streaming = enable; 793 } 794 795 return error; 796 } 797 798 /* 799 * tvp7002_log_status() - Print information about register settings 800 * @sd: ptr to v4l2_subdev struct 801 * 802 * Log register values of a TVP7002 decoder device. 803 * Returns zero or -EINVAL if read operation fails. 804 */ 805 static int tvp7002_log_status(struct v4l2_subdev *sd) 806 { 807 struct tvp7002 *device = to_tvp7002(sd); 808 const struct v4l2_bt_timings *bt; 809 int detected; 810 811 /* Find my current timings */ 812 tvp7002_query_dv(sd, &detected); 813 814 bt = &device->current_timings->timings.bt; 815 v4l2_info(sd, "Selected DV Timings: %ux%u\n", bt->width, bt->height); 816 if (detected == NUM_TIMINGS) { 817 v4l2_info(sd, "Detected DV Timings: None\n"); 818 } else { 819 bt = &tvp7002_timings[detected].timings.bt; 820 v4l2_info(sd, "Detected DV Timings: %ux%u\n", 821 bt->width, bt->height); 822 } 823 v4l2_info(sd, "Streaming enabled: %s\n", 824 device->streaming ? "yes" : "no"); 825 826 /* Print the current value of the gain control */ 827 v4l2_ctrl_handler_log_status(&device->hdl, sd->name); 828 829 return 0; 830 } 831 832 static int tvp7002_enum_dv_timings(struct v4l2_subdev *sd, 833 struct v4l2_enum_dv_timings *timings) 834 { 835 /* Check requested format index is within range */ 836 if (timings->index >= NUM_TIMINGS) 837 return -EINVAL; 838 839 timings->timings = tvp7002_timings[timings->index].timings; 840 return 0; 841 } 842 843 static const struct v4l2_ctrl_ops tvp7002_ctrl_ops = { 844 .s_ctrl = tvp7002_s_ctrl, 845 }; 846 847 /* 848 * tvp7002_enum_mbus_code() - Enum supported digital video format on pad 849 * @sd: pointer to standard V4L2 sub-device structure 850 * @fh: file handle for the subdev 851 * @code: pointer to subdev enum mbus code struct 852 * 853 * Enumerate supported digital video formats for pad. 854 */ 855 static int 856 tvp7002_enum_mbus_code(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh, 857 struct v4l2_subdev_mbus_code_enum *code) 858 { 859 /* Check requested format index is within range */ 860 if (code->index != 0) 861 return -EINVAL; 862 863 code->code = V4L2_MBUS_FMT_YUYV10_1X20; 864 865 return 0; 866 } 867 868 /* 869 * tvp7002_get_pad_format() - get video format on pad 870 * @sd: pointer to standard V4L2 sub-device structure 871 * @fh: file handle for the subdev 872 * @fmt: pointer to subdev format struct 873 * 874 * get video format for pad. 875 */ 876 static int 877 tvp7002_get_pad_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh, 878 struct v4l2_subdev_format *fmt) 879 { 880 struct tvp7002 *tvp7002 = to_tvp7002(sd); 881 882 fmt->format.code = V4L2_MBUS_FMT_YUYV10_1X20; 883 fmt->format.width = tvp7002->current_timings->timings.bt.width; 884 fmt->format.height = tvp7002->current_timings->timings.bt.height; 885 fmt->format.field = tvp7002->current_timings->scanmode; 886 fmt->format.colorspace = tvp7002->current_timings->color_space; 887 888 return 0; 889 } 890 891 /* 892 * tvp7002_set_pad_format() - set video format on pad 893 * @sd: pointer to standard V4L2 sub-device structure 894 * @fh: file handle for the subdev 895 * @fmt: pointer to subdev format struct 896 * 897 * set video format for pad. 898 */ 899 static int 900 tvp7002_set_pad_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh, 901 struct v4l2_subdev_format *fmt) 902 { 903 return tvp7002_get_pad_format(sd, fh, fmt); 904 } 905 906 /* V4L2 core operation handlers */ 907 static const struct v4l2_subdev_core_ops tvp7002_core_ops = { 908 .log_status = tvp7002_log_status, 909 .g_ext_ctrls = v4l2_subdev_g_ext_ctrls, 910 .try_ext_ctrls = v4l2_subdev_try_ext_ctrls, 911 .s_ext_ctrls = v4l2_subdev_s_ext_ctrls, 912 .g_ctrl = v4l2_subdev_g_ctrl, 913 .s_ctrl = v4l2_subdev_s_ctrl, 914 .queryctrl = v4l2_subdev_queryctrl, 915 .querymenu = v4l2_subdev_querymenu, 916 #ifdef CONFIG_VIDEO_ADV_DEBUG 917 .g_register = tvp7002_g_register, 918 .s_register = tvp7002_s_register, 919 #endif 920 }; 921 922 /* Specific video subsystem operation handlers */ 923 static const struct v4l2_subdev_video_ops tvp7002_video_ops = { 924 .g_dv_timings = tvp7002_g_dv_timings, 925 .s_dv_timings = tvp7002_s_dv_timings, 926 .enum_dv_timings = tvp7002_enum_dv_timings, 927 .query_dv_timings = tvp7002_query_dv_timings, 928 .s_stream = tvp7002_s_stream, 929 .g_mbus_fmt = tvp7002_mbus_fmt, 930 .try_mbus_fmt = tvp7002_mbus_fmt, 931 .s_mbus_fmt = tvp7002_mbus_fmt, 932 .enum_mbus_fmt = tvp7002_enum_mbus_fmt, 933 }; 934 935 /* media pad related operation handlers */ 936 static const struct v4l2_subdev_pad_ops tvp7002_pad_ops = { 937 .enum_mbus_code = tvp7002_enum_mbus_code, 938 .get_fmt = tvp7002_get_pad_format, 939 .set_fmt = tvp7002_set_pad_format, 940 }; 941 942 /* V4L2 top level operation handlers */ 943 static const struct v4l2_subdev_ops tvp7002_ops = { 944 .core = &tvp7002_core_ops, 945 .video = &tvp7002_video_ops, 946 .pad = &tvp7002_pad_ops, 947 }; 948 949 static struct tvp7002_config * 950 tvp7002_get_pdata(struct i2c_client *client) 951 { 952 struct v4l2_of_endpoint bus_cfg; 953 struct tvp7002_config *pdata; 954 struct device_node *endpoint; 955 unsigned int flags; 956 957 if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node) 958 return client->dev.platform_data; 959 960 endpoint = v4l2_of_get_next_endpoint(client->dev.of_node, NULL); 961 if (!endpoint) 962 return NULL; 963 964 pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL); 965 if (!pdata) 966 goto done; 967 968 v4l2_of_parse_endpoint(endpoint, &bus_cfg); 969 flags = bus_cfg.bus.parallel.flags; 970 971 if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) 972 pdata->hs_polarity = 1; 973 974 if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) 975 pdata->vs_polarity = 1; 976 977 if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING) 978 pdata->clk_polarity = 1; 979 980 if (flags & V4L2_MBUS_FIELD_EVEN_HIGH) 981 pdata->fid_polarity = 1; 982 983 if (flags & V4L2_MBUS_VIDEO_SOG_ACTIVE_HIGH) 984 pdata->sog_polarity = 1; 985 986 done: 987 of_node_put(endpoint); 988 return pdata; 989 } 990 991 /* 992 * tvp7002_probe - Probe a TVP7002 device 993 * @c: ptr to i2c_client struct 994 * @id: ptr to i2c_device_id struct 995 * 996 * Initialize the TVP7002 device 997 * Returns zero when successful, -EINVAL if register read fails or 998 * -EIO if i2c access is not available. 999 */ 1000 static int tvp7002_probe(struct i2c_client *c, const struct i2c_device_id *id) 1001 { 1002 struct tvp7002_config *pdata = tvp7002_get_pdata(c); 1003 struct v4l2_subdev *sd; 1004 struct tvp7002 *device; 1005 struct v4l2_dv_timings timings; 1006 int polarity_a; 1007 int polarity_b; 1008 u8 revision; 1009 int error; 1010 1011 if (pdata == NULL) { 1012 dev_err(&c->dev, "No platform data\n"); 1013 return -EINVAL; 1014 } 1015 1016 /* Check if the adapter supports the needed features */ 1017 if (!i2c_check_functionality(c->adapter, 1018 I2C_FUNC_SMBUS_READ_BYTE | I2C_FUNC_SMBUS_WRITE_BYTE_DATA)) 1019 return -EIO; 1020 1021 device = devm_kzalloc(&c->dev, sizeof(struct tvp7002), GFP_KERNEL); 1022 1023 if (!device) 1024 return -ENOMEM; 1025 1026 sd = &device->sd; 1027 device->pdata = pdata; 1028 device->current_timings = tvp7002_timings; 1029 1030 /* Tell v4l2 the device is ready */ 1031 v4l2_i2c_subdev_init(sd, c, &tvp7002_ops); 1032 v4l_info(c, "tvp7002 found @ 0x%02x (%s)\n", 1033 c->addr, c->adapter->name); 1034 1035 error = tvp7002_read(sd, TVP7002_CHIP_REV, &revision); 1036 if (error < 0) 1037 return error; 1038 1039 /* Get revision number */ 1040 v4l2_info(sd, "Rev. %02x detected.\n", revision); 1041 if (revision != 0x02) 1042 v4l2_info(sd, "Unknown revision detected.\n"); 1043 1044 /* Initializes TVP7002 to its default values */ 1045 error = tvp7002_write_inittab(sd, tvp7002_init_default); 1046 1047 if (error < 0) 1048 return error; 1049 1050 /* Set polarity information after registers have been set */ 1051 polarity_a = 0x20 | device->pdata->hs_polarity << 5 1052 | device->pdata->vs_polarity << 2; 1053 error = tvp7002_write(sd, TVP7002_SYNC_CTL_1, polarity_a); 1054 if (error < 0) 1055 return error; 1056 1057 polarity_b = 0x01 | device->pdata->fid_polarity << 2 1058 | device->pdata->sog_polarity << 1 1059 | device->pdata->clk_polarity; 1060 error = tvp7002_write(sd, TVP7002_MISC_CTL_3, polarity_b); 1061 if (error < 0) 1062 return error; 1063 1064 /* Set registers according to default video mode */ 1065 timings = device->current_timings->timings; 1066 error = tvp7002_s_dv_timings(sd, &timings); 1067 1068 #if defined(CONFIG_MEDIA_CONTROLLER) 1069 device->pad.flags = MEDIA_PAD_FL_SOURCE; 1070 device->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1071 device->sd.entity.flags |= MEDIA_ENT_T_V4L2_SUBDEV_DECODER; 1072 1073 error = media_entity_init(&device->sd.entity, 1, &device->pad, 0); 1074 if (error < 0) 1075 return error; 1076 #endif 1077 1078 v4l2_ctrl_handler_init(&device->hdl, 1); 1079 v4l2_ctrl_new_std(&device->hdl, &tvp7002_ctrl_ops, 1080 V4L2_CID_GAIN, 0, 255, 1, 0); 1081 sd->ctrl_handler = &device->hdl; 1082 if (device->hdl.error) { 1083 error = device->hdl.error; 1084 goto error; 1085 } 1086 v4l2_ctrl_handler_setup(&device->hdl); 1087 1088 error = v4l2_async_register_subdev(&device->sd); 1089 if (error) 1090 goto error; 1091 1092 return 0; 1093 1094 error: 1095 v4l2_ctrl_handler_free(&device->hdl); 1096 #if defined(CONFIG_MEDIA_CONTROLLER) 1097 media_entity_cleanup(&device->sd.entity); 1098 #endif 1099 return error; 1100 } 1101 1102 /* 1103 * tvp7002_remove - Remove TVP7002 device support 1104 * @c: ptr to i2c_client struct 1105 * 1106 * Reset the TVP7002 device 1107 * Returns zero. 1108 */ 1109 static int tvp7002_remove(struct i2c_client *c) 1110 { 1111 struct v4l2_subdev *sd = i2c_get_clientdata(c); 1112 struct tvp7002 *device = to_tvp7002(sd); 1113 1114 v4l2_dbg(1, debug, sd, "Removing tvp7002 adapter" 1115 "on address 0x%x\n", c->addr); 1116 v4l2_async_unregister_subdev(&device->sd); 1117 #if defined(CONFIG_MEDIA_CONTROLLER) 1118 media_entity_cleanup(&device->sd.entity); 1119 #endif 1120 v4l2_device_unregister_subdev(sd); 1121 v4l2_ctrl_handler_free(&device->hdl); 1122 return 0; 1123 } 1124 1125 /* I2C Device ID table */ 1126 static const struct i2c_device_id tvp7002_id[] = { 1127 { "tvp7002", 0 }, 1128 { } 1129 }; 1130 MODULE_DEVICE_TABLE(i2c, tvp7002_id); 1131 1132 #if IS_ENABLED(CONFIG_OF) 1133 static const struct of_device_id tvp7002_of_match[] = { 1134 { .compatible = "ti,tvp7002", }, 1135 { /* sentinel */ }, 1136 }; 1137 MODULE_DEVICE_TABLE(of, tvp7002_of_match); 1138 #endif 1139 1140 /* I2C driver data */ 1141 static struct i2c_driver tvp7002_driver = { 1142 .driver = { 1143 .of_match_table = of_match_ptr(tvp7002_of_match), 1144 .owner = THIS_MODULE, 1145 .name = TVP7002_MODULE_NAME, 1146 }, 1147 .probe = tvp7002_probe, 1148 .remove = tvp7002_remove, 1149 .id_table = tvp7002_id, 1150 }; 1151 1152 module_i2c_driver(tvp7002_driver); 1153