1 /* 2 * ths8200 - Texas Instruments THS8200 video encoder driver 3 * 4 * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. 5 * 6 * This program is free software; you may redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; version 2 of the License. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation version 2. 13 * 14 * This program is distributed .as is. WITHOUT ANY WARRANTY of any 15 * kind, whether express or implied; without even the implied warranty 16 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 */ 19 20 #include <linux/i2c.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/v4l2-dv-timings.h> 24 25 #include <media/v4l2-dv-timings.h> 26 #include <media/v4l2-async.h> 27 #include <media/v4l2-device.h> 28 29 #include "ths8200_regs.h" 30 31 static int debug; 32 module_param(debug, int, 0644); 33 MODULE_PARM_DESC(debug, "debug level (0-2)"); 34 35 MODULE_DESCRIPTION("Texas Instruments THS8200 video encoder driver"); 36 MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>"); 37 MODULE_AUTHOR("Martin Bugge <martin.bugge@cisco.com>"); 38 MODULE_LICENSE("GPL v2"); 39 40 struct ths8200_state { 41 struct v4l2_subdev sd; 42 uint8_t chip_version; 43 /* Is the ths8200 powered on? */ 44 bool power_on; 45 struct v4l2_dv_timings dv_timings; 46 }; 47 48 static const struct v4l2_dv_timings_cap ths8200_timings_cap = { 49 .type = V4L2_DV_BT_656_1120, 50 /* keep this initialization for compatibility with GCC < 4.4.6 */ 51 .reserved = { 0 }, 52 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1080, 25000000, 148500000, 53 V4L2_DV_BT_STD_CEA861, V4L2_DV_BT_CAP_PROGRESSIVE) 54 }; 55 56 static inline struct ths8200_state *to_state(struct v4l2_subdev *sd) 57 { 58 return container_of(sd, struct ths8200_state, sd); 59 } 60 61 static inline unsigned hblanking(const struct v4l2_bt_timings *t) 62 { 63 return V4L2_DV_BT_BLANKING_WIDTH(t); 64 } 65 66 static inline unsigned htotal(const struct v4l2_bt_timings *t) 67 { 68 return V4L2_DV_BT_FRAME_WIDTH(t); 69 } 70 71 static inline unsigned vblanking(const struct v4l2_bt_timings *t) 72 { 73 return V4L2_DV_BT_BLANKING_HEIGHT(t); 74 } 75 76 static inline unsigned vtotal(const struct v4l2_bt_timings *t) 77 { 78 return V4L2_DV_BT_FRAME_HEIGHT(t); 79 } 80 81 static int ths8200_read(struct v4l2_subdev *sd, u8 reg) 82 { 83 struct i2c_client *client = v4l2_get_subdevdata(sd); 84 85 return i2c_smbus_read_byte_data(client, reg); 86 } 87 88 static int ths8200_write(struct v4l2_subdev *sd, u8 reg, u8 val) 89 { 90 struct i2c_client *client = v4l2_get_subdevdata(sd); 91 int ret; 92 int i; 93 94 for (i = 0; i < 3; i++) { 95 ret = i2c_smbus_write_byte_data(client, reg, val); 96 if (ret == 0) 97 return 0; 98 } 99 v4l2_err(sd, "I2C Write Problem\n"); 100 return ret; 101 } 102 103 /* To set specific bits in the register, a clear-mask is given (to be AND-ed), 104 * and then the value-mask (to be OR-ed). 105 */ 106 static inline void 107 ths8200_write_and_or(struct v4l2_subdev *sd, u8 reg, 108 uint8_t clr_mask, uint8_t val_mask) 109 { 110 ths8200_write(sd, reg, (ths8200_read(sd, reg) & clr_mask) | val_mask); 111 } 112 113 #ifdef CONFIG_VIDEO_ADV_DEBUG 114 115 static int ths8200_g_register(struct v4l2_subdev *sd, 116 struct v4l2_dbg_register *reg) 117 { 118 reg->val = ths8200_read(sd, reg->reg & 0xff); 119 reg->size = 1; 120 121 return 0; 122 } 123 124 static int ths8200_s_register(struct v4l2_subdev *sd, 125 const struct v4l2_dbg_register *reg) 126 { 127 ths8200_write(sd, reg->reg & 0xff, reg->val & 0xff); 128 129 return 0; 130 } 131 #endif 132 133 static int ths8200_log_status(struct v4l2_subdev *sd) 134 { 135 struct ths8200_state *state = to_state(sd); 136 uint8_t reg_03 = ths8200_read(sd, THS8200_CHIP_CTL); 137 138 v4l2_info(sd, "----- Chip status -----\n"); 139 v4l2_info(sd, "version: %u\n", state->chip_version); 140 v4l2_info(sd, "power: %s\n", (reg_03 & 0x0c) ? "off" : "on"); 141 v4l2_info(sd, "reset: %s\n", (reg_03 & 0x01) ? "off" : "on"); 142 v4l2_info(sd, "test pattern: %s\n", 143 (reg_03 & 0x20) ? "enabled" : "disabled"); 144 v4l2_info(sd, "format: %ux%u\n", 145 ths8200_read(sd, THS8200_DTG2_PIXEL_CNT_MSB) * 256 + 146 ths8200_read(sd, THS8200_DTG2_PIXEL_CNT_LSB), 147 (ths8200_read(sd, THS8200_DTG2_LINE_CNT_MSB) & 0x07) * 256 + 148 ths8200_read(sd, THS8200_DTG2_LINE_CNT_LSB)); 149 v4l2_print_dv_timings(sd->name, "Configured format:", 150 &state->dv_timings, true); 151 return 0; 152 } 153 154 /* Power up/down ths8200 */ 155 static int ths8200_s_power(struct v4l2_subdev *sd, int on) 156 { 157 struct ths8200_state *state = to_state(sd); 158 159 v4l2_dbg(1, debug, sd, "%s: power %s\n", __func__, on ? "on" : "off"); 160 161 state->power_on = on; 162 163 /* Power up/down - leave in reset state until input video is present */ 164 ths8200_write_and_or(sd, THS8200_CHIP_CTL, 0xf2, (on ? 0x00 : 0x0c)); 165 166 return 0; 167 } 168 169 static const struct v4l2_subdev_core_ops ths8200_core_ops = { 170 .log_status = ths8200_log_status, 171 .s_power = ths8200_s_power, 172 #ifdef CONFIG_VIDEO_ADV_DEBUG 173 .g_register = ths8200_g_register, 174 .s_register = ths8200_s_register, 175 #endif 176 }; 177 178 /* ----------------------------------------------------------------------------- 179 * V4L2 subdev video operations 180 */ 181 182 static int ths8200_s_stream(struct v4l2_subdev *sd, int enable) 183 { 184 struct ths8200_state *state = to_state(sd); 185 186 if (enable && !state->power_on) 187 ths8200_s_power(sd, true); 188 189 ths8200_write_and_or(sd, THS8200_CHIP_CTL, 0xfe, 190 (enable ? 0x01 : 0x00)); 191 192 v4l2_dbg(1, debug, sd, "%s: %sable\n", 193 __func__, (enable ? "en" : "dis")); 194 195 return 0; 196 } 197 198 static void ths8200_core_init(struct v4l2_subdev *sd) 199 { 200 /* setup clocks */ 201 ths8200_write_and_or(sd, THS8200_CHIP_CTL, 0x3f, 0xc0); 202 203 /**** Data path control (DATA) ****/ 204 /* Set FSADJ 700 mV, 205 * bypass 422-444 interpolation, 206 * input format 30 bit RGB444 207 */ 208 ths8200_write(sd, THS8200_DATA_CNTL, 0x70); 209 210 /* DTG Mode (Video blocked during blanking 211 * VESA slave 212 */ 213 ths8200_write(sd, THS8200_DTG1_MODE, 0x87); 214 215 /**** Display Timing Generator Control, Part 1 (DTG1). ****/ 216 217 /* Disable embedded syncs on the output by setting 218 * the amplitude to zero for all channels. 219 */ 220 ths8200_write(sd, THS8200_DTG1_Y_SYNC_MSB, 0x2a); 221 ths8200_write(sd, THS8200_DTG1_CBCR_SYNC_MSB, 0x2a); 222 } 223 224 static void ths8200_setup(struct v4l2_subdev *sd, struct v4l2_bt_timings *bt) 225 { 226 uint8_t polarity = 0; 227 uint16_t line_start_active_video = (bt->vsync + bt->vbackporch); 228 uint16_t line_start_front_porch = (vtotal(bt) - bt->vfrontporch); 229 230 /*** System ****/ 231 /* Set chip in reset while it is configured */ 232 ths8200_s_stream(sd, false); 233 234 /* configure video output timings */ 235 ths8200_write(sd, THS8200_DTG1_SPEC_A, bt->hsync); 236 ths8200_write(sd, THS8200_DTG1_SPEC_B, bt->hfrontporch); 237 238 /* Zero for progressive scan formats.*/ 239 if (!bt->interlaced) 240 ths8200_write(sd, THS8200_DTG1_SPEC_C, 0x00); 241 242 /* Distance from leading edge of h sync to start of active video. 243 * MSB in 0x2b 244 */ 245 ths8200_write(sd, THS8200_DTG1_SPEC_D_LSB, 246 (bt->hbackporch + bt->hsync) & 0xff); 247 /* Zero for SDTV-mode. MSB in 0x2b */ 248 ths8200_write(sd, THS8200_DTG1_SPEC_E_LSB, 0x00); 249 /* 250 * MSB for dtg1_spec(d/e/h). See comment for 251 * corresponding LSB registers. 252 */ 253 ths8200_write(sd, THS8200_DTG1_SPEC_DEH_MSB, 254 ((bt->hbackporch + bt->hsync) & 0x100) >> 1); 255 256 /* h front porch */ 257 ths8200_write(sd, THS8200_DTG1_SPEC_K_LSB, (bt->hfrontporch) & 0xff); 258 ths8200_write(sd, THS8200_DTG1_SPEC_K_MSB, 259 ((bt->hfrontporch) & 0x700) >> 8); 260 261 /* Half the line length. Used to calculate SDTV line types. */ 262 ths8200_write(sd, THS8200_DTG1_SPEC_G_LSB, (htotal(bt)/2) & 0xff); 263 ths8200_write(sd, THS8200_DTG1_SPEC_G_MSB, 264 ((htotal(bt)/2) >> 8) & 0x0f); 265 266 /* Total pixels per line (ex. 720p: 1650) */ 267 ths8200_write(sd, THS8200_DTG1_TOT_PIXELS_MSB, htotal(bt) >> 8); 268 ths8200_write(sd, THS8200_DTG1_TOT_PIXELS_LSB, htotal(bt) & 0xff); 269 270 /* Frame height and field height */ 271 /* Field height should be programmed higher than frame_size for 272 * progressive scan formats 273 */ 274 ths8200_write(sd, THS8200_DTG1_FRAME_FIELD_SZ_MSB, 275 ((vtotal(bt) >> 4) & 0xf0) + 0x7); 276 ths8200_write(sd, THS8200_DTG1_FRAME_SZ_LSB, vtotal(bt) & 0xff); 277 278 /* Should be programmed higher than frame_size 279 * for progressive formats 280 */ 281 if (!bt->interlaced) 282 ths8200_write(sd, THS8200_DTG1_FIELD_SZ_LSB, 0xff); 283 284 /**** Display Timing Generator Control, Part 2 (DTG2). ****/ 285 /* Set breakpoint line numbers and types 286 * THS8200 generates line types with different properties. A line type 287 * that sets all the RGB-outputs to zero is used in the blanking areas, 288 * while a line type that enable the RGB-outputs is used in active video 289 * area. The line numbers for start of active video, start of front 290 * porch and after the last line in the frame must be set with the 291 * corresponding line types. 292 * 293 * Line types: 294 * 0x9 - Full normal sync pulse: Blocks data when dtg1_pass is off. 295 * Used in blanking area. 296 * 0x0 - Active video: Video data is always passed. Used in active 297 * video area. 298 */ 299 ths8200_write_and_or(sd, THS8200_DTG2_BP1_2_MSB, 0x88, 300 ((line_start_active_video >> 4) & 0x70) + 301 ((line_start_front_porch >> 8) & 0x07)); 302 ths8200_write(sd, THS8200_DTG2_BP3_4_MSB, ((vtotal(bt)) >> 4) & 0x70); 303 ths8200_write(sd, THS8200_DTG2_BP1_LSB, line_start_active_video & 0xff); 304 ths8200_write(sd, THS8200_DTG2_BP2_LSB, line_start_front_porch & 0xff); 305 ths8200_write(sd, THS8200_DTG2_BP3_LSB, (vtotal(bt)) & 0xff); 306 307 /* line types */ 308 ths8200_write(sd, THS8200_DTG2_LINETYPE1, 0x90); 309 ths8200_write(sd, THS8200_DTG2_LINETYPE2, 0x90); 310 311 /* h sync width transmitted */ 312 ths8200_write(sd, THS8200_DTG2_HLENGTH_LSB, bt->hsync & 0xff); 313 ths8200_write_and_or(sd, THS8200_DTG2_HLENGTH_LSB_HDLY_MSB, 0x3f, 314 (bt->hsync >> 2) & 0xc0); 315 316 /* The pixel value h sync is asserted on */ 317 ths8200_write_and_or(sd, THS8200_DTG2_HLENGTH_LSB_HDLY_MSB, 0xe0, 318 (htotal(bt) >> 8) & 0x1f); 319 ths8200_write(sd, THS8200_DTG2_HLENGTH_HDLY_LSB, htotal(bt)); 320 321 /* v sync width transmitted */ 322 ths8200_write(sd, THS8200_DTG2_VLENGTH1_LSB, (bt->vsync) & 0xff); 323 ths8200_write_and_or(sd, THS8200_DTG2_VLENGTH1_MSB_VDLY1_MSB, 0x3f, 324 ((bt->vsync) >> 2) & 0xc0); 325 326 /* The pixel value v sync is asserted on */ 327 ths8200_write_and_or(sd, THS8200_DTG2_VLENGTH1_MSB_VDLY1_MSB, 0xf8, 328 (vtotal(bt)>>8) & 0x7); 329 ths8200_write(sd, THS8200_DTG2_VDLY1_LSB, vtotal(bt)); 330 331 /* For progressive video vlength2 must be set to all 0 and vdly2 must 332 * be set to all 1. 333 */ 334 ths8200_write(sd, THS8200_DTG2_VLENGTH2_LSB, 0x00); 335 ths8200_write(sd, THS8200_DTG2_VLENGTH2_MSB_VDLY2_MSB, 0x07); 336 ths8200_write(sd, THS8200_DTG2_VDLY2_LSB, 0xff); 337 338 /* Internal delay factors to synchronize the sync pulses and the data */ 339 /* Experimental values delays (hor 4, ver 1) */ 340 ths8200_write(sd, THS8200_DTG2_HS_IN_DLY_MSB, (htotal(bt)>>8) & 0x1f); 341 ths8200_write(sd, THS8200_DTG2_HS_IN_DLY_LSB, (htotal(bt) - 4) & 0xff); 342 ths8200_write(sd, THS8200_DTG2_VS_IN_DLY_MSB, 0); 343 ths8200_write(sd, THS8200_DTG2_VS_IN_DLY_LSB, 1); 344 345 /* Polarity of received and transmitted sync signals */ 346 if (bt->polarities & V4L2_DV_HSYNC_POS_POL) { 347 polarity |= 0x01; /* HS_IN */ 348 polarity |= 0x08; /* HS_OUT */ 349 } 350 if (bt->polarities & V4L2_DV_VSYNC_POS_POL) { 351 polarity |= 0x02; /* VS_IN */ 352 polarity |= 0x10; /* VS_OUT */ 353 } 354 355 /* RGB mode, no embedded timings */ 356 /* Timing of video input bus is derived from HS, VS, and FID dedicated 357 * inputs 358 */ 359 ths8200_write(sd, THS8200_DTG2_CNTL, 0x47 | polarity); 360 361 /* leave reset */ 362 ths8200_s_stream(sd, true); 363 364 v4l2_dbg(1, debug, sd, "%s: frame %dx%d, polarity %d\n" 365 "horizontal: front porch %d, back porch %d, sync %d\n" 366 "vertical: sync %d\n", __func__, htotal(bt), vtotal(bt), 367 polarity, bt->hfrontporch, bt->hbackporch, 368 bt->hsync, bt->vsync); 369 } 370 371 static int ths8200_s_dv_timings(struct v4l2_subdev *sd, 372 struct v4l2_dv_timings *timings) 373 { 374 struct ths8200_state *state = to_state(sd); 375 376 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 377 378 if (!v4l2_valid_dv_timings(timings, &ths8200_timings_cap, 379 NULL, NULL)) 380 return -EINVAL; 381 382 if (!v4l2_find_dv_timings_cap(timings, &ths8200_timings_cap, 10, 383 NULL, NULL)) { 384 v4l2_dbg(1, debug, sd, "Unsupported format\n"); 385 return -EINVAL; 386 } 387 388 timings->bt.flags &= ~V4L2_DV_FL_REDUCED_FPS; 389 390 /* save timings */ 391 state->dv_timings = *timings; 392 393 ths8200_setup(sd, &timings->bt); 394 395 return 0; 396 } 397 398 static int ths8200_g_dv_timings(struct v4l2_subdev *sd, 399 struct v4l2_dv_timings *timings) 400 { 401 struct ths8200_state *state = to_state(sd); 402 403 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 404 405 *timings = state->dv_timings; 406 407 return 0; 408 } 409 410 static int ths8200_enum_dv_timings(struct v4l2_subdev *sd, 411 struct v4l2_enum_dv_timings *timings) 412 { 413 return v4l2_enum_dv_timings_cap(timings, &ths8200_timings_cap, 414 NULL, NULL); 415 } 416 417 static int ths8200_dv_timings_cap(struct v4l2_subdev *sd, 418 struct v4l2_dv_timings_cap *cap) 419 { 420 *cap = ths8200_timings_cap; 421 return 0; 422 } 423 424 /* Specific video subsystem operation handlers */ 425 static const struct v4l2_subdev_video_ops ths8200_video_ops = { 426 .s_stream = ths8200_s_stream, 427 .s_dv_timings = ths8200_s_dv_timings, 428 .g_dv_timings = ths8200_g_dv_timings, 429 .enum_dv_timings = ths8200_enum_dv_timings, 430 .dv_timings_cap = ths8200_dv_timings_cap, 431 }; 432 433 /* V4L2 top level operation handlers */ 434 static const struct v4l2_subdev_ops ths8200_ops = { 435 .core = &ths8200_core_ops, 436 .video = &ths8200_video_ops, 437 }; 438 439 static int ths8200_probe(struct i2c_client *client, 440 const struct i2c_device_id *id) 441 { 442 struct ths8200_state *state; 443 struct v4l2_subdev *sd; 444 int error; 445 446 /* Check if the adapter supports the needed features */ 447 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 448 return -EIO; 449 450 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); 451 if (!state) 452 return -ENOMEM; 453 454 sd = &state->sd; 455 v4l2_i2c_subdev_init(sd, client, &ths8200_ops); 456 457 state->chip_version = ths8200_read(sd, THS8200_VERSION); 458 v4l2_dbg(1, debug, sd, "chip version 0x%x\n", state->chip_version); 459 460 ths8200_core_init(sd); 461 462 error = v4l2_async_register_subdev(&state->sd); 463 if (error) 464 return error; 465 466 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, 467 client->addr << 1, client->adapter->name); 468 469 return 0; 470 } 471 472 static int ths8200_remove(struct i2c_client *client) 473 { 474 struct v4l2_subdev *sd = i2c_get_clientdata(client); 475 struct ths8200_state *decoder = to_state(sd); 476 477 v4l2_dbg(1, debug, sd, "%s removed @ 0x%x (%s)\n", client->name, 478 client->addr << 1, client->adapter->name); 479 480 ths8200_s_power(sd, false); 481 v4l2_async_unregister_subdev(&decoder->sd); 482 v4l2_device_unregister_subdev(sd); 483 484 return 0; 485 } 486 487 static struct i2c_device_id ths8200_id[] = { 488 { "ths8200", 0 }, 489 {}, 490 }; 491 MODULE_DEVICE_TABLE(i2c, ths8200_id); 492 493 #if IS_ENABLED(CONFIG_OF) 494 static const struct of_device_id ths8200_of_match[] = { 495 { .compatible = "ti,ths8200", }, 496 { /* sentinel */ }, 497 }; 498 MODULE_DEVICE_TABLE(of, ths8200_of_match); 499 #endif 500 501 static struct i2c_driver ths8200_driver = { 502 .driver = { 503 .owner = THIS_MODULE, 504 .name = "ths8200", 505 .of_match_table = of_match_ptr(ths8200_of_match), 506 }, 507 .probe = ths8200_probe, 508 .remove = ths8200_remove, 509 .id_table = ths8200_id, 510 }; 511 512 module_i2c_driver(ths8200_driver); 513