1 /* 2 * ths8200 - Texas Instruments THS8200 video encoder driver 3 * 4 * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. 5 * 6 * This program is free software; you may redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; version 2 of the License. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation version 2. 13 * 14 * This program is distributed .as is. WITHOUT ANY WARRANTY of any 15 * kind, whether express or implied; without even the implied warranty 16 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 */ 19 20 #include <linux/i2c.h> 21 #include <linux/module.h> 22 #include <linux/v4l2-dv-timings.h> 23 24 #include <media/v4l2-device.h> 25 26 #include "ths8200_regs.h" 27 28 static int debug; 29 module_param(debug, int, 0644); 30 MODULE_PARM_DESC(debug, "debug level (0-2)"); 31 32 MODULE_DESCRIPTION("Texas Instruments THS8200 video encoder driver"); 33 MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>"); 34 MODULE_AUTHOR("Martin Bugge <martin.bugge@cisco.com>"); 35 MODULE_LICENSE("GPL v2"); 36 37 struct ths8200_state { 38 struct v4l2_subdev sd; 39 uint8_t chip_version; 40 /* Is the ths8200 powered on? */ 41 bool power_on; 42 struct v4l2_dv_timings dv_timings; 43 }; 44 45 static const struct v4l2_dv_timings ths8200_timings[] = { 46 V4L2_DV_BT_CEA_720X480P59_94, 47 V4L2_DV_BT_CEA_1280X720P24, 48 V4L2_DV_BT_CEA_1280X720P25, 49 V4L2_DV_BT_CEA_1280X720P30, 50 V4L2_DV_BT_CEA_1280X720P50, 51 V4L2_DV_BT_CEA_1280X720P60, 52 V4L2_DV_BT_CEA_1920X1080P24, 53 V4L2_DV_BT_CEA_1920X1080P25, 54 V4L2_DV_BT_CEA_1920X1080P30, 55 V4L2_DV_BT_CEA_1920X1080P50, 56 V4L2_DV_BT_CEA_1920X1080P60, 57 }; 58 59 static inline struct ths8200_state *to_state(struct v4l2_subdev *sd) 60 { 61 return container_of(sd, struct ths8200_state, sd); 62 } 63 64 static inline unsigned hblanking(const struct v4l2_bt_timings *t) 65 { 66 return t->hfrontporch + t->hsync + t->hbackporch; 67 } 68 69 static inline unsigned htotal(const struct v4l2_bt_timings *t) 70 { 71 return t->width + t->hfrontporch + t->hsync + t->hbackporch; 72 } 73 74 static inline unsigned vblanking(const struct v4l2_bt_timings *t) 75 { 76 return t->vfrontporch + t->vsync + t->vbackporch; 77 } 78 79 static inline unsigned vtotal(const struct v4l2_bt_timings *t) 80 { 81 return t->height + t->vfrontporch + t->vsync + t->vbackporch; 82 } 83 84 static int ths8200_read(struct v4l2_subdev *sd, u8 reg) 85 { 86 struct i2c_client *client = v4l2_get_subdevdata(sd); 87 88 return i2c_smbus_read_byte_data(client, reg); 89 } 90 91 static int ths8200_write(struct v4l2_subdev *sd, u8 reg, u8 val) 92 { 93 struct i2c_client *client = v4l2_get_subdevdata(sd); 94 int ret; 95 int i; 96 97 for (i = 0; i < 3; i++) { 98 ret = i2c_smbus_write_byte_data(client, reg, val); 99 if (ret == 0) 100 return 0; 101 } 102 v4l2_err(sd, "I2C Write Problem\n"); 103 return ret; 104 } 105 106 /* To set specific bits in the register, a clear-mask is given (to be AND-ed), 107 * and then the value-mask (to be OR-ed). 108 */ 109 static inline void 110 ths8200_write_and_or(struct v4l2_subdev *sd, u8 reg, 111 uint8_t clr_mask, uint8_t val_mask) 112 { 113 ths8200_write(sd, reg, (ths8200_read(sd, reg) & clr_mask) | val_mask); 114 } 115 116 #ifdef CONFIG_VIDEO_ADV_DEBUG 117 118 static int ths8200_g_register(struct v4l2_subdev *sd, 119 struct v4l2_dbg_register *reg) 120 { 121 reg->val = ths8200_read(sd, reg->reg & 0xff); 122 reg->size = 1; 123 124 return 0; 125 } 126 127 static int ths8200_s_register(struct v4l2_subdev *sd, 128 const struct v4l2_dbg_register *reg) 129 { 130 ths8200_write(sd, reg->reg & 0xff, reg->val & 0xff); 131 132 return 0; 133 } 134 #endif 135 136 static void ths8200_print_timings(struct v4l2_subdev *sd, 137 struct v4l2_dv_timings *timings, 138 const char *txt, bool detailed) 139 { 140 struct v4l2_bt_timings *bt = &timings->bt; 141 u32 htot, vtot; 142 143 if (timings->type != V4L2_DV_BT_656_1120) 144 return; 145 146 htot = htotal(bt); 147 vtot = vtotal(bt); 148 149 v4l2_info(sd, "%s %dx%d%s%d (%dx%d)", 150 txt, bt->width, bt->height, bt->interlaced ? "i" : "p", 151 (htot * vtot) > 0 ? ((u32)bt->pixelclock / (htot * vtot)) : 0, 152 htot, vtot); 153 154 if (detailed) { 155 v4l2_info(sd, " horizontal: fp = %d, %ssync = %d, bp = %d\n", 156 bt->hfrontporch, 157 (bt->polarities & V4L2_DV_HSYNC_POS_POL) ? "+" : "-", 158 bt->hsync, bt->hbackporch); 159 v4l2_info(sd, " vertical: fp = %d, %ssync = %d, bp = %d\n", 160 bt->vfrontporch, 161 (bt->polarities & V4L2_DV_VSYNC_POS_POL) ? "+" : "-", 162 bt->vsync, bt->vbackporch); 163 v4l2_info(sd, 164 " pixelclock: %lld, flags: 0x%x, standards: 0x%x\n", 165 bt->pixelclock, bt->flags, bt->standards); 166 } 167 } 168 169 static int ths8200_log_status(struct v4l2_subdev *sd) 170 { 171 struct ths8200_state *state = to_state(sd); 172 uint8_t reg_03 = ths8200_read(sd, THS8200_CHIP_CTL); 173 174 v4l2_info(sd, "----- Chip status -----\n"); 175 v4l2_info(sd, "version: %u\n", state->chip_version); 176 v4l2_info(sd, "power: %s\n", (reg_03 & 0x0c) ? "off" : "on"); 177 v4l2_info(sd, "reset: %s\n", (reg_03 & 0x01) ? "off" : "on"); 178 v4l2_info(sd, "test pattern: %s\n", 179 (reg_03 & 0x20) ? "enabled" : "disabled"); 180 v4l2_info(sd, "format: %ux%u\n", 181 ths8200_read(sd, THS8200_DTG2_PIXEL_CNT_MSB) * 256 + 182 ths8200_read(sd, THS8200_DTG2_PIXEL_CNT_LSB), 183 (ths8200_read(sd, THS8200_DTG2_LINE_CNT_MSB) & 0x07) * 256 + 184 ths8200_read(sd, THS8200_DTG2_LINE_CNT_LSB)); 185 ths8200_print_timings(sd, &state->dv_timings, 186 "Configured format:", true); 187 188 return 0; 189 } 190 191 /* Power up/down ths8200 */ 192 static int ths8200_s_power(struct v4l2_subdev *sd, int on) 193 { 194 struct ths8200_state *state = to_state(sd); 195 196 v4l2_dbg(1, debug, sd, "%s: power %s\n", __func__, on ? "on" : "off"); 197 198 state->power_on = on; 199 200 /* Power up/down - leave in reset state until input video is present */ 201 ths8200_write_and_or(sd, THS8200_CHIP_CTL, 0xf2, (on ? 0x00 : 0x0c)); 202 203 return 0; 204 } 205 206 static const struct v4l2_subdev_core_ops ths8200_core_ops = { 207 .log_status = ths8200_log_status, 208 .s_power = ths8200_s_power, 209 #ifdef CONFIG_VIDEO_ADV_DEBUG 210 .g_register = ths8200_g_register, 211 .s_register = ths8200_s_register, 212 #endif 213 }; 214 215 /* ----------------------------------------------------------------------------- 216 * V4L2 subdev video operations 217 */ 218 219 static int ths8200_s_stream(struct v4l2_subdev *sd, int enable) 220 { 221 struct ths8200_state *state = to_state(sd); 222 223 if (enable && !state->power_on) 224 ths8200_s_power(sd, true); 225 226 ths8200_write_and_or(sd, THS8200_CHIP_CTL, 0xfe, 227 (enable ? 0x01 : 0x00)); 228 229 v4l2_dbg(1, debug, sd, "%s: %sable\n", 230 __func__, (enable ? "en" : "dis")); 231 232 return 0; 233 } 234 235 static void ths8200_core_init(struct v4l2_subdev *sd) 236 { 237 /* setup clocks */ 238 ths8200_write_and_or(sd, THS8200_CHIP_CTL, 0x3f, 0xc0); 239 240 /**** Data path control (DATA) ****/ 241 /* Set FSADJ 700 mV, 242 * bypass 422-444 interpolation, 243 * input format 30 bit RGB444 244 */ 245 ths8200_write(sd, THS8200_DATA_CNTL, 0x70); 246 247 /* DTG Mode (Video blocked during blanking 248 * VESA slave 249 */ 250 ths8200_write(sd, THS8200_DTG1_MODE, 0x87); 251 252 /**** Display Timing Generator Control, Part 1 (DTG1). ****/ 253 254 /* Disable embedded syncs on the output by setting 255 * the amplitude to zero for all channels. 256 */ 257 ths8200_write(sd, THS8200_DTG1_Y_SYNC_MSB, 0x2a); 258 ths8200_write(sd, THS8200_DTG1_CBCR_SYNC_MSB, 0x2a); 259 } 260 261 static void ths8200_setup(struct v4l2_subdev *sd, struct v4l2_bt_timings *bt) 262 { 263 uint8_t polarity = 0; 264 uint16_t line_start_active_video = (bt->vsync + bt->vbackporch); 265 uint16_t line_start_front_porch = (vtotal(bt) - bt->vfrontporch); 266 267 /*** System ****/ 268 /* Set chip in reset while it is configured */ 269 ths8200_s_stream(sd, false); 270 271 /* configure video output timings */ 272 ths8200_write(sd, THS8200_DTG1_SPEC_A, bt->hsync); 273 ths8200_write(sd, THS8200_DTG1_SPEC_B, bt->hfrontporch); 274 275 /* Zero for progressive scan formats.*/ 276 if (!bt->interlaced) 277 ths8200_write(sd, THS8200_DTG1_SPEC_C, 0x00); 278 279 /* Distance from leading edge of h sync to start of active video. 280 * MSB in 0x2b 281 */ 282 ths8200_write(sd, THS8200_DTG1_SPEC_D_LSB, 283 (bt->hbackporch + bt->hsync) & 0xff); 284 /* Zero for SDTV-mode. MSB in 0x2b */ 285 ths8200_write(sd, THS8200_DTG1_SPEC_E_LSB, 0x00); 286 /* 287 * MSB for dtg1_spec(d/e/h). See comment for 288 * corresponding LSB registers. 289 */ 290 ths8200_write(sd, THS8200_DTG1_SPEC_DEH_MSB, 291 ((bt->hbackporch + bt->hsync) & 0x100) >> 1); 292 293 /* h front porch */ 294 ths8200_write(sd, THS8200_DTG1_SPEC_K_LSB, (bt->hfrontporch) & 0xff); 295 ths8200_write(sd, THS8200_DTG1_SPEC_K_MSB, 296 ((bt->hfrontporch) & 0x700) >> 8); 297 298 /* Half the line length. Used to calculate SDTV line types. */ 299 ths8200_write(sd, THS8200_DTG1_SPEC_G_LSB, (htotal(bt)/2) & 0xff); 300 ths8200_write(sd, THS8200_DTG1_SPEC_G_MSB, 301 ((htotal(bt)/2) >> 8) & 0x0f); 302 303 /* Total pixels per line (ex. 720p: 1650) */ 304 ths8200_write(sd, THS8200_DTG1_TOT_PIXELS_MSB, htotal(bt) >> 8); 305 ths8200_write(sd, THS8200_DTG1_TOT_PIXELS_LSB, htotal(bt) & 0xff); 306 307 /* Frame height and field height */ 308 /* Field height should be programmed higher than frame_size for 309 * progressive scan formats 310 */ 311 ths8200_write(sd, THS8200_DTG1_FRAME_FIELD_SZ_MSB, 312 ((vtotal(bt) >> 4) & 0xf0) + 0x7); 313 ths8200_write(sd, THS8200_DTG1_FRAME_SZ_LSB, vtotal(bt) & 0xff); 314 315 /* Should be programmed higher than frame_size 316 * for progressive formats 317 */ 318 if (!bt->interlaced) 319 ths8200_write(sd, THS8200_DTG1_FIELD_SZ_LSB, 0xff); 320 321 /**** Display Timing Generator Control, Part 2 (DTG2). ****/ 322 /* Set breakpoint line numbers and types 323 * THS8200 generates line types with different properties. A line type 324 * that sets all the RGB-outputs to zero is used in the blanking areas, 325 * while a line type that enable the RGB-outputs is used in active video 326 * area. The line numbers for start of active video, start of front 327 * porch and after the last line in the frame must be set with the 328 * corresponding line types. 329 * 330 * Line types: 331 * 0x9 - Full normal sync pulse: Blocks data when dtg1_pass is off. 332 * Used in blanking area. 333 * 0x0 - Active video: Video data is always passed. Used in active 334 * video area. 335 */ 336 ths8200_write_and_or(sd, THS8200_DTG2_BP1_2_MSB, 0x88, 337 ((line_start_active_video >> 4) & 0x70) + 338 ((line_start_front_porch >> 8) & 0x07)); 339 ths8200_write(sd, THS8200_DTG2_BP3_4_MSB, ((vtotal(bt)) >> 4) & 0x70); 340 ths8200_write(sd, THS8200_DTG2_BP1_LSB, line_start_active_video & 0xff); 341 ths8200_write(sd, THS8200_DTG2_BP2_LSB, line_start_front_porch & 0xff); 342 ths8200_write(sd, THS8200_DTG2_BP3_LSB, (vtotal(bt)) & 0xff); 343 344 /* line types */ 345 ths8200_write(sd, THS8200_DTG2_LINETYPE1, 0x90); 346 ths8200_write(sd, THS8200_DTG2_LINETYPE2, 0x90); 347 348 /* h sync width transmitted */ 349 ths8200_write(sd, THS8200_DTG2_HLENGTH_LSB, bt->hsync & 0xff); 350 ths8200_write_and_or(sd, THS8200_DTG2_HLENGTH_LSB_HDLY_MSB, 0x3f, 351 (bt->hsync >> 2) & 0xc0); 352 353 /* The pixel value h sync is asserted on */ 354 ths8200_write_and_or(sd, THS8200_DTG2_HLENGTH_LSB_HDLY_MSB, 0xe0, 355 (htotal(bt) >> 8) & 0x1f); 356 ths8200_write(sd, THS8200_DTG2_HLENGTH_HDLY_LSB, htotal(bt)); 357 358 /* v sync width transmitted */ 359 ths8200_write(sd, THS8200_DTG2_VLENGTH1_LSB, (bt->vsync) & 0xff); 360 ths8200_write_and_or(sd, THS8200_DTG2_VLENGTH1_MSB_VDLY1_MSB, 0x3f, 361 ((bt->vsync) >> 2) & 0xc0); 362 363 /* The pixel value v sync is asserted on */ 364 ths8200_write_and_or(sd, THS8200_DTG2_VLENGTH1_MSB_VDLY1_MSB, 0xf8, 365 (vtotal(bt)>>8) & 0x7); 366 ths8200_write(sd, THS8200_DTG2_VDLY1_LSB, vtotal(bt)); 367 368 /* For progressive video vlength2 must be set to all 0 and vdly2 must 369 * be set to all 1. 370 */ 371 ths8200_write(sd, THS8200_DTG2_VLENGTH2_LSB, 0x00); 372 ths8200_write(sd, THS8200_DTG2_VLENGTH2_MSB_VDLY2_MSB, 0x07); 373 ths8200_write(sd, THS8200_DTG2_VDLY2_LSB, 0xff); 374 375 /* Internal delay factors to synchronize the sync pulses and the data */ 376 /* Experimental values delays (hor 4, ver 1) */ 377 ths8200_write(sd, THS8200_DTG2_HS_IN_DLY_MSB, (htotal(bt)>>8) & 0x1f); 378 ths8200_write(sd, THS8200_DTG2_HS_IN_DLY_LSB, (htotal(bt) - 4) & 0xff); 379 ths8200_write(sd, THS8200_DTG2_VS_IN_DLY_MSB, 0); 380 ths8200_write(sd, THS8200_DTG2_VS_IN_DLY_LSB, 1); 381 382 /* Polarity of received and transmitted sync signals */ 383 if (bt->polarities & V4L2_DV_HSYNC_POS_POL) { 384 polarity |= 0x01; /* HS_IN */ 385 polarity |= 0x08; /* HS_OUT */ 386 } 387 if (bt->polarities & V4L2_DV_VSYNC_POS_POL) { 388 polarity |= 0x02; /* VS_IN */ 389 polarity |= 0x10; /* VS_OUT */ 390 } 391 392 /* RGB mode, no embedded timings */ 393 /* Timing of video input bus is derived from HS, VS, and FID dedicated 394 * inputs 395 */ 396 ths8200_write(sd, THS8200_DTG2_CNTL, 0x47 | polarity); 397 398 /* leave reset */ 399 ths8200_s_stream(sd, true); 400 401 v4l2_dbg(1, debug, sd, "%s: frame %dx%d, polarity %d\n" 402 "horizontal: front porch %d, back porch %d, sync %d\n" 403 "vertical: sync %d\n", __func__, htotal(bt), vtotal(bt), 404 polarity, bt->hfrontporch, bt->hbackporch, 405 bt->hsync, bt->vsync); 406 } 407 408 static int ths8200_s_dv_timings(struct v4l2_subdev *sd, 409 struct v4l2_dv_timings *timings) 410 { 411 struct ths8200_state *state = to_state(sd); 412 int i; 413 414 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 415 416 if (timings->type != V4L2_DV_BT_656_1120) 417 return -EINVAL; 418 419 /* TODO Support interlaced formats */ 420 if (timings->bt.interlaced) { 421 v4l2_dbg(1, debug, sd, "TODO Support interlaced formats\n"); 422 return -EINVAL; 423 } 424 425 for (i = 0; i < ARRAY_SIZE(ths8200_timings); i++) { 426 if (v4l_match_dv_timings(&ths8200_timings[i], timings, 10)) 427 break; 428 } 429 430 if (i == ARRAY_SIZE(ths8200_timings)) { 431 v4l2_dbg(1, debug, sd, "Unsupported format\n"); 432 return -EINVAL; 433 } 434 435 timings->bt.flags &= ~V4L2_DV_FL_REDUCED_FPS; 436 437 /* save timings */ 438 state->dv_timings = *timings; 439 440 ths8200_setup(sd, &timings->bt); 441 442 return 0; 443 } 444 445 static int ths8200_g_dv_timings(struct v4l2_subdev *sd, 446 struct v4l2_dv_timings *timings) 447 { 448 struct ths8200_state *state = to_state(sd); 449 450 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 451 452 *timings = state->dv_timings; 453 454 return 0; 455 } 456 457 static int ths8200_enum_dv_timings(struct v4l2_subdev *sd, 458 struct v4l2_enum_dv_timings *timings) 459 { 460 /* Check requested format index is within range */ 461 if (timings->index >= ARRAY_SIZE(ths8200_timings)) 462 return -EINVAL; 463 464 timings->timings = ths8200_timings[timings->index]; 465 466 return 0; 467 } 468 469 static int ths8200_dv_timings_cap(struct v4l2_subdev *sd, 470 struct v4l2_dv_timings_cap *cap) 471 { 472 cap->type = V4L2_DV_BT_656_1120; 473 cap->bt.max_width = 1920; 474 cap->bt.max_height = 1080; 475 cap->bt.min_pixelclock = 27000000; 476 cap->bt.max_pixelclock = 148500000; 477 cap->bt.standards = V4L2_DV_BT_STD_CEA861; 478 cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE; 479 480 return 0; 481 } 482 483 /* Specific video subsystem operation handlers */ 484 static const struct v4l2_subdev_video_ops ths8200_video_ops = { 485 .s_stream = ths8200_s_stream, 486 .s_dv_timings = ths8200_s_dv_timings, 487 .g_dv_timings = ths8200_g_dv_timings, 488 .enum_dv_timings = ths8200_enum_dv_timings, 489 .dv_timings_cap = ths8200_dv_timings_cap, 490 }; 491 492 /* V4L2 top level operation handlers */ 493 static const struct v4l2_subdev_ops ths8200_ops = { 494 .core = &ths8200_core_ops, 495 .video = &ths8200_video_ops, 496 }; 497 498 static int ths8200_probe(struct i2c_client *client, 499 const struct i2c_device_id *id) 500 { 501 struct ths8200_state *state; 502 struct v4l2_subdev *sd; 503 504 /* Check if the adapter supports the needed features */ 505 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 506 return -EIO; 507 508 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); 509 if (!state) 510 return -ENOMEM; 511 512 sd = &state->sd; 513 v4l2_i2c_subdev_init(sd, client, &ths8200_ops); 514 515 state->chip_version = ths8200_read(sd, THS8200_VERSION); 516 v4l2_dbg(1, debug, sd, "chip version 0x%x\n", state->chip_version); 517 518 ths8200_core_init(sd); 519 520 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, 521 client->addr << 1, client->adapter->name); 522 523 return 0; 524 } 525 526 static int ths8200_remove(struct i2c_client *client) 527 { 528 struct v4l2_subdev *sd = i2c_get_clientdata(client); 529 530 v4l2_dbg(1, debug, sd, "%s removed @ 0x%x (%s)\n", client->name, 531 client->addr << 1, client->adapter->name); 532 533 ths8200_s_power(sd, false); 534 535 v4l2_device_unregister_subdev(sd); 536 537 return 0; 538 } 539 540 static struct i2c_device_id ths8200_id[] = { 541 { "ths8200", 0 }, 542 {}, 543 }; 544 MODULE_DEVICE_TABLE(i2c, ths8200_id); 545 546 static struct i2c_driver ths8200_driver = { 547 .driver = { 548 .owner = THIS_MODULE, 549 .name = "ths8200", 550 }, 551 .probe = ths8200_probe, 552 .remove = ths8200_remove, 553 .id_table = ths8200_id, 554 }; 555 556 module_i2c_driver(ths8200_driver); 557