1 /* 2 * ths8200 - Texas Instruments THS8200 video encoder driver 3 * 4 * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. 5 * 6 * This program is free software; you may redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; version 2 of the License. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation version 2. 13 * 14 * This program is distributed .as is. WITHOUT ANY WARRANTY of any 15 * kind, whether express or implied; without even the implied warranty 16 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 */ 19 20 #include <linux/i2c.h> 21 #include <linux/module.h> 22 #include <linux/v4l2-dv-timings.h> 23 24 #include <media/v4l2-dv-timings.h> 25 #include <media/v4l2-async.h> 26 #include <media/v4l2-device.h> 27 28 #include "ths8200_regs.h" 29 30 static int debug; 31 module_param(debug, int, 0644); 32 MODULE_PARM_DESC(debug, "debug level (0-2)"); 33 34 MODULE_DESCRIPTION("Texas Instruments THS8200 video encoder driver"); 35 MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>"); 36 MODULE_AUTHOR("Martin Bugge <martin.bugge@cisco.com>"); 37 MODULE_LICENSE("GPL v2"); 38 39 struct ths8200_state { 40 struct v4l2_subdev sd; 41 uint8_t chip_version; 42 /* Is the ths8200 powered on? */ 43 bool power_on; 44 struct v4l2_dv_timings dv_timings; 45 }; 46 47 static const struct v4l2_dv_timings_cap ths8200_timings_cap = { 48 .type = V4L2_DV_BT_656_1120, 49 /* Allow gcc 4.5.4 to build this */ 50 .reserved = { }, 51 { 52 .bt = { 53 .max_width = 1920, 54 .max_height = 1080, 55 .min_pixelclock = 25000000, 56 .max_pixelclock = 148500000, 57 .standards = V4L2_DV_BT_STD_CEA861, 58 .capabilities = V4L2_DV_BT_CAP_PROGRESSIVE, 59 }, 60 }, 61 }; 62 63 static inline struct ths8200_state *to_state(struct v4l2_subdev *sd) 64 { 65 return container_of(sd, struct ths8200_state, sd); 66 } 67 68 static inline unsigned hblanking(const struct v4l2_bt_timings *t) 69 { 70 return V4L2_DV_BT_BLANKING_WIDTH(t); 71 } 72 73 static inline unsigned htotal(const struct v4l2_bt_timings *t) 74 { 75 return V4L2_DV_BT_FRAME_WIDTH(t); 76 } 77 78 static inline unsigned vblanking(const struct v4l2_bt_timings *t) 79 { 80 return V4L2_DV_BT_BLANKING_HEIGHT(t); 81 } 82 83 static inline unsigned vtotal(const struct v4l2_bt_timings *t) 84 { 85 return V4L2_DV_BT_FRAME_HEIGHT(t); 86 } 87 88 static int ths8200_read(struct v4l2_subdev *sd, u8 reg) 89 { 90 struct i2c_client *client = v4l2_get_subdevdata(sd); 91 92 return i2c_smbus_read_byte_data(client, reg); 93 } 94 95 static int ths8200_write(struct v4l2_subdev *sd, u8 reg, u8 val) 96 { 97 struct i2c_client *client = v4l2_get_subdevdata(sd); 98 int ret; 99 int i; 100 101 for (i = 0; i < 3; i++) { 102 ret = i2c_smbus_write_byte_data(client, reg, val); 103 if (ret == 0) 104 return 0; 105 } 106 v4l2_err(sd, "I2C Write Problem\n"); 107 return ret; 108 } 109 110 /* To set specific bits in the register, a clear-mask is given (to be AND-ed), 111 * and then the value-mask (to be OR-ed). 112 */ 113 static inline void 114 ths8200_write_and_or(struct v4l2_subdev *sd, u8 reg, 115 uint8_t clr_mask, uint8_t val_mask) 116 { 117 ths8200_write(sd, reg, (ths8200_read(sd, reg) & clr_mask) | val_mask); 118 } 119 120 #ifdef CONFIG_VIDEO_ADV_DEBUG 121 122 static int ths8200_g_register(struct v4l2_subdev *sd, 123 struct v4l2_dbg_register *reg) 124 { 125 reg->val = ths8200_read(sd, reg->reg & 0xff); 126 reg->size = 1; 127 128 return 0; 129 } 130 131 static int ths8200_s_register(struct v4l2_subdev *sd, 132 const struct v4l2_dbg_register *reg) 133 { 134 ths8200_write(sd, reg->reg & 0xff, reg->val & 0xff); 135 136 return 0; 137 } 138 #endif 139 140 static int ths8200_log_status(struct v4l2_subdev *sd) 141 { 142 struct ths8200_state *state = to_state(sd); 143 uint8_t reg_03 = ths8200_read(sd, THS8200_CHIP_CTL); 144 145 v4l2_info(sd, "----- Chip status -----\n"); 146 v4l2_info(sd, "version: %u\n", state->chip_version); 147 v4l2_info(sd, "power: %s\n", (reg_03 & 0x0c) ? "off" : "on"); 148 v4l2_info(sd, "reset: %s\n", (reg_03 & 0x01) ? "off" : "on"); 149 v4l2_info(sd, "test pattern: %s\n", 150 (reg_03 & 0x20) ? "enabled" : "disabled"); 151 v4l2_info(sd, "format: %ux%u\n", 152 ths8200_read(sd, THS8200_DTG2_PIXEL_CNT_MSB) * 256 + 153 ths8200_read(sd, THS8200_DTG2_PIXEL_CNT_LSB), 154 (ths8200_read(sd, THS8200_DTG2_LINE_CNT_MSB) & 0x07) * 256 + 155 ths8200_read(sd, THS8200_DTG2_LINE_CNT_LSB)); 156 v4l2_print_dv_timings(sd->name, "Configured format:", 157 &state->dv_timings, true); 158 return 0; 159 } 160 161 /* Power up/down ths8200 */ 162 static int ths8200_s_power(struct v4l2_subdev *sd, int on) 163 { 164 struct ths8200_state *state = to_state(sd); 165 166 v4l2_dbg(1, debug, sd, "%s: power %s\n", __func__, on ? "on" : "off"); 167 168 state->power_on = on; 169 170 /* Power up/down - leave in reset state until input video is present */ 171 ths8200_write_and_or(sd, THS8200_CHIP_CTL, 0xf2, (on ? 0x00 : 0x0c)); 172 173 return 0; 174 } 175 176 static const struct v4l2_subdev_core_ops ths8200_core_ops = { 177 .log_status = ths8200_log_status, 178 .s_power = ths8200_s_power, 179 #ifdef CONFIG_VIDEO_ADV_DEBUG 180 .g_register = ths8200_g_register, 181 .s_register = ths8200_s_register, 182 #endif 183 }; 184 185 /* ----------------------------------------------------------------------------- 186 * V4L2 subdev video operations 187 */ 188 189 static int ths8200_s_stream(struct v4l2_subdev *sd, int enable) 190 { 191 struct ths8200_state *state = to_state(sd); 192 193 if (enable && !state->power_on) 194 ths8200_s_power(sd, true); 195 196 ths8200_write_and_or(sd, THS8200_CHIP_CTL, 0xfe, 197 (enable ? 0x01 : 0x00)); 198 199 v4l2_dbg(1, debug, sd, "%s: %sable\n", 200 __func__, (enable ? "en" : "dis")); 201 202 return 0; 203 } 204 205 static void ths8200_core_init(struct v4l2_subdev *sd) 206 { 207 /* setup clocks */ 208 ths8200_write_and_or(sd, THS8200_CHIP_CTL, 0x3f, 0xc0); 209 210 /**** Data path control (DATA) ****/ 211 /* Set FSADJ 700 mV, 212 * bypass 422-444 interpolation, 213 * input format 30 bit RGB444 214 */ 215 ths8200_write(sd, THS8200_DATA_CNTL, 0x70); 216 217 /* DTG Mode (Video blocked during blanking 218 * VESA slave 219 */ 220 ths8200_write(sd, THS8200_DTG1_MODE, 0x87); 221 222 /**** Display Timing Generator Control, Part 1 (DTG1). ****/ 223 224 /* Disable embedded syncs on the output by setting 225 * the amplitude to zero for all channels. 226 */ 227 ths8200_write(sd, THS8200_DTG1_Y_SYNC_MSB, 0x2a); 228 ths8200_write(sd, THS8200_DTG1_CBCR_SYNC_MSB, 0x2a); 229 } 230 231 static void ths8200_setup(struct v4l2_subdev *sd, struct v4l2_bt_timings *bt) 232 { 233 uint8_t polarity = 0; 234 uint16_t line_start_active_video = (bt->vsync + bt->vbackporch); 235 uint16_t line_start_front_porch = (vtotal(bt) - bt->vfrontporch); 236 237 /*** System ****/ 238 /* Set chip in reset while it is configured */ 239 ths8200_s_stream(sd, false); 240 241 /* configure video output timings */ 242 ths8200_write(sd, THS8200_DTG1_SPEC_A, bt->hsync); 243 ths8200_write(sd, THS8200_DTG1_SPEC_B, bt->hfrontporch); 244 245 /* Zero for progressive scan formats.*/ 246 if (!bt->interlaced) 247 ths8200_write(sd, THS8200_DTG1_SPEC_C, 0x00); 248 249 /* Distance from leading edge of h sync to start of active video. 250 * MSB in 0x2b 251 */ 252 ths8200_write(sd, THS8200_DTG1_SPEC_D_LSB, 253 (bt->hbackporch + bt->hsync) & 0xff); 254 /* Zero for SDTV-mode. MSB in 0x2b */ 255 ths8200_write(sd, THS8200_DTG1_SPEC_E_LSB, 0x00); 256 /* 257 * MSB for dtg1_spec(d/e/h). See comment for 258 * corresponding LSB registers. 259 */ 260 ths8200_write(sd, THS8200_DTG1_SPEC_DEH_MSB, 261 ((bt->hbackporch + bt->hsync) & 0x100) >> 1); 262 263 /* h front porch */ 264 ths8200_write(sd, THS8200_DTG1_SPEC_K_LSB, (bt->hfrontporch) & 0xff); 265 ths8200_write(sd, THS8200_DTG1_SPEC_K_MSB, 266 ((bt->hfrontporch) & 0x700) >> 8); 267 268 /* Half the line length. Used to calculate SDTV line types. */ 269 ths8200_write(sd, THS8200_DTG1_SPEC_G_LSB, (htotal(bt)/2) & 0xff); 270 ths8200_write(sd, THS8200_DTG1_SPEC_G_MSB, 271 ((htotal(bt)/2) >> 8) & 0x0f); 272 273 /* Total pixels per line (ex. 720p: 1650) */ 274 ths8200_write(sd, THS8200_DTG1_TOT_PIXELS_MSB, htotal(bt) >> 8); 275 ths8200_write(sd, THS8200_DTG1_TOT_PIXELS_LSB, htotal(bt) & 0xff); 276 277 /* Frame height and field height */ 278 /* Field height should be programmed higher than frame_size for 279 * progressive scan formats 280 */ 281 ths8200_write(sd, THS8200_DTG1_FRAME_FIELD_SZ_MSB, 282 ((vtotal(bt) >> 4) & 0xf0) + 0x7); 283 ths8200_write(sd, THS8200_DTG1_FRAME_SZ_LSB, vtotal(bt) & 0xff); 284 285 /* Should be programmed higher than frame_size 286 * for progressive formats 287 */ 288 if (!bt->interlaced) 289 ths8200_write(sd, THS8200_DTG1_FIELD_SZ_LSB, 0xff); 290 291 /**** Display Timing Generator Control, Part 2 (DTG2). ****/ 292 /* Set breakpoint line numbers and types 293 * THS8200 generates line types with different properties. A line type 294 * that sets all the RGB-outputs to zero is used in the blanking areas, 295 * while a line type that enable the RGB-outputs is used in active video 296 * area. The line numbers for start of active video, start of front 297 * porch and after the last line in the frame must be set with the 298 * corresponding line types. 299 * 300 * Line types: 301 * 0x9 - Full normal sync pulse: Blocks data when dtg1_pass is off. 302 * Used in blanking area. 303 * 0x0 - Active video: Video data is always passed. Used in active 304 * video area. 305 */ 306 ths8200_write_and_or(sd, THS8200_DTG2_BP1_2_MSB, 0x88, 307 ((line_start_active_video >> 4) & 0x70) + 308 ((line_start_front_porch >> 8) & 0x07)); 309 ths8200_write(sd, THS8200_DTG2_BP3_4_MSB, ((vtotal(bt)) >> 4) & 0x70); 310 ths8200_write(sd, THS8200_DTG2_BP1_LSB, line_start_active_video & 0xff); 311 ths8200_write(sd, THS8200_DTG2_BP2_LSB, line_start_front_porch & 0xff); 312 ths8200_write(sd, THS8200_DTG2_BP3_LSB, (vtotal(bt)) & 0xff); 313 314 /* line types */ 315 ths8200_write(sd, THS8200_DTG2_LINETYPE1, 0x90); 316 ths8200_write(sd, THS8200_DTG2_LINETYPE2, 0x90); 317 318 /* h sync width transmitted */ 319 ths8200_write(sd, THS8200_DTG2_HLENGTH_LSB, bt->hsync & 0xff); 320 ths8200_write_and_or(sd, THS8200_DTG2_HLENGTH_LSB_HDLY_MSB, 0x3f, 321 (bt->hsync >> 2) & 0xc0); 322 323 /* The pixel value h sync is asserted on */ 324 ths8200_write_and_or(sd, THS8200_DTG2_HLENGTH_LSB_HDLY_MSB, 0xe0, 325 (htotal(bt) >> 8) & 0x1f); 326 ths8200_write(sd, THS8200_DTG2_HLENGTH_HDLY_LSB, htotal(bt)); 327 328 /* v sync width transmitted */ 329 ths8200_write(sd, THS8200_DTG2_VLENGTH1_LSB, (bt->vsync) & 0xff); 330 ths8200_write_and_or(sd, THS8200_DTG2_VLENGTH1_MSB_VDLY1_MSB, 0x3f, 331 ((bt->vsync) >> 2) & 0xc0); 332 333 /* The pixel value v sync is asserted on */ 334 ths8200_write_and_or(sd, THS8200_DTG2_VLENGTH1_MSB_VDLY1_MSB, 0xf8, 335 (vtotal(bt)>>8) & 0x7); 336 ths8200_write(sd, THS8200_DTG2_VDLY1_LSB, vtotal(bt)); 337 338 /* For progressive video vlength2 must be set to all 0 and vdly2 must 339 * be set to all 1. 340 */ 341 ths8200_write(sd, THS8200_DTG2_VLENGTH2_LSB, 0x00); 342 ths8200_write(sd, THS8200_DTG2_VLENGTH2_MSB_VDLY2_MSB, 0x07); 343 ths8200_write(sd, THS8200_DTG2_VDLY2_LSB, 0xff); 344 345 /* Internal delay factors to synchronize the sync pulses and the data */ 346 /* Experimental values delays (hor 4, ver 1) */ 347 ths8200_write(sd, THS8200_DTG2_HS_IN_DLY_MSB, (htotal(bt)>>8) & 0x1f); 348 ths8200_write(sd, THS8200_DTG2_HS_IN_DLY_LSB, (htotal(bt) - 4) & 0xff); 349 ths8200_write(sd, THS8200_DTG2_VS_IN_DLY_MSB, 0); 350 ths8200_write(sd, THS8200_DTG2_VS_IN_DLY_LSB, 1); 351 352 /* Polarity of received and transmitted sync signals */ 353 if (bt->polarities & V4L2_DV_HSYNC_POS_POL) { 354 polarity |= 0x01; /* HS_IN */ 355 polarity |= 0x08; /* HS_OUT */ 356 } 357 if (bt->polarities & V4L2_DV_VSYNC_POS_POL) { 358 polarity |= 0x02; /* VS_IN */ 359 polarity |= 0x10; /* VS_OUT */ 360 } 361 362 /* RGB mode, no embedded timings */ 363 /* Timing of video input bus is derived from HS, VS, and FID dedicated 364 * inputs 365 */ 366 ths8200_write(sd, THS8200_DTG2_CNTL, 0x47 | polarity); 367 368 /* leave reset */ 369 ths8200_s_stream(sd, true); 370 371 v4l2_dbg(1, debug, sd, "%s: frame %dx%d, polarity %d\n" 372 "horizontal: front porch %d, back porch %d, sync %d\n" 373 "vertical: sync %d\n", __func__, htotal(bt), vtotal(bt), 374 polarity, bt->hfrontporch, bt->hbackporch, 375 bt->hsync, bt->vsync); 376 } 377 378 static int ths8200_s_dv_timings(struct v4l2_subdev *sd, 379 struct v4l2_dv_timings *timings) 380 { 381 struct ths8200_state *state = to_state(sd); 382 383 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 384 385 if (!v4l2_valid_dv_timings(timings, &ths8200_timings_cap, 386 NULL, NULL)) 387 return -EINVAL; 388 389 if (!v4l2_find_dv_timings_cap(timings, &ths8200_timings_cap, 10, 390 NULL, NULL)) { 391 v4l2_dbg(1, debug, sd, "Unsupported format\n"); 392 return -EINVAL; 393 } 394 395 timings->bt.flags &= ~V4L2_DV_FL_REDUCED_FPS; 396 397 /* save timings */ 398 state->dv_timings = *timings; 399 400 ths8200_setup(sd, &timings->bt); 401 402 return 0; 403 } 404 405 static int ths8200_g_dv_timings(struct v4l2_subdev *sd, 406 struct v4l2_dv_timings *timings) 407 { 408 struct ths8200_state *state = to_state(sd); 409 410 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 411 412 *timings = state->dv_timings; 413 414 return 0; 415 } 416 417 static int ths8200_enum_dv_timings(struct v4l2_subdev *sd, 418 struct v4l2_enum_dv_timings *timings) 419 { 420 return v4l2_enum_dv_timings_cap(timings, &ths8200_timings_cap, 421 NULL, NULL); 422 } 423 424 static int ths8200_dv_timings_cap(struct v4l2_subdev *sd, 425 struct v4l2_dv_timings_cap *cap) 426 { 427 *cap = ths8200_timings_cap; 428 return 0; 429 } 430 431 /* Specific video subsystem operation handlers */ 432 static const struct v4l2_subdev_video_ops ths8200_video_ops = { 433 .s_stream = ths8200_s_stream, 434 .s_dv_timings = ths8200_s_dv_timings, 435 .g_dv_timings = ths8200_g_dv_timings, 436 .enum_dv_timings = ths8200_enum_dv_timings, 437 .dv_timings_cap = ths8200_dv_timings_cap, 438 }; 439 440 /* V4L2 top level operation handlers */ 441 static const struct v4l2_subdev_ops ths8200_ops = { 442 .core = &ths8200_core_ops, 443 .video = &ths8200_video_ops, 444 }; 445 446 static int ths8200_probe(struct i2c_client *client, 447 const struct i2c_device_id *id) 448 { 449 struct ths8200_state *state; 450 struct v4l2_subdev *sd; 451 int error; 452 453 /* Check if the adapter supports the needed features */ 454 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 455 return -EIO; 456 457 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); 458 if (!state) 459 return -ENOMEM; 460 461 sd = &state->sd; 462 v4l2_i2c_subdev_init(sd, client, &ths8200_ops); 463 464 state->chip_version = ths8200_read(sd, THS8200_VERSION); 465 v4l2_dbg(1, debug, sd, "chip version 0x%x\n", state->chip_version); 466 467 ths8200_core_init(sd); 468 469 error = v4l2_async_register_subdev(&state->sd); 470 if (error) 471 return error; 472 473 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, 474 client->addr << 1, client->adapter->name); 475 476 return 0; 477 } 478 479 static int ths8200_remove(struct i2c_client *client) 480 { 481 struct v4l2_subdev *sd = i2c_get_clientdata(client); 482 struct ths8200_state *decoder = to_state(sd); 483 484 v4l2_dbg(1, debug, sd, "%s removed @ 0x%x (%s)\n", client->name, 485 client->addr << 1, client->adapter->name); 486 487 ths8200_s_power(sd, false); 488 v4l2_async_unregister_subdev(&decoder->sd); 489 v4l2_device_unregister_subdev(sd); 490 491 return 0; 492 } 493 494 static struct i2c_device_id ths8200_id[] = { 495 { "ths8200", 0 }, 496 {}, 497 }; 498 MODULE_DEVICE_TABLE(i2c, ths8200_id); 499 500 #if IS_ENABLED(CONFIG_OF) 501 static const struct of_device_id ths8200_of_match[] = { 502 { .compatible = "ti,ths8200", }, 503 { /* sentinel */ }, 504 }; 505 MODULE_DEVICE_TABLE(of, ths8200_of_match); 506 #endif 507 508 static struct i2c_driver ths8200_driver = { 509 .driver = { 510 .owner = THIS_MODULE, 511 .name = "ths8200", 512 .of_match_table = of_match_ptr(ths8200_of_match), 513 }, 514 .probe = ths8200_probe, 515 .remove = ths8200_remove, 516 .id_table = ths8200_id, 517 }; 518 519 module_i2c_driver(ths8200_driver); 520