1 /* 2 * ths8200 - Texas Instruments THS8200 video encoder driver 3 * 4 * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. 5 * 6 * This program is free software; you may redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; version 2 of the License. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation version 2. 13 * 14 * This program is distributed .as is. WITHOUT ANY WARRANTY of any 15 * kind, whether express or implied; without even the implied warranty 16 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 */ 19 20 #include <linux/i2c.h> 21 #include <linux/module.h> 22 #include <linux/v4l2-dv-timings.h> 23 24 #include <media/v4l2-async.h> 25 #include <media/v4l2-device.h> 26 27 #include "ths8200_regs.h" 28 29 static int debug; 30 module_param(debug, int, 0644); 31 MODULE_PARM_DESC(debug, "debug level (0-2)"); 32 33 MODULE_DESCRIPTION("Texas Instruments THS8200 video encoder driver"); 34 MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>"); 35 MODULE_AUTHOR("Martin Bugge <martin.bugge@cisco.com>"); 36 MODULE_LICENSE("GPL v2"); 37 38 struct ths8200_state { 39 struct v4l2_subdev sd; 40 uint8_t chip_version; 41 /* Is the ths8200 powered on? */ 42 bool power_on; 43 struct v4l2_dv_timings dv_timings; 44 }; 45 46 static const struct v4l2_dv_timings ths8200_timings[] = { 47 V4L2_DV_BT_CEA_720X480P59_94, 48 V4L2_DV_BT_CEA_1280X720P24, 49 V4L2_DV_BT_CEA_1280X720P25, 50 V4L2_DV_BT_CEA_1280X720P30, 51 V4L2_DV_BT_CEA_1280X720P50, 52 V4L2_DV_BT_CEA_1280X720P60, 53 V4L2_DV_BT_CEA_1920X1080P24, 54 V4L2_DV_BT_CEA_1920X1080P25, 55 V4L2_DV_BT_CEA_1920X1080P30, 56 V4L2_DV_BT_CEA_1920X1080P50, 57 V4L2_DV_BT_CEA_1920X1080P60, 58 }; 59 60 static inline struct ths8200_state *to_state(struct v4l2_subdev *sd) 61 { 62 return container_of(sd, struct ths8200_state, sd); 63 } 64 65 static inline unsigned hblanking(const struct v4l2_bt_timings *t) 66 { 67 return t->hfrontporch + t->hsync + t->hbackporch; 68 } 69 70 static inline unsigned htotal(const struct v4l2_bt_timings *t) 71 { 72 return t->width + t->hfrontporch + t->hsync + t->hbackporch; 73 } 74 75 static inline unsigned vblanking(const struct v4l2_bt_timings *t) 76 { 77 return t->vfrontporch + t->vsync + t->vbackporch; 78 } 79 80 static inline unsigned vtotal(const struct v4l2_bt_timings *t) 81 { 82 return t->height + t->vfrontporch + t->vsync + t->vbackporch; 83 } 84 85 static int ths8200_read(struct v4l2_subdev *sd, u8 reg) 86 { 87 struct i2c_client *client = v4l2_get_subdevdata(sd); 88 89 return i2c_smbus_read_byte_data(client, reg); 90 } 91 92 static int ths8200_write(struct v4l2_subdev *sd, u8 reg, u8 val) 93 { 94 struct i2c_client *client = v4l2_get_subdevdata(sd); 95 int ret; 96 int i; 97 98 for (i = 0; i < 3; i++) { 99 ret = i2c_smbus_write_byte_data(client, reg, val); 100 if (ret == 0) 101 return 0; 102 } 103 v4l2_err(sd, "I2C Write Problem\n"); 104 return ret; 105 } 106 107 /* To set specific bits in the register, a clear-mask is given (to be AND-ed), 108 * and then the value-mask (to be OR-ed). 109 */ 110 static inline void 111 ths8200_write_and_or(struct v4l2_subdev *sd, u8 reg, 112 uint8_t clr_mask, uint8_t val_mask) 113 { 114 ths8200_write(sd, reg, (ths8200_read(sd, reg) & clr_mask) | val_mask); 115 } 116 117 #ifdef CONFIG_VIDEO_ADV_DEBUG 118 119 static int ths8200_g_register(struct v4l2_subdev *sd, 120 struct v4l2_dbg_register *reg) 121 { 122 reg->val = ths8200_read(sd, reg->reg & 0xff); 123 reg->size = 1; 124 125 return 0; 126 } 127 128 static int ths8200_s_register(struct v4l2_subdev *sd, 129 const struct v4l2_dbg_register *reg) 130 { 131 ths8200_write(sd, reg->reg & 0xff, reg->val & 0xff); 132 133 return 0; 134 } 135 #endif 136 137 static void ths8200_print_timings(struct v4l2_subdev *sd, 138 struct v4l2_dv_timings *timings, 139 const char *txt, bool detailed) 140 { 141 struct v4l2_bt_timings *bt = &timings->bt; 142 u32 htot, vtot; 143 144 if (timings->type != V4L2_DV_BT_656_1120) 145 return; 146 147 htot = htotal(bt); 148 vtot = vtotal(bt); 149 150 v4l2_info(sd, "%s %dx%d%s%d (%dx%d)", 151 txt, bt->width, bt->height, bt->interlaced ? "i" : "p", 152 (htot * vtot) > 0 ? ((u32)bt->pixelclock / (htot * vtot)) : 0, 153 htot, vtot); 154 155 if (detailed) { 156 v4l2_info(sd, " horizontal: fp = %d, %ssync = %d, bp = %d\n", 157 bt->hfrontporch, 158 (bt->polarities & V4L2_DV_HSYNC_POS_POL) ? "+" : "-", 159 bt->hsync, bt->hbackporch); 160 v4l2_info(sd, " vertical: fp = %d, %ssync = %d, bp = %d\n", 161 bt->vfrontporch, 162 (bt->polarities & V4L2_DV_VSYNC_POS_POL) ? "+" : "-", 163 bt->vsync, bt->vbackporch); 164 v4l2_info(sd, 165 " pixelclock: %lld, flags: 0x%x, standards: 0x%x\n", 166 bt->pixelclock, bt->flags, bt->standards); 167 } 168 } 169 170 static int ths8200_log_status(struct v4l2_subdev *sd) 171 { 172 struct ths8200_state *state = to_state(sd); 173 uint8_t reg_03 = ths8200_read(sd, THS8200_CHIP_CTL); 174 175 v4l2_info(sd, "----- Chip status -----\n"); 176 v4l2_info(sd, "version: %u\n", state->chip_version); 177 v4l2_info(sd, "power: %s\n", (reg_03 & 0x0c) ? "off" : "on"); 178 v4l2_info(sd, "reset: %s\n", (reg_03 & 0x01) ? "off" : "on"); 179 v4l2_info(sd, "test pattern: %s\n", 180 (reg_03 & 0x20) ? "enabled" : "disabled"); 181 v4l2_info(sd, "format: %ux%u\n", 182 ths8200_read(sd, THS8200_DTG2_PIXEL_CNT_MSB) * 256 + 183 ths8200_read(sd, THS8200_DTG2_PIXEL_CNT_LSB), 184 (ths8200_read(sd, THS8200_DTG2_LINE_CNT_MSB) & 0x07) * 256 + 185 ths8200_read(sd, THS8200_DTG2_LINE_CNT_LSB)); 186 ths8200_print_timings(sd, &state->dv_timings, 187 "Configured format:", true); 188 189 return 0; 190 } 191 192 /* Power up/down ths8200 */ 193 static int ths8200_s_power(struct v4l2_subdev *sd, int on) 194 { 195 struct ths8200_state *state = to_state(sd); 196 197 v4l2_dbg(1, debug, sd, "%s: power %s\n", __func__, on ? "on" : "off"); 198 199 state->power_on = on; 200 201 /* Power up/down - leave in reset state until input video is present */ 202 ths8200_write_and_or(sd, THS8200_CHIP_CTL, 0xf2, (on ? 0x00 : 0x0c)); 203 204 return 0; 205 } 206 207 static const struct v4l2_subdev_core_ops ths8200_core_ops = { 208 .log_status = ths8200_log_status, 209 .s_power = ths8200_s_power, 210 #ifdef CONFIG_VIDEO_ADV_DEBUG 211 .g_register = ths8200_g_register, 212 .s_register = ths8200_s_register, 213 #endif 214 }; 215 216 /* ----------------------------------------------------------------------------- 217 * V4L2 subdev video operations 218 */ 219 220 static int ths8200_s_stream(struct v4l2_subdev *sd, int enable) 221 { 222 struct ths8200_state *state = to_state(sd); 223 224 if (enable && !state->power_on) 225 ths8200_s_power(sd, true); 226 227 ths8200_write_and_or(sd, THS8200_CHIP_CTL, 0xfe, 228 (enable ? 0x01 : 0x00)); 229 230 v4l2_dbg(1, debug, sd, "%s: %sable\n", 231 __func__, (enable ? "en" : "dis")); 232 233 return 0; 234 } 235 236 static void ths8200_core_init(struct v4l2_subdev *sd) 237 { 238 /* setup clocks */ 239 ths8200_write_and_or(sd, THS8200_CHIP_CTL, 0x3f, 0xc0); 240 241 /**** Data path control (DATA) ****/ 242 /* Set FSADJ 700 mV, 243 * bypass 422-444 interpolation, 244 * input format 30 bit RGB444 245 */ 246 ths8200_write(sd, THS8200_DATA_CNTL, 0x70); 247 248 /* DTG Mode (Video blocked during blanking 249 * VESA slave 250 */ 251 ths8200_write(sd, THS8200_DTG1_MODE, 0x87); 252 253 /**** Display Timing Generator Control, Part 1 (DTG1). ****/ 254 255 /* Disable embedded syncs on the output by setting 256 * the amplitude to zero for all channels. 257 */ 258 ths8200_write(sd, THS8200_DTG1_Y_SYNC_MSB, 0x2a); 259 ths8200_write(sd, THS8200_DTG1_CBCR_SYNC_MSB, 0x2a); 260 } 261 262 static void ths8200_setup(struct v4l2_subdev *sd, struct v4l2_bt_timings *bt) 263 { 264 uint8_t polarity = 0; 265 uint16_t line_start_active_video = (bt->vsync + bt->vbackporch); 266 uint16_t line_start_front_porch = (vtotal(bt) - bt->vfrontporch); 267 268 /*** System ****/ 269 /* Set chip in reset while it is configured */ 270 ths8200_s_stream(sd, false); 271 272 /* configure video output timings */ 273 ths8200_write(sd, THS8200_DTG1_SPEC_A, bt->hsync); 274 ths8200_write(sd, THS8200_DTG1_SPEC_B, bt->hfrontporch); 275 276 /* Zero for progressive scan formats.*/ 277 if (!bt->interlaced) 278 ths8200_write(sd, THS8200_DTG1_SPEC_C, 0x00); 279 280 /* Distance from leading edge of h sync to start of active video. 281 * MSB in 0x2b 282 */ 283 ths8200_write(sd, THS8200_DTG1_SPEC_D_LSB, 284 (bt->hbackporch + bt->hsync) & 0xff); 285 /* Zero for SDTV-mode. MSB in 0x2b */ 286 ths8200_write(sd, THS8200_DTG1_SPEC_E_LSB, 0x00); 287 /* 288 * MSB for dtg1_spec(d/e/h). See comment for 289 * corresponding LSB registers. 290 */ 291 ths8200_write(sd, THS8200_DTG1_SPEC_DEH_MSB, 292 ((bt->hbackporch + bt->hsync) & 0x100) >> 1); 293 294 /* h front porch */ 295 ths8200_write(sd, THS8200_DTG1_SPEC_K_LSB, (bt->hfrontporch) & 0xff); 296 ths8200_write(sd, THS8200_DTG1_SPEC_K_MSB, 297 ((bt->hfrontporch) & 0x700) >> 8); 298 299 /* Half the line length. Used to calculate SDTV line types. */ 300 ths8200_write(sd, THS8200_DTG1_SPEC_G_LSB, (htotal(bt)/2) & 0xff); 301 ths8200_write(sd, THS8200_DTG1_SPEC_G_MSB, 302 ((htotal(bt)/2) >> 8) & 0x0f); 303 304 /* Total pixels per line (ex. 720p: 1650) */ 305 ths8200_write(sd, THS8200_DTG1_TOT_PIXELS_MSB, htotal(bt) >> 8); 306 ths8200_write(sd, THS8200_DTG1_TOT_PIXELS_LSB, htotal(bt) & 0xff); 307 308 /* Frame height and field height */ 309 /* Field height should be programmed higher than frame_size for 310 * progressive scan formats 311 */ 312 ths8200_write(sd, THS8200_DTG1_FRAME_FIELD_SZ_MSB, 313 ((vtotal(bt) >> 4) & 0xf0) + 0x7); 314 ths8200_write(sd, THS8200_DTG1_FRAME_SZ_LSB, vtotal(bt) & 0xff); 315 316 /* Should be programmed higher than frame_size 317 * for progressive formats 318 */ 319 if (!bt->interlaced) 320 ths8200_write(sd, THS8200_DTG1_FIELD_SZ_LSB, 0xff); 321 322 /**** Display Timing Generator Control, Part 2 (DTG2). ****/ 323 /* Set breakpoint line numbers and types 324 * THS8200 generates line types with different properties. A line type 325 * that sets all the RGB-outputs to zero is used in the blanking areas, 326 * while a line type that enable the RGB-outputs is used in active video 327 * area. The line numbers for start of active video, start of front 328 * porch and after the last line in the frame must be set with the 329 * corresponding line types. 330 * 331 * Line types: 332 * 0x9 - Full normal sync pulse: Blocks data when dtg1_pass is off. 333 * Used in blanking area. 334 * 0x0 - Active video: Video data is always passed. Used in active 335 * video area. 336 */ 337 ths8200_write_and_or(sd, THS8200_DTG2_BP1_2_MSB, 0x88, 338 ((line_start_active_video >> 4) & 0x70) + 339 ((line_start_front_porch >> 8) & 0x07)); 340 ths8200_write(sd, THS8200_DTG2_BP3_4_MSB, ((vtotal(bt)) >> 4) & 0x70); 341 ths8200_write(sd, THS8200_DTG2_BP1_LSB, line_start_active_video & 0xff); 342 ths8200_write(sd, THS8200_DTG2_BP2_LSB, line_start_front_porch & 0xff); 343 ths8200_write(sd, THS8200_DTG2_BP3_LSB, (vtotal(bt)) & 0xff); 344 345 /* line types */ 346 ths8200_write(sd, THS8200_DTG2_LINETYPE1, 0x90); 347 ths8200_write(sd, THS8200_DTG2_LINETYPE2, 0x90); 348 349 /* h sync width transmitted */ 350 ths8200_write(sd, THS8200_DTG2_HLENGTH_LSB, bt->hsync & 0xff); 351 ths8200_write_and_or(sd, THS8200_DTG2_HLENGTH_LSB_HDLY_MSB, 0x3f, 352 (bt->hsync >> 2) & 0xc0); 353 354 /* The pixel value h sync is asserted on */ 355 ths8200_write_and_or(sd, THS8200_DTG2_HLENGTH_LSB_HDLY_MSB, 0xe0, 356 (htotal(bt) >> 8) & 0x1f); 357 ths8200_write(sd, THS8200_DTG2_HLENGTH_HDLY_LSB, htotal(bt)); 358 359 /* v sync width transmitted */ 360 ths8200_write(sd, THS8200_DTG2_VLENGTH1_LSB, (bt->vsync) & 0xff); 361 ths8200_write_and_or(sd, THS8200_DTG2_VLENGTH1_MSB_VDLY1_MSB, 0x3f, 362 ((bt->vsync) >> 2) & 0xc0); 363 364 /* The pixel value v sync is asserted on */ 365 ths8200_write_and_or(sd, THS8200_DTG2_VLENGTH1_MSB_VDLY1_MSB, 0xf8, 366 (vtotal(bt)>>8) & 0x7); 367 ths8200_write(sd, THS8200_DTG2_VDLY1_LSB, vtotal(bt)); 368 369 /* For progressive video vlength2 must be set to all 0 and vdly2 must 370 * be set to all 1. 371 */ 372 ths8200_write(sd, THS8200_DTG2_VLENGTH2_LSB, 0x00); 373 ths8200_write(sd, THS8200_DTG2_VLENGTH2_MSB_VDLY2_MSB, 0x07); 374 ths8200_write(sd, THS8200_DTG2_VDLY2_LSB, 0xff); 375 376 /* Internal delay factors to synchronize the sync pulses and the data */ 377 /* Experimental values delays (hor 4, ver 1) */ 378 ths8200_write(sd, THS8200_DTG2_HS_IN_DLY_MSB, (htotal(bt)>>8) & 0x1f); 379 ths8200_write(sd, THS8200_DTG2_HS_IN_DLY_LSB, (htotal(bt) - 4) & 0xff); 380 ths8200_write(sd, THS8200_DTG2_VS_IN_DLY_MSB, 0); 381 ths8200_write(sd, THS8200_DTG2_VS_IN_DLY_LSB, 1); 382 383 /* Polarity of received and transmitted sync signals */ 384 if (bt->polarities & V4L2_DV_HSYNC_POS_POL) { 385 polarity |= 0x01; /* HS_IN */ 386 polarity |= 0x08; /* HS_OUT */ 387 } 388 if (bt->polarities & V4L2_DV_VSYNC_POS_POL) { 389 polarity |= 0x02; /* VS_IN */ 390 polarity |= 0x10; /* VS_OUT */ 391 } 392 393 /* RGB mode, no embedded timings */ 394 /* Timing of video input bus is derived from HS, VS, and FID dedicated 395 * inputs 396 */ 397 ths8200_write(sd, THS8200_DTG2_CNTL, 0x47 | polarity); 398 399 /* leave reset */ 400 ths8200_s_stream(sd, true); 401 402 v4l2_dbg(1, debug, sd, "%s: frame %dx%d, polarity %d\n" 403 "horizontal: front porch %d, back porch %d, sync %d\n" 404 "vertical: sync %d\n", __func__, htotal(bt), vtotal(bt), 405 polarity, bt->hfrontporch, bt->hbackporch, 406 bt->hsync, bt->vsync); 407 } 408 409 static int ths8200_s_dv_timings(struct v4l2_subdev *sd, 410 struct v4l2_dv_timings *timings) 411 { 412 struct ths8200_state *state = to_state(sd); 413 int i; 414 415 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 416 417 if (timings->type != V4L2_DV_BT_656_1120) 418 return -EINVAL; 419 420 /* TODO Support interlaced formats */ 421 if (timings->bt.interlaced) { 422 v4l2_dbg(1, debug, sd, "TODO Support interlaced formats\n"); 423 return -EINVAL; 424 } 425 426 for (i = 0; i < ARRAY_SIZE(ths8200_timings); i++) { 427 if (v4l_match_dv_timings(&ths8200_timings[i], timings, 10)) 428 break; 429 } 430 431 if (i == ARRAY_SIZE(ths8200_timings)) { 432 v4l2_dbg(1, debug, sd, "Unsupported format\n"); 433 return -EINVAL; 434 } 435 436 timings->bt.flags &= ~V4L2_DV_FL_REDUCED_FPS; 437 438 /* save timings */ 439 state->dv_timings = *timings; 440 441 ths8200_setup(sd, &timings->bt); 442 443 return 0; 444 } 445 446 static int ths8200_g_dv_timings(struct v4l2_subdev *sd, 447 struct v4l2_dv_timings *timings) 448 { 449 struct ths8200_state *state = to_state(sd); 450 451 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 452 453 *timings = state->dv_timings; 454 455 return 0; 456 } 457 458 static int ths8200_enum_dv_timings(struct v4l2_subdev *sd, 459 struct v4l2_enum_dv_timings *timings) 460 { 461 /* Check requested format index is within range */ 462 if (timings->index >= ARRAY_SIZE(ths8200_timings)) 463 return -EINVAL; 464 465 timings->timings = ths8200_timings[timings->index]; 466 467 return 0; 468 } 469 470 static int ths8200_dv_timings_cap(struct v4l2_subdev *sd, 471 struct v4l2_dv_timings_cap *cap) 472 { 473 cap->type = V4L2_DV_BT_656_1120; 474 cap->bt.max_width = 1920; 475 cap->bt.max_height = 1080; 476 cap->bt.min_pixelclock = 27000000; 477 cap->bt.max_pixelclock = 148500000; 478 cap->bt.standards = V4L2_DV_BT_STD_CEA861; 479 cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE; 480 481 return 0; 482 } 483 484 /* Specific video subsystem operation handlers */ 485 static const struct v4l2_subdev_video_ops ths8200_video_ops = { 486 .s_stream = ths8200_s_stream, 487 .s_dv_timings = ths8200_s_dv_timings, 488 .g_dv_timings = ths8200_g_dv_timings, 489 .enum_dv_timings = ths8200_enum_dv_timings, 490 .dv_timings_cap = ths8200_dv_timings_cap, 491 }; 492 493 /* V4L2 top level operation handlers */ 494 static const struct v4l2_subdev_ops ths8200_ops = { 495 .core = &ths8200_core_ops, 496 .video = &ths8200_video_ops, 497 }; 498 499 static int ths8200_probe(struct i2c_client *client, 500 const struct i2c_device_id *id) 501 { 502 struct ths8200_state *state; 503 struct v4l2_subdev *sd; 504 int error; 505 506 /* Check if the adapter supports the needed features */ 507 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 508 return -EIO; 509 510 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); 511 if (!state) 512 return -ENOMEM; 513 514 sd = &state->sd; 515 v4l2_i2c_subdev_init(sd, client, &ths8200_ops); 516 517 state->chip_version = ths8200_read(sd, THS8200_VERSION); 518 v4l2_dbg(1, debug, sd, "chip version 0x%x\n", state->chip_version); 519 520 ths8200_core_init(sd); 521 522 error = v4l2_async_register_subdev(&state->sd); 523 if (error) 524 return error; 525 526 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, 527 client->addr << 1, client->adapter->name); 528 529 return 0; 530 } 531 532 static int ths8200_remove(struct i2c_client *client) 533 { 534 struct v4l2_subdev *sd = i2c_get_clientdata(client); 535 struct ths8200_state *decoder = to_state(sd); 536 537 v4l2_dbg(1, debug, sd, "%s removed @ 0x%x (%s)\n", client->name, 538 client->addr << 1, client->adapter->name); 539 540 ths8200_s_power(sd, false); 541 v4l2_async_unregister_subdev(&decoder->sd); 542 v4l2_device_unregister_subdev(sd); 543 544 return 0; 545 } 546 547 static struct i2c_device_id ths8200_id[] = { 548 { "ths8200", 0 }, 549 {}, 550 }; 551 MODULE_DEVICE_TABLE(i2c, ths8200_id); 552 553 #if IS_ENABLED(CONFIG_OF) 554 static const struct of_device_id ths8200_of_match[] = { 555 { .compatible = "ti,ths8200", }, 556 { /* sentinel */ }, 557 }; 558 MODULE_DEVICE_TABLE(of, ths8200_of_match); 559 #endif 560 561 static struct i2c_driver ths8200_driver = { 562 .driver = { 563 .owner = THIS_MODULE, 564 .name = "ths8200", 565 .of_match_table = of_match_ptr(ths8200_of_match), 566 }, 567 .probe = ths8200_probe, 568 .remove = ths8200_remove, 569 .id_table = ths8200_id, 570 }; 571 572 module_i2c_driver(ths8200_driver); 573