xref: /openbmc/linux/drivers/media/i2c/tda1997x.c (revision c96651a0)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2018 Gateworks Corporation
4  */
5 #include <linux/delay.h>
6 #include <linux/hdmi.h>
7 #include <linux/i2c.h>
8 #include <linux/init.h>
9 #include <linux/interrupt.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/of_graph.h>
13 #include <linux/platform_device.h>
14 #include <linux/regulator/consumer.h>
15 #include <linux/types.h>
16 #include <linux/v4l2-dv-timings.h>
17 #include <linux/videodev2.h>
18 
19 #include <media/v4l2-ctrls.h>
20 #include <media/v4l2-device.h>
21 #include <media/v4l2-dv-timings.h>
22 #include <media/v4l2-event.h>
23 #include <media/v4l2-fwnode.h>
24 #include <media/i2c/tda1997x.h>
25 
26 #include <sound/core.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/soc.h>
30 
31 #include <dt-bindings/media/tda1997x.h>
32 
33 #include "tda1997x_regs.h"
34 
35 #define TDA1997X_MBUS_CODES	5
36 
37 /* debug level */
38 static int debug;
39 module_param(debug, int, 0644);
40 MODULE_PARM_DESC(debug, "debug level (0-2)");
41 
42 /* Audio formats */
43 static const char * const audtype_names[] = {
44 	"PCM",			/* PCM Samples */
45 	"HBR",			/* High Bit Rate Audio */
46 	"OBA",			/* One-Bit Audio */
47 	"DST"			/* Direct Stream Transfer */
48 };
49 
50 /* Audio output port formats */
51 enum audfmt_types {
52 	AUDFMT_TYPE_DISABLED = 0,
53 	AUDFMT_TYPE_I2S,
54 	AUDFMT_TYPE_SPDIF,
55 };
56 static const char * const audfmt_names[] = {
57 	"Disabled",
58 	"I2S",
59 	"SPDIF",
60 };
61 
62 /* Video input formats */
63 static const char * const hdmi_colorspace_names[] = {
64 	"RGB", "YUV422", "YUV444", "YUV420", "", "", "", "",
65 };
66 static const char * const hdmi_colorimetry_names[] = {
67 	"", "ITU601", "ITU709", "Extended",
68 };
69 static const char * const v4l2_quantization_names[] = {
70 	"Default",
71 	"Full Range (0-255)",
72 	"Limited Range (16-235)",
73 };
74 
75 /* Video output port formats */
76 static const char * const vidfmt_names[] = {
77 	"RGB444/YUV444",	/* RGB/YUV444 16bit data bus, 8bpp */
78 	"YUV422 semi-planar",	/* YUV422 16bit data base, 8bpp */
79 	"YUV422 CCIR656",	/* BT656 (YUV 8bpp 2 clock per pixel) */
80 	"Invalid",
81 };
82 
83 /*
84  * Colorspace conversion matrices
85  */
86 struct color_matrix_coefs {
87 	const char *name;
88 	/* Input offsets */
89 	s16 offint1;
90 	s16 offint2;
91 	s16 offint3;
92 	/* Coeficients */
93 	s16 p11coef;
94 	s16 p12coef;
95 	s16 p13coef;
96 	s16 p21coef;
97 	s16 p22coef;
98 	s16 p23coef;
99 	s16 p31coef;
100 	s16 p32coef;
101 	s16 p33coef;
102 	/* Output offsets */
103 	s16 offout1;
104 	s16 offout2;
105 	s16 offout3;
106 };
107 
108 enum {
109 	ITU709_RGBFULL,
110 	ITU601_RGBFULL,
111 	RGBLIMITED_RGBFULL,
112 	RGBLIMITED_ITU601,
113 	RGBLIMITED_ITU709,
114 	RGBFULL_ITU601,
115 	RGBFULL_ITU709,
116 };
117 
118 /* NB: 4096 is 1.0 using fixed point numbers */
119 static const struct color_matrix_coefs conv_matrix[] = {
120 	{
121 		"YUV709 -> RGB full",
122 		 -256, -2048,  -2048,
123 		 4769, -2183,   -873,
124 		 4769,  7343,      0,
125 		 4769,     0,   8652,
126 		    0,     0,      0,
127 	},
128 	{
129 		"YUV601 -> RGB full",
130 		 -256, -2048,  -2048,
131 		 4769, -3330,  -1602,
132 		 4769,  6538,      0,
133 		 4769,     0,   8264,
134 		  256,   256,    256,
135 	},
136 	{
137 		"RGB limited -> RGB full",
138 		 -256,  -256,   -256,
139 		    0,  4769,      0,
140 		    0,     0,   4769,
141 		 4769,     0,      0,
142 		    0,     0,      0,
143 	},
144 	{
145 		"RGB limited -> ITU601",
146 		 -256,  -256,   -256,
147 		 2404,  1225,    467,
148 		-1754,  2095,   -341,
149 		-1388,  -707,   2095,
150 		  256,  2048,   2048,
151 	},
152 	{
153 		"RGB limited -> ITU709",
154 		 -256,  -256,   -256,
155 		 2918,   867,    295,
156 		-1894,  2087,   -190,
157 		-1607,  -477,   2087,
158 		  256,  2048,   2048,
159 	},
160 	{
161 		"RGB full -> ITU601",
162 		    0,     0,      0,
163 		 2065,  1052,    401,
164 		-1506,  1799,   -293,
165 		-1192,  -607,   1799,
166 		  256,  2048,   2048,
167 	},
168 	{
169 		"RGB full -> ITU709",
170 		    0,     0,      0,
171 		 2506,   745,    253,
172 		-1627,  1792,   -163,
173 		-1380,  -410,   1792,
174 		  256,  2048,   2048,
175 	},
176 };
177 
178 static const struct v4l2_dv_timings_cap tda1997x_dv_timings_cap = {
179 	.type = V4L2_DV_BT_656_1120,
180 	/* keep this initialization for compatibility with GCC < 4.4.6 */
181 	.reserved = { 0 },
182 
183 	V4L2_INIT_BT_TIMINGS(
184 		640, 1920,			/* min/max width */
185 		350, 1200,			/* min/max height */
186 		13000000, 165000000,		/* min/max pixelclock */
187 		/* standards */
188 		V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
189 			V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
190 		/* capabilities */
191 		V4L2_DV_BT_CAP_INTERLACED | V4L2_DV_BT_CAP_PROGRESSIVE |
192 			V4L2_DV_BT_CAP_REDUCED_BLANKING |
193 			V4L2_DV_BT_CAP_CUSTOM
194 	)
195 };
196 
197 /* regulator supplies */
198 static const char * const tda1997x_supply_name[] = {
199 	"DOVDD", /* Digital I/O supply */
200 	"DVDD",  /* Digital Core supply */
201 	"AVDD",  /* Analog supply */
202 };
203 
204 #define TDA1997X_NUM_SUPPLIES ARRAY_SIZE(tda1997x_supply_name)
205 
206 enum tda1997x_type {
207 	TDA19971,
208 	TDA19973,
209 };
210 
211 enum tda1997x_hdmi_pads {
212 	TDA1997X_PAD_SOURCE,
213 	TDA1997X_NUM_PADS,
214 };
215 
216 struct tda1997x_chip_info {
217 	enum tda1997x_type type;
218 	const char *name;
219 };
220 
221 struct tda1997x_state {
222 	const struct tda1997x_chip_info *info;
223 	struct tda1997x_platform_data pdata;
224 	struct i2c_client *client;
225 	struct i2c_client *client_cec;
226 	struct v4l2_subdev sd;
227 	struct regulator_bulk_data supplies[TDA1997X_NUM_SUPPLIES];
228 	struct media_pad pads[TDA1997X_NUM_PADS];
229 	struct mutex lock;
230 	struct mutex page_lock;
231 	char page;
232 
233 	/* detected info from chip */
234 	int chip_revision;
235 	char port_30bit;
236 	char output_2p5;
237 	char tmdsb_clk;
238 	char tmdsb_soc;
239 
240 	/* status info */
241 	char hdmi_status;
242 	char mptrw_in_progress;
243 	char activity_status;
244 	char input_detect[2];
245 
246 	/* video */
247 	struct hdmi_avi_infoframe avi_infoframe;
248 	struct v4l2_hdmi_colorimetry colorimetry;
249 	u32 rgb_quantization_range;
250 	struct v4l2_dv_timings timings;
251 	int fps;
252 	const struct color_matrix_coefs *conv;
253 	u32 mbus_codes[TDA1997X_MBUS_CODES];	/* available modes */
254 	u32 mbus_code;		/* current mode */
255 	u8 vid_fmt;
256 
257 	/* controls */
258 	struct v4l2_ctrl_handler hdl;
259 	struct v4l2_ctrl *detect_tx_5v_ctrl;
260 	struct v4l2_ctrl *rgb_quantization_range_ctrl;
261 
262 	/* audio */
263 	u8  audio_ch_alloc;
264 	int audio_samplerate;
265 	int audio_channels;
266 	int audio_samplesize;
267 	int audio_type;
268 	struct mutex audio_lock;
269 	struct snd_pcm_substream *audio_stream;
270 
271 	/* EDID */
272 	struct {
273 		u8 edid[256];
274 		u32 present;
275 		unsigned int blocks;
276 	} edid;
277 	struct delayed_work delayed_work_enable_hpd;
278 };
279 
280 static const struct v4l2_event tda1997x_ev_fmt = {
281 	.type = V4L2_EVENT_SOURCE_CHANGE,
282 	.u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
283 };
284 
285 static const struct tda1997x_chip_info tda1997x_chip_info[] = {
286 	[TDA19971] = {
287 		.type = TDA19971,
288 		.name = "tda19971",
289 	},
290 	[TDA19973] = {
291 		.type = TDA19973,
292 		.name = "tda19973",
293 	},
294 };
295 
296 static inline struct tda1997x_state *to_state(struct v4l2_subdev *sd)
297 {
298 	return container_of(sd, struct tda1997x_state, sd);
299 }
300 
301 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
302 {
303 	return &container_of(ctrl->handler, struct tda1997x_state, hdl)->sd;
304 }
305 
306 static int tda1997x_cec_read(struct v4l2_subdev *sd, u8 reg)
307 {
308 	struct tda1997x_state *state = to_state(sd);
309 	int val;
310 
311 	val = i2c_smbus_read_byte_data(state->client_cec, reg);
312 	if (val < 0) {
313 		v4l_err(state->client, "read reg error: reg=%2x\n", reg);
314 		val = -1;
315 	}
316 
317 	return val;
318 }
319 
320 static int tda1997x_cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
321 {
322 	struct tda1997x_state *state = to_state(sd);
323 	int ret = 0;
324 
325 	ret = i2c_smbus_write_byte_data(state->client_cec, reg, val);
326 	if (ret < 0) {
327 		v4l_err(state->client, "write reg error:reg=%2x,val=%2x\n",
328 			reg, val);
329 		ret = -1;
330 	}
331 
332 	return ret;
333 }
334 
335 /* -----------------------------------------------------------------------------
336  * I2C transfer
337  */
338 
339 static int tda1997x_setpage(struct v4l2_subdev *sd, u8 page)
340 {
341 	struct tda1997x_state *state = to_state(sd);
342 	int ret;
343 
344 	if (state->page != page) {
345 		ret = i2c_smbus_write_byte_data(state->client,
346 			REG_CURPAGE_00H, page);
347 		if (ret < 0) {
348 			v4l_err(state->client,
349 				"write reg error:reg=%2x,val=%2x\n",
350 				REG_CURPAGE_00H, page);
351 			return ret;
352 		}
353 		state->page = page;
354 	}
355 	return 0;
356 }
357 
358 static inline int io_read(struct v4l2_subdev *sd, u16 reg)
359 {
360 	struct tda1997x_state *state = to_state(sd);
361 	int val;
362 
363 	mutex_lock(&state->page_lock);
364 	if (tda1997x_setpage(sd, reg >> 8)) {
365 		val = -1;
366 		goto out;
367 	}
368 
369 	val = i2c_smbus_read_byte_data(state->client, reg&0xff);
370 	if (val < 0) {
371 		v4l_err(state->client, "read reg error: reg=%2x\n", reg & 0xff);
372 		val = -1;
373 		goto out;
374 	}
375 
376 out:
377 	mutex_unlock(&state->page_lock);
378 	return val;
379 }
380 
381 static inline long io_read16(struct v4l2_subdev *sd, u16 reg)
382 {
383 	int val;
384 	long lval = 0;
385 
386 	val = io_read(sd, reg);
387 	if (val < 0)
388 		return val;
389 	lval |= (val << 8);
390 	val = io_read(sd, reg + 1);
391 	if (val < 0)
392 		return val;
393 	lval |= val;
394 
395 	return lval;
396 }
397 
398 static inline long io_read24(struct v4l2_subdev *sd, u16 reg)
399 {
400 	int val;
401 	long lval = 0;
402 
403 	val = io_read(sd, reg);
404 	if (val < 0)
405 		return val;
406 	lval |= (val << 16);
407 	val = io_read(sd, reg + 1);
408 	if (val < 0)
409 		return val;
410 	lval |= (val << 8);
411 	val = io_read(sd, reg + 2);
412 	if (val < 0)
413 		return val;
414 	lval |= val;
415 
416 	return lval;
417 }
418 
419 static unsigned int io_readn(struct v4l2_subdev *sd, u16 reg, u8 len, u8 *data)
420 {
421 	int i;
422 	int sz = 0;
423 	int val;
424 
425 	for (i = 0; i < len; i++) {
426 		val = io_read(sd, reg + i);
427 		if (val < 0)
428 			break;
429 		data[i] = val;
430 		sz++;
431 	}
432 
433 	return sz;
434 }
435 
436 static int io_write(struct v4l2_subdev *sd, u16 reg, u8 val)
437 {
438 	struct tda1997x_state *state = to_state(sd);
439 	s32 ret = 0;
440 
441 	mutex_lock(&state->page_lock);
442 	if (tda1997x_setpage(sd, reg >> 8)) {
443 		ret = -1;
444 		goto out;
445 	}
446 
447 	ret = i2c_smbus_write_byte_data(state->client, reg & 0xff, val);
448 	if (ret < 0) {
449 		v4l_err(state->client, "write reg error:reg=%2x,val=%2x\n",
450 			reg&0xff, val);
451 		ret = -1;
452 		goto out;
453 	}
454 
455 out:
456 	mutex_unlock(&state->page_lock);
457 	return ret;
458 }
459 
460 static int io_write16(struct v4l2_subdev *sd, u16 reg, u16 val)
461 {
462 	int ret;
463 
464 	ret = io_write(sd, reg, (val >> 8) & 0xff);
465 	if (ret < 0)
466 		return ret;
467 	ret = io_write(sd, reg + 1, val & 0xff);
468 	if (ret < 0)
469 		return ret;
470 	return 0;
471 }
472 
473 static int io_write24(struct v4l2_subdev *sd, u16 reg, u32 val)
474 {
475 	int ret;
476 
477 	ret = io_write(sd, reg, (val >> 16) & 0xff);
478 	if (ret < 0)
479 		return ret;
480 	ret = io_write(sd, reg + 1, (val >> 8) & 0xff);
481 	if (ret < 0)
482 		return ret;
483 	ret = io_write(sd, reg + 2, val & 0xff);
484 	if (ret < 0)
485 		return ret;
486 	return 0;
487 }
488 
489 /* -----------------------------------------------------------------------------
490  * Hotplug
491  */
492 
493 enum hpd_mode {
494 	HPD_LOW_BP,	/* HPD low and pulse of at least 100ms */
495 	HPD_LOW_OTHER,	/* HPD low and pulse of at least 100ms */
496 	HPD_HIGH_BP,	/* HIGH */
497 	HPD_HIGH_OTHER,
498 	HPD_PULSE,	/* HPD low pulse */
499 };
500 
501 /* manual HPD (Hot Plug Detect) control */
502 static int tda1997x_manual_hpd(struct v4l2_subdev *sd, enum hpd_mode mode)
503 {
504 	u8 hpd_auto, hpd_pwr, hpd_man;
505 
506 	hpd_auto = io_read(sd, REG_HPD_AUTO_CTRL);
507 	hpd_pwr = io_read(sd, REG_HPD_POWER);
508 	hpd_man = io_read(sd, REG_HPD_MAN_CTRL);
509 
510 	/* mask out unused bits */
511 	hpd_man &= (HPD_MAN_CTRL_HPD_PULSE |
512 		    HPD_MAN_CTRL_5VEN |
513 		    HPD_MAN_CTRL_HPD_B |
514 		    HPD_MAN_CTRL_HPD_A);
515 
516 	switch (mode) {
517 	/* HPD low and pulse of at least 100ms */
518 	case HPD_LOW_BP:
519 		/* hpd_bp=0 */
520 		hpd_pwr &= ~HPD_POWER_BP_MASK;
521 		/* disable HPD_A and HPD_B */
522 		hpd_man &= ~(HPD_MAN_CTRL_HPD_A | HPD_MAN_CTRL_HPD_B);
523 		io_write(sd, REG_HPD_POWER, hpd_pwr);
524 		io_write(sd, REG_HPD_MAN_CTRL, hpd_man);
525 		break;
526 	/* HPD high */
527 	case HPD_HIGH_BP:
528 		/* hpd_bp=1 */
529 		hpd_pwr &= ~HPD_POWER_BP_MASK;
530 		hpd_pwr |= 1 << HPD_POWER_BP_SHIFT;
531 		io_write(sd, REG_HPD_POWER, hpd_pwr);
532 		break;
533 	/* HPD low and pulse of at least 100ms */
534 	case HPD_LOW_OTHER:
535 		/* disable HPD_A and HPD_B */
536 		hpd_man &= ~(HPD_MAN_CTRL_HPD_A | HPD_MAN_CTRL_HPD_B);
537 		/* hp_other=0 */
538 		hpd_auto &= ~HPD_AUTO_HP_OTHER;
539 		io_write(sd, REG_HPD_AUTO_CTRL, hpd_auto);
540 		io_write(sd, REG_HPD_MAN_CTRL, hpd_man);
541 		break;
542 	/* HPD high */
543 	case HPD_HIGH_OTHER:
544 		hpd_auto |= HPD_AUTO_HP_OTHER;
545 		io_write(sd, REG_HPD_AUTO_CTRL, hpd_auto);
546 		break;
547 	/* HPD low pulse */
548 	case HPD_PULSE:
549 		/* disable HPD_A and HPD_B */
550 		hpd_man &= ~(HPD_MAN_CTRL_HPD_A | HPD_MAN_CTRL_HPD_B);
551 		io_write(sd, REG_HPD_MAN_CTRL, hpd_man);
552 		break;
553 	}
554 
555 	return 0;
556 }
557 
558 static void tda1997x_delayed_work_enable_hpd(struct work_struct *work)
559 {
560 	struct delayed_work *dwork = to_delayed_work(work);
561 	struct tda1997x_state *state = container_of(dwork,
562 						    struct tda1997x_state,
563 						    delayed_work_enable_hpd);
564 	struct v4l2_subdev *sd = &state->sd;
565 
566 	v4l2_dbg(2, debug, sd, "%s\n", __func__);
567 
568 	/* Set HPD high */
569 	tda1997x_manual_hpd(sd, HPD_HIGH_OTHER);
570 	tda1997x_manual_hpd(sd, HPD_HIGH_BP);
571 
572 	state->edid.present = 1;
573 }
574 
575 static void tda1997x_disable_edid(struct v4l2_subdev *sd)
576 {
577 	struct tda1997x_state *state = to_state(sd);
578 
579 	v4l2_dbg(1, debug, sd, "%s\n", __func__);
580 	cancel_delayed_work_sync(&state->delayed_work_enable_hpd);
581 
582 	/* Set HPD low */
583 	tda1997x_manual_hpd(sd, HPD_LOW_BP);
584 }
585 
586 static void tda1997x_enable_edid(struct v4l2_subdev *sd)
587 {
588 	struct tda1997x_state *state = to_state(sd);
589 
590 	v4l2_dbg(1, debug, sd, "%s\n", __func__);
591 
592 	/* Enable hotplug after 100ms */
593 	schedule_delayed_work(&state->delayed_work_enable_hpd, HZ / 10);
594 }
595 
596 /* -----------------------------------------------------------------------------
597  * Signal Control
598  */
599 
600 /*
601  * configure vid_fmt based on mbus_code
602  */
603 static int
604 tda1997x_setup_format(struct tda1997x_state *state, u32 code)
605 {
606 	v4l_dbg(1, debug, state->client, "%s code=0x%x\n", __func__, code);
607 	switch (code) {
608 	case MEDIA_BUS_FMT_RGB121212_1X36:
609 	case MEDIA_BUS_FMT_RGB888_1X24:
610 	case MEDIA_BUS_FMT_YUV12_1X36:
611 	case MEDIA_BUS_FMT_YUV8_1X24:
612 		state->vid_fmt = OF_FMT_444;
613 		break;
614 	case MEDIA_BUS_FMT_UYVY12_1X24:
615 	case MEDIA_BUS_FMT_UYVY10_1X20:
616 	case MEDIA_BUS_FMT_UYVY8_1X16:
617 		state->vid_fmt = OF_FMT_422_SMPT;
618 		break;
619 	case MEDIA_BUS_FMT_UYVY12_2X12:
620 	case MEDIA_BUS_FMT_UYVY10_2X10:
621 	case MEDIA_BUS_FMT_UYVY8_2X8:
622 		state->vid_fmt = OF_FMT_422_CCIR;
623 		break;
624 	default:
625 		v4l_err(state->client, "incompatible format (0x%x)\n", code);
626 		return -EINVAL;
627 	}
628 	v4l_dbg(1, debug, state->client, "%s code=0x%x fmt=%s\n", __func__,
629 		code, vidfmt_names[state->vid_fmt]);
630 	state->mbus_code = code;
631 
632 	return 0;
633 }
634 
635 /*
636  * The color conversion matrix will convert between the colorimetry of the
637  * HDMI input to the desired output format RGB|YUV. RGB output is to be
638  * full-range and YUV is to be limited range.
639  *
640  * RGB full-range uses values from 0 to 255 which is recommended on a monitor
641  * and RGB Limited uses values from 16 to 236 (16=black, 235=white) which is
642  * typically recommended on a TV.
643  */
644 static void
645 tda1997x_configure_csc(struct v4l2_subdev *sd)
646 {
647 	struct tda1997x_state *state = to_state(sd);
648 	struct hdmi_avi_infoframe *avi = &state->avi_infoframe;
649 	struct v4l2_hdmi_colorimetry *c = &state->colorimetry;
650 	/* Blanking code values depend on output colorspace (RGB or YUV) */
651 	struct blanking_codes {
652 		s16 code_gy;
653 		s16 code_bu;
654 		s16 code_rv;
655 	};
656 	static const struct blanking_codes rgb_blanking = { 64, 64, 64 };
657 	static const struct blanking_codes yuv_blanking = { 64, 512, 512 };
658 	const struct blanking_codes *blanking_codes = NULL;
659 	u8 reg;
660 
661 	v4l_dbg(1, debug, state->client, "input:%s quant:%s output:%s\n",
662 		hdmi_colorspace_names[avi->colorspace],
663 		v4l2_quantization_names[c->quantization],
664 		vidfmt_names[state->vid_fmt]);
665 	state->conv = NULL;
666 	switch (state->vid_fmt) {
667 	/* RGB output */
668 	case OF_FMT_444:
669 		blanking_codes = &rgb_blanking;
670 		if (c->colorspace == V4L2_COLORSPACE_SRGB) {
671 			if (c->quantization == V4L2_QUANTIZATION_LIM_RANGE)
672 				state->conv = &conv_matrix[RGBLIMITED_RGBFULL];
673 		} else {
674 			if (c->colorspace == V4L2_COLORSPACE_REC709)
675 				state->conv = &conv_matrix[ITU709_RGBFULL];
676 			else if (c->colorspace == V4L2_COLORSPACE_SMPTE170M)
677 				state->conv = &conv_matrix[ITU601_RGBFULL];
678 		}
679 		break;
680 
681 	/* YUV output */
682 	case OF_FMT_422_SMPT: /* semi-planar */
683 	case OF_FMT_422_CCIR: /* CCIR656 */
684 		blanking_codes = &yuv_blanking;
685 		if ((c->colorspace == V4L2_COLORSPACE_SRGB) &&
686 		    (c->quantization == V4L2_QUANTIZATION_FULL_RANGE)) {
687 			if (state->timings.bt.height <= 576)
688 				state->conv = &conv_matrix[RGBFULL_ITU601];
689 			else
690 				state->conv = &conv_matrix[RGBFULL_ITU709];
691 		} else if ((c->colorspace == V4L2_COLORSPACE_SRGB) &&
692 			   (c->quantization == V4L2_QUANTIZATION_LIM_RANGE)) {
693 			if (state->timings.bt.height <= 576)
694 				state->conv = &conv_matrix[RGBLIMITED_ITU601];
695 			else
696 				state->conv = &conv_matrix[RGBLIMITED_ITU709];
697 		}
698 		break;
699 	}
700 
701 	if (state->conv) {
702 		v4l_dbg(1, debug, state->client, "%s\n",
703 			state->conv->name);
704 		/* enable matrix conversion */
705 		reg = io_read(sd, REG_VDP_CTRL);
706 		reg &= ~VDP_CTRL_MATRIX_BP;
707 		io_write(sd, REG_VDP_CTRL, reg);
708 		/* offset inputs */
709 		io_write16(sd, REG_VDP_MATRIX + 0, state->conv->offint1);
710 		io_write16(sd, REG_VDP_MATRIX + 2, state->conv->offint2);
711 		io_write16(sd, REG_VDP_MATRIX + 4, state->conv->offint3);
712 		/* coefficients */
713 		io_write16(sd, REG_VDP_MATRIX + 6, state->conv->p11coef);
714 		io_write16(sd, REG_VDP_MATRIX + 8, state->conv->p12coef);
715 		io_write16(sd, REG_VDP_MATRIX + 10, state->conv->p13coef);
716 		io_write16(sd, REG_VDP_MATRIX + 12, state->conv->p21coef);
717 		io_write16(sd, REG_VDP_MATRIX + 14, state->conv->p22coef);
718 		io_write16(sd, REG_VDP_MATRIX + 16, state->conv->p23coef);
719 		io_write16(sd, REG_VDP_MATRIX + 18, state->conv->p31coef);
720 		io_write16(sd, REG_VDP_MATRIX + 20, state->conv->p32coef);
721 		io_write16(sd, REG_VDP_MATRIX + 22, state->conv->p33coef);
722 		/* offset outputs */
723 		io_write16(sd, REG_VDP_MATRIX + 24, state->conv->offout1);
724 		io_write16(sd, REG_VDP_MATRIX + 26, state->conv->offout2);
725 		io_write16(sd, REG_VDP_MATRIX + 28, state->conv->offout3);
726 	} else {
727 		/* disable matrix conversion */
728 		reg = io_read(sd, REG_VDP_CTRL);
729 		reg |= VDP_CTRL_MATRIX_BP;
730 		io_write(sd, REG_VDP_CTRL, reg);
731 	}
732 
733 	/* SetBlankingCodes */
734 	if (blanking_codes) {
735 		io_write16(sd, REG_BLK_GY, blanking_codes->code_gy);
736 		io_write16(sd, REG_BLK_BU, blanking_codes->code_bu);
737 		io_write16(sd, REG_BLK_RV, blanking_codes->code_rv);
738 	}
739 }
740 
741 /* Configure frame detection window and VHREF timing generator */
742 static void
743 tda1997x_configure_vhref(struct v4l2_subdev *sd)
744 {
745 	struct tda1997x_state *state = to_state(sd);
746 	const struct v4l2_bt_timings *bt = &state->timings.bt;
747 	int width, lines;
748 	u16 href_start, href_end;
749 	u16 vref_f1_start, vref_f2_start;
750 	u8 vref_f1_width, vref_f2_width;
751 	u8 field_polarity;
752 	u16 fieldref_f1_start, fieldref_f2_start;
753 	u8 reg;
754 
755 	href_start = bt->hbackporch + bt->hsync + 1;
756 	href_end = href_start + bt->width;
757 	vref_f1_start = bt->height + bt->vbackporch + bt->vsync +
758 			bt->il_vbackporch + bt->il_vsync +
759 			bt->il_vfrontporch;
760 	vref_f1_width = bt->vbackporch + bt->vsync + bt->vfrontporch;
761 	vref_f2_start = 0;
762 	vref_f2_width = 0;
763 	fieldref_f1_start = 0;
764 	fieldref_f2_start = 0;
765 	if (bt->interlaced) {
766 		vref_f2_start = (bt->height / 2) +
767 				(bt->il_vbackporch + bt->il_vsync - 1);
768 		vref_f2_width = bt->il_vbackporch + bt->il_vsync +
769 				bt->il_vfrontporch;
770 		fieldref_f2_start = vref_f2_start + bt->il_vfrontporch +
771 				    fieldref_f1_start;
772 	}
773 	field_polarity = 0;
774 
775 	width = V4L2_DV_BT_FRAME_WIDTH(bt);
776 	lines = V4L2_DV_BT_FRAME_HEIGHT(bt);
777 
778 	/*
779 	 * Configure Frame Detection Window:
780 	 *  horiz area where the VHREF module consider a VSYNC a new frame
781 	 */
782 	io_write16(sd, REG_FDW_S, 0x2ef); /* start position */
783 	io_write16(sd, REG_FDW_E, 0x141); /* end position */
784 
785 	/* Set Pixel And Line Counters */
786 	if (state->chip_revision == 0)
787 		io_write16(sd, REG_PXCNT_PR, 4);
788 	else
789 		io_write16(sd, REG_PXCNT_PR, 1);
790 	io_write16(sd, REG_PXCNT_NPIX, width & MASK_VHREF);
791 	io_write16(sd, REG_LCNT_PR, 1);
792 	io_write16(sd, REG_LCNT_NLIN, lines & MASK_VHREF);
793 
794 	/*
795 	 * Configure the VHRef timing generator responsible for rebuilding all
796 	 * horiz and vert synch and ref signals from its input allowing auto
797 	 * detection algorithms and forcing predefined modes (480i & 576i)
798 	 */
799 	reg = VHREF_STD_DET_OFF << VHREF_STD_DET_SHIFT;
800 	io_write(sd, REG_VHREF_CTRL, reg);
801 
802 	/*
803 	 * Configure the VHRef timing values. In case the VHREF generator has
804 	 * been configured in manual mode, this will allow to manually set all
805 	 * horiz and vert ref values (non-active pixel areas) of the generator
806 	 * and allows setting the frame reference params.
807 	 */
808 	/* horizontal reference start/end */
809 	io_write16(sd, REG_HREF_S, href_start & MASK_VHREF);
810 	io_write16(sd, REG_HREF_E, href_end & MASK_VHREF);
811 	/* vertical reference f1 start/end */
812 	io_write16(sd, REG_VREF_F1_S, vref_f1_start & MASK_VHREF);
813 	io_write(sd, REG_VREF_F1_WIDTH, vref_f1_width);
814 	/* vertical reference f2 start/end */
815 	io_write16(sd, REG_VREF_F2_S, vref_f2_start & MASK_VHREF);
816 	io_write(sd, REG_VREF_F2_WIDTH, vref_f2_width);
817 
818 	/* F1/F2 FREF, field polarity */
819 	reg = fieldref_f1_start & MASK_VHREF;
820 	reg |= field_polarity << 8;
821 	io_write16(sd, REG_FREF_F1_S, reg);
822 	reg = fieldref_f2_start & MASK_VHREF;
823 	io_write16(sd, REG_FREF_F2_S, reg);
824 }
825 
826 /* Configure Video Output port signals */
827 static int
828 tda1997x_configure_vidout(struct tda1997x_state *state)
829 {
830 	struct v4l2_subdev *sd = &state->sd;
831 	struct tda1997x_platform_data *pdata = &state->pdata;
832 	u8 prefilter;
833 	u8 reg;
834 
835 	/* Configure pixel clock generator: delay, polarity, rate */
836 	reg = (state->vid_fmt == OF_FMT_422_CCIR) ?
837 	       PCLK_SEL_X2 : PCLK_SEL_X1;
838 	reg |= pdata->vidout_delay_pclk << PCLK_DELAY_SHIFT;
839 	reg |= pdata->vidout_inv_pclk << PCLK_INV_SHIFT;
840 	io_write(sd, REG_PCLK, reg);
841 
842 	/* Configure pre-filter */
843 	prefilter = 0; /* filters off */
844 	/* YUV422 mode requires conversion */
845 	if ((state->vid_fmt == OF_FMT_422_SMPT) ||
846 	    (state->vid_fmt == OF_FMT_422_CCIR)) {
847 		/* 2/7 taps for Rv and Bu */
848 		prefilter = FILTERS_CTRL_2_7TAP << FILTERS_CTRL_BU_SHIFT |
849 			    FILTERS_CTRL_2_7TAP << FILTERS_CTRL_RV_SHIFT;
850 	}
851 	io_write(sd, REG_FILTERS_CTRL, prefilter);
852 
853 	/* Configure video port */
854 	reg = state->vid_fmt & OF_FMT_MASK;
855 	if (state->vid_fmt == OF_FMT_422_CCIR)
856 		reg |= (OF_BLK | OF_TRC);
857 	reg |= OF_VP_ENABLE;
858 	io_write(sd, REG_OF, reg);
859 
860 	/* Configure formatter and conversions */
861 	reg = io_read(sd, REG_VDP_CTRL);
862 	/* pre-filter is needed unless (REG_FILTERS_CTRL == 0) */
863 	if (!prefilter)
864 		reg |= VDP_CTRL_PREFILTER_BP;
865 	else
866 		reg &= ~VDP_CTRL_PREFILTER_BP;
867 	/* formatter is needed for YUV422 and for trc/blc codes */
868 	if (state->vid_fmt == OF_FMT_444)
869 		reg |= VDP_CTRL_FORMATTER_BP;
870 	/* formatter and compdel needed for timing/blanking codes */
871 	else
872 		reg &= ~(VDP_CTRL_FORMATTER_BP | VDP_CTRL_COMPDEL_BP);
873 	/* activate compdel for small sync delays */
874 	if ((pdata->vidout_delay_vs < 4) || (pdata->vidout_delay_hs < 4))
875 		reg &= ~VDP_CTRL_COMPDEL_BP;
876 	io_write(sd, REG_VDP_CTRL, reg);
877 
878 	/* Configure DE output signal: delay, polarity, and source */
879 	reg = pdata->vidout_delay_de << DE_FREF_DELAY_SHIFT |
880 	      pdata->vidout_inv_de << DE_FREF_INV_SHIFT |
881 	      pdata->vidout_sel_de << DE_FREF_SEL_SHIFT;
882 	io_write(sd, REG_DE_FREF, reg);
883 
884 	/* Configure HS/HREF output signal: delay, polarity, and source */
885 	if (state->vid_fmt != OF_FMT_422_CCIR) {
886 		reg = pdata->vidout_delay_hs << HS_HREF_DELAY_SHIFT |
887 		      pdata->vidout_inv_hs << HS_HREF_INV_SHIFT |
888 		      pdata->vidout_sel_hs << HS_HREF_SEL_SHIFT;
889 	} else
890 		reg = HS_HREF_SEL_NONE << HS_HREF_SEL_SHIFT;
891 	io_write(sd, REG_HS_HREF, reg);
892 
893 	/* Configure VS/VREF output signal: delay, polarity, and source */
894 	if (state->vid_fmt != OF_FMT_422_CCIR) {
895 		reg = pdata->vidout_delay_vs << VS_VREF_DELAY_SHIFT |
896 		      pdata->vidout_inv_vs << VS_VREF_INV_SHIFT |
897 		      pdata->vidout_sel_vs << VS_VREF_SEL_SHIFT;
898 	} else
899 		reg = VS_VREF_SEL_NONE << VS_VREF_SEL_SHIFT;
900 	io_write(sd, REG_VS_VREF, reg);
901 
902 	return 0;
903 }
904 
905 /* Configure Audio output port signals */
906 static int
907 tda1997x_configure_audout(struct v4l2_subdev *sd, u8 channel_assignment)
908 {
909 	struct tda1997x_state *state = to_state(sd);
910 	struct tda1997x_platform_data *pdata = &state->pdata;
911 	bool sp_used_by_fifo = true;
912 	u8 reg;
913 
914 	if (!pdata->audout_format)
915 		return 0;
916 
917 	/* channel assignment (CEA-861-D Table 20) */
918 	io_write(sd, REG_AUDIO_PATH, channel_assignment);
919 
920 	/* Audio output configuration */
921 	reg = 0;
922 	switch (pdata->audout_format) {
923 	case AUDFMT_TYPE_I2S:
924 		reg |= AUDCFG_BUS_I2S << AUDCFG_BUS_SHIFT;
925 		break;
926 	case AUDFMT_TYPE_SPDIF:
927 		reg |= AUDCFG_BUS_SPDIF << AUDCFG_BUS_SHIFT;
928 		break;
929 	}
930 	switch (state->audio_type) {
931 	case AUDCFG_TYPE_PCM:
932 		reg |= AUDCFG_TYPE_PCM << AUDCFG_TYPE_SHIFT;
933 		break;
934 	case AUDCFG_TYPE_OBA:
935 		reg |= AUDCFG_TYPE_OBA << AUDCFG_TYPE_SHIFT;
936 		break;
937 	case AUDCFG_TYPE_DST:
938 		reg |= AUDCFG_TYPE_DST << AUDCFG_TYPE_SHIFT;
939 		sp_used_by_fifo = false;
940 		break;
941 	case AUDCFG_TYPE_HBR:
942 		reg |= AUDCFG_TYPE_HBR << AUDCFG_TYPE_SHIFT;
943 		if (pdata->audout_layout == 1) {
944 			/* demuxed via AP0:AP3 */
945 			reg |= AUDCFG_HBR_DEMUX << AUDCFG_HBR_SHIFT;
946 			if (pdata->audout_format == AUDFMT_TYPE_SPDIF)
947 				sp_used_by_fifo = false;
948 		} else {
949 			/* straight via AP0 */
950 			reg |= AUDCFG_HBR_STRAIGHT << AUDCFG_HBR_SHIFT;
951 		}
952 		break;
953 	}
954 	if (pdata->audout_width == 32)
955 		reg |= AUDCFG_I2SW_32 << AUDCFG_I2SW_SHIFT;
956 	else
957 		reg |= AUDCFG_I2SW_16 << AUDCFG_I2SW_SHIFT;
958 
959 	/* automatic hardware mute */
960 	if (pdata->audio_auto_mute)
961 		reg |= AUDCFG_AUTO_MUTE_EN;
962 	/* clock polarity */
963 	if (pdata->audout_invert_clk)
964 		reg |= AUDCFG_CLK_INVERT;
965 	io_write(sd, REG_AUDCFG, reg);
966 
967 	/* audio layout */
968 	reg = (pdata->audout_layout) ? AUDIO_LAYOUT_LAYOUT1 : 0;
969 	if (!pdata->audout_layoutauto)
970 		reg |= AUDIO_LAYOUT_MANUAL;
971 	if (sp_used_by_fifo)
972 		reg |= AUDIO_LAYOUT_SP_FLAG;
973 	io_write(sd, REG_AUDIO_LAYOUT, reg);
974 
975 	/* FIFO Latency value */
976 	io_write(sd, REG_FIFO_LATENCY_VAL, 0x80);
977 
978 	/* Audio output port config */
979 	if (sp_used_by_fifo) {
980 		reg = AUDIO_OUT_ENABLE_AP0;
981 		if (channel_assignment >= 0x01)
982 			reg |= AUDIO_OUT_ENABLE_AP1;
983 		if (channel_assignment >= 0x04)
984 			reg |= AUDIO_OUT_ENABLE_AP2;
985 		if (channel_assignment >= 0x0c)
986 			reg |= AUDIO_OUT_ENABLE_AP3;
987 		/* specific cases where AP1 is not used */
988 		if ((channel_assignment == 0x04)
989 		 || (channel_assignment == 0x08)
990 		 || (channel_assignment == 0x0c)
991 		 || (channel_assignment == 0x10)
992 		 || (channel_assignment == 0x14)
993 		 || (channel_assignment == 0x18)
994 		 || (channel_assignment == 0x1c))
995 			reg &= ~AUDIO_OUT_ENABLE_AP1;
996 		/* specific cases where AP2 is not used */
997 		if ((channel_assignment >= 0x14)
998 		 && (channel_assignment <= 0x17))
999 			reg &= ~AUDIO_OUT_ENABLE_AP2;
1000 	} else {
1001 		reg = AUDIO_OUT_ENABLE_AP3 |
1002 		      AUDIO_OUT_ENABLE_AP2 |
1003 		      AUDIO_OUT_ENABLE_AP1 |
1004 		      AUDIO_OUT_ENABLE_AP0;
1005 	}
1006 	if (pdata->audout_format == AUDFMT_TYPE_I2S)
1007 		reg |= (AUDIO_OUT_ENABLE_ACLK | AUDIO_OUT_ENABLE_WS);
1008 	io_write(sd, REG_AUDIO_OUT_ENABLE, reg);
1009 
1010 	/* reset test mode to normal audio freq auto selection */
1011 	io_write(sd, REG_TEST_MODE, 0x00);
1012 
1013 	return 0;
1014 }
1015 
1016 /* Soft Reset of specific hdmi info */
1017 static int
1018 tda1997x_hdmi_info_reset(struct v4l2_subdev *sd, u8 info_rst, bool reset_sus)
1019 {
1020 	u8 reg;
1021 
1022 	/* reset infoframe engine packets */
1023 	reg = io_read(sd, REG_HDMI_INFO_RST);
1024 	io_write(sd, REG_HDMI_INFO_RST, info_rst);
1025 
1026 	/* if infoframe engine has been reset clear INT_FLG_MODE */
1027 	if (reg & RESET_IF) {
1028 		reg = io_read(sd, REG_INT_FLG_CLR_MODE);
1029 		io_write(sd, REG_INT_FLG_CLR_MODE, reg);
1030 	}
1031 
1032 	/* Disable REFTIM to restart start-up-sequencer (SUS) */
1033 	reg = io_read(sd, REG_RATE_CTRL);
1034 	reg &= ~RATE_REFTIM_ENABLE;
1035 	if (!reset_sus)
1036 		reg |= RATE_REFTIM_ENABLE;
1037 	reg = io_write(sd, REG_RATE_CTRL, reg);
1038 
1039 	return 0;
1040 }
1041 
1042 static void
1043 tda1997x_power_mode(struct tda1997x_state *state, bool enable)
1044 {
1045 	struct v4l2_subdev *sd = &state->sd;
1046 	u8 reg;
1047 
1048 	if (enable) {
1049 		/* Automatic control of TMDS */
1050 		io_write(sd, REG_PON_OVR_EN, PON_DIS);
1051 		/* Enable current bias unit */
1052 		io_write(sd, REG_CFG1, PON_EN);
1053 		/* Enable deep color PLL */
1054 		io_write(sd, REG_DEEP_PLL7_BYP, PON_DIS);
1055 		/* Output buffers active */
1056 		reg = io_read(sd, REG_OF);
1057 		reg &= ~OF_VP_ENABLE;
1058 		io_write(sd, REG_OF, reg);
1059 	} else {
1060 		/* Power down EDID mode sequence */
1061 		/* Output buffers in HiZ */
1062 		reg = io_read(sd, REG_OF);
1063 		reg |= OF_VP_ENABLE;
1064 		io_write(sd, REG_OF, reg);
1065 		/* Disable deep color PLL */
1066 		io_write(sd, REG_DEEP_PLL7_BYP, PON_EN);
1067 		/* Disable current bias unit */
1068 		io_write(sd, REG_CFG1, PON_DIS);
1069 		/* Manual control of TMDS */
1070 		io_write(sd, REG_PON_OVR_EN, PON_EN);
1071 	}
1072 }
1073 
1074 static bool
1075 tda1997x_detect_tx_5v(struct v4l2_subdev *sd)
1076 {
1077 	u8 reg = io_read(sd, REG_DETECT_5V);
1078 
1079 	return ((reg & DETECT_5V_SEL) ? 1 : 0);
1080 }
1081 
1082 static bool
1083 tda1997x_detect_tx_hpd(struct v4l2_subdev *sd)
1084 {
1085 	u8 reg = io_read(sd, REG_DETECT_5V);
1086 
1087 	return ((reg & DETECT_HPD) ? 1 : 0);
1088 }
1089 
1090 static int
1091 tda1997x_detect_std(struct tda1997x_state *state,
1092 		    struct v4l2_dv_timings *timings)
1093 {
1094 	struct v4l2_subdev *sd = &state->sd;
1095 	u32 vper;
1096 	u16 hper;
1097 	u16 hsper;
1098 	int i;
1099 
1100 	/*
1101 	 * Read the FMT registers
1102 	 *   REG_V_PER: Period of a frame (or two fields) in MCLK(27MHz) cycles
1103 	 *   REG_H_PER: Period of a line in MCLK(27MHz) cycles
1104 	 *   REG_HS_WIDTH: Period of horiz sync pulse in MCLK(27MHz) cycles
1105 	 */
1106 	vper = io_read24(sd, REG_V_PER) & MASK_VPER;
1107 	hper = io_read16(sd, REG_H_PER) & MASK_HPER;
1108 	hsper = io_read16(sd, REG_HS_WIDTH) & MASK_HSWIDTH;
1109 	v4l2_dbg(1, debug, sd, "Signal Timings: %u/%u/%u\n", vper, hper, hsper);
1110 
1111 	if (!state->input_detect[0] && !state->input_detect[1])
1112 		return -ENOLINK;
1113 
1114 	for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
1115 		const struct v4l2_bt_timings *bt;
1116 		u32 lines, width, _hper, _hsper;
1117 		u32 vmin, vmax, hmin, hmax, hsmin, hsmax;
1118 		bool vmatch, hmatch, hsmatch;
1119 
1120 		bt = &v4l2_dv_timings_presets[i].bt;
1121 		width = V4L2_DV_BT_FRAME_WIDTH(bt);
1122 		lines = V4L2_DV_BT_FRAME_HEIGHT(bt);
1123 		_hper = (u32)bt->pixelclock / width;
1124 		if (bt->interlaced)
1125 			lines /= 2;
1126 		/* vper +/- 0.7% */
1127 		vmin = ((27000000 / 1000) * 993) / _hper * lines;
1128 		vmax = ((27000000 / 1000) * 1007) / _hper * lines;
1129 		/* hper +/- 1.0% */
1130 		hmin = ((27000000 / 100) * 99) / _hper;
1131 		hmax = ((27000000 / 100) * 101) / _hper;
1132 		/* hsper +/- 2 (take care to avoid 32bit overflow) */
1133 		_hsper = 27000 * bt->hsync / ((u32)bt->pixelclock/1000);
1134 		hsmin = _hsper - 2;
1135 		hsmax = _hsper + 2;
1136 
1137 		/* vmatch matches the framerate */
1138 		vmatch = ((vper <= vmax) && (vper >= vmin)) ? 1 : 0;
1139 		/* hmatch matches the width */
1140 		hmatch = ((hper <= hmax) && (hper >= hmin)) ? 1 : 0;
1141 		/* hsmatch matches the hswidth */
1142 		hsmatch = ((hsper <= hsmax) && (hsper >= hsmin)) ? 1 : 0;
1143 		if (hmatch && vmatch && hsmatch) {
1144 			v4l2_print_dv_timings(sd->name, "Detected format: ",
1145 					      &v4l2_dv_timings_presets[i],
1146 					      false);
1147 			if (timings)
1148 				*timings = v4l2_dv_timings_presets[i];
1149 			return 0;
1150 		}
1151 	}
1152 
1153 	v4l_err(state->client, "no resolution match for timings: %d/%d/%d\n",
1154 		vper, hper, hsper);
1155 	return -ERANGE;
1156 }
1157 
1158 /* some sort of errata workaround for chip revision 0 (N1) */
1159 static void tda1997x_reset_n1(struct tda1997x_state *state)
1160 {
1161 	struct v4l2_subdev *sd = &state->sd;
1162 	u8 reg;
1163 
1164 	/* clear HDMI mode flag in BCAPS */
1165 	io_write(sd, REG_CLK_CFG, CLK_CFG_SEL_ACLK_EN | CLK_CFG_SEL_ACLK);
1166 	io_write(sd, REG_PON_OVR_EN, PON_EN);
1167 	io_write(sd, REG_PON_CBIAS, PON_EN);
1168 	io_write(sd, REG_PON_PLL, PON_EN);
1169 
1170 	reg = io_read(sd, REG_MODE_REC_CFG1);
1171 	reg &= ~0x06;
1172 	reg |= 0x02;
1173 	io_write(sd, REG_MODE_REC_CFG1, reg);
1174 	io_write(sd, REG_CLK_CFG, CLK_CFG_DIS);
1175 	io_write(sd, REG_PON_OVR_EN, PON_DIS);
1176 	reg = io_read(sd, REG_MODE_REC_CFG1);
1177 	reg &= ~0x06;
1178 	io_write(sd, REG_MODE_REC_CFG1, reg);
1179 }
1180 
1181 /*
1182  * Activity detection must only be notified when stable_clk_x AND active_x
1183  * bits are set to 1. If only stable_clk_x bit is set to 1 but not
1184  * active_x, it means that the TMDS clock is not in the defined range
1185  * and activity detection must not be notified.
1186  */
1187 static u8
1188 tda1997x_read_activity_status_regs(struct v4l2_subdev *sd)
1189 {
1190 	u8 reg, status = 0;
1191 
1192 	/* Read CLK_A_STATUS register */
1193 	reg = io_read(sd, REG_CLK_A_STATUS);
1194 	/* ignore if not active */
1195 	if ((reg & MASK_CLK_STABLE) && !(reg & MASK_CLK_ACTIVE))
1196 		reg &= ~MASK_CLK_STABLE;
1197 	status |= ((reg & MASK_CLK_STABLE) >> 2);
1198 
1199 	/* Read CLK_B_STATUS register */
1200 	reg = io_read(sd, REG_CLK_B_STATUS);
1201 	/* ignore if not active */
1202 	if ((reg & MASK_CLK_STABLE) && !(reg & MASK_CLK_ACTIVE))
1203 		reg &= ~MASK_CLK_STABLE;
1204 	status |= ((reg & MASK_CLK_STABLE) >> 1);
1205 
1206 	/* Read the SUS_STATUS register */
1207 	reg = io_read(sd, REG_SUS_STATUS);
1208 
1209 	/* If state = 5 => TMDS is locked */
1210 	if ((reg & MASK_SUS_STATUS) == LAST_STATE_REACHED)
1211 		status |= MASK_SUS_STATE;
1212 	else
1213 		status &= ~MASK_SUS_STATE;
1214 
1215 	return status;
1216 }
1217 
1218 static void
1219 set_rgb_quantization_range(struct tda1997x_state *state)
1220 {
1221 	struct v4l2_hdmi_colorimetry *c = &state->colorimetry;
1222 
1223 	state->colorimetry = v4l2_hdmi_rx_colorimetry(&state->avi_infoframe,
1224 						      NULL,
1225 						      state->timings.bt.height);
1226 	/* If ycbcr_enc is V4L2_YCBCR_ENC_DEFAULT, we receive RGB */
1227 	if (c->ycbcr_enc == V4L2_YCBCR_ENC_DEFAULT) {
1228 		switch (state->rgb_quantization_range) {
1229 		case V4L2_DV_RGB_RANGE_LIMITED:
1230 			c->quantization = V4L2_QUANTIZATION_FULL_RANGE;
1231 			break;
1232 		case V4L2_DV_RGB_RANGE_FULL:
1233 			c->quantization = V4L2_QUANTIZATION_LIM_RANGE;
1234 			break;
1235 		}
1236 	}
1237 	v4l_dbg(1, debug, state->client,
1238 		"colorspace=%d/%d colorimetry=%d range=%s content=%d\n",
1239 		state->avi_infoframe.colorspace, c->colorspace,
1240 		state->avi_infoframe.colorimetry,
1241 		v4l2_quantization_names[c->quantization],
1242 		state->avi_infoframe.content_type);
1243 }
1244 
1245 /* parse an infoframe and do some sanity checks on it */
1246 static unsigned int
1247 tda1997x_parse_infoframe(struct tda1997x_state *state, u16 addr)
1248 {
1249 	struct v4l2_subdev *sd = &state->sd;
1250 	union hdmi_infoframe frame;
1251 	u8 buffer[40] = { 0 };
1252 	u8 reg;
1253 	int len, err;
1254 
1255 	/* read data */
1256 	len = io_readn(sd, addr, sizeof(buffer), buffer);
1257 	err = hdmi_infoframe_unpack(&frame, buffer, len);
1258 	if (err) {
1259 		v4l_err(state->client,
1260 			"failed parsing %d byte infoframe: 0x%04x/0x%02x\n",
1261 			len, addr, buffer[0]);
1262 		return err;
1263 	}
1264 	hdmi_infoframe_log(KERN_INFO, &state->client->dev, &frame);
1265 	switch (frame.any.type) {
1266 	/* Audio InfoFrame: see HDMI spec 8.2.2 */
1267 	case HDMI_INFOFRAME_TYPE_AUDIO:
1268 		/* sample rate */
1269 		switch (frame.audio.sample_frequency) {
1270 		case HDMI_AUDIO_SAMPLE_FREQUENCY_32000:
1271 			state->audio_samplerate = 32000;
1272 			break;
1273 		case HDMI_AUDIO_SAMPLE_FREQUENCY_44100:
1274 			state->audio_samplerate = 44100;
1275 			break;
1276 		case HDMI_AUDIO_SAMPLE_FREQUENCY_48000:
1277 			state->audio_samplerate = 48000;
1278 			break;
1279 		case HDMI_AUDIO_SAMPLE_FREQUENCY_88200:
1280 			state->audio_samplerate = 88200;
1281 			break;
1282 		case HDMI_AUDIO_SAMPLE_FREQUENCY_96000:
1283 			state->audio_samplerate = 96000;
1284 			break;
1285 		case HDMI_AUDIO_SAMPLE_FREQUENCY_176400:
1286 			state->audio_samplerate = 176400;
1287 			break;
1288 		case HDMI_AUDIO_SAMPLE_FREQUENCY_192000:
1289 			state->audio_samplerate = 192000;
1290 			break;
1291 		default:
1292 		case HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM:
1293 			break;
1294 		}
1295 
1296 		/* sample size */
1297 		switch (frame.audio.sample_size) {
1298 		case HDMI_AUDIO_SAMPLE_SIZE_16:
1299 			state->audio_samplesize = 16;
1300 			break;
1301 		case HDMI_AUDIO_SAMPLE_SIZE_20:
1302 			state->audio_samplesize = 20;
1303 			break;
1304 		case HDMI_AUDIO_SAMPLE_SIZE_24:
1305 			state->audio_samplesize = 24;
1306 			break;
1307 		case HDMI_AUDIO_SAMPLE_SIZE_STREAM:
1308 		default:
1309 			break;
1310 		}
1311 
1312 		/* Channel Count */
1313 		state->audio_channels = frame.audio.channels;
1314 		if (frame.audio.channel_allocation &&
1315 		    frame.audio.channel_allocation != state->audio_ch_alloc) {
1316 			/* use the channel assignment from the infoframe */
1317 			state->audio_ch_alloc = frame.audio.channel_allocation;
1318 			tda1997x_configure_audout(sd, state->audio_ch_alloc);
1319 			/* reset the audio FIFO */
1320 			tda1997x_hdmi_info_reset(sd, RESET_AUDIO, false);
1321 		}
1322 		break;
1323 
1324 	/* Auxiliary Video information (AVI) InfoFrame: see HDMI spec 8.2.1 */
1325 	case HDMI_INFOFRAME_TYPE_AVI:
1326 		state->avi_infoframe = frame.avi;
1327 		set_rgb_quantization_range(state);
1328 
1329 		/* configure upsampler: 0=bypass 1=repeatchroma 2=interpolate */
1330 		reg = io_read(sd, REG_PIX_REPEAT);
1331 		reg &= ~PIX_REPEAT_MASK_UP_SEL;
1332 		if (frame.avi.colorspace == HDMI_COLORSPACE_YUV422)
1333 			reg |= (PIX_REPEAT_CHROMA << PIX_REPEAT_SHIFT);
1334 		io_write(sd, REG_PIX_REPEAT, reg);
1335 
1336 		/* ConfigurePixelRepeater: repeat n-times each pixel */
1337 		reg = io_read(sd, REG_PIX_REPEAT);
1338 		reg &= ~PIX_REPEAT_MASK_REP;
1339 		reg |= frame.avi.pixel_repeat;
1340 		io_write(sd, REG_PIX_REPEAT, reg);
1341 
1342 		/* configure the receiver with the new colorspace */
1343 		tda1997x_configure_csc(sd);
1344 		break;
1345 	default:
1346 		break;
1347 	}
1348 	return 0;
1349 }
1350 
1351 static void tda1997x_irq_sus(struct tda1997x_state *state, u8 *flags)
1352 {
1353 	struct v4l2_subdev *sd = &state->sd;
1354 	u8 reg, source;
1355 
1356 	source = io_read(sd, REG_INT_FLG_CLR_SUS);
1357 	io_write(sd, REG_INT_FLG_CLR_SUS, source);
1358 
1359 	if (source & MASK_MPT) {
1360 		/* reset MTP in use flag if set */
1361 		if (state->mptrw_in_progress)
1362 			state->mptrw_in_progress = 0;
1363 	}
1364 
1365 	if (source & MASK_SUS_END) {
1366 		/* reset audio FIFO */
1367 		reg = io_read(sd, REG_HDMI_INFO_RST);
1368 		reg |= MASK_SR_FIFO_FIFO_CTRL;
1369 		io_write(sd, REG_HDMI_INFO_RST, reg);
1370 		reg &= ~MASK_SR_FIFO_FIFO_CTRL;
1371 		io_write(sd, REG_HDMI_INFO_RST, reg);
1372 
1373 		/* reset HDMI flags */
1374 		state->hdmi_status = 0;
1375 	}
1376 
1377 	/* filter FMT interrupt based on SUS state */
1378 	reg = io_read(sd, REG_SUS_STATUS);
1379 	if (((reg & MASK_SUS_STATUS) != LAST_STATE_REACHED)
1380 	   || (source & MASK_MPT)) {
1381 		source &= ~MASK_FMT;
1382 	}
1383 
1384 	if (source & (MASK_FMT | MASK_SUS_END)) {
1385 		reg = io_read(sd, REG_SUS_STATUS);
1386 		if ((reg & MASK_SUS_STATUS) != LAST_STATE_REACHED) {
1387 			v4l_err(state->client, "BAD SUS STATUS\n");
1388 			return;
1389 		}
1390 		if (debug)
1391 			tda1997x_detect_std(state, NULL);
1392 		/* notify user of change in resolution */
1393 		v4l2_subdev_notify_event(&state->sd, &tda1997x_ev_fmt);
1394 	}
1395 }
1396 
1397 static void tda1997x_irq_ddc(struct tda1997x_state *state, u8 *flags)
1398 {
1399 	struct v4l2_subdev *sd = &state->sd;
1400 	u8 source;
1401 
1402 	source = io_read(sd, REG_INT_FLG_CLR_DDC);
1403 	io_write(sd, REG_INT_FLG_CLR_DDC, source);
1404 	if (source & MASK_EDID_MTP) {
1405 		/* reset MTP in use flag if set */
1406 		if (state->mptrw_in_progress)
1407 			state->mptrw_in_progress = 0;
1408 	}
1409 
1410 	/* Detection of +5V */
1411 	if (source & MASK_DET_5V) {
1412 		v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
1413 				 tda1997x_detect_tx_5v(sd));
1414 	}
1415 }
1416 
1417 static void tda1997x_irq_rate(struct tda1997x_state *state, u8 *flags)
1418 {
1419 	struct v4l2_subdev *sd = &state->sd;
1420 	u8 reg, source;
1421 
1422 	u8 irq_status;
1423 
1424 	source = io_read(sd, REG_INT_FLG_CLR_RATE);
1425 	io_write(sd, REG_INT_FLG_CLR_RATE, source);
1426 
1427 	/* read status regs */
1428 	irq_status = tda1997x_read_activity_status_regs(sd);
1429 
1430 	/*
1431 	 * read clock status reg until INT_FLG_CLR_RATE is still 0
1432 	 * after the read to make sure its the last one
1433 	 */
1434 	reg = source;
1435 	while (reg != 0) {
1436 		irq_status = tda1997x_read_activity_status_regs(sd);
1437 		reg = io_read(sd, REG_INT_FLG_CLR_RATE);
1438 		io_write(sd, REG_INT_FLG_CLR_RATE, reg);
1439 		source |= reg;
1440 	}
1441 
1442 	/* we only pay attention to stability change events */
1443 	if (source & (MASK_RATE_A_ST | MASK_RATE_B_ST)) {
1444 		int input = (source & MASK_RATE_A_ST)?0:1;
1445 		u8 mask = 1<<input;
1446 
1447 		/* state change */
1448 		if ((irq_status & mask) != (state->activity_status & mask)) {
1449 			/* activity lost */
1450 			if ((irq_status & mask) == 0) {
1451 				v4l_info(state->client,
1452 					 "HDMI-%c: Digital Activity Lost\n",
1453 					 input+'A');
1454 
1455 				/* bypass up/down sampler and pixel repeater */
1456 				reg = io_read(sd, REG_PIX_REPEAT);
1457 				reg &= ~PIX_REPEAT_MASK_UP_SEL;
1458 				reg &= ~PIX_REPEAT_MASK_REP;
1459 				io_write(sd, REG_PIX_REPEAT, reg);
1460 
1461 				if (state->chip_revision == 0)
1462 					tda1997x_reset_n1(state);
1463 
1464 				state->input_detect[input] = 0;
1465 				v4l2_subdev_notify_event(sd, &tda1997x_ev_fmt);
1466 			}
1467 
1468 			/* activity detected */
1469 			else {
1470 				v4l_info(state->client,
1471 					 "HDMI-%c: Digital Activity Detected\n",
1472 					 input+'A');
1473 				state->input_detect[input] = 1;
1474 			}
1475 
1476 			/* hold onto current state */
1477 			state->activity_status = (irq_status & mask);
1478 		}
1479 	}
1480 }
1481 
1482 static void tda1997x_irq_info(struct tda1997x_state *state, u8 *flags)
1483 {
1484 	struct v4l2_subdev *sd = &state->sd;
1485 	u8 source;
1486 
1487 	source = io_read(sd, REG_INT_FLG_CLR_INFO);
1488 	io_write(sd, REG_INT_FLG_CLR_INFO, source);
1489 
1490 	/* Audio infoframe */
1491 	if (source & MASK_AUD_IF) {
1492 		tda1997x_parse_infoframe(state, AUD_IF);
1493 		source &= ~MASK_AUD_IF;
1494 	}
1495 
1496 	/* Source Product Descriptor infoframe change */
1497 	if (source & MASK_SPD_IF) {
1498 		tda1997x_parse_infoframe(state, SPD_IF);
1499 		source &= ~MASK_SPD_IF;
1500 	}
1501 
1502 	/* Auxiliary Video Information infoframe */
1503 	if (source & MASK_AVI_IF) {
1504 		tda1997x_parse_infoframe(state, AVI_IF);
1505 		source &= ~MASK_AVI_IF;
1506 	}
1507 }
1508 
1509 static void tda1997x_irq_audio(struct tda1997x_state *state, u8 *flags)
1510 {
1511 	struct v4l2_subdev *sd = &state->sd;
1512 	u8 reg, source;
1513 
1514 	source = io_read(sd, REG_INT_FLG_CLR_AUDIO);
1515 	io_write(sd, REG_INT_FLG_CLR_AUDIO, source);
1516 
1517 	/* reset audio FIFO on FIFO pointer error or audio mute */
1518 	if (source & MASK_ERROR_FIFO_PT ||
1519 	    source & MASK_MUTE_FLG) {
1520 		/* audio reset audio FIFO */
1521 		reg = io_read(sd, REG_SUS_STATUS);
1522 		if ((reg & MASK_SUS_STATUS) == LAST_STATE_REACHED) {
1523 			reg = io_read(sd, REG_HDMI_INFO_RST);
1524 			reg |= MASK_SR_FIFO_FIFO_CTRL;
1525 			io_write(sd, REG_HDMI_INFO_RST, reg);
1526 			reg &= ~MASK_SR_FIFO_FIFO_CTRL;
1527 			io_write(sd, REG_HDMI_INFO_RST, reg);
1528 			/* reset channel status IT if present */
1529 			source &= ~(MASK_CH_STATE);
1530 		}
1531 	}
1532 	if (source & MASK_AUDIO_FREQ_FLG) {
1533 		static const int freq[] = {
1534 			0, 32000, 44100, 48000, 88200, 96000, 176400, 192000
1535 		};
1536 
1537 		reg = io_read(sd, REG_AUDIO_FREQ);
1538 		state->audio_samplerate = freq[reg & 7];
1539 		v4l_info(state->client, "Audio Frequency Change: %dHz\n",
1540 			 state->audio_samplerate);
1541 	}
1542 	if (source & MASK_AUDIO_FLG) {
1543 		reg = io_read(sd, REG_AUDIO_FLAGS);
1544 		if (reg & BIT(AUDCFG_TYPE_DST))
1545 			state->audio_type = AUDCFG_TYPE_DST;
1546 		if (reg & BIT(AUDCFG_TYPE_OBA))
1547 			state->audio_type = AUDCFG_TYPE_OBA;
1548 		if (reg & BIT(AUDCFG_TYPE_HBR))
1549 			state->audio_type = AUDCFG_TYPE_HBR;
1550 		if (reg & BIT(AUDCFG_TYPE_PCM))
1551 			state->audio_type = AUDCFG_TYPE_PCM;
1552 		v4l_info(state->client, "Audio Type: %s\n",
1553 			 audtype_names[state->audio_type]);
1554 	}
1555 }
1556 
1557 static void tda1997x_irq_hdcp(struct tda1997x_state *state, u8 *flags)
1558 {
1559 	struct v4l2_subdev *sd = &state->sd;
1560 	u8 reg, source;
1561 
1562 	source = io_read(sd, REG_INT_FLG_CLR_HDCP);
1563 	io_write(sd, REG_INT_FLG_CLR_HDCP, source);
1564 
1565 	/* reset MTP in use flag if set */
1566 	if (source & MASK_HDCP_MTP)
1567 		state->mptrw_in_progress = 0;
1568 	if (source & MASK_STATE_C5) {
1569 		/* REPEATER: mask AUDIO and IF irqs to avoid IF during auth */
1570 		reg = io_read(sd, REG_INT_MASK_TOP);
1571 		reg &= ~(INTERRUPT_AUDIO | INTERRUPT_INFO);
1572 		io_write(sd, REG_INT_MASK_TOP, reg);
1573 		*flags &= (INTERRUPT_AUDIO | INTERRUPT_INFO);
1574 	}
1575 }
1576 
1577 static irqreturn_t tda1997x_isr_thread(int irq, void *d)
1578 {
1579 	struct tda1997x_state *state = d;
1580 	struct v4l2_subdev *sd = &state->sd;
1581 	u8 flags;
1582 
1583 	mutex_lock(&state->lock);
1584 	do {
1585 		/* read interrupt flags */
1586 		flags = io_read(sd, REG_INT_FLG_CLR_TOP);
1587 		if (flags == 0)
1588 			break;
1589 
1590 		/* SUS interrupt source (Input activity events) */
1591 		if (flags & INTERRUPT_SUS)
1592 			tda1997x_irq_sus(state, &flags);
1593 		/* DDC interrupt source (Display Data Channel) */
1594 		else if (flags & INTERRUPT_DDC)
1595 			tda1997x_irq_ddc(state, &flags);
1596 		/* RATE interrupt source (Digital Input activity) */
1597 		else if (flags & INTERRUPT_RATE)
1598 			tda1997x_irq_rate(state, &flags);
1599 		/* Infoframe change interrupt */
1600 		else if (flags & INTERRUPT_INFO)
1601 			tda1997x_irq_info(state, &flags);
1602 		/* Audio interrupt source:
1603 		 *   freq change, DST,OBA,HBR,ASP flags, mute, FIFO err
1604 		 */
1605 		else if (flags & INTERRUPT_AUDIO)
1606 			tda1997x_irq_audio(state, &flags);
1607 		/* HDCP interrupt source (content protection) */
1608 		if (flags & INTERRUPT_HDCP)
1609 			tda1997x_irq_hdcp(state, &flags);
1610 	} while (flags != 0);
1611 	mutex_unlock(&state->lock);
1612 
1613 	return IRQ_HANDLED;
1614 }
1615 
1616 /* -----------------------------------------------------------------------------
1617  * v4l2_subdev_video_ops
1618  */
1619 
1620 static int
1621 tda1997x_g_input_status(struct v4l2_subdev *sd, u32 *status)
1622 {
1623 	struct tda1997x_state *state = to_state(sd);
1624 	u32 vper;
1625 	u16 hper;
1626 	u16 hsper;
1627 
1628 	mutex_lock(&state->lock);
1629 	vper = io_read24(sd, REG_V_PER) & MASK_VPER;
1630 	hper = io_read16(sd, REG_H_PER) & MASK_HPER;
1631 	hsper = io_read16(sd, REG_HS_WIDTH) & MASK_HSWIDTH;
1632 	/*
1633 	 * The tda1997x supports A/B inputs but only a single output.
1634 	 * The irq handler monitors for timing changes on both inputs and
1635 	 * sets the input_detect array to 0|1 depending on signal presence.
1636 	 * I believe selection of A vs B is automatic.
1637 	 *
1638 	 * The vper/hper/hsper registers provide the frame period, line period
1639 	 * and horiz sync period (units of MCLK clock cycles (27MHz)) and
1640 	 * testing shows these values to be random if no signal is present
1641 	 * or locked.
1642 	 */
1643 	v4l2_dbg(1, debug, sd, "inputs:%d/%d timings:%d/%d/%d\n",
1644 		 state->input_detect[0], state->input_detect[1],
1645 		 vper, hper, hsper);
1646 	if (!state->input_detect[0] && !state->input_detect[1])
1647 		*status = V4L2_IN_ST_NO_SIGNAL;
1648 	else if (!vper || !hper || !hsper)
1649 		*status = V4L2_IN_ST_NO_SYNC;
1650 	else
1651 		*status = 0;
1652 	mutex_unlock(&state->lock);
1653 
1654 	return 0;
1655 };
1656 
1657 static int tda1997x_s_dv_timings(struct v4l2_subdev *sd,
1658 				struct v4l2_dv_timings *timings)
1659 {
1660 	struct tda1997x_state *state = to_state(sd);
1661 
1662 	v4l_dbg(1, debug, state->client, "%s\n", __func__);
1663 
1664 	if (v4l2_match_dv_timings(&state->timings, timings, 0, false))
1665 		return 0; /* no changes */
1666 
1667 	if (!v4l2_valid_dv_timings(timings, &tda1997x_dv_timings_cap,
1668 				   NULL, NULL))
1669 		return -ERANGE;
1670 
1671 	mutex_lock(&state->lock);
1672 	state->timings = *timings;
1673 	/* setup frame detection window and VHREF timing generator */
1674 	tda1997x_configure_vhref(sd);
1675 	/* configure colorspace conversion */
1676 	tda1997x_configure_csc(sd);
1677 	mutex_unlock(&state->lock);
1678 
1679 	return 0;
1680 }
1681 
1682 static int tda1997x_g_dv_timings(struct v4l2_subdev *sd,
1683 				 struct v4l2_dv_timings *timings)
1684 {
1685 	struct tda1997x_state *state = to_state(sd);
1686 
1687 	v4l_dbg(1, debug, state->client, "%s\n", __func__);
1688 	mutex_lock(&state->lock);
1689 	*timings = state->timings;
1690 	mutex_unlock(&state->lock);
1691 
1692 	return 0;
1693 }
1694 
1695 static int tda1997x_query_dv_timings(struct v4l2_subdev *sd,
1696 				     struct v4l2_dv_timings *timings)
1697 {
1698 	struct tda1997x_state *state = to_state(sd);
1699 	int ret;
1700 
1701 	v4l_dbg(1, debug, state->client, "%s\n", __func__);
1702 	memset(timings, 0, sizeof(struct v4l2_dv_timings));
1703 	mutex_lock(&state->lock);
1704 	ret = tda1997x_detect_std(state, timings);
1705 	mutex_unlock(&state->lock);
1706 
1707 	return ret;
1708 }
1709 
1710 static const struct v4l2_subdev_video_ops tda1997x_video_ops = {
1711 	.g_input_status = tda1997x_g_input_status,
1712 	.s_dv_timings = tda1997x_s_dv_timings,
1713 	.g_dv_timings = tda1997x_g_dv_timings,
1714 	.query_dv_timings = tda1997x_query_dv_timings,
1715 };
1716 
1717 
1718 /* -----------------------------------------------------------------------------
1719  * v4l2_subdev_pad_ops
1720  */
1721 
1722 static int tda1997x_init_cfg(struct v4l2_subdev *sd,
1723 			     struct v4l2_subdev_state *sd_state)
1724 {
1725 	struct tda1997x_state *state = to_state(sd);
1726 	struct v4l2_mbus_framefmt *mf;
1727 
1728 	mf = v4l2_subdev_get_try_format(sd, sd_state, 0);
1729 	mf->code = state->mbus_codes[0];
1730 
1731 	return 0;
1732 }
1733 
1734 static int tda1997x_enum_mbus_code(struct v4l2_subdev *sd,
1735 				  struct v4l2_subdev_state *sd_state,
1736 				  struct v4l2_subdev_mbus_code_enum *code)
1737 {
1738 	struct tda1997x_state *state = to_state(sd);
1739 
1740 	v4l_dbg(1, debug, state->client, "%s %d\n", __func__, code->index);
1741 	if (code->index >= ARRAY_SIZE(state->mbus_codes))
1742 		return -EINVAL;
1743 
1744 	if (!state->mbus_codes[code->index])
1745 		return -EINVAL;
1746 
1747 	code->code = state->mbus_codes[code->index];
1748 
1749 	return 0;
1750 }
1751 
1752 static void tda1997x_fill_format(struct tda1997x_state *state,
1753 				 struct v4l2_mbus_framefmt *format)
1754 {
1755 	const struct v4l2_bt_timings *bt;
1756 
1757 	memset(format, 0, sizeof(*format));
1758 	bt = &state->timings.bt;
1759 	format->width = bt->width;
1760 	format->height = bt->height;
1761 	format->colorspace = state->colorimetry.colorspace;
1762 	format->field = (bt->interlaced) ?
1763 		V4L2_FIELD_SEQ_TB : V4L2_FIELD_NONE;
1764 }
1765 
1766 static int tda1997x_get_format(struct v4l2_subdev *sd,
1767 			       struct v4l2_subdev_state *sd_state,
1768 			       struct v4l2_subdev_format *format)
1769 {
1770 	struct tda1997x_state *state = to_state(sd);
1771 
1772 	v4l_dbg(1, debug, state->client, "%s pad=%d which=%d\n",
1773 		__func__, format->pad, format->which);
1774 
1775 	tda1997x_fill_format(state, &format->format);
1776 
1777 	if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1778 		struct v4l2_mbus_framefmt *fmt;
1779 
1780 		fmt = v4l2_subdev_get_try_format(sd, sd_state, format->pad);
1781 		format->format.code = fmt->code;
1782 	} else
1783 		format->format.code = state->mbus_code;
1784 
1785 	return 0;
1786 }
1787 
1788 static int tda1997x_set_format(struct v4l2_subdev *sd,
1789 			       struct v4l2_subdev_state *sd_state,
1790 			       struct v4l2_subdev_format *format)
1791 {
1792 	struct tda1997x_state *state = to_state(sd);
1793 	u32 code = 0;
1794 	int i;
1795 
1796 	v4l_dbg(1, debug, state->client, "%s pad=%d which=%d fmt=0x%x\n",
1797 		__func__, format->pad, format->which, format->format.code);
1798 
1799 	for (i = 0; i < ARRAY_SIZE(state->mbus_codes); i++) {
1800 		if (format->format.code == state->mbus_codes[i]) {
1801 			code = state->mbus_codes[i];
1802 			break;
1803 		}
1804 	}
1805 	if (!code)
1806 		code = state->mbus_codes[0];
1807 
1808 	tda1997x_fill_format(state, &format->format);
1809 	format->format.code = code;
1810 
1811 	if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1812 		struct v4l2_mbus_framefmt *fmt;
1813 
1814 		fmt = v4l2_subdev_get_try_format(sd, sd_state, format->pad);
1815 		*fmt = format->format;
1816 	} else {
1817 		int ret = tda1997x_setup_format(state, format->format.code);
1818 
1819 		if (ret)
1820 			return ret;
1821 		/* mbus_code has changed - re-configure csc/vidout */
1822 		tda1997x_configure_csc(sd);
1823 		tda1997x_configure_vidout(state);
1824 	}
1825 
1826 	return 0;
1827 }
1828 
1829 static int tda1997x_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
1830 {
1831 	struct tda1997x_state *state = to_state(sd);
1832 
1833 	v4l_dbg(1, debug, state->client, "%s pad=%d\n", __func__, edid->pad);
1834 	memset(edid->reserved, 0, sizeof(edid->reserved));
1835 
1836 	if (edid->start_block == 0 && edid->blocks == 0) {
1837 		edid->blocks = state->edid.blocks;
1838 		return 0;
1839 	}
1840 
1841 	if (!state->edid.present)
1842 		return -ENODATA;
1843 
1844 	if (edid->start_block >= state->edid.blocks)
1845 		return -EINVAL;
1846 
1847 	if (edid->start_block + edid->blocks > state->edid.blocks)
1848 		edid->blocks = state->edid.blocks - edid->start_block;
1849 
1850 	memcpy(edid->edid, state->edid.edid + edid->start_block * 128,
1851 	       edid->blocks * 128);
1852 
1853 	return 0;
1854 }
1855 
1856 static int tda1997x_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
1857 {
1858 	struct tda1997x_state *state = to_state(sd);
1859 	int i;
1860 
1861 	v4l_dbg(1, debug, state->client, "%s pad=%d\n", __func__, edid->pad);
1862 	memset(edid->reserved, 0, sizeof(edid->reserved));
1863 
1864 	if (edid->start_block != 0)
1865 		return -EINVAL;
1866 
1867 	if (edid->blocks == 0) {
1868 		state->edid.blocks = 0;
1869 		state->edid.present = 0;
1870 		tda1997x_disable_edid(sd);
1871 		return 0;
1872 	}
1873 
1874 	if (edid->blocks > 2) {
1875 		edid->blocks = 2;
1876 		return -E2BIG;
1877 	}
1878 
1879 	tda1997x_disable_edid(sd);
1880 
1881 	/* write base EDID */
1882 	for (i = 0; i < 128; i++)
1883 		io_write(sd, REG_EDID_IN_BYTE0 + i, edid->edid[i]);
1884 
1885 	/* write CEA Extension */
1886 	for (i = 0; i < 128; i++)
1887 		io_write(sd, REG_EDID_IN_BYTE128 + i, edid->edid[i+128]);
1888 
1889 	/* store state */
1890 	memcpy(state->edid.edid, edid->edid, 256);
1891 	state->edid.blocks = edid->blocks;
1892 
1893 	tda1997x_enable_edid(sd);
1894 
1895 	return 0;
1896 }
1897 
1898 static int tda1997x_get_dv_timings_cap(struct v4l2_subdev *sd,
1899 				       struct v4l2_dv_timings_cap *cap)
1900 {
1901 	*cap = tda1997x_dv_timings_cap;
1902 	return 0;
1903 }
1904 
1905 static int tda1997x_enum_dv_timings(struct v4l2_subdev *sd,
1906 				    struct v4l2_enum_dv_timings *timings)
1907 {
1908 	return v4l2_enum_dv_timings_cap(timings, &tda1997x_dv_timings_cap,
1909 					NULL, NULL);
1910 }
1911 
1912 static const struct v4l2_subdev_pad_ops tda1997x_pad_ops = {
1913 	.init_cfg = tda1997x_init_cfg,
1914 	.enum_mbus_code = tda1997x_enum_mbus_code,
1915 	.get_fmt = tda1997x_get_format,
1916 	.set_fmt = tda1997x_set_format,
1917 	.get_edid = tda1997x_get_edid,
1918 	.set_edid = tda1997x_set_edid,
1919 	.dv_timings_cap = tda1997x_get_dv_timings_cap,
1920 	.enum_dv_timings = tda1997x_enum_dv_timings,
1921 };
1922 
1923 /* -----------------------------------------------------------------------------
1924  * v4l2_subdev_core_ops
1925  */
1926 
1927 static int tda1997x_log_infoframe(struct v4l2_subdev *sd, int addr)
1928 {
1929 	struct tda1997x_state *state = to_state(sd);
1930 	union hdmi_infoframe frame;
1931 	u8 buffer[40] = { 0 };
1932 	int len, err;
1933 
1934 	/* read data */
1935 	len = io_readn(sd, addr, sizeof(buffer), buffer);
1936 	v4l2_dbg(1, debug, sd, "infoframe: addr=%d len=%d\n", addr, len);
1937 	err = hdmi_infoframe_unpack(&frame, buffer, len);
1938 	if (err) {
1939 		v4l_err(state->client,
1940 			"failed parsing %d byte infoframe: 0x%04x/0x%02x\n",
1941 			len, addr, buffer[0]);
1942 		return err;
1943 	}
1944 	hdmi_infoframe_log(KERN_INFO, &state->client->dev, &frame);
1945 
1946 	return 0;
1947 }
1948 
1949 static int tda1997x_log_status(struct v4l2_subdev *sd)
1950 {
1951 	struct tda1997x_state *state = to_state(sd);
1952 	struct v4l2_dv_timings timings;
1953 	struct hdmi_avi_infoframe *avi = &state->avi_infoframe;
1954 
1955 	v4l2_info(sd, "-----Chip status-----\n");
1956 	v4l2_info(sd, "Chip: %s N%d\n", state->info->name,
1957 		  state->chip_revision + 1);
1958 	v4l2_info(sd, "EDID Enabled: %s\n", state->edid.present ? "yes" : "no");
1959 
1960 	v4l2_info(sd, "-----Signal status-----\n");
1961 	v4l2_info(sd, "Cable detected (+5V power): %s\n",
1962 		  tda1997x_detect_tx_5v(sd) ? "yes" : "no");
1963 	v4l2_info(sd, "HPD detected: %s\n",
1964 		  tda1997x_detect_tx_hpd(sd) ? "yes" : "no");
1965 
1966 	v4l2_info(sd, "-----Video Timings-----\n");
1967 	switch (tda1997x_detect_std(state, &timings)) {
1968 	case -ENOLINK:
1969 		v4l2_info(sd, "No video detected\n");
1970 		break;
1971 	case -ERANGE:
1972 		v4l2_info(sd, "Invalid signal detected\n");
1973 		break;
1974 	}
1975 	v4l2_print_dv_timings(sd->name, "Configured format: ",
1976 			      &state->timings, true);
1977 
1978 	v4l2_info(sd, "-----Color space-----\n");
1979 	v4l2_info(sd, "Input color space: %s %s %s",
1980 		  hdmi_colorspace_names[avi->colorspace],
1981 		  (avi->colorspace == HDMI_COLORSPACE_RGB) ? "" :
1982 			hdmi_colorimetry_names[avi->colorimetry],
1983 		  v4l2_quantization_names[state->colorimetry.quantization]);
1984 	v4l2_info(sd, "Output color space: %s",
1985 		  vidfmt_names[state->vid_fmt]);
1986 	v4l2_info(sd, "Color space conversion: %s", state->conv ?
1987 		  state->conv->name : "None");
1988 
1989 	v4l2_info(sd, "-----Audio-----\n");
1990 	if (state->audio_channels) {
1991 		v4l2_info(sd, "audio: %dch %dHz\n", state->audio_channels,
1992 			  state->audio_samplerate);
1993 	} else {
1994 		v4l2_info(sd, "audio: none\n");
1995 	}
1996 
1997 	v4l2_info(sd, "-----Infoframes-----\n");
1998 	tda1997x_log_infoframe(sd, AUD_IF);
1999 	tda1997x_log_infoframe(sd, SPD_IF);
2000 	tda1997x_log_infoframe(sd, AVI_IF);
2001 
2002 	return 0;
2003 }
2004 
2005 static int tda1997x_subscribe_event(struct v4l2_subdev *sd,
2006 				    struct v4l2_fh *fh,
2007 				    struct v4l2_event_subscription *sub)
2008 {
2009 	switch (sub->type) {
2010 	case V4L2_EVENT_SOURCE_CHANGE:
2011 		return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
2012 	case V4L2_EVENT_CTRL:
2013 		return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
2014 	default:
2015 		return -EINVAL;
2016 	}
2017 }
2018 
2019 static const struct v4l2_subdev_core_ops tda1997x_core_ops = {
2020 	.log_status = tda1997x_log_status,
2021 	.subscribe_event = tda1997x_subscribe_event,
2022 	.unsubscribe_event = v4l2_event_subdev_unsubscribe,
2023 };
2024 
2025 /* -----------------------------------------------------------------------------
2026  * v4l2_subdev_ops
2027  */
2028 
2029 static const struct v4l2_subdev_ops tda1997x_subdev_ops = {
2030 	.core = &tda1997x_core_ops,
2031 	.video = &tda1997x_video_ops,
2032 	.pad = &tda1997x_pad_ops,
2033 };
2034 
2035 /* -----------------------------------------------------------------------------
2036  * v4l2_controls
2037  */
2038 
2039 static int tda1997x_s_ctrl(struct v4l2_ctrl *ctrl)
2040 {
2041 	struct v4l2_subdev *sd = to_sd(ctrl);
2042 	struct tda1997x_state *state = to_state(sd);
2043 
2044 	switch (ctrl->id) {
2045 	/* allow overriding the default RGB quantization range */
2046 	case V4L2_CID_DV_RX_RGB_RANGE:
2047 		state->rgb_quantization_range = ctrl->val;
2048 		set_rgb_quantization_range(state);
2049 		tda1997x_configure_csc(sd);
2050 		return 0;
2051 	}
2052 
2053 	return -EINVAL;
2054 };
2055 
2056 static int tda1997x_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
2057 {
2058 	struct v4l2_subdev *sd = to_sd(ctrl);
2059 	struct tda1997x_state *state = to_state(sd);
2060 
2061 	if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) {
2062 		ctrl->val = state->avi_infoframe.content_type;
2063 		return 0;
2064 	}
2065 	return -EINVAL;
2066 };
2067 
2068 static const struct v4l2_ctrl_ops tda1997x_ctrl_ops = {
2069 	.s_ctrl = tda1997x_s_ctrl,
2070 	.g_volatile_ctrl = tda1997x_g_volatile_ctrl,
2071 };
2072 
2073 static int tda1997x_core_init(struct v4l2_subdev *sd)
2074 {
2075 	struct tda1997x_state *state = to_state(sd);
2076 	struct tda1997x_platform_data *pdata = &state->pdata;
2077 	u8 reg;
2078 	int i;
2079 
2080 	/* disable HPD */
2081 	io_write(sd, REG_HPD_AUTO_CTRL, HPD_AUTO_HPD_UNSEL);
2082 	if (state->chip_revision == 0) {
2083 		io_write(sd, REG_MAN_SUS_HDMI_SEL, MAN_DIS_HDCP | MAN_RST_HDCP);
2084 		io_write(sd, REG_CGU_DBG_SEL, 1 << CGU_DBG_CLK_SEL_SHIFT);
2085 	}
2086 
2087 	/* reset infoframe at end of start-up-sequencer */
2088 	io_write(sd, REG_SUS_SET_RGB2, 0x06);
2089 	io_write(sd, REG_SUS_SET_RGB3, 0x06);
2090 
2091 	/* Enable TMDS pull-ups */
2092 	io_write(sd, REG_RT_MAN_CTRL, RT_MAN_CTRL_RT |
2093 		 RT_MAN_CTRL_RT_B | RT_MAN_CTRL_RT_A);
2094 
2095 	/* enable sync measurement timing */
2096 	tda1997x_cec_write(sd, REG_PWR_CONTROL & 0xff, 0x04);
2097 	/* adjust CEC clock divider */
2098 	tda1997x_cec_write(sd, REG_OSC_DIVIDER & 0xff, 0x03);
2099 	tda1997x_cec_write(sd, REG_EN_OSC_PERIOD_LSB & 0xff, 0xa0);
2100 	io_write(sd, REG_TIMER_D, 0x54);
2101 	/* enable power switch */
2102 	reg = tda1997x_cec_read(sd, REG_CONTROL & 0xff);
2103 	reg |= 0x20;
2104 	tda1997x_cec_write(sd, REG_CONTROL & 0xff, reg);
2105 	mdelay(50);
2106 
2107 	/* read the chip version */
2108 	reg = io_read(sd, REG_VERSION);
2109 	/* get the chip configuration */
2110 	reg = io_read(sd, REG_CMTP_REG10);
2111 
2112 	/* enable interrupts we care about */
2113 	io_write(sd, REG_INT_MASK_TOP,
2114 		 INTERRUPT_HDCP | INTERRUPT_AUDIO | INTERRUPT_INFO |
2115 		 INTERRUPT_RATE | INTERRUPT_SUS);
2116 	/* config_mtp,fmt,sus_end,sus_st */
2117 	io_write(sd, REG_INT_MASK_SUS, MASK_MPT | MASK_FMT | MASK_SUS_END);
2118 	/* rate stability change for inputs A/B */
2119 	io_write(sd, REG_INT_MASK_RATE, MASK_RATE_B_ST | MASK_RATE_A_ST);
2120 	/* aud,spd,avi*/
2121 	io_write(sd, REG_INT_MASK_INFO,
2122 		 MASK_AUD_IF | MASK_SPD_IF | MASK_AVI_IF);
2123 	/* audio_freq,audio_flg,mute_flg,fifo_err */
2124 	io_write(sd, REG_INT_MASK_AUDIO,
2125 		 MASK_AUDIO_FREQ_FLG | MASK_AUDIO_FLG | MASK_MUTE_FLG |
2126 		 MASK_ERROR_FIFO_PT);
2127 	/* HDCP C5 state reached */
2128 	io_write(sd, REG_INT_MASK_HDCP, MASK_STATE_C5);
2129 	/* 5V detect and HDP pulse end */
2130 	io_write(sd, REG_INT_MASK_DDC, MASK_DET_5V);
2131 	/* don't care about AFE/MODE */
2132 	io_write(sd, REG_INT_MASK_AFE, 0);
2133 	io_write(sd, REG_INT_MASK_MODE, 0);
2134 
2135 	/* clear all interrupts */
2136 	io_write(sd, REG_INT_FLG_CLR_TOP, 0xff);
2137 	io_write(sd, REG_INT_FLG_CLR_SUS, 0xff);
2138 	io_write(sd, REG_INT_FLG_CLR_DDC, 0xff);
2139 	io_write(sd, REG_INT_FLG_CLR_RATE, 0xff);
2140 	io_write(sd, REG_INT_FLG_CLR_MODE, 0xff);
2141 	io_write(sd, REG_INT_FLG_CLR_INFO, 0xff);
2142 	io_write(sd, REG_INT_FLG_CLR_AUDIO, 0xff);
2143 	io_write(sd, REG_INT_FLG_CLR_HDCP, 0xff);
2144 	io_write(sd, REG_INT_FLG_CLR_AFE, 0xff);
2145 
2146 	/* init TMDS equalizer */
2147 	if (state->chip_revision == 0)
2148 		io_write(sd, REG_CGU_DBG_SEL, 1 << CGU_DBG_CLK_SEL_SHIFT);
2149 	io_write24(sd, REG_CLK_MIN_RATE, CLK_MIN_RATE);
2150 	io_write24(sd, REG_CLK_MAX_RATE, CLK_MAX_RATE);
2151 	if (state->chip_revision == 0)
2152 		io_write(sd, REG_WDL_CFG, WDL_CFG_VAL);
2153 	/* DC filter */
2154 	io_write(sd, REG_DEEP_COLOR_CTRL, DC_FILTER_VAL);
2155 	/* disable test pattern */
2156 	io_write(sd, REG_SVC_MODE, 0x00);
2157 	/* update HDMI INFO CTRL */
2158 	io_write(sd, REG_INFO_CTRL, 0xff);
2159 	/* write HDMI INFO EXCEED value */
2160 	io_write(sd, REG_INFO_EXCEED, 3);
2161 
2162 	if (state->chip_revision == 0)
2163 		tda1997x_reset_n1(state);
2164 
2165 	/*
2166 	 * No HDCP acknowledge when HDCP is disabled
2167 	 * and reset SUS to force format detection
2168 	 */
2169 	tda1997x_hdmi_info_reset(sd, NACK_HDCP, true);
2170 
2171 	/* Set HPD low */
2172 	tda1997x_manual_hpd(sd, HPD_LOW_BP);
2173 
2174 	/* Configure receiver capabilities */
2175 	io_write(sd, REG_HDCP_BCAPS, HDCP_HDMI | HDCP_FAST_REAUTH);
2176 
2177 	/* Configure HDMI: Auto HDCP mode, packet controlled mute */
2178 	reg = HDMI_CTRL_MUTE_AUTO << HDMI_CTRL_MUTE_SHIFT;
2179 	reg |= HDMI_CTRL_HDCP_AUTO << HDMI_CTRL_HDCP_SHIFT;
2180 	io_write(sd, REG_HDMI_CTRL, reg);
2181 
2182 	/* reset start-up-sequencer to force format detection */
2183 	tda1997x_hdmi_info_reset(sd, 0, true);
2184 
2185 	/* disable matrix conversion */
2186 	reg = io_read(sd, REG_VDP_CTRL);
2187 	reg |= VDP_CTRL_MATRIX_BP;
2188 	io_write(sd, REG_VDP_CTRL, reg);
2189 
2190 	/* set video output mode */
2191 	tda1997x_configure_vidout(state);
2192 
2193 	/* configure video output port */
2194 	for (i = 0; i < 9; i++) {
2195 		v4l_dbg(1, debug, state->client, "vidout_cfg[%d]=0x%02x\n", i,
2196 			pdata->vidout_port_cfg[i]);
2197 		io_write(sd, REG_VP35_32_CTRL + i, pdata->vidout_port_cfg[i]);
2198 	}
2199 
2200 	/* configure audio output port */
2201 	tda1997x_configure_audout(sd, 0);
2202 
2203 	/* configure audio clock freq */
2204 	switch (pdata->audout_mclk_fs) {
2205 	case 512:
2206 		reg = AUDIO_CLOCK_SEL_512FS;
2207 		break;
2208 	case 256:
2209 		reg = AUDIO_CLOCK_SEL_256FS;
2210 		break;
2211 	case 128:
2212 		reg = AUDIO_CLOCK_SEL_128FS;
2213 		break;
2214 	case 64:
2215 		reg = AUDIO_CLOCK_SEL_64FS;
2216 		break;
2217 	case 32:
2218 		reg = AUDIO_CLOCK_SEL_32FS;
2219 		break;
2220 	default:
2221 		reg = AUDIO_CLOCK_SEL_16FS;
2222 		break;
2223 	}
2224 	io_write(sd, REG_AUDIO_CLOCK, reg);
2225 
2226 	/* reset advanced infoframes (ISRC1/ISRC2/ACP) */
2227 	tda1997x_hdmi_info_reset(sd, RESET_AI, false);
2228 	/* reset infoframe */
2229 	tda1997x_hdmi_info_reset(sd, RESET_IF, false);
2230 	/* reset audio infoframes */
2231 	tda1997x_hdmi_info_reset(sd, RESET_AUDIO, false);
2232 	/* reset gamut */
2233 	tda1997x_hdmi_info_reset(sd, RESET_GAMUT, false);
2234 
2235 	/* get initial HDMI status */
2236 	state->hdmi_status = io_read(sd, REG_HDMI_FLAGS);
2237 
2238 	io_write(sd, REG_EDID_ENABLE, EDID_ENABLE_A_EN | EDID_ENABLE_B_EN);
2239 	return 0;
2240 }
2241 
2242 static int tda1997x_set_power(struct tda1997x_state *state, bool on)
2243 {
2244 	int ret = 0;
2245 
2246 	if (on) {
2247 		ret = regulator_bulk_enable(TDA1997X_NUM_SUPPLIES,
2248 					     state->supplies);
2249 		msleep(300);
2250 	} else {
2251 		ret = regulator_bulk_disable(TDA1997X_NUM_SUPPLIES,
2252 					     state->supplies);
2253 	}
2254 
2255 	return ret;
2256 }
2257 
2258 static const struct i2c_device_id tda1997x_i2c_id[] = {
2259 	{"tda19971", (kernel_ulong_t)&tda1997x_chip_info[TDA19971]},
2260 	{"tda19973", (kernel_ulong_t)&tda1997x_chip_info[TDA19973]},
2261 	{ },
2262 };
2263 MODULE_DEVICE_TABLE(i2c, tda1997x_i2c_id);
2264 
2265 static const struct of_device_id tda1997x_of_id[] __maybe_unused = {
2266 	{ .compatible = "nxp,tda19971", .data = &tda1997x_chip_info[TDA19971] },
2267 	{ .compatible = "nxp,tda19973", .data = &tda1997x_chip_info[TDA19973] },
2268 	{ },
2269 };
2270 MODULE_DEVICE_TABLE(of, tda1997x_of_id);
2271 
2272 static int tda1997x_parse_dt(struct tda1997x_state *state)
2273 {
2274 	struct tda1997x_platform_data *pdata = &state->pdata;
2275 	struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 };
2276 	struct device_node *ep;
2277 	struct device_node *np;
2278 	unsigned int flags;
2279 	const char *str;
2280 	int ret;
2281 	u32 v;
2282 
2283 	/*
2284 	 * setup default values:
2285 	 * - HREF: active high from start to end of row
2286 	 * - VS: Vertical Sync active high at beginning of frame
2287 	 * - DE: Active high when data valid
2288 	 * - A_CLK: 128*Fs
2289 	 */
2290 	pdata->vidout_sel_hs = HS_HREF_SEL_HREF_VHREF;
2291 	pdata->vidout_sel_vs = VS_VREF_SEL_VREF_HDMI;
2292 	pdata->vidout_sel_de = DE_FREF_SEL_DE_VHREF;
2293 
2294 	np = state->client->dev.of_node;
2295 	ep = of_graph_get_next_endpoint(np, NULL);
2296 	if (!ep)
2297 		return -EINVAL;
2298 
2299 	ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep), &bus_cfg);
2300 	if (ret) {
2301 		of_node_put(ep);
2302 		return ret;
2303 	}
2304 	of_node_put(ep);
2305 	pdata->vidout_bus_type = bus_cfg.bus_type;
2306 
2307 	/* polarity of HS/VS/DE */
2308 	flags = bus_cfg.bus.parallel.flags;
2309 	if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
2310 		pdata->vidout_inv_hs = 1;
2311 	if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
2312 		pdata->vidout_inv_vs = 1;
2313 	if (flags & V4L2_MBUS_DATA_ACTIVE_LOW)
2314 		pdata->vidout_inv_de = 1;
2315 	pdata->vidout_bus_width = bus_cfg.bus.parallel.bus_width;
2316 
2317 	/* video output port config */
2318 	ret = of_property_count_u32_elems(np, "nxp,vidout-portcfg");
2319 	if (ret > 0) {
2320 		u32 reg, val, i;
2321 
2322 		for (i = 0; i < ret / 2 && i < 9; i++) {
2323 			of_property_read_u32_index(np, "nxp,vidout-portcfg",
2324 						   i * 2, &reg);
2325 			of_property_read_u32_index(np, "nxp,vidout-portcfg",
2326 						   i * 2 + 1, &val);
2327 			if (reg < 9)
2328 				pdata->vidout_port_cfg[reg] = val;
2329 		}
2330 	} else {
2331 		v4l_err(state->client, "nxp,vidout-portcfg missing\n");
2332 		return -EINVAL;
2333 	}
2334 
2335 	/* default to channel layout dictated by packet header */
2336 	pdata->audout_layoutauto = true;
2337 
2338 	pdata->audout_format = AUDFMT_TYPE_DISABLED;
2339 	if (!of_property_read_string(np, "nxp,audout-format", &str)) {
2340 		if (strcmp(str, "i2s") == 0)
2341 			pdata->audout_format = AUDFMT_TYPE_I2S;
2342 		else if (strcmp(str, "spdif") == 0)
2343 			pdata->audout_format = AUDFMT_TYPE_SPDIF;
2344 		else {
2345 			v4l_err(state->client, "nxp,audout-format invalid\n");
2346 			return -EINVAL;
2347 		}
2348 		if (!of_property_read_u32(np, "nxp,audout-layout", &v)) {
2349 			switch (v) {
2350 			case 0:
2351 			case 1:
2352 				break;
2353 			default:
2354 				v4l_err(state->client,
2355 					"nxp,audout-layout invalid\n");
2356 				return -EINVAL;
2357 			}
2358 			pdata->audout_layout = v;
2359 		}
2360 		if (!of_property_read_u32(np, "nxp,audout-width", &v)) {
2361 			switch (v) {
2362 			case 16:
2363 			case 32:
2364 				break;
2365 			default:
2366 				v4l_err(state->client,
2367 					"nxp,audout-width invalid\n");
2368 				return -EINVAL;
2369 			}
2370 			pdata->audout_width = v;
2371 		}
2372 		if (!of_property_read_u32(np, "nxp,audout-mclk-fs", &v)) {
2373 			switch (v) {
2374 			case 512:
2375 			case 256:
2376 			case 128:
2377 			case 64:
2378 			case 32:
2379 			case 16:
2380 				break;
2381 			default:
2382 				v4l_err(state->client,
2383 					"nxp,audout-mclk-fs invalid\n");
2384 				return -EINVAL;
2385 			}
2386 			pdata->audout_mclk_fs = v;
2387 		}
2388 	}
2389 
2390 	return 0;
2391 }
2392 
2393 static int tda1997x_get_regulators(struct tda1997x_state *state)
2394 {
2395 	int i;
2396 
2397 	for (i = 0; i < TDA1997X_NUM_SUPPLIES; i++)
2398 		state->supplies[i].supply = tda1997x_supply_name[i];
2399 
2400 	return devm_regulator_bulk_get(&state->client->dev,
2401 				       TDA1997X_NUM_SUPPLIES,
2402 				       state->supplies);
2403 }
2404 
2405 static int tda1997x_identify_module(struct tda1997x_state *state)
2406 {
2407 	struct v4l2_subdev *sd = &state->sd;
2408 	enum tda1997x_type type;
2409 	u8 reg;
2410 
2411 	/* Read chip configuration*/
2412 	reg = io_read(sd, REG_CMTP_REG10);
2413 	state->tmdsb_clk = (reg >> 6) & 0x01; /* use tmds clock B_inv for B */
2414 	state->tmdsb_soc = (reg >> 5) & 0x01; /* tmds of input B */
2415 	state->port_30bit = (reg >> 2) & 0x03; /* 30bit vs 24bit */
2416 	state->output_2p5 = (reg >> 1) & 0x01; /* output supply 2.5v */
2417 	switch ((reg >> 4) & 0x03) {
2418 	case 0x00:
2419 		type = TDA19971;
2420 		break;
2421 	case 0x02:
2422 	case 0x03:
2423 		type = TDA19973;
2424 		break;
2425 	default:
2426 		dev_err(&state->client->dev, "unsupported chip ID\n");
2427 		return -EIO;
2428 	}
2429 	if (state->info->type != type) {
2430 		dev_err(&state->client->dev, "chip id mismatch\n");
2431 		return -EIO;
2432 	}
2433 
2434 	/* read chip revision */
2435 	state->chip_revision = io_read(sd, REG_CMTP_REG11);
2436 
2437 	return 0;
2438 }
2439 
2440 static const struct media_entity_operations tda1997x_media_ops = {
2441 	.link_validate = v4l2_subdev_link_validate,
2442 };
2443 
2444 
2445 /* -----------------------------------------------------------------------------
2446  * HDMI Audio Codec
2447  */
2448 
2449 /* refine sample-rate based on HDMI source */
2450 static int tda1997x_pcm_startup(struct snd_pcm_substream *substream,
2451 				struct snd_soc_dai *dai)
2452 {
2453 	struct v4l2_subdev *sd = snd_soc_dai_get_drvdata(dai);
2454 	struct tda1997x_state *state = to_state(sd);
2455 	struct snd_soc_component *component = dai->component;
2456 	struct snd_pcm_runtime *rtd = substream->runtime;
2457 	int rate, err;
2458 
2459 	rate = state->audio_samplerate;
2460 	err = snd_pcm_hw_constraint_minmax(rtd, SNDRV_PCM_HW_PARAM_RATE,
2461 					   rate, rate);
2462 	if (err < 0) {
2463 		dev_err(component->dev, "failed to constrain samplerate to %dHz\n",
2464 			rate);
2465 		return err;
2466 	}
2467 	dev_info(component->dev, "set samplerate constraint to %dHz\n", rate);
2468 
2469 	return 0;
2470 }
2471 
2472 static const struct snd_soc_dai_ops tda1997x_dai_ops = {
2473 	.startup = tda1997x_pcm_startup,
2474 };
2475 
2476 static struct snd_soc_dai_driver tda1997x_audio_dai = {
2477 	.name = "tda1997x",
2478 	.capture = {
2479 		.stream_name = "Capture",
2480 		.channels_min = 2,
2481 		.channels_max = 8,
2482 		.rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
2483 			 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
2484 			 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
2485 			 SNDRV_PCM_RATE_192000,
2486 	},
2487 	.ops = &tda1997x_dai_ops,
2488 };
2489 
2490 static int tda1997x_codec_probe(struct snd_soc_component *component)
2491 {
2492 	return 0;
2493 }
2494 
2495 static void tda1997x_codec_remove(struct snd_soc_component *component)
2496 {
2497 }
2498 
2499 static struct snd_soc_component_driver tda1997x_codec_driver = {
2500 	.probe			= tda1997x_codec_probe,
2501 	.remove			= tda1997x_codec_remove,
2502 	.idle_bias_on		= 1,
2503 	.use_pmdown_time	= 1,
2504 	.endianness		= 1,
2505 	.non_legacy_dai_naming	= 1,
2506 };
2507 
2508 static int tda1997x_probe(struct i2c_client *client,
2509 			 const struct i2c_device_id *id)
2510 {
2511 	struct tda1997x_state *state;
2512 	struct tda1997x_platform_data *pdata;
2513 	struct v4l2_subdev *sd;
2514 	struct v4l2_ctrl_handler *hdl;
2515 	struct v4l2_ctrl *ctrl;
2516 	static const struct v4l2_dv_timings cea1920x1080 =
2517 		V4L2_DV_BT_CEA_1920X1080P60;
2518 	u32 *mbus_codes;
2519 	int i, ret;
2520 
2521 	/* Check if the adapter supports the needed features */
2522 	if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2523 		return -EIO;
2524 
2525 	state = kzalloc(sizeof(struct tda1997x_state), GFP_KERNEL);
2526 	if (!state)
2527 		return -ENOMEM;
2528 
2529 	state->client = client;
2530 	pdata = &state->pdata;
2531 	if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) {
2532 		const struct of_device_id *oid;
2533 
2534 		oid = of_match_node(tda1997x_of_id, client->dev.of_node);
2535 		state->info = oid->data;
2536 
2537 		ret = tda1997x_parse_dt(state);
2538 		if (ret < 0) {
2539 			v4l_err(client, "DT parsing error\n");
2540 			goto err_free_state;
2541 		}
2542 	} else if (client->dev.platform_data) {
2543 		struct tda1997x_platform_data *pdata =
2544 			client->dev.platform_data;
2545 		state->info =
2546 			(const struct tda1997x_chip_info *)id->driver_data;
2547 		state->pdata = *pdata;
2548 	} else {
2549 		v4l_err(client, "No platform data\n");
2550 		ret = -ENODEV;
2551 		goto err_free_state;
2552 	}
2553 
2554 	ret = tda1997x_get_regulators(state);
2555 	if (ret)
2556 		goto err_free_state;
2557 
2558 	ret = tda1997x_set_power(state, 1);
2559 	if (ret)
2560 		goto err_free_state;
2561 
2562 	mutex_init(&state->page_lock);
2563 	mutex_init(&state->lock);
2564 	state->page = 0xff;
2565 
2566 	INIT_DELAYED_WORK(&state->delayed_work_enable_hpd,
2567 			  tda1997x_delayed_work_enable_hpd);
2568 
2569 	/* set video format based on chip and bus width */
2570 	ret = tda1997x_identify_module(state);
2571 	if (ret)
2572 		goto err_free_mutex;
2573 
2574 	/* initialize subdev */
2575 	sd = &state->sd;
2576 	v4l2_i2c_subdev_init(sd, client, &tda1997x_subdev_ops);
2577 	snprintf(sd->name, sizeof(sd->name), "%s %d-%04x",
2578 		 id->name, i2c_adapter_id(client->adapter),
2579 		 client->addr);
2580 	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
2581 	sd->entity.function = MEDIA_ENT_F_DV_DECODER;
2582 	sd->entity.ops = &tda1997x_media_ops;
2583 
2584 	/* set allowed mbus modes based on chip, bus-type, and bus-width */
2585 	i = 0;
2586 	mbus_codes = state->mbus_codes;
2587 	switch (state->info->type) {
2588 	case TDA19973:
2589 		switch (pdata->vidout_bus_type) {
2590 		case V4L2_MBUS_PARALLEL:
2591 			switch (pdata->vidout_bus_width) {
2592 			case 36:
2593 				mbus_codes[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
2594 				mbus_codes[i++] = MEDIA_BUS_FMT_YUV12_1X36;
2595 				fallthrough;
2596 			case 24:
2597 				mbus_codes[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
2598 				break;
2599 			}
2600 			break;
2601 		case V4L2_MBUS_BT656:
2602 			switch (pdata->vidout_bus_width) {
2603 			case 36:
2604 			case 24:
2605 			case 12:
2606 				mbus_codes[i++] = MEDIA_BUS_FMT_UYVY12_2X12;
2607 				mbus_codes[i++] = MEDIA_BUS_FMT_UYVY10_2X10;
2608 				mbus_codes[i++] = MEDIA_BUS_FMT_UYVY8_2X8;
2609 				break;
2610 			}
2611 			break;
2612 		default:
2613 			break;
2614 		}
2615 		break;
2616 	case TDA19971:
2617 		switch (pdata->vidout_bus_type) {
2618 		case V4L2_MBUS_PARALLEL:
2619 			switch (pdata->vidout_bus_width) {
2620 			case 24:
2621 				mbus_codes[i++] = MEDIA_BUS_FMT_RGB888_1X24;
2622 				mbus_codes[i++] = MEDIA_BUS_FMT_YUV8_1X24;
2623 				mbus_codes[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
2624 				fallthrough;
2625 			case 20:
2626 				mbus_codes[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
2627 				fallthrough;
2628 			case 16:
2629 				mbus_codes[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
2630 				break;
2631 			}
2632 			break;
2633 		case V4L2_MBUS_BT656:
2634 			switch (pdata->vidout_bus_width) {
2635 			case 24:
2636 			case 20:
2637 			case 16:
2638 			case 12:
2639 				mbus_codes[i++] = MEDIA_BUS_FMT_UYVY12_2X12;
2640 				fallthrough;
2641 			case 10:
2642 				mbus_codes[i++] = MEDIA_BUS_FMT_UYVY10_2X10;
2643 				fallthrough;
2644 			case 8:
2645 				mbus_codes[i++] = MEDIA_BUS_FMT_UYVY8_2X8;
2646 				break;
2647 			}
2648 			break;
2649 		default:
2650 			break;
2651 		}
2652 		break;
2653 	}
2654 	if (WARN_ON(i > ARRAY_SIZE(state->mbus_codes))) {
2655 		ret = -EINVAL;
2656 		goto err_free_mutex;
2657 	}
2658 
2659 	/* default format */
2660 	tda1997x_setup_format(state, state->mbus_codes[0]);
2661 	state->timings = cea1920x1080;
2662 
2663 	/*
2664 	 * default to SRGB full range quantization
2665 	 * (in case we don't get an infoframe such as DVI signal
2666 	 */
2667 	state->colorimetry.colorspace = V4L2_COLORSPACE_SRGB;
2668 	state->colorimetry.quantization = V4L2_QUANTIZATION_FULL_RANGE;
2669 
2670 	/* disable/reset HDCP to get correct I2C access to Rx HDMI */
2671 	io_write(sd, REG_MAN_SUS_HDMI_SEL, MAN_RST_HDCP | MAN_DIS_HDCP);
2672 
2673 	/*
2674 	 * if N2 version, reset compdel_bp as it may generate some small pixel
2675 	 * shifts in case of embedded sync/or delay lower than 4
2676 	 */
2677 	if (state->chip_revision != 0) {
2678 		io_write(sd, REG_MAN_SUS_HDMI_SEL, 0x00);
2679 		io_write(sd, REG_VDP_CTRL, 0x1f);
2680 	}
2681 
2682 	v4l_info(client, "NXP %s N%d detected\n", state->info->name,
2683 		 state->chip_revision + 1);
2684 	v4l_info(client, "video: %dbit %s %d formats available\n",
2685 		pdata->vidout_bus_width,
2686 		(pdata->vidout_bus_type == V4L2_MBUS_PARALLEL) ?
2687 			"parallel" : "BT656",
2688 		i);
2689 	if (pdata->audout_format) {
2690 		v4l_info(client, "audio: %dch %s layout%d sysclk=%d*fs\n",
2691 			 pdata->audout_layout ? 2 : 8,
2692 			 audfmt_names[pdata->audout_format],
2693 			 pdata->audout_layout,
2694 			 pdata->audout_mclk_fs);
2695 	}
2696 
2697 	ret = 0x34 + ((io_read(sd, REG_SLAVE_ADDR)>>4) & 0x03);
2698 	state->client_cec = devm_i2c_new_dummy_device(&client->dev,
2699 						      client->adapter, ret);
2700 	if (IS_ERR(state->client_cec)) {
2701 		ret = PTR_ERR(state->client_cec);
2702 		goto err_free_mutex;
2703 	}
2704 
2705 	v4l_info(client, "CEC slave address 0x%02x\n", ret);
2706 
2707 	ret = tda1997x_core_init(sd);
2708 	if (ret)
2709 		goto err_free_mutex;
2710 
2711 	/* control handlers */
2712 	hdl = &state->hdl;
2713 	v4l2_ctrl_handler_init(hdl, 3);
2714 	ctrl = v4l2_ctrl_new_std_menu(hdl, &tda1997x_ctrl_ops,
2715 			V4L2_CID_DV_RX_IT_CONTENT_TYPE,
2716 			V4L2_DV_IT_CONTENT_TYPE_NO_ITC, 0,
2717 			V4L2_DV_IT_CONTENT_TYPE_NO_ITC);
2718 	if (ctrl)
2719 		ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
2720 	/* custom controls */
2721 	state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
2722 			V4L2_CID_DV_RX_POWER_PRESENT, 0, 1, 0, 0);
2723 	state->rgb_quantization_range_ctrl = v4l2_ctrl_new_std_menu(hdl,
2724 			&tda1997x_ctrl_ops,
2725 			V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL, 0,
2726 			V4L2_DV_RGB_RANGE_AUTO);
2727 	state->sd.ctrl_handler = hdl;
2728 	if (hdl->error) {
2729 		ret = hdl->error;
2730 		goto err_free_handler;
2731 	}
2732 	v4l2_ctrl_handler_setup(hdl);
2733 
2734 	/* initialize source pads */
2735 	state->pads[TDA1997X_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
2736 	ret = media_entity_pads_init(&sd->entity, TDA1997X_NUM_PADS,
2737 		state->pads);
2738 	if (ret) {
2739 		v4l_err(client, "failed entity_init: %d", ret);
2740 		goto err_free_handler;
2741 	}
2742 
2743 	ret = v4l2_async_register_subdev(sd);
2744 	if (ret)
2745 		goto err_free_media;
2746 
2747 	/* register audio DAI */
2748 	if (pdata->audout_format) {
2749 		u64 formats;
2750 
2751 		if (pdata->audout_width == 32)
2752 			formats = SNDRV_PCM_FMTBIT_S32_LE;
2753 		else
2754 			formats = SNDRV_PCM_FMTBIT_S16_LE;
2755 		tda1997x_audio_dai.capture.formats = formats;
2756 		ret = devm_snd_soc_register_component(&state->client->dev,
2757 					     &tda1997x_codec_driver,
2758 					     &tda1997x_audio_dai, 1);
2759 		if (ret) {
2760 			dev_err(&client->dev, "register audio codec failed\n");
2761 			goto err_free_media;
2762 		}
2763 		v4l_info(state->client, "registered audio codec\n");
2764 	}
2765 
2766 	/* request irq */
2767 	ret = devm_request_threaded_irq(&client->dev, client->irq,
2768 					NULL, tda1997x_isr_thread,
2769 					IRQF_TRIGGER_LOW | IRQF_ONESHOT,
2770 					KBUILD_MODNAME, state);
2771 	if (ret) {
2772 		v4l_err(client, "irq%d reg failed: %d\n", client->irq, ret);
2773 		goto err_free_media;
2774 	}
2775 
2776 	return 0;
2777 
2778 err_free_media:
2779 	media_entity_cleanup(&sd->entity);
2780 err_free_handler:
2781 	v4l2_ctrl_handler_free(&state->hdl);
2782 err_free_mutex:
2783 	cancel_delayed_work(&state->delayed_work_enable_hpd);
2784 	mutex_destroy(&state->page_lock);
2785 	mutex_destroy(&state->lock);
2786 err_free_state:
2787 	kfree(state);
2788 	dev_err(&client->dev, "%s failed: %d\n", __func__, ret);
2789 
2790 	return ret;
2791 }
2792 
2793 static int tda1997x_remove(struct i2c_client *client)
2794 {
2795 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
2796 	struct tda1997x_state *state = to_state(sd);
2797 	struct tda1997x_platform_data *pdata = &state->pdata;
2798 
2799 	if (pdata->audout_format) {
2800 		mutex_destroy(&state->audio_lock);
2801 	}
2802 
2803 	disable_irq(state->client->irq);
2804 	tda1997x_power_mode(state, 0);
2805 
2806 	v4l2_async_unregister_subdev(sd);
2807 	media_entity_cleanup(&sd->entity);
2808 	v4l2_ctrl_handler_free(&state->hdl);
2809 	regulator_bulk_disable(TDA1997X_NUM_SUPPLIES, state->supplies);
2810 	cancel_delayed_work_sync(&state->delayed_work_enable_hpd);
2811 	mutex_destroy(&state->page_lock);
2812 	mutex_destroy(&state->lock);
2813 
2814 	kfree(state);
2815 
2816 	return 0;
2817 }
2818 
2819 static struct i2c_driver tda1997x_i2c_driver = {
2820 	.driver = {
2821 		.name = "tda1997x",
2822 		.of_match_table = of_match_ptr(tda1997x_of_id),
2823 	},
2824 	.probe = tda1997x_probe,
2825 	.remove = tda1997x_remove,
2826 	.id_table = tda1997x_i2c_id,
2827 };
2828 
2829 module_i2c_driver(tda1997x_i2c_driver);
2830 
2831 MODULE_AUTHOR("Tim Harvey <tharvey@gateworks.com>");
2832 MODULE_DESCRIPTION("TDA1997X HDMI Receiver driver");
2833 MODULE_LICENSE("GPL v2");
2834