1 /*
2  * tc358743 - Toshiba HDMI to CSI-2 bridge - register names and bit masks
3  *
4  * Copyright 2015 Cisco Systems, Inc. and/or its affiliates. All rights
5  * reserved.
6  *
7  * This program is free software; you may redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; version 2 of the License.
10  *
11  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
12  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
13  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
14  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
15  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
16  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
17  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
18  * SOFTWARE.
19  *
20  */
21 
22 /*
23  * References (c = chapter, p = page):
24  * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60
25  */
26 
27 /* Bit masks has prefix 'MASK_' and options after '_'. */
28 
29 #ifndef __TC358743_REGS_H
30 #define __TC358743_REGS_H
31 
32 #define CHIPID                                0x0000
33 #define MASK_CHIPID                           0xff00
34 #define MASK_REVID                            0x00ff
35 
36 #define SYSCTL                                0x0002
37 #define MASK_IRRST                            0x0800
38 #define MASK_CECRST                           0x0400
39 #define MASK_CTXRST                           0x0200
40 #define MASK_HDMIRST                          0x0100
41 #define MASK_SLEEP                            0x0001
42 
43 #define CONFCTL                               0x0004
44 #define MASK_PWRISO                           0x8000
45 #define MASK_ACLKOPT                          0x1000
46 #define MASK_AUDCHNUM                         0x0c00
47 #define MASK_AUDCHNUM_8                       0x0000
48 #define MASK_AUDCHNUM_6                       0x0400
49 #define MASK_AUDCHNUM_4                       0x0800
50 #define MASK_AUDCHNUM_2                       0x0c00
51 #define MASK_AUDCHSEL                         0x0200
52 #define MASK_I2SDLYOPT                        0x0100
53 #define MASK_YCBCRFMT                         0x00c0
54 #define MASK_YCBCRFMT_444                     0x0000
55 #define MASK_YCBCRFMT_422_12_BIT              0x0040
56 #define MASK_YCBCRFMT_COLORBAR                0x0080
57 #define MASK_YCBCRFMT_422_8_BIT               0x00c0
58 #define MASK_INFRMEN                          0x0020
59 #define MASK_AUDOUTSEL                        0x0018
60 #define MASK_AUDOUTSEL_CSI                    0x0000
61 #define MASK_AUDOUTSEL_I2S                    0x0010
62 #define MASK_AUDOUTSEL_TDM                    0x0018
63 #define MASK_AUTOINDEX                        0x0004
64 #define MASK_ABUFEN                           0x0002
65 #define MASK_VBUFEN                           0x0001
66 
67 #define FIFOCTL                               0x0006
68 
69 #define INTSTATUS                             0x0014
70 #define MASK_AMUTE_INT                        0x0400
71 #define MASK_HDMI_INT                         0x0200
72 #define MASK_CSI_INT                          0x0100
73 #define MASK_SYS_INT                          0x0020
74 #define MASK_CEC_EINT                         0x0010
75 #define MASK_CEC_TINT                         0x0008
76 #define MASK_CEC_RINT                         0x0004
77 #define MASK_IR_EINT                          0x0002
78 #define MASK_IR_DINT                          0x0001
79 
80 #define INTMASK                               0x0016
81 #define MASK_AMUTE_MSK                        0x0400
82 #define MASK_HDMI_MSK                         0x0200
83 #define MASK_CSI_MSK                          0x0100
84 #define MASK_SYS_MSK                          0x0020
85 #define MASK_CEC_EMSK                         0x0010
86 #define MASK_CEC_TMSK                         0x0008
87 #define MASK_CEC_RMSK                         0x0004
88 #define MASK_IR_EMSK                          0x0002
89 #define MASK_IR_DMSK                          0x0001
90 
91 #define INTFLAG                               0x0018
92 #define INTSYSSTATUS                          0x001A
93 
94 #define PLLCTL0                               0x0020
95 #define MASK_PLL_PRD                          0xf000
96 #define SET_PLL_PRD(prd)                      ((((prd) - 1) << 12) &\
97 						MASK_PLL_PRD)
98 #define MASK_PLL_FBD                          0x01ff
99 #define SET_PLL_FBD(fbd)                      (((fbd) - 1) & MASK_PLL_FBD)
100 
101 #define PLLCTL1                               0x0022
102 #define MASK_PLL_FRS                          0x0c00
103 #define SET_PLL_FRS(frs)                      (((frs) << 10) & MASK_PLL_FRS)
104 #define MASK_PLL_LBWS                         0x0300
105 #define MASK_LFBREN                           0x0040
106 #define MASK_BYPCKEN                          0x0020
107 #define MASK_CKEN                             0x0010
108 #define MASK_RESETB                           0x0002
109 #define MASK_PLL_EN                           0x0001
110 
111 #define CLW_CNTRL                             0x0140
112 #define MASK_CLW_LANEDISABLE                  0x0001
113 
114 #define D0W_CNTRL                             0x0144
115 #define MASK_D0W_LANEDISABLE                  0x0001
116 
117 #define D1W_CNTRL                             0x0148
118 #define MASK_D1W_LANEDISABLE                  0x0001
119 
120 #define D2W_CNTRL                             0x014C
121 #define MASK_D2W_LANEDISABLE                  0x0001
122 
123 #define D3W_CNTRL                             0x0150
124 #define MASK_D3W_LANEDISABLE                  0x0001
125 
126 #define STARTCNTRL                            0x0204
127 #define MASK_START                            0x00000001
128 
129 #define LINEINITCNT                           0x0210
130 #define LPTXTIMECNT                           0x0214
131 #define TCLK_HEADERCNT                        0x0218
132 #define TCLK_TRAILCNT                         0x021C
133 #define THS_HEADERCNT                         0x0220
134 #define TWAKEUP                               0x0224
135 #define TCLK_POSTCNT                          0x0228
136 #define THS_TRAILCNT                          0x022C
137 #define HSTXVREGCNT                           0x0230
138 
139 #define HSTXVREGEN                            0x0234
140 #define MASK_D3M_HSTXVREGEN                   0x0010
141 #define MASK_D2M_HSTXVREGEN                   0x0008
142 #define MASK_D1M_HSTXVREGEN                   0x0004
143 #define MASK_D0M_HSTXVREGEN                   0x0002
144 #define MASK_CLM_HSTXVREGEN                   0x0001
145 
146 
147 #define TXOPTIONCNTRL                         0x0238
148 #define MASK_CONTCLKMODE                      0x00000001
149 
150 #define CSI_CONTROL                           0x040C
151 #define MASK_CSI_MODE                         0x8000
152 #define MASK_HTXTOEN                          0x0400
153 #define MASK_TXHSMD                           0x0080
154 #define MASK_HSCKMD                           0x0020
155 #define MASK_NOL                              0x0006
156 #define MASK_NOL_1                            0x0000
157 #define MASK_NOL_2                            0x0002
158 #define MASK_NOL_3                            0x0004
159 #define MASK_NOL_4                            0x0006
160 #define MASK_EOTDIS                           0x0001
161 
162 #define CSI_INT                               0x0414
163 #define MASK_INTHLT                           0x00000008
164 #define MASK_INTER                            0x00000004
165 
166 #define CSI_INT_ENA                           0x0418
167 #define MASK_IENHLT                           0x00000008
168 #define MASK_IENER                            0x00000004
169 
170 #define CSI_ERR                               0x044C
171 #define MASK_INER                             0x00000200
172 #define MASK_WCER                             0x00000100
173 #define MASK_QUNK                             0x00000010
174 #define MASK_TXBRK                            0x00000002
175 
176 #define CSI_ERR_INTENA                        0x0450
177 #define CSI_ERR_HALT                          0x0454
178 
179 #define CSI_CONFW                             0x0500
180 #define MASK_MODE                             0xe0000000
181 #define MASK_MODE_SET                         0xa0000000
182 #define MASK_MODE_CLEAR                       0xc0000000
183 #define MASK_ADDRESS                          0x1f000000
184 #define MASK_ADDRESS_CSI_CONTROL              0x03000000
185 #define MASK_ADDRESS_CSI_INT_ENA              0x06000000
186 #define MASK_ADDRESS_CSI_ERR_INTENA           0x14000000
187 #define MASK_ADDRESS_CSI_ERR_HALT             0x15000000
188 #define MASK_DATA                             0x0000ffff
189 
190 #define CSI_INT_CLR                           0x050C
191 #define MASK_ICRER                            0x00000004
192 
193 #define CSI_START                             0x0518
194 #define MASK_STRT                             0x00000001
195 
196 #define CECEN                                 0x0600
197 #define MASK_CECEN                            0x0001
198 
199 #define HDMI_INT0                             0x8500
200 #define MASK_I_KEY                            0x80
201 #define MASK_I_MISC                           0x02
202 #define MASK_I_PHYERR                         0x01
203 
204 #define HDMI_INT1                             0x8501
205 #define MASK_I_GBD                            0x80
206 #define MASK_I_HDCP                           0x40
207 #define MASK_I_ERR                            0x20
208 #define MASK_I_AUD                            0x10
209 #define MASK_I_CBIT                           0x08
210 #define MASK_I_PACKET                         0x04
211 #define MASK_I_CLK                            0x02
212 #define MASK_I_SYS                            0x01
213 
214 #define SYS_INT                               0x8502
215 #define MASK_I_ACR_CTS                        0x80
216 #define MASK_I_ACRN                           0x40
217 #define MASK_I_DVI                            0x20
218 #define MASK_I_HDMI                           0x10
219 #define MASK_I_NOPMBDET                       0x08
220 #define MASK_I_DPMBDET                        0x04
221 #define MASK_I_TMDS                           0x02
222 #define MASK_I_DDC                            0x01
223 
224 #define CLK_INT                               0x8503
225 #define MASK_I_OUT_H_CHG                      0x40
226 #define MASK_I_IN_DE_CHG                      0x20
227 #define MASK_I_IN_HV_CHG                      0x10
228 #define MASK_I_DC_CHG                         0x08
229 #define MASK_I_PXCLK_CHG                      0x04
230 #define MASK_I_PHYCLK_CHG                     0x02
231 #define MASK_I_TMDSCLK_CHG                    0x01
232 
233 #define CBIT_INT                              0x8505
234 #define MASK_I_AF_LOCK                        0x80
235 #define MASK_I_AF_UNLOCK                      0x40
236 #define MASK_I_CBIT_FS                        0x02
237 
238 #define AUDIO_INT                             0x8506
239 
240 #define ERR_INT                               0x8507
241 #define MASK_I_EESS_ERR                       0x80
242 
243 #define HDCP_INT                              0x8508
244 #define MASK_I_AVM_SET                        0x80
245 #define MASK_I_AVM_CLR                        0x40
246 #define MASK_I_LINKERR                        0x20
247 #define MASK_I_SHA_END                        0x10
248 #define MASK_I_R0_END                         0x08
249 #define MASK_I_KM_END                         0x04
250 #define MASK_I_AKSV_END                       0x02
251 #define MASK_I_AN_END                         0x01
252 
253 #define MISC_INT                              0x850B
254 #define MASK_I_AS_LAYOUT                      0x10
255 #define MASK_I_NO_SPD                         0x08
256 #define MASK_I_NO_VS                          0x03
257 #define MASK_I_SYNC_CHG                       0x02
258 #define MASK_I_AUDIO_MUTE                     0x01
259 
260 #define KEY_INT                               0x850F
261 
262 #define SYS_INTM                              0x8512
263 #define MASK_M_ACR_CTS                        0x80
264 #define MASK_M_ACR_N                          0x40
265 #define MASK_M_DVI_DET                        0x20
266 #define MASK_M_HDMI_DET                       0x10
267 #define MASK_M_NOPMBDET                       0x08
268 #define MASK_M_BPMBDET                        0x04
269 #define MASK_M_TMDS                           0x02
270 #define MASK_M_DDC                            0x01
271 
272 #define CLK_INTM                              0x8513
273 #define MASK_M_OUT_H_CHG                      0x40
274 #define MASK_M_IN_DE_CHG                      0x20
275 #define MASK_M_IN_HV_CHG                      0x10
276 #define MASK_M_DC_CHG                         0x08
277 #define MASK_M_PXCLK_CHG                      0x04
278 #define MASK_M_PHYCLK_CHG                     0x02
279 #define MASK_M_TMDS_CHG                       0x01
280 
281 #define PACKET_INTM                           0x8514
282 
283 #define CBIT_INTM                             0x8515
284 #define MASK_M_AF_LOCK                        0x80
285 #define MASK_M_AF_UNLOCK                      0x40
286 #define MASK_M_CBIT_FS                        0x02
287 
288 #define AUDIO_INTM                            0x8516
289 #define MASK_M_BUFINIT_END                    0x01
290 
291 #define ERR_INTM                              0x8517
292 #define MASK_M_EESS_ERR                       0x80
293 
294 #define HDCP_INTM                             0x8518
295 #define MASK_M_AVM_SET                        0x80
296 #define MASK_M_AVM_CLR                        0x40
297 #define MASK_M_LINKERR                        0x20
298 #define MASK_M_SHA_END                        0x10
299 #define MASK_M_R0_END                         0x08
300 #define MASK_M_KM_END                         0x04
301 #define MASK_M_AKSV_END                       0x02
302 #define MASK_M_AN_END                         0x01
303 
304 #define MISC_INTM                             0x851B
305 #define MASK_M_AS_LAYOUT                      0x10
306 #define MASK_M_NO_SPD                         0x08
307 #define MASK_M_NO_VS                          0x03
308 #define MASK_M_SYNC_CHG                       0x02
309 #define MASK_M_AUDIO_MUTE                     0x01
310 
311 #define KEY_INTM                              0x851F
312 
313 #define SYS_STATUS                            0x8520
314 #define MASK_S_SYNC                           0x80
315 #define MASK_S_AVMUTE                         0x40
316 #define MASK_S_HDCP                           0x20
317 #define MASK_S_HDMI                           0x10
318 #define MASK_S_PHY_SCDT                       0x08
319 #define MASK_S_PHY_PLL                        0x04
320 #define MASK_S_TMDS                           0x02
321 #define MASK_S_DDC5V                          0x01
322 
323 #define CSI_STATUS                            0x0410
324 #define MASK_S_WSYNC                          0x0400
325 #define MASK_S_TXACT                          0x0200
326 #define MASK_S_RXACT                          0x0100
327 #define MASK_S_HLT                            0x0001
328 
329 #define VI_STATUS1                            0x8522
330 #define MASK_S_V_GBD                          0x08
331 #define MASK_S_DEEPCOLOR                      0x0c
332 #define MASK_S_V_422                          0x02
333 #define MASK_S_V_INTERLACE                    0x01
334 
335 #define AU_STATUS0                            0x8523
336 #define MASK_S_A_SAMPLE                       0x01
337 
338 #define VI_STATUS3                            0x8528
339 #define MASK_S_V_COLOR                        0x1e
340 #define MASK_LIMITED                          0x01
341 
342 #define PHY_CTL0                              0x8531
343 #define MASK_PHY_SYSCLK_IND                   0x02
344 #define MASK_PHY_CTL                          0x01
345 
346 
347 #define PHY_CTL1                              0x8532 /* Not in REF_01 */
348 #define MASK_PHY_AUTO_RST1                    0xf0
349 #define MASK_PHY_AUTO_RST1_OFF                0x00
350 #define SET_PHY_AUTO_RST1_US(us)             ((((us) / 200) << 4) & \
351 						MASK_PHY_AUTO_RST1)
352 #define MASK_FREQ_RANGE_MODE                  0x0f
353 #define SET_FREQ_RANGE_MODE_CYCLES(cycles)   (((cycles) - 1) & \
354 						MASK_FREQ_RANGE_MODE)
355 
356 #define PHY_CTL2                              0x8533 /* Not in REF_01 */
357 #define MASK_PHY_AUTO_RST4                    0x04
358 #define MASK_PHY_AUTO_RST3                    0x02
359 #define MASK_PHY_AUTO_RST2                    0x01
360 #define MASK_PHY_AUTO_RSTn                    (MASK_PHY_AUTO_RST4 | \
361 						MASK_PHY_AUTO_RST3 | \
362 						MASK_PHY_AUTO_RST2)
363 
364 #define PHY_EN                                0x8534
365 #define MASK_ENABLE_PHY                       0x01
366 
367 #define PHY_RST                               0x8535
368 #define MASK_RESET_CTRL                       0x01   /* Reset active low */
369 
370 #define PHY_BIAS                              0x8536 /* Not in REF_01 */
371 
372 #define PHY_CSQ                               0x853F /* Not in REF_01 */
373 #define MASK_CSQ_CNT                          0x0f
374 #define SET_CSQ_CNT_LEVEL(n)                 (n & MASK_CSQ_CNT)
375 
376 #define SYS_FREQ0                             0x8540
377 #define SYS_FREQ1                             0x8541
378 
379 #define SYS_CLK                               0x8542 /* Not in REF_01 */
380 #define MASK_CLK_DIFF                         0x0C
381 #define MASK_CLK_DIV                          0x03
382 
383 #define DDC_CTL                               0x8543
384 #define MASK_DDC_ACK_POL                      0x08
385 #define MASK_DDC_ACTION                       0x04
386 #define MASK_DDC5V_MODE                       0x03
387 #define MASK_DDC5V_MODE_0MS                   0x00
388 #define MASK_DDC5V_MODE_50MS                  0x01
389 #define MASK_DDC5V_MODE_100MS                 0x02
390 #define MASK_DDC5V_MODE_200MS                 0x03
391 
392 #define HPD_CTL                               0x8544
393 #define MASK_HPD_CTL0                         0x10
394 #define MASK_HPD_OUT0                         0x01
395 
396 #define ANA_CTL                               0x8545
397 #define MASK_APPL_PCSX                        0x30
398 #define MASK_APPL_PCSX_HIZ                    0x00
399 #define MASK_APPL_PCSX_L_FIX                  0x10
400 #define MASK_APPL_PCSX_H_FIX                  0x20
401 #define MASK_APPL_PCSX_NORMAL                 0x30
402 #define MASK_ANALOG_ON                        0x01
403 
404 #define AVM_CTL                               0x8546
405 
406 #define INIT_END                              0x854A
407 #define MASK_INIT_END                         0x01
408 
409 #define HDMI_DET                              0x8552 /* Not in REF_01 */
410 #define MASK_HDMI_DET_MOD1                    0x80
411 #define MASK_HDMI_DET_MOD0                    0x40
412 #define MASK_HDMI_DET_V                       0x30
413 #define MASK_HDMI_DET_V_SYNC                  0x00
414 #define MASK_HDMI_DET_V_ASYNC_25MS            0x10
415 #define MASK_HDMI_DET_V_ASYNC_50MS            0x20
416 #define MASK_HDMI_DET_V_ASYNC_100MS           0x30
417 #define MASK_HDMI_DET_NUM                     0x0f
418 
419 #define HDCP_MODE                             0x8560
420 #define MASK_MODE_RST_TN                      0x20
421 #define MASK_LINE_REKEY                       0x10
422 #define MASK_AUTO_CLR                         0x04
423 
424 #define HDCP_REG1                             0x8563 /* Not in REF_01 */
425 #define MASK_AUTH_UNAUTH_SEL                  0x70
426 #define MASK_AUTH_UNAUTH_SEL_12_FRAMES        0x70
427 #define MASK_AUTH_UNAUTH_SEL_8_FRAMES         0x60
428 #define MASK_AUTH_UNAUTH_SEL_4_FRAMES         0x50
429 #define MASK_AUTH_UNAUTH_SEL_2_FRAMES         0x40
430 #define MASK_AUTH_UNAUTH_SEL_64_FRAMES        0x30
431 #define MASK_AUTH_UNAUTH_SEL_32_FRAMES        0x20
432 #define MASK_AUTH_UNAUTH_SEL_16_FRAMES        0x10
433 #define MASK_AUTH_UNAUTH_SEL_ONCE             0x00
434 #define MASK_AUTH_UNAUTH                      0x01
435 #define MASK_AUTH_UNAUTH_AUTO                 0x01
436 
437 #define HDCP_REG2                             0x8564 /* Not in REF_01 */
438 #define MASK_AUTO_P3_RESET                    0x0F
439 #define SET_AUTO_P3_RESET_FRAMES(n)          (n & MASK_AUTO_P3_RESET)
440 #define MASK_AUTO_P3_RESET_OFF                0x00
441 
442 #define VI_MODE                               0x8570
443 #define MASK_RGB_DVI                          0x08 /* Not in REF_01 */
444 
445 #define VOUT_SET2                             0x8573
446 #define MASK_SEL422                           0x80
447 #define MASK_VOUT_422FIL_100                  0x40
448 #define MASK_VOUTCOLORMODE                    0x03
449 #define MASK_VOUTCOLORMODE_THROUGH            0x00
450 #define MASK_VOUTCOLORMODE_AUTO               0x01
451 #define MASK_VOUTCOLORMODE_MANUAL             0x03
452 
453 #define VOUT_SET3                             0x8574
454 #define MASK_VOUT_EXTCNT                      0x08
455 
456 #define VI_REP                                0x8576
457 #define MASK_VOUT_COLOR_SEL                   0xe0
458 #define MASK_VOUT_COLOR_RGB_FULL              0x00
459 #define MASK_VOUT_COLOR_RGB_LIMITED           0x20
460 #define MASK_VOUT_COLOR_601_YCBCR_FULL        0x40
461 #define MASK_VOUT_COLOR_601_YCBCR_LIMITED     0x60
462 #define MASK_VOUT_COLOR_709_YCBCR_FULL        0x80
463 #define MASK_VOUT_COLOR_709_YCBCR_LIMITED     0xa0
464 #define MASK_VOUT_COLOR_FULL_TO_LIMITED       0xc0
465 #define MASK_VOUT_COLOR_LIMITED_TO_FULL       0xe0
466 #define MASK_IN_REP_HEN                       0x10
467 #define MASK_IN_REP                           0x0f
468 
469 #define VI_MUTE                               0x857F
470 #define MASK_AUTO_MUTE                        0xc0
471 #define MASK_VI_MUTE                          0x10
472 
473 #define DE_WIDTH_H_LO                         0x8582 /* Not in REF_01 */
474 #define DE_WIDTH_H_HI                         0x8583 /* Not in REF_01 */
475 #define DE_WIDTH_V_LO                         0x8588 /* Not in REF_01 */
476 #define DE_WIDTH_V_HI                         0x8589 /* Not in REF_01 */
477 #define H_SIZE_LO                             0x858A /* Not in REF_01 */
478 #define H_SIZE_HI                             0x858B /* Not in REF_01 */
479 #define V_SIZE_LO                             0x858C /* Not in REF_01 */
480 #define V_SIZE_HI                             0x858D /* Not in REF_01 */
481 #define FV_CNT_LO                             0x85A1 /* Not in REF_01 */
482 #define FV_CNT_HI                             0x85A2 /* Not in REF_01 */
483 
484 #define FH_MIN0                               0x85AA /* Not in REF_01 */
485 #define FH_MIN1                               0x85AB /* Not in REF_01 */
486 #define FH_MAX0                               0x85AC /* Not in REF_01 */
487 #define FH_MAX1                               0x85AD /* Not in REF_01 */
488 
489 #define HV_RST                                0x85AF /* Not in REF_01 */
490 #define MASK_H_PI_RST                         0x20
491 #define MASK_V_PI_RST                         0x10
492 
493 #define EDID_MODE                             0x85C7
494 #define MASK_EDID_SPEED                       0x40
495 #define MASK_EDID_MODE                        0x03
496 #define MASK_EDID_MODE_DISABLE                0x00
497 #define MASK_EDID_MODE_DDC2B                  0x01
498 #define MASK_EDID_MODE_E_DDC                  0x02
499 
500 #define EDID_LEN1                             0x85CA
501 #define EDID_LEN2                             0x85CB
502 
503 #define HDCP_REG3                             0x85D1 /* Not in REF_01 */
504 #define KEY_RD_CMD                            0x01
505 
506 #define FORCE_MUTE                            0x8600
507 #define MASK_FORCE_AMUTE                      0x10
508 #define MASK_FORCE_DMUTE                      0x01
509 
510 #define CMD_AUD                               0x8601
511 #define MASK_CMD_BUFINIT                      0x04
512 #define MASK_CMD_LOCKDET                      0x02
513 #define MASK_CMD_MUTE                         0x01
514 
515 #define AUTO_CMD0                             0x8602
516 #define MASK_AUTO_MUTE7                       0x80
517 #define MASK_AUTO_MUTE6                       0x40
518 #define MASK_AUTO_MUTE5                       0x20
519 #define MASK_AUTO_MUTE4                       0x10
520 #define MASK_AUTO_MUTE3                       0x08
521 #define MASK_AUTO_MUTE2                       0x04
522 #define MASK_AUTO_MUTE1                       0x02
523 #define MASK_AUTO_MUTE0                       0x01
524 
525 #define AUTO_CMD1                             0x8603
526 #define MASK_AUTO_MUTE10                      0x04
527 #define MASK_AUTO_MUTE9                       0x02
528 #define MASK_AUTO_MUTE8                       0x01
529 
530 #define AUTO_CMD2                             0x8604
531 #define MASK_AUTO_PLAY3                       0x08
532 #define MASK_AUTO_PLAY2                       0x04
533 
534 #define BUFINIT_START                         0x8606
535 #define SET_BUFINIT_START_MS(milliseconds)   ((milliseconds) / 100)
536 
537 #define FS_MUTE                               0x8607
538 #define MASK_FS_ELSE_MUTE                     0x80
539 #define MASK_FS22_MUTE                        0x40
540 #define MASK_FS24_MUTE                        0x20
541 #define MASK_FS88_MUTE                        0x10
542 #define MASK_FS96_MUTE                        0x08
543 #define MASK_FS176_MUTE                       0x04
544 #define MASK_FS192_MUTE                       0x02
545 #define MASK_FS_NO_MUTE                       0x01
546 
547 #define FS_IMODE                              0x8620
548 #define MASK_NLPCM_HMODE                      0x40
549 #define MASK_NLPCM_SMODE                      0x20
550 #define MASK_NLPCM_IMODE                      0x10
551 #define MASK_FS_HMODE                         0x08
552 #define MASK_FS_AMODE                         0x04
553 #define MASK_FS_SMODE                         0x02
554 #define MASK_FS_IMODE                         0x01
555 
556 #define FS_SET                                0x8621
557 #define MASK_FS                               0x0f
558 
559 #define LOCKDET_REF0                          0x8630
560 #define LOCKDET_REF1                          0x8631
561 #define LOCKDET_REF2                          0x8632
562 
563 #define ACR_MODE                              0x8640
564 #define MASK_ACR_LOAD                         0x10
565 #define MASK_N_MODE                           0x04
566 #define MASK_CTS_MODE                         0x01
567 
568 #define ACR_MDF0                              0x8641
569 #define MASK_ACR_L2MDF                        0x70
570 #define MASK_ACR_L2MDF_0_PPM                  0x00
571 #define MASK_ACR_L2MDF_61_PPM                 0x10
572 #define MASK_ACR_L2MDF_122_PPM                0x20
573 #define MASK_ACR_L2MDF_244_PPM                0x30
574 #define MASK_ACR_L2MDF_488_PPM                0x40
575 #define MASK_ACR_L2MDF_976_PPM                0x50
576 #define MASK_ACR_L2MDF_1976_PPM               0x60
577 #define MASK_ACR_L2MDF_3906_PPM               0x70
578 #define MASK_ACR_L1MDF                        0x07
579 #define MASK_ACR_L1MDF_0_PPM                  0x00
580 #define MASK_ACR_L1MDF_61_PPM                 0x01
581 #define MASK_ACR_L1MDF_122_PPM                0x02
582 #define MASK_ACR_L1MDF_244_PPM                0x03
583 #define MASK_ACR_L1MDF_488_PPM                0x04
584 #define MASK_ACR_L1MDF_976_PPM                0x05
585 #define MASK_ACR_L1MDF_1976_PPM               0x06
586 #define MASK_ACR_L1MDF_3906_PPM               0x07
587 
588 #define ACR_MDF1                              0x8642
589 #define MASK_ACR_L3MDF                        0x07
590 #define MASK_ACR_L3MDF_0_PPM                  0x00
591 #define MASK_ACR_L3MDF_61_PPM                 0x01
592 #define MASK_ACR_L3MDF_122_PPM                0x02
593 #define MASK_ACR_L3MDF_244_PPM                0x03
594 #define MASK_ACR_L3MDF_488_PPM                0x04
595 #define MASK_ACR_L3MDF_976_PPM                0x05
596 #define MASK_ACR_L3MDF_1976_PPM               0x06
597 #define MASK_ACR_L3MDF_3906_PPM               0x07
598 
599 #define SDO_MODE1                             0x8652
600 #define MASK_SDO_BIT_LENG                     0x70
601 #define MASK_SDO_FMT                          0x03
602 #define MASK_SDO_FMT_RIGHT                    0x00
603 #define MASK_SDO_FMT_LEFT                     0x01
604 #define MASK_SDO_FMT_I2S                      0x02
605 
606 #define DIV_MODE                              0x8665 /* Not in REF_01 */
607 #define MASK_DIV_DLY                          0xf0
608 #define SET_DIV_DLY_MS(milliseconds)         ((((milliseconds) / 100) << 4) & \
609 						MASK_DIV_DLY)
610 #define MASK_DIV_MODE                         0x01
611 
612 #define NCO_F0_MOD                            0x8670
613 #define MASK_NCO_F0_MOD                       0x03
614 #define MASK_NCO_F0_MOD_42MHZ                 0x00
615 #define MASK_NCO_F0_MOD_27MHZ                 0x01
616 
617 #define PK_INT_MODE                           0x8709
618 #define MASK_ISRC2_INT_MODE                   0x80
619 #define MASK_ISRC_INT_MODE                    0x40
620 #define MASK_ACP_INT_MODE                     0x20
621 #define MASK_VS_INT_MODE                      0x10
622 #define MASK_SPD_INT_MODE                     0x08
623 #define MASK_MS_INT_MODE                      0x04
624 #define MASK_AUD_INT_MODE                     0x02
625 #define MASK_AVI_INT_MODE                     0x01
626 
627 #define NO_PKT_LIMIT                          0x870B
628 #define MASK_NO_ACP_LIMIT                     0xf0
629 #define SET_NO_ACP_LIMIT_MS(milliseconds)    ((((milliseconds) / 80) << 4) & \
630 						MASK_NO_ACP_LIMIT)
631 #define MASK_NO_AVI_LIMIT                     0x0f
632 #define SET_NO_AVI_LIMIT_MS(milliseconds)    (((milliseconds) / 80) & \
633 						MASK_NO_AVI_LIMIT)
634 
635 #define NO_PKT_CLR                            0x870C
636 #define MASK_NO_VS_CLR                        0x40
637 #define MASK_NO_SPD_CLR                       0x20
638 #define MASK_NO_ACP_CLR                       0x10
639 #define MASK_NO_AVI_CLR1                      0x02
640 #define MASK_NO_AVI_CLR0                      0x01
641 
642 #define ERR_PK_LIMIT                          0x870D
643 #define NO_PKT_LIMIT2                         0x870E
644 #define PK_AVI_0HEAD                          0x8710
645 #define PK_AVI_1HEAD                          0x8711
646 #define PK_AVI_2HEAD                          0x8712
647 #define PK_AVI_0BYTE                          0x8713
648 #define PK_AVI_1BYTE                          0x8714
649 #define PK_AVI_2BYTE                          0x8715
650 #define PK_AVI_3BYTE                          0x8716
651 #define PK_AVI_4BYTE                          0x8717
652 #define PK_AVI_5BYTE                          0x8718
653 #define PK_AVI_6BYTE                          0x8719
654 #define PK_AVI_7BYTE                          0x871A
655 #define PK_AVI_8BYTE                          0x871B
656 #define PK_AVI_9BYTE                          0x871C
657 #define PK_AVI_10BYTE                         0x871D
658 #define PK_AVI_11BYTE                         0x871E
659 #define PK_AVI_12BYTE                         0x871F
660 #define PK_AVI_13BYTE                         0x8720
661 #define PK_AVI_14BYTE                         0x8721
662 #define PK_AVI_15BYTE                         0x8722
663 #define PK_AVI_16BYTE                         0x8723
664 
665 #define BKSV                                  0x8800
666 
667 #define BCAPS                                 0x8840
668 #define MASK_HDMI_RSVD                        0x80
669 #define MASK_REPEATER                         0x40
670 #define MASK_READY                            0x20
671 #define MASK_FASTI2C                          0x10
672 #define MASK_1_1_FEA                          0x02
673 #define MASK_FAST_REAU                        0x01
674 
675 #define BSTATUS1                              0x8842
676 #define MASK_MAX_EXCED                        0x08
677 
678 #define EDID_RAM                              0x8C00
679 #define NO_GDB_LIMIT                          0x9007
680 
681 #endif
682