1 /* 2 * tc358743 - Toshiba HDMI to CSI-2 bridge 3 * 4 * Copyright 2015 Cisco Systems, Inc. and/or its affiliates. All rights 5 * reserved. 6 * 7 * This program is free software; you may redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; version 2 of the License. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 12 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 13 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 15 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 16 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 17 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 18 * SOFTWARE. 19 * 20 */ 21 22 /* 23 * References (c = chapter, p = page): 24 * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60 25 * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls 26 */ 27 28 #include <linux/kernel.h> 29 #include <linux/module.h> 30 #include <linux/slab.h> 31 #include <linux/i2c.h> 32 #include <linux/clk.h> 33 #include <linux/delay.h> 34 #include <linux/gpio/consumer.h> 35 #include <linux/interrupt.h> 36 #include <linux/timer.h> 37 #include <linux/of_graph.h> 38 #include <linux/videodev2.h> 39 #include <linux/workqueue.h> 40 #include <linux/v4l2-dv-timings.h> 41 #include <linux/hdmi.h> 42 #include <media/v4l2-dv-timings.h> 43 #include <media/v4l2-device.h> 44 #include <media/v4l2-ctrls.h> 45 #include <media/v4l2-event.h> 46 #include <media/v4l2-fwnode.h> 47 #include <media/i2c/tc358743.h> 48 49 #include "tc358743_regs.h" 50 51 static int debug; 52 module_param(debug, int, 0644); 53 MODULE_PARM_DESC(debug, "debug level (0-3)"); 54 55 MODULE_DESCRIPTION("Toshiba TC358743 HDMI to CSI-2 bridge driver"); 56 MODULE_AUTHOR("Ramakrishnan Muthukrishnan <ram@rkrishnan.org>"); 57 MODULE_AUTHOR("Mikhail Khelik <mkhelik@cisco.com>"); 58 MODULE_AUTHOR("Mats Randgaard <matrandg@cisco.com>"); 59 MODULE_LICENSE("GPL"); 60 61 #define EDID_NUM_BLOCKS_MAX 8 62 #define EDID_BLOCK_SIZE 128 63 64 #define I2C_MAX_XFER_SIZE (EDID_BLOCK_SIZE + 2) 65 66 #define POLL_INTERVAL_MS 1000 67 68 static const struct v4l2_dv_timings_cap tc358743_timings_cap = { 69 .type = V4L2_DV_BT_656_1120, 70 /* keep this initialization for compatibility with GCC < 4.4.6 */ 71 .reserved = { 0 }, 72 /* Pixel clock from REF_01 p. 20. Min/max height/width are unknown */ 73 V4L2_INIT_BT_TIMINGS(1, 10000, 1, 10000, 0, 165000000, 74 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 75 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, 76 V4L2_DV_BT_CAP_PROGRESSIVE | 77 V4L2_DV_BT_CAP_REDUCED_BLANKING | 78 V4L2_DV_BT_CAP_CUSTOM) 79 }; 80 81 struct tc358743_state { 82 struct tc358743_platform_data pdata; 83 struct v4l2_fwnode_bus_mipi_csi2 bus; 84 struct v4l2_subdev sd; 85 struct media_pad pad; 86 struct v4l2_ctrl_handler hdl; 87 struct i2c_client *i2c_client; 88 /* CONFCTL is modified in ops and tc358743_hdmi_sys_int_handler */ 89 struct mutex confctl_mutex; 90 91 /* controls */ 92 struct v4l2_ctrl *detect_tx_5v_ctrl; 93 struct v4l2_ctrl *audio_sampling_rate_ctrl; 94 struct v4l2_ctrl *audio_present_ctrl; 95 96 struct delayed_work delayed_work_enable_hotplug; 97 98 struct timer_list timer; 99 struct work_struct work_i2c_poll; 100 101 /* edid */ 102 u8 edid_blocks_written; 103 104 struct v4l2_dv_timings timings; 105 u32 mbus_fmt_code; 106 u8 csi_lanes_in_use; 107 108 struct gpio_desc *reset_gpio; 109 }; 110 111 static void tc358743_enable_interrupts(struct v4l2_subdev *sd, 112 bool cable_connected); 113 static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd); 114 115 static inline struct tc358743_state *to_state(struct v4l2_subdev *sd) 116 { 117 return container_of(sd, struct tc358743_state, sd); 118 } 119 120 /* --------------- I2C --------------- */ 121 122 static void i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n) 123 { 124 struct tc358743_state *state = to_state(sd); 125 struct i2c_client *client = state->i2c_client; 126 int err; 127 u8 buf[2] = { reg >> 8, reg & 0xff }; 128 struct i2c_msg msgs[] = { 129 { 130 .addr = client->addr, 131 .flags = 0, 132 .len = 2, 133 .buf = buf, 134 }, 135 { 136 .addr = client->addr, 137 .flags = I2C_M_RD, 138 .len = n, 139 .buf = values, 140 }, 141 }; 142 143 err = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); 144 if (err != ARRAY_SIZE(msgs)) { 145 v4l2_err(sd, "%s: reading register 0x%x from 0x%x failed\n", 146 __func__, reg, client->addr); 147 } 148 } 149 150 static void i2c_wr(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n) 151 { 152 struct tc358743_state *state = to_state(sd); 153 struct i2c_client *client = state->i2c_client; 154 int err, i; 155 struct i2c_msg msg; 156 u8 data[I2C_MAX_XFER_SIZE]; 157 158 if ((2 + n) > I2C_MAX_XFER_SIZE) { 159 n = I2C_MAX_XFER_SIZE - 2; 160 v4l2_warn(sd, "i2c wr reg=%04x: len=%d is too big!\n", 161 reg, 2 + n); 162 } 163 164 msg.addr = client->addr; 165 msg.buf = data; 166 msg.len = 2 + n; 167 msg.flags = 0; 168 169 data[0] = reg >> 8; 170 data[1] = reg & 0xff; 171 172 for (i = 0; i < n; i++) 173 data[2 + i] = values[i]; 174 175 err = i2c_transfer(client->adapter, &msg, 1); 176 if (err != 1) { 177 v4l2_err(sd, "%s: writing register 0x%x from 0x%x failed\n", 178 __func__, reg, client->addr); 179 return; 180 } 181 182 if (debug < 3) 183 return; 184 185 switch (n) { 186 case 1: 187 v4l2_info(sd, "I2C write 0x%04x = 0x%02x", 188 reg, data[2]); 189 break; 190 case 2: 191 v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x", 192 reg, data[3], data[2]); 193 break; 194 case 4: 195 v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x%02x%02x", 196 reg, data[5], data[4], data[3], data[2]); 197 break; 198 default: 199 v4l2_info(sd, "I2C write %d bytes from address 0x%04x\n", 200 n, reg); 201 } 202 } 203 204 static noinline u32 i2c_rdreg(struct v4l2_subdev *sd, u16 reg, u32 n) 205 { 206 __le32 val = 0; 207 208 i2c_rd(sd, reg, (u8 __force *)&val, n); 209 210 return le32_to_cpu(val); 211 } 212 213 static noinline void i2c_wrreg(struct v4l2_subdev *sd, u16 reg, u32 val, u32 n) 214 { 215 __le32 raw = cpu_to_le32(val); 216 217 i2c_wr(sd, reg, (u8 __force *)&raw, n); 218 } 219 220 static u8 i2c_rd8(struct v4l2_subdev *sd, u16 reg) 221 { 222 return i2c_rdreg(sd, reg, 1); 223 } 224 225 static void i2c_wr8(struct v4l2_subdev *sd, u16 reg, u8 val) 226 { 227 i2c_wrreg(sd, reg, val, 1); 228 } 229 230 static void i2c_wr8_and_or(struct v4l2_subdev *sd, u16 reg, 231 u8 mask, u8 val) 232 { 233 i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 1) & mask) | val, 1); 234 } 235 236 static u16 i2c_rd16(struct v4l2_subdev *sd, u16 reg) 237 { 238 return i2c_rdreg(sd, reg, 2); 239 } 240 241 static void i2c_wr16(struct v4l2_subdev *sd, u16 reg, u16 val) 242 { 243 i2c_wrreg(sd, reg, val, 2); 244 } 245 246 static void i2c_wr16_and_or(struct v4l2_subdev *sd, u16 reg, u16 mask, u16 val) 247 { 248 i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 2) & mask) | val, 2); 249 } 250 251 static u32 i2c_rd32(struct v4l2_subdev *sd, u16 reg) 252 { 253 return i2c_rdreg(sd, reg, 4); 254 } 255 256 static void i2c_wr32(struct v4l2_subdev *sd, u16 reg, u32 val) 257 { 258 i2c_wrreg(sd, reg, val, 4); 259 } 260 261 /* --------------- STATUS --------------- */ 262 263 static inline bool is_hdmi(struct v4l2_subdev *sd) 264 { 265 return i2c_rd8(sd, SYS_STATUS) & MASK_S_HDMI; 266 } 267 268 static inline bool tx_5v_power_present(struct v4l2_subdev *sd) 269 { 270 return i2c_rd8(sd, SYS_STATUS) & MASK_S_DDC5V; 271 } 272 273 static inline bool no_signal(struct v4l2_subdev *sd) 274 { 275 return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_TMDS); 276 } 277 278 static inline bool no_sync(struct v4l2_subdev *sd) 279 { 280 return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_SYNC); 281 } 282 283 static inline bool audio_present(struct v4l2_subdev *sd) 284 { 285 return i2c_rd8(sd, AU_STATUS0) & MASK_S_A_SAMPLE; 286 } 287 288 static int get_audio_sampling_rate(struct v4l2_subdev *sd) 289 { 290 static const int code_to_rate[] = { 291 44100, 0, 48000, 32000, 22050, 384000, 24000, 352800, 292 88200, 768000, 96000, 705600, 176400, 0, 192000, 0 293 }; 294 295 /* Register FS_SET is not cleared when the cable is disconnected */ 296 if (no_signal(sd)) 297 return 0; 298 299 return code_to_rate[i2c_rd8(sd, FS_SET) & MASK_FS]; 300 } 301 302 /* --------------- TIMINGS --------------- */ 303 304 static inline unsigned fps(const struct v4l2_bt_timings *t) 305 { 306 if (!V4L2_DV_BT_FRAME_HEIGHT(t) || !V4L2_DV_BT_FRAME_WIDTH(t)) 307 return 0; 308 309 return DIV_ROUND_CLOSEST((unsigned)t->pixelclock, 310 V4L2_DV_BT_FRAME_HEIGHT(t) * V4L2_DV_BT_FRAME_WIDTH(t)); 311 } 312 313 static int tc358743_get_detected_timings(struct v4l2_subdev *sd, 314 struct v4l2_dv_timings *timings) 315 { 316 struct v4l2_bt_timings *bt = &timings->bt; 317 unsigned width, height, frame_width, frame_height, frame_interval, fps; 318 319 memset(timings, 0, sizeof(struct v4l2_dv_timings)); 320 321 if (no_signal(sd)) { 322 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); 323 return -ENOLINK; 324 } 325 if (no_sync(sd)) { 326 v4l2_dbg(1, debug, sd, "%s: no sync on signal\n", __func__); 327 return -ENOLCK; 328 } 329 330 timings->type = V4L2_DV_BT_656_1120; 331 bt->interlaced = i2c_rd8(sd, VI_STATUS1) & MASK_S_V_INTERLACE ? 332 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; 333 334 width = ((i2c_rd8(sd, DE_WIDTH_H_HI) & 0x1f) << 8) + 335 i2c_rd8(sd, DE_WIDTH_H_LO); 336 height = ((i2c_rd8(sd, DE_WIDTH_V_HI) & 0x1f) << 8) + 337 i2c_rd8(sd, DE_WIDTH_V_LO); 338 frame_width = ((i2c_rd8(sd, H_SIZE_HI) & 0x1f) << 8) + 339 i2c_rd8(sd, H_SIZE_LO); 340 frame_height = (((i2c_rd8(sd, V_SIZE_HI) & 0x3f) << 8) + 341 i2c_rd8(sd, V_SIZE_LO)) / 2; 342 /* frame interval in milliseconds * 10 343 * Require SYS_FREQ0 and SYS_FREQ1 are precisely set */ 344 frame_interval = ((i2c_rd8(sd, FV_CNT_HI) & 0x3) << 8) + 345 i2c_rd8(sd, FV_CNT_LO); 346 fps = (frame_interval > 0) ? 347 DIV_ROUND_CLOSEST(10000, frame_interval) : 0; 348 349 bt->width = width; 350 bt->height = height; 351 bt->vsync = frame_height - height; 352 bt->hsync = frame_width - width; 353 bt->pixelclock = frame_width * frame_height * fps; 354 if (bt->interlaced == V4L2_DV_INTERLACED) { 355 bt->height *= 2; 356 bt->il_vsync = bt->vsync + 1; 357 bt->pixelclock /= 2; 358 } 359 360 return 0; 361 } 362 363 /* --------------- HOTPLUG / HDCP / EDID --------------- */ 364 365 static void tc358743_delayed_work_enable_hotplug(struct work_struct *work) 366 { 367 struct delayed_work *dwork = to_delayed_work(work); 368 struct tc358743_state *state = container_of(dwork, 369 struct tc358743_state, delayed_work_enable_hotplug); 370 struct v4l2_subdev *sd = &state->sd; 371 372 v4l2_dbg(2, debug, sd, "%s:\n", __func__); 373 374 i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, MASK_HPD_OUT0); 375 } 376 377 static void tc358743_set_hdmi_hdcp(struct v4l2_subdev *sd, bool enable) 378 { 379 v4l2_dbg(2, debug, sd, "%s: %s\n", __func__, enable ? 380 "enable" : "disable"); 381 382 if (enable) { 383 i2c_wr8_and_or(sd, HDCP_REG3, ~KEY_RD_CMD, KEY_RD_CMD); 384 385 i2c_wr8_and_or(sd, HDCP_MODE, ~MASK_MANUAL_AUTHENTICATION, 0); 386 387 i2c_wr8_and_or(sd, HDCP_REG1, 0xff, 388 MASK_AUTH_UNAUTH_SEL_16_FRAMES | 389 MASK_AUTH_UNAUTH_AUTO); 390 391 i2c_wr8_and_or(sd, HDCP_REG2, ~MASK_AUTO_P3_RESET, 392 SET_AUTO_P3_RESET_FRAMES(0x0f)); 393 } else { 394 i2c_wr8_and_or(sd, HDCP_MODE, ~MASK_MANUAL_AUTHENTICATION, 395 MASK_MANUAL_AUTHENTICATION); 396 } 397 } 398 399 static void tc358743_disable_edid(struct v4l2_subdev *sd) 400 { 401 struct tc358743_state *state = to_state(sd); 402 403 v4l2_dbg(2, debug, sd, "%s:\n", __func__); 404 405 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); 406 407 /* DDC access to EDID is also disabled when hotplug is disabled. See 408 * register DDC_CTL */ 409 i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, 0x0); 410 } 411 412 static void tc358743_enable_edid(struct v4l2_subdev *sd) 413 { 414 struct tc358743_state *state = to_state(sd); 415 416 if (state->edid_blocks_written == 0) { 417 v4l2_dbg(2, debug, sd, "%s: no EDID -> no hotplug\n", __func__); 418 tc358743_s_ctrl_detect_tx_5v(sd); 419 return; 420 } 421 422 v4l2_dbg(2, debug, sd, "%s:\n", __func__); 423 424 /* Enable hotplug after 100 ms. DDC access to EDID is also enabled when 425 * hotplug is enabled. See register DDC_CTL */ 426 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 10); 427 428 tc358743_enable_interrupts(sd, true); 429 tc358743_s_ctrl_detect_tx_5v(sd); 430 } 431 432 static void tc358743_erase_bksv(struct v4l2_subdev *sd) 433 { 434 int i; 435 436 for (i = 0; i < 5; i++) 437 i2c_wr8(sd, BKSV + i, 0); 438 } 439 440 /* --------------- AVI infoframe --------------- */ 441 442 static void print_avi_infoframe(struct v4l2_subdev *sd) 443 { 444 struct i2c_client *client = v4l2_get_subdevdata(sd); 445 struct device *dev = &client->dev; 446 union hdmi_infoframe frame; 447 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)]; 448 449 if (!is_hdmi(sd)) { 450 v4l2_info(sd, "DVI-D signal - AVI infoframe not supported\n"); 451 return; 452 } 453 454 i2c_rd(sd, PK_AVI_0HEAD, buffer, HDMI_INFOFRAME_SIZE(AVI)); 455 456 if (hdmi_infoframe_unpack(&frame, buffer) < 0) { 457 v4l2_err(sd, "%s: unpack of AVI infoframe failed\n", __func__); 458 return; 459 } 460 461 hdmi_infoframe_log(KERN_INFO, dev, &frame); 462 } 463 464 /* --------------- CTRLS --------------- */ 465 466 static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd) 467 { 468 struct tc358743_state *state = to_state(sd); 469 470 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, 471 tx_5v_power_present(sd)); 472 } 473 474 static int tc358743_s_ctrl_audio_sampling_rate(struct v4l2_subdev *sd) 475 { 476 struct tc358743_state *state = to_state(sd); 477 478 return v4l2_ctrl_s_ctrl(state->audio_sampling_rate_ctrl, 479 get_audio_sampling_rate(sd)); 480 } 481 482 static int tc358743_s_ctrl_audio_present(struct v4l2_subdev *sd) 483 { 484 struct tc358743_state *state = to_state(sd); 485 486 return v4l2_ctrl_s_ctrl(state->audio_present_ctrl, 487 audio_present(sd)); 488 } 489 490 static int tc358743_update_controls(struct v4l2_subdev *sd) 491 { 492 int ret = 0; 493 494 ret |= tc358743_s_ctrl_detect_tx_5v(sd); 495 ret |= tc358743_s_ctrl_audio_sampling_rate(sd); 496 ret |= tc358743_s_ctrl_audio_present(sd); 497 498 return ret; 499 } 500 501 /* --------------- INIT --------------- */ 502 503 static void tc358743_reset_phy(struct v4l2_subdev *sd) 504 { 505 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 506 507 i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, 0); 508 i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, MASK_RESET_CTRL); 509 } 510 511 static void tc358743_reset(struct v4l2_subdev *sd, uint16_t mask) 512 { 513 u16 sysctl = i2c_rd16(sd, SYSCTL); 514 515 i2c_wr16(sd, SYSCTL, sysctl | mask); 516 i2c_wr16(sd, SYSCTL, sysctl & ~mask); 517 } 518 519 static inline void tc358743_sleep_mode(struct v4l2_subdev *sd, bool enable) 520 { 521 i2c_wr16_and_or(sd, SYSCTL, ~MASK_SLEEP, 522 enable ? MASK_SLEEP : 0); 523 } 524 525 static inline void enable_stream(struct v4l2_subdev *sd, bool enable) 526 { 527 struct tc358743_state *state = to_state(sd); 528 529 v4l2_dbg(3, debug, sd, "%s: %sable\n", 530 __func__, enable ? "en" : "dis"); 531 532 if (enable) { 533 /* It is critical for CSI receiver to see lane transition 534 * LP11->HS. Set to non-continuous mode to enable clock lane 535 * LP11 state. */ 536 i2c_wr32(sd, TXOPTIONCNTRL, 0); 537 /* Set to continuous mode to trigger LP11->HS transition */ 538 i2c_wr32(sd, TXOPTIONCNTRL, MASK_CONTCLKMODE); 539 /* Unmute video */ 540 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE); 541 } else { 542 /* Mute video so that all data lanes go to LSP11 state. 543 * No data is output to CSI Tx block. */ 544 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE | MASK_VI_MUTE); 545 } 546 547 mutex_lock(&state->confctl_mutex); 548 i2c_wr16_and_or(sd, CONFCTL, ~(MASK_VBUFEN | MASK_ABUFEN), 549 enable ? (MASK_VBUFEN | MASK_ABUFEN) : 0x0); 550 mutex_unlock(&state->confctl_mutex); 551 } 552 553 static void tc358743_set_pll(struct v4l2_subdev *sd) 554 { 555 struct tc358743_state *state = to_state(sd); 556 struct tc358743_platform_data *pdata = &state->pdata; 557 u16 pllctl0 = i2c_rd16(sd, PLLCTL0); 558 u16 pllctl1 = i2c_rd16(sd, PLLCTL1); 559 u16 pllctl0_new = SET_PLL_PRD(pdata->pll_prd) | 560 SET_PLL_FBD(pdata->pll_fbd); 561 u32 hsck = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd; 562 563 v4l2_dbg(2, debug, sd, "%s:\n", __func__); 564 565 /* Only rewrite when needed (new value or disabled), since rewriting 566 * triggers another format change event. */ 567 if ((pllctl0 != pllctl0_new) || ((pllctl1 & MASK_PLL_EN) == 0)) { 568 u16 pll_frs; 569 570 if (hsck > 500000000) 571 pll_frs = 0x0; 572 else if (hsck > 250000000) 573 pll_frs = 0x1; 574 else if (hsck > 125000000) 575 pll_frs = 0x2; 576 else 577 pll_frs = 0x3; 578 579 v4l2_dbg(1, debug, sd, "%s: updating PLL clock\n", __func__); 580 tc358743_sleep_mode(sd, true); 581 i2c_wr16(sd, PLLCTL0, pllctl0_new); 582 i2c_wr16_and_or(sd, PLLCTL1, 583 ~(MASK_PLL_FRS | MASK_RESETB | MASK_PLL_EN), 584 (SET_PLL_FRS(pll_frs) | MASK_RESETB | 585 MASK_PLL_EN)); 586 udelay(10); /* REF_02, Sheet "Source HDMI" */ 587 i2c_wr16_and_or(sd, PLLCTL1, ~MASK_CKEN, MASK_CKEN); 588 tc358743_sleep_mode(sd, false); 589 } 590 } 591 592 static void tc358743_set_ref_clk(struct v4l2_subdev *sd) 593 { 594 struct tc358743_state *state = to_state(sd); 595 struct tc358743_platform_data *pdata = &state->pdata; 596 u32 sys_freq; 597 u32 lockdet_ref; 598 u16 fh_min; 599 u16 fh_max; 600 601 BUG_ON(!(pdata->refclk_hz == 26000000 || 602 pdata->refclk_hz == 27000000 || 603 pdata->refclk_hz == 42000000)); 604 605 sys_freq = pdata->refclk_hz / 10000; 606 i2c_wr8(sd, SYS_FREQ0, sys_freq & 0x00ff); 607 i2c_wr8(sd, SYS_FREQ1, (sys_freq & 0xff00) >> 8); 608 609 i2c_wr8_and_or(sd, PHY_CTL0, ~MASK_PHY_SYSCLK_IND, 610 (pdata->refclk_hz == 42000000) ? 611 MASK_PHY_SYSCLK_IND : 0x0); 612 613 fh_min = pdata->refclk_hz / 100000; 614 i2c_wr8(sd, FH_MIN0, fh_min & 0x00ff); 615 i2c_wr8(sd, FH_MIN1, (fh_min & 0xff00) >> 8); 616 617 fh_max = (fh_min * 66) / 10; 618 i2c_wr8(sd, FH_MAX0, fh_max & 0x00ff); 619 i2c_wr8(sd, FH_MAX1, (fh_max & 0xff00) >> 8); 620 621 lockdet_ref = pdata->refclk_hz / 100; 622 i2c_wr8(sd, LOCKDET_REF0, lockdet_ref & 0x0000ff); 623 i2c_wr8(sd, LOCKDET_REF1, (lockdet_ref & 0x00ff00) >> 8); 624 i2c_wr8(sd, LOCKDET_REF2, (lockdet_ref & 0x0f0000) >> 16); 625 626 i2c_wr8_and_or(sd, NCO_F0_MOD, ~MASK_NCO_F0_MOD, 627 (pdata->refclk_hz == 27000000) ? 628 MASK_NCO_F0_MOD_27MHZ : 0x0); 629 } 630 631 static void tc358743_set_csi_color_space(struct v4l2_subdev *sd) 632 { 633 struct tc358743_state *state = to_state(sd); 634 635 switch (state->mbus_fmt_code) { 636 case MEDIA_BUS_FMT_UYVY8_1X16: 637 v4l2_dbg(2, debug, sd, "%s: YCbCr 422 16-bit\n", __func__); 638 i2c_wr8_and_or(sd, VOUT_SET2, 639 ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff, 640 MASK_SEL422 | MASK_VOUT_422FIL_100); 641 i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff, 642 MASK_VOUT_COLOR_601_YCBCR_LIMITED); 643 mutex_lock(&state->confctl_mutex); 644 i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT, 645 MASK_YCBCRFMT_422_8_BIT); 646 mutex_unlock(&state->confctl_mutex); 647 break; 648 case MEDIA_BUS_FMT_RGB888_1X24: 649 v4l2_dbg(2, debug, sd, "%s: RGB 888 24-bit\n", __func__); 650 i2c_wr8_and_or(sd, VOUT_SET2, 651 ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff, 652 0x00); 653 i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff, 654 MASK_VOUT_COLOR_RGB_FULL); 655 mutex_lock(&state->confctl_mutex); 656 i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT, 0); 657 mutex_unlock(&state->confctl_mutex); 658 break; 659 default: 660 v4l2_dbg(2, debug, sd, "%s: Unsupported format code 0x%x\n", 661 __func__, state->mbus_fmt_code); 662 } 663 } 664 665 static unsigned tc358743_num_csi_lanes_needed(struct v4l2_subdev *sd) 666 { 667 struct tc358743_state *state = to_state(sd); 668 struct v4l2_bt_timings *bt = &state->timings.bt; 669 struct tc358743_platform_data *pdata = &state->pdata; 670 u32 bits_pr_pixel = 671 (state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16) ? 16 : 24; 672 u32 bps = bt->width * bt->height * fps(bt) * bits_pr_pixel; 673 u32 bps_pr_lane = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd; 674 675 return DIV_ROUND_UP(bps, bps_pr_lane); 676 } 677 678 static void tc358743_set_csi(struct v4l2_subdev *sd) 679 { 680 struct tc358743_state *state = to_state(sd); 681 struct tc358743_platform_data *pdata = &state->pdata; 682 unsigned lanes = tc358743_num_csi_lanes_needed(sd); 683 684 v4l2_dbg(3, debug, sd, "%s:\n", __func__); 685 686 state->csi_lanes_in_use = lanes; 687 688 tc358743_reset(sd, MASK_CTXRST); 689 690 if (lanes < 1) 691 i2c_wr32(sd, CLW_CNTRL, MASK_CLW_LANEDISABLE); 692 if (lanes < 1) 693 i2c_wr32(sd, D0W_CNTRL, MASK_D0W_LANEDISABLE); 694 if (lanes < 2) 695 i2c_wr32(sd, D1W_CNTRL, MASK_D1W_LANEDISABLE); 696 if (lanes < 3) 697 i2c_wr32(sd, D2W_CNTRL, MASK_D2W_LANEDISABLE); 698 if (lanes < 4) 699 i2c_wr32(sd, D3W_CNTRL, MASK_D3W_LANEDISABLE); 700 701 i2c_wr32(sd, LINEINITCNT, pdata->lineinitcnt); 702 i2c_wr32(sd, LPTXTIMECNT, pdata->lptxtimecnt); 703 i2c_wr32(sd, TCLK_HEADERCNT, pdata->tclk_headercnt); 704 i2c_wr32(sd, TCLK_TRAILCNT, pdata->tclk_trailcnt); 705 i2c_wr32(sd, THS_HEADERCNT, pdata->ths_headercnt); 706 i2c_wr32(sd, TWAKEUP, pdata->twakeup); 707 i2c_wr32(sd, TCLK_POSTCNT, pdata->tclk_postcnt); 708 i2c_wr32(sd, THS_TRAILCNT, pdata->ths_trailcnt); 709 i2c_wr32(sd, HSTXVREGCNT, pdata->hstxvregcnt); 710 711 i2c_wr32(sd, HSTXVREGEN, 712 ((lanes > 0) ? MASK_CLM_HSTXVREGEN : 0x0) | 713 ((lanes > 0) ? MASK_D0M_HSTXVREGEN : 0x0) | 714 ((lanes > 1) ? MASK_D1M_HSTXVREGEN : 0x0) | 715 ((lanes > 2) ? MASK_D2M_HSTXVREGEN : 0x0) | 716 ((lanes > 3) ? MASK_D3M_HSTXVREGEN : 0x0)); 717 718 i2c_wr32(sd, TXOPTIONCNTRL, (state->bus.flags & 719 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) ? MASK_CONTCLKMODE : 0); 720 i2c_wr32(sd, STARTCNTRL, MASK_START); 721 i2c_wr32(sd, CSI_START, MASK_STRT); 722 723 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET | 724 MASK_ADDRESS_CSI_CONTROL | 725 MASK_CSI_MODE | 726 MASK_TXHSMD | 727 ((lanes == 4) ? MASK_NOL_4 : 728 (lanes == 3) ? MASK_NOL_3 : 729 (lanes == 2) ? MASK_NOL_2 : MASK_NOL_1)); 730 731 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET | 732 MASK_ADDRESS_CSI_ERR_INTENA | MASK_TXBRK | MASK_QUNK | 733 MASK_WCER | MASK_INER); 734 735 i2c_wr32(sd, CSI_CONFW, MASK_MODE_CLEAR | 736 MASK_ADDRESS_CSI_ERR_HALT | MASK_TXBRK | MASK_QUNK); 737 738 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET | 739 MASK_ADDRESS_CSI_INT_ENA | MASK_INTER); 740 } 741 742 static void tc358743_set_hdmi_phy(struct v4l2_subdev *sd) 743 { 744 struct tc358743_state *state = to_state(sd); 745 struct tc358743_platform_data *pdata = &state->pdata; 746 747 /* Default settings from REF_02, sheet "Source HDMI" 748 * and custom settings as platform data */ 749 i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, 0x0); 750 i2c_wr8(sd, PHY_CTL1, SET_PHY_AUTO_RST1_US(1600) | 751 SET_FREQ_RANGE_MODE_CYCLES(1)); 752 i2c_wr8_and_or(sd, PHY_CTL2, ~MASK_PHY_AUTO_RSTn, 753 (pdata->hdmi_phy_auto_reset_tmds_detected ? 754 MASK_PHY_AUTO_RST2 : 0) | 755 (pdata->hdmi_phy_auto_reset_tmds_in_range ? 756 MASK_PHY_AUTO_RST3 : 0) | 757 (pdata->hdmi_phy_auto_reset_tmds_valid ? 758 MASK_PHY_AUTO_RST4 : 0)); 759 i2c_wr8(sd, PHY_BIAS, 0x40); 760 i2c_wr8(sd, PHY_CSQ, SET_CSQ_CNT_LEVEL(0x0a)); 761 i2c_wr8(sd, AVM_CTL, 45); 762 i2c_wr8_and_or(sd, HDMI_DET, ~MASK_HDMI_DET_V, 763 pdata->hdmi_detection_delay << 4); 764 i2c_wr8_and_or(sd, HV_RST, ~(MASK_H_PI_RST | MASK_V_PI_RST), 765 (pdata->hdmi_phy_auto_reset_hsync_out_of_range ? 766 MASK_H_PI_RST : 0) | 767 (pdata->hdmi_phy_auto_reset_vsync_out_of_range ? 768 MASK_V_PI_RST : 0)); 769 i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, MASK_ENABLE_PHY); 770 } 771 772 static void tc358743_set_hdmi_audio(struct v4l2_subdev *sd) 773 { 774 struct tc358743_state *state = to_state(sd); 775 776 /* Default settings from REF_02, sheet "Source HDMI" */ 777 i2c_wr8(sd, FORCE_MUTE, 0x00); 778 i2c_wr8(sd, AUTO_CMD0, MASK_AUTO_MUTE7 | MASK_AUTO_MUTE6 | 779 MASK_AUTO_MUTE5 | MASK_AUTO_MUTE4 | 780 MASK_AUTO_MUTE1 | MASK_AUTO_MUTE0); 781 i2c_wr8(sd, AUTO_CMD1, MASK_AUTO_MUTE9); 782 i2c_wr8(sd, AUTO_CMD2, MASK_AUTO_PLAY3 | MASK_AUTO_PLAY2); 783 i2c_wr8(sd, BUFINIT_START, SET_BUFINIT_START_MS(500)); 784 i2c_wr8(sd, FS_MUTE, 0x00); 785 i2c_wr8(sd, FS_IMODE, MASK_NLPCM_SMODE | MASK_FS_SMODE); 786 i2c_wr8(sd, ACR_MODE, MASK_CTS_MODE); 787 i2c_wr8(sd, ACR_MDF0, MASK_ACR_L2MDF_1976_PPM | MASK_ACR_L1MDF_976_PPM); 788 i2c_wr8(sd, ACR_MDF1, MASK_ACR_L3MDF_3906_PPM); 789 i2c_wr8(sd, SDO_MODE1, MASK_SDO_FMT_I2S); 790 i2c_wr8(sd, DIV_MODE, SET_DIV_DLY_MS(100)); 791 792 mutex_lock(&state->confctl_mutex); 793 i2c_wr16_and_or(sd, CONFCTL, 0xffff, MASK_AUDCHNUM_2 | 794 MASK_AUDOUTSEL_I2S | MASK_AUTOINDEX); 795 mutex_unlock(&state->confctl_mutex); 796 } 797 798 static void tc358743_set_hdmi_info_frame_mode(struct v4l2_subdev *sd) 799 { 800 /* Default settings from REF_02, sheet "Source HDMI" */ 801 i2c_wr8(sd, PK_INT_MODE, MASK_ISRC2_INT_MODE | MASK_ISRC_INT_MODE | 802 MASK_ACP_INT_MODE | MASK_VS_INT_MODE | 803 MASK_SPD_INT_MODE | MASK_MS_INT_MODE | 804 MASK_AUD_INT_MODE | MASK_AVI_INT_MODE); 805 i2c_wr8(sd, NO_PKT_LIMIT, 0x2c); 806 i2c_wr8(sd, NO_PKT_CLR, 0x53); 807 i2c_wr8(sd, ERR_PK_LIMIT, 0x01); 808 i2c_wr8(sd, NO_PKT_LIMIT2, 0x30); 809 i2c_wr8(sd, NO_GDB_LIMIT, 0x10); 810 } 811 812 static void tc358743_initial_setup(struct v4l2_subdev *sd) 813 { 814 struct tc358743_state *state = to_state(sd); 815 struct tc358743_platform_data *pdata = &state->pdata; 816 817 /* CEC and IR are not supported by this driver */ 818 i2c_wr16_and_or(sd, SYSCTL, ~(MASK_CECRST | MASK_IRRST), 819 (MASK_CECRST | MASK_IRRST)); 820 821 tc358743_reset(sd, MASK_CTXRST | MASK_HDMIRST); 822 tc358743_sleep_mode(sd, false); 823 824 i2c_wr16(sd, FIFOCTL, pdata->fifo_level); 825 826 tc358743_set_ref_clk(sd); 827 828 i2c_wr8_and_or(sd, DDC_CTL, ~MASK_DDC5V_MODE, 829 pdata->ddc5v_delay & MASK_DDC5V_MODE); 830 i2c_wr8_and_or(sd, EDID_MODE, ~MASK_EDID_MODE, MASK_EDID_MODE_E_DDC); 831 832 tc358743_set_hdmi_phy(sd); 833 tc358743_set_hdmi_hdcp(sd, pdata->enable_hdcp); 834 tc358743_set_hdmi_audio(sd); 835 tc358743_set_hdmi_info_frame_mode(sd); 836 837 /* All CE and IT formats are detected as RGB full range in DVI mode */ 838 i2c_wr8_and_or(sd, VI_MODE, ~MASK_RGB_DVI, 0); 839 840 i2c_wr8_and_or(sd, VOUT_SET2, ~MASK_VOUTCOLORMODE, 841 MASK_VOUTCOLORMODE_AUTO); 842 i2c_wr8(sd, VOUT_SET3, MASK_VOUT_EXTCNT); 843 } 844 845 /* --------------- IRQ --------------- */ 846 847 static void tc358743_format_change(struct v4l2_subdev *sd) 848 { 849 struct tc358743_state *state = to_state(sd); 850 struct v4l2_dv_timings timings; 851 const struct v4l2_event tc358743_ev_fmt = { 852 .type = V4L2_EVENT_SOURCE_CHANGE, 853 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, 854 }; 855 856 if (tc358743_get_detected_timings(sd, &timings)) { 857 enable_stream(sd, false); 858 859 v4l2_dbg(1, debug, sd, "%s: No signal\n", 860 __func__); 861 } else { 862 if (!v4l2_match_dv_timings(&state->timings, &timings, 0, false)) 863 enable_stream(sd, false); 864 865 if (debug) 866 v4l2_print_dv_timings(sd->name, 867 "tc358743_format_change: New format: ", 868 &timings, false); 869 } 870 871 if (sd->devnode) 872 v4l2_subdev_notify_event(sd, &tc358743_ev_fmt); 873 } 874 875 static void tc358743_init_interrupts(struct v4l2_subdev *sd) 876 { 877 u16 i; 878 879 /* clear interrupt status registers */ 880 for (i = SYS_INT; i <= KEY_INT; i++) 881 i2c_wr8(sd, i, 0xff); 882 883 i2c_wr16(sd, INTSTATUS, 0xffff); 884 } 885 886 static void tc358743_enable_interrupts(struct v4l2_subdev *sd, 887 bool cable_connected) 888 { 889 v4l2_dbg(2, debug, sd, "%s: cable connected = %d\n", __func__, 890 cable_connected); 891 892 if (cable_connected) { 893 i2c_wr8(sd, SYS_INTM, ~(MASK_M_DDC | MASK_M_DVI_DET | 894 MASK_M_HDMI_DET) & 0xff); 895 i2c_wr8(sd, CLK_INTM, ~MASK_M_IN_DE_CHG); 896 i2c_wr8(sd, CBIT_INTM, ~(MASK_M_CBIT_FS | MASK_M_AF_LOCK | 897 MASK_M_AF_UNLOCK) & 0xff); 898 i2c_wr8(sd, AUDIO_INTM, ~MASK_M_BUFINIT_END); 899 i2c_wr8(sd, MISC_INTM, ~MASK_M_SYNC_CHG); 900 } else { 901 i2c_wr8(sd, SYS_INTM, ~MASK_M_DDC & 0xff); 902 i2c_wr8(sd, CLK_INTM, 0xff); 903 i2c_wr8(sd, CBIT_INTM, 0xff); 904 i2c_wr8(sd, AUDIO_INTM, 0xff); 905 i2c_wr8(sd, MISC_INTM, 0xff); 906 } 907 } 908 909 static void tc358743_hdmi_audio_int_handler(struct v4l2_subdev *sd, 910 bool *handled) 911 { 912 u8 audio_int_mask = i2c_rd8(sd, AUDIO_INTM); 913 u8 audio_int = i2c_rd8(sd, AUDIO_INT) & ~audio_int_mask; 914 915 i2c_wr8(sd, AUDIO_INT, audio_int); 916 917 v4l2_dbg(3, debug, sd, "%s: AUDIO_INT = 0x%02x\n", __func__, audio_int); 918 919 tc358743_s_ctrl_audio_sampling_rate(sd); 920 tc358743_s_ctrl_audio_present(sd); 921 } 922 923 static void tc358743_csi_err_int_handler(struct v4l2_subdev *sd, bool *handled) 924 { 925 v4l2_err(sd, "%s: CSI_ERR = 0x%x\n", __func__, i2c_rd32(sd, CSI_ERR)); 926 927 i2c_wr32(sd, CSI_INT_CLR, MASK_ICRER); 928 } 929 930 static void tc358743_hdmi_misc_int_handler(struct v4l2_subdev *sd, 931 bool *handled) 932 { 933 u8 misc_int_mask = i2c_rd8(sd, MISC_INTM); 934 u8 misc_int = i2c_rd8(sd, MISC_INT) & ~misc_int_mask; 935 936 i2c_wr8(sd, MISC_INT, misc_int); 937 938 v4l2_dbg(3, debug, sd, "%s: MISC_INT = 0x%02x\n", __func__, misc_int); 939 940 if (misc_int & MASK_I_SYNC_CHG) { 941 /* Reset the HDMI PHY to try to trigger proper lock on the 942 * incoming video format. Erase BKSV to prevent that old keys 943 * are used when a new source is connected. */ 944 if (no_sync(sd) || no_signal(sd)) { 945 tc358743_reset_phy(sd); 946 tc358743_erase_bksv(sd); 947 } 948 949 tc358743_format_change(sd); 950 951 misc_int &= ~MASK_I_SYNC_CHG; 952 if (handled) 953 *handled = true; 954 } 955 956 if (misc_int) { 957 v4l2_err(sd, "%s: Unhandled MISC_INT interrupts: 0x%02x\n", 958 __func__, misc_int); 959 } 960 } 961 962 static void tc358743_hdmi_cbit_int_handler(struct v4l2_subdev *sd, 963 bool *handled) 964 { 965 u8 cbit_int_mask = i2c_rd8(sd, CBIT_INTM); 966 u8 cbit_int = i2c_rd8(sd, CBIT_INT) & ~cbit_int_mask; 967 968 i2c_wr8(sd, CBIT_INT, cbit_int); 969 970 v4l2_dbg(3, debug, sd, "%s: CBIT_INT = 0x%02x\n", __func__, cbit_int); 971 972 if (cbit_int & MASK_I_CBIT_FS) { 973 974 v4l2_dbg(1, debug, sd, "%s: Audio sample rate changed\n", 975 __func__); 976 tc358743_s_ctrl_audio_sampling_rate(sd); 977 978 cbit_int &= ~MASK_I_CBIT_FS; 979 if (handled) 980 *handled = true; 981 } 982 983 if (cbit_int & (MASK_I_AF_LOCK | MASK_I_AF_UNLOCK)) { 984 985 v4l2_dbg(1, debug, sd, "%s: Audio present changed\n", 986 __func__); 987 tc358743_s_ctrl_audio_present(sd); 988 989 cbit_int &= ~(MASK_I_AF_LOCK | MASK_I_AF_UNLOCK); 990 if (handled) 991 *handled = true; 992 } 993 994 if (cbit_int) { 995 v4l2_err(sd, "%s: Unhandled CBIT_INT interrupts: 0x%02x\n", 996 __func__, cbit_int); 997 } 998 } 999 1000 static void tc358743_hdmi_clk_int_handler(struct v4l2_subdev *sd, bool *handled) 1001 { 1002 u8 clk_int_mask = i2c_rd8(sd, CLK_INTM); 1003 u8 clk_int = i2c_rd8(sd, CLK_INT) & ~clk_int_mask; 1004 1005 /* Bit 7 and bit 6 are set even when they are masked */ 1006 i2c_wr8(sd, CLK_INT, clk_int | 0x80 | MASK_I_OUT_H_CHG); 1007 1008 v4l2_dbg(3, debug, sd, "%s: CLK_INT = 0x%02x\n", __func__, clk_int); 1009 1010 if (clk_int & (MASK_I_IN_DE_CHG)) { 1011 1012 v4l2_dbg(1, debug, sd, "%s: DE size or position has changed\n", 1013 __func__); 1014 1015 /* If the source switch to a new resolution with the same pixel 1016 * frequency as the existing (e.g. 1080p25 -> 720p50), the 1017 * I_SYNC_CHG interrupt is not always triggered, while the 1018 * I_IN_DE_CHG interrupt seems to work fine. Format change 1019 * notifications are only sent when the signal is stable to 1020 * reduce the number of notifications. */ 1021 if (!no_signal(sd) && !no_sync(sd)) 1022 tc358743_format_change(sd); 1023 1024 clk_int &= ~(MASK_I_IN_DE_CHG); 1025 if (handled) 1026 *handled = true; 1027 } 1028 1029 if (clk_int) { 1030 v4l2_err(sd, "%s: Unhandled CLK_INT interrupts: 0x%02x\n", 1031 __func__, clk_int); 1032 } 1033 } 1034 1035 static void tc358743_hdmi_sys_int_handler(struct v4l2_subdev *sd, bool *handled) 1036 { 1037 struct tc358743_state *state = to_state(sd); 1038 u8 sys_int_mask = i2c_rd8(sd, SYS_INTM); 1039 u8 sys_int = i2c_rd8(sd, SYS_INT) & ~sys_int_mask; 1040 1041 i2c_wr8(sd, SYS_INT, sys_int); 1042 1043 v4l2_dbg(3, debug, sd, "%s: SYS_INT = 0x%02x\n", __func__, sys_int); 1044 1045 if (sys_int & MASK_I_DDC) { 1046 bool tx_5v = tx_5v_power_present(sd); 1047 1048 v4l2_dbg(1, debug, sd, "%s: Tx 5V power present: %s\n", 1049 __func__, tx_5v ? "yes" : "no"); 1050 1051 if (tx_5v) { 1052 tc358743_enable_edid(sd); 1053 } else { 1054 tc358743_enable_interrupts(sd, false); 1055 tc358743_disable_edid(sd); 1056 memset(&state->timings, 0, sizeof(state->timings)); 1057 tc358743_erase_bksv(sd); 1058 tc358743_update_controls(sd); 1059 } 1060 1061 sys_int &= ~MASK_I_DDC; 1062 if (handled) 1063 *handled = true; 1064 } 1065 1066 if (sys_int & MASK_I_DVI) { 1067 v4l2_dbg(1, debug, sd, "%s: HDMI->DVI change detected\n", 1068 __func__); 1069 1070 /* Reset the HDMI PHY to try to trigger proper lock on the 1071 * incoming video format. Erase BKSV to prevent that old keys 1072 * are used when a new source is connected. */ 1073 if (no_sync(sd) || no_signal(sd)) { 1074 tc358743_reset_phy(sd); 1075 tc358743_erase_bksv(sd); 1076 } 1077 1078 sys_int &= ~MASK_I_DVI; 1079 if (handled) 1080 *handled = true; 1081 } 1082 1083 if (sys_int & MASK_I_HDMI) { 1084 v4l2_dbg(1, debug, sd, "%s: DVI->HDMI change detected\n", 1085 __func__); 1086 1087 /* Register is reset in DVI mode (REF_01, c. 6.6.41) */ 1088 i2c_wr8(sd, ANA_CTL, MASK_APPL_PCSX_NORMAL | MASK_ANALOG_ON); 1089 1090 sys_int &= ~MASK_I_HDMI; 1091 if (handled) 1092 *handled = true; 1093 } 1094 1095 if (sys_int) { 1096 v4l2_err(sd, "%s: Unhandled SYS_INT interrupts: 0x%02x\n", 1097 __func__, sys_int); 1098 } 1099 } 1100 1101 /* --------------- CORE OPS --------------- */ 1102 1103 static int tc358743_log_status(struct v4l2_subdev *sd) 1104 { 1105 struct tc358743_state *state = to_state(sd); 1106 struct v4l2_dv_timings timings; 1107 uint8_t hdmi_sys_status = i2c_rd8(sd, SYS_STATUS); 1108 uint16_t sysctl = i2c_rd16(sd, SYSCTL); 1109 u8 vi_status3 = i2c_rd8(sd, VI_STATUS3); 1110 const int deep_color_mode[4] = { 8, 10, 12, 16 }; 1111 static const char * const input_color_space[] = { 1112 "RGB", "YCbCr 601", "Adobe RGB", "YCbCr 709", "NA (4)", 1113 "xvYCC 601", "NA(6)", "xvYCC 709", "NA(8)", "sYCC601", 1114 "NA(10)", "NA(11)", "NA(12)", "Adobe YCC 601"}; 1115 1116 v4l2_info(sd, "-----Chip status-----\n"); 1117 v4l2_info(sd, "Chip ID: 0x%02x\n", 1118 (i2c_rd16(sd, CHIPID) & MASK_CHIPID) >> 8); 1119 v4l2_info(sd, "Chip revision: 0x%02x\n", 1120 i2c_rd16(sd, CHIPID) & MASK_REVID); 1121 v4l2_info(sd, "Reset: IR: %d, CEC: %d, CSI TX: %d, HDMI: %d\n", 1122 !!(sysctl & MASK_IRRST), 1123 !!(sysctl & MASK_CECRST), 1124 !!(sysctl & MASK_CTXRST), 1125 !!(sysctl & MASK_HDMIRST)); 1126 v4l2_info(sd, "Sleep mode: %s\n", sysctl & MASK_SLEEP ? "on" : "off"); 1127 v4l2_info(sd, "Cable detected (+5V power): %s\n", 1128 hdmi_sys_status & MASK_S_DDC5V ? "yes" : "no"); 1129 v4l2_info(sd, "DDC lines enabled: %s\n", 1130 (i2c_rd8(sd, EDID_MODE) & MASK_EDID_MODE_E_DDC) ? 1131 "yes" : "no"); 1132 v4l2_info(sd, "Hotplug enabled: %s\n", 1133 (i2c_rd8(sd, HPD_CTL) & MASK_HPD_OUT0) ? 1134 "yes" : "no"); 1135 v4l2_info(sd, "CEC enabled: %s\n", 1136 (i2c_rd16(sd, CECEN) & MASK_CECEN) ? "yes" : "no"); 1137 v4l2_info(sd, "-----Signal status-----\n"); 1138 v4l2_info(sd, "TMDS signal detected: %s\n", 1139 hdmi_sys_status & MASK_S_TMDS ? "yes" : "no"); 1140 v4l2_info(sd, "Stable sync signal: %s\n", 1141 hdmi_sys_status & MASK_S_SYNC ? "yes" : "no"); 1142 v4l2_info(sd, "PHY PLL locked: %s\n", 1143 hdmi_sys_status & MASK_S_PHY_PLL ? "yes" : "no"); 1144 v4l2_info(sd, "PHY DE detected: %s\n", 1145 hdmi_sys_status & MASK_S_PHY_SCDT ? "yes" : "no"); 1146 1147 if (tc358743_get_detected_timings(sd, &timings)) { 1148 v4l2_info(sd, "No video detected\n"); 1149 } else { 1150 v4l2_print_dv_timings(sd->name, "Detected format: ", &timings, 1151 true); 1152 } 1153 v4l2_print_dv_timings(sd->name, "Configured format: ", &state->timings, 1154 true); 1155 1156 v4l2_info(sd, "-----CSI-TX status-----\n"); 1157 v4l2_info(sd, "Lanes needed: %d\n", 1158 tc358743_num_csi_lanes_needed(sd)); 1159 v4l2_info(sd, "Lanes in use: %d\n", 1160 state->csi_lanes_in_use); 1161 v4l2_info(sd, "Waiting for particular sync signal: %s\n", 1162 (i2c_rd16(sd, CSI_STATUS) & MASK_S_WSYNC) ? 1163 "yes" : "no"); 1164 v4l2_info(sd, "Transmit mode: %s\n", 1165 (i2c_rd16(sd, CSI_STATUS) & MASK_S_TXACT) ? 1166 "yes" : "no"); 1167 v4l2_info(sd, "Receive mode: %s\n", 1168 (i2c_rd16(sd, CSI_STATUS) & MASK_S_RXACT) ? 1169 "yes" : "no"); 1170 v4l2_info(sd, "Stopped: %s\n", 1171 (i2c_rd16(sd, CSI_STATUS) & MASK_S_HLT) ? 1172 "yes" : "no"); 1173 v4l2_info(sd, "Color space: %s\n", 1174 state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16 ? 1175 "YCbCr 422 16-bit" : 1176 state->mbus_fmt_code == MEDIA_BUS_FMT_RGB888_1X24 ? 1177 "RGB 888 24-bit" : "Unsupported"); 1178 1179 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); 1180 v4l2_info(sd, "HDCP encrypted content: %s\n", 1181 hdmi_sys_status & MASK_S_HDCP ? "yes" : "no"); 1182 v4l2_info(sd, "Input color space: %s %s range\n", 1183 input_color_space[(vi_status3 & MASK_S_V_COLOR) >> 1], 1184 (vi_status3 & MASK_LIMITED) ? "limited" : "full"); 1185 if (!is_hdmi(sd)) 1186 return 0; 1187 v4l2_info(sd, "AV Mute: %s\n", hdmi_sys_status & MASK_S_AVMUTE ? "on" : 1188 "off"); 1189 v4l2_info(sd, "Deep color mode: %d-bits per channel\n", 1190 deep_color_mode[(i2c_rd8(sd, VI_STATUS1) & 1191 MASK_S_DEEPCOLOR) >> 2]); 1192 print_avi_infoframe(sd); 1193 1194 return 0; 1195 } 1196 1197 #ifdef CONFIG_VIDEO_ADV_DEBUG 1198 static void tc358743_print_register_map(struct v4l2_subdev *sd) 1199 { 1200 v4l2_info(sd, "0x0000-0x00FF: Global Control Register\n"); 1201 v4l2_info(sd, "0x0100-0x01FF: CSI2-TX PHY Register\n"); 1202 v4l2_info(sd, "0x0200-0x03FF: CSI2-TX PPI Register\n"); 1203 v4l2_info(sd, "0x0400-0x05FF: Reserved\n"); 1204 v4l2_info(sd, "0x0600-0x06FF: CEC Register\n"); 1205 v4l2_info(sd, "0x0700-0x84FF: Reserved\n"); 1206 v4l2_info(sd, "0x8500-0x85FF: HDMIRX System Control Register\n"); 1207 v4l2_info(sd, "0x8600-0x86FF: HDMIRX Audio Control Register\n"); 1208 v4l2_info(sd, "0x8700-0x87FF: HDMIRX InfoFrame packet data Register\n"); 1209 v4l2_info(sd, "0x8800-0x88FF: HDMIRX HDCP Port Register\n"); 1210 v4l2_info(sd, "0x8900-0x89FF: HDMIRX Video Output Port & 3D Register\n"); 1211 v4l2_info(sd, "0x8A00-0x8BFF: Reserved\n"); 1212 v4l2_info(sd, "0x8C00-0x8FFF: HDMIRX EDID-RAM (1024bytes)\n"); 1213 v4l2_info(sd, "0x9000-0x90FF: HDMIRX GBD Extraction Control\n"); 1214 v4l2_info(sd, "0x9100-0x92FF: HDMIRX GBD RAM read\n"); 1215 v4l2_info(sd, "0x9300- : Reserved\n"); 1216 } 1217 1218 static int tc358743_get_reg_size(u16 address) 1219 { 1220 /* REF_01 p. 66-72 */ 1221 if (address <= 0x00ff) 1222 return 2; 1223 else if ((address >= 0x0100) && (address <= 0x06FF)) 1224 return 4; 1225 else if ((address >= 0x0700) && (address <= 0x84ff)) 1226 return 2; 1227 else 1228 return 1; 1229 } 1230 1231 static int tc358743_g_register(struct v4l2_subdev *sd, 1232 struct v4l2_dbg_register *reg) 1233 { 1234 if (reg->reg > 0xffff) { 1235 tc358743_print_register_map(sd); 1236 return -EINVAL; 1237 } 1238 1239 reg->size = tc358743_get_reg_size(reg->reg); 1240 1241 reg->val = i2c_rdreg(sd, reg->reg, reg->size); 1242 1243 return 0; 1244 } 1245 1246 static int tc358743_s_register(struct v4l2_subdev *sd, 1247 const struct v4l2_dbg_register *reg) 1248 { 1249 if (reg->reg > 0xffff) { 1250 tc358743_print_register_map(sd); 1251 return -EINVAL; 1252 } 1253 1254 /* It should not be possible for the user to enable HDCP with a simple 1255 * v4l2-dbg command. 1256 * 1257 * DO NOT REMOVE THIS unless all other issues with HDCP have been 1258 * resolved. 1259 */ 1260 if (reg->reg == HDCP_MODE || 1261 reg->reg == HDCP_REG1 || 1262 reg->reg == HDCP_REG2 || 1263 reg->reg == HDCP_REG3 || 1264 reg->reg == BCAPS) 1265 return 0; 1266 1267 i2c_wrreg(sd, (u16)reg->reg, reg->val, 1268 tc358743_get_reg_size(reg->reg)); 1269 1270 return 0; 1271 } 1272 #endif 1273 1274 static int tc358743_isr(struct v4l2_subdev *sd, u32 status, bool *handled) 1275 { 1276 u16 intstatus = i2c_rd16(sd, INTSTATUS); 1277 1278 v4l2_dbg(1, debug, sd, "%s: IntStatus = 0x%04x\n", __func__, intstatus); 1279 1280 if (intstatus & MASK_HDMI_INT) { 1281 u8 hdmi_int0 = i2c_rd8(sd, HDMI_INT0); 1282 u8 hdmi_int1 = i2c_rd8(sd, HDMI_INT1); 1283 1284 if (hdmi_int0 & MASK_I_MISC) 1285 tc358743_hdmi_misc_int_handler(sd, handled); 1286 if (hdmi_int1 & MASK_I_CBIT) 1287 tc358743_hdmi_cbit_int_handler(sd, handled); 1288 if (hdmi_int1 & MASK_I_CLK) 1289 tc358743_hdmi_clk_int_handler(sd, handled); 1290 if (hdmi_int1 & MASK_I_SYS) 1291 tc358743_hdmi_sys_int_handler(sd, handled); 1292 if (hdmi_int1 & MASK_I_AUD) 1293 tc358743_hdmi_audio_int_handler(sd, handled); 1294 1295 i2c_wr16(sd, INTSTATUS, MASK_HDMI_INT); 1296 intstatus &= ~MASK_HDMI_INT; 1297 } 1298 1299 if (intstatus & MASK_CSI_INT) { 1300 u32 csi_int = i2c_rd32(sd, CSI_INT); 1301 1302 if (csi_int & MASK_INTER) 1303 tc358743_csi_err_int_handler(sd, handled); 1304 1305 i2c_wr16(sd, INTSTATUS, MASK_CSI_INT); 1306 } 1307 1308 intstatus = i2c_rd16(sd, INTSTATUS); 1309 if (intstatus) { 1310 v4l2_dbg(1, debug, sd, 1311 "%s: Unhandled IntStatus interrupts: 0x%02x\n", 1312 __func__, intstatus); 1313 } 1314 1315 return 0; 1316 } 1317 1318 static irqreturn_t tc358743_irq_handler(int irq, void *dev_id) 1319 { 1320 struct tc358743_state *state = dev_id; 1321 bool handled; 1322 1323 tc358743_isr(&state->sd, 0, &handled); 1324 1325 return handled ? IRQ_HANDLED : IRQ_NONE; 1326 } 1327 1328 static void tc358743_irq_poll_timer(unsigned long arg) 1329 { 1330 struct tc358743_state *state = (struct tc358743_state *)arg; 1331 1332 schedule_work(&state->work_i2c_poll); 1333 1334 mod_timer(&state->timer, jiffies + msecs_to_jiffies(POLL_INTERVAL_MS)); 1335 } 1336 1337 static void tc358743_work_i2c_poll(struct work_struct *work) 1338 { 1339 struct tc358743_state *state = container_of(work, 1340 struct tc358743_state, work_i2c_poll); 1341 bool handled; 1342 1343 tc358743_isr(&state->sd, 0, &handled); 1344 } 1345 1346 static int tc358743_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh, 1347 struct v4l2_event_subscription *sub) 1348 { 1349 switch (sub->type) { 1350 case V4L2_EVENT_SOURCE_CHANGE: 1351 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub); 1352 case V4L2_EVENT_CTRL: 1353 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub); 1354 default: 1355 return -EINVAL; 1356 } 1357 } 1358 1359 /* --------------- VIDEO OPS --------------- */ 1360 1361 static int tc358743_g_input_status(struct v4l2_subdev *sd, u32 *status) 1362 { 1363 *status = 0; 1364 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0; 1365 *status |= no_sync(sd) ? V4L2_IN_ST_NO_SYNC : 0; 1366 1367 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status); 1368 1369 return 0; 1370 } 1371 1372 static int tc358743_s_dv_timings(struct v4l2_subdev *sd, 1373 struct v4l2_dv_timings *timings) 1374 { 1375 struct tc358743_state *state = to_state(sd); 1376 1377 if (!timings) 1378 return -EINVAL; 1379 1380 if (debug) 1381 v4l2_print_dv_timings(sd->name, "tc358743_s_dv_timings: ", 1382 timings, false); 1383 1384 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) { 1385 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__); 1386 return 0; 1387 } 1388 1389 if (!v4l2_valid_dv_timings(timings, 1390 &tc358743_timings_cap, NULL, NULL)) { 1391 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__); 1392 return -ERANGE; 1393 } 1394 1395 state->timings = *timings; 1396 1397 enable_stream(sd, false); 1398 tc358743_set_pll(sd); 1399 tc358743_set_csi(sd); 1400 1401 return 0; 1402 } 1403 1404 static int tc358743_g_dv_timings(struct v4l2_subdev *sd, 1405 struct v4l2_dv_timings *timings) 1406 { 1407 struct tc358743_state *state = to_state(sd); 1408 1409 *timings = state->timings; 1410 1411 return 0; 1412 } 1413 1414 static int tc358743_enum_dv_timings(struct v4l2_subdev *sd, 1415 struct v4l2_enum_dv_timings *timings) 1416 { 1417 if (timings->pad != 0) 1418 return -EINVAL; 1419 1420 return v4l2_enum_dv_timings_cap(timings, 1421 &tc358743_timings_cap, NULL, NULL); 1422 } 1423 1424 static int tc358743_query_dv_timings(struct v4l2_subdev *sd, 1425 struct v4l2_dv_timings *timings) 1426 { 1427 int ret; 1428 1429 ret = tc358743_get_detected_timings(sd, timings); 1430 if (ret) 1431 return ret; 1432 1433 if (debug) 1434 v4l2_print_dv_timings(sd->name, "tc358743_query_dv_timings: ", 1435 timings, false); 1436 1437 if (!v4l2_valid_dv_timings(timings, 1438 &tc358743_timings_cap, NULL, NULL)) { 1439 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__); 1440 return -ERANGE; 1441 } 1442 1443 return 0; 1444 } 1445 1446 static int tc358743_dv_timings_cap(struct v4l2_subdev *sd, 1447 struct v4l2_dv_timings_cap *cap) 1448 { 1449 if (cap->pad != 0) 1450 return -EINVAL; 1451 1452 *cap = tc358743_timings_cap; 1453 1454 return 0; 1455 } 1456 1457 static int tc358743_g_mbus_config(struct v4l2_subdev *sd, 1458 struct v4l2_mbus_config *cfg) 1459 { 1460 struct tc358743_state *state = to_state(sd); 1461 1462 cfg->type = V4L2_MBUS_CSI2; 1463 1464 /* Support for non-continuous CSI-2 clock is missing in the driver */ 1465 cfg->flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK; 1466 1467 switch (state->csi_lanes_in_use) { 1468 case 1: 1469 cfg->flags |= V4L2_MBUS_CSI2_1_LANE; 1470 break; 1471 case 2: 1472 cfg->flags |= V4L2_MBUS_CSI2_2_LANE; 1473 break; 1474 case 3: 1475 cfg->flags |= V4L2_MBUS_CSI2_3_LANE; 1476 break; 1477 case 4: 1478 cfg->flags |= V4L2_MBUS_CSI2_4_LANE; 1479 break; 1480 default: 1481 return -EINVAL; 1482 } 1483 1484 return 0; 1485 } 1486 1487 static int tc358743_s_stream(struct v4l2_subdev *sd, int enable) 1488 { 1489 enable_stream(sd, enable); 1490 if (!enable) { 1491 /* Put all lanes in PL-11 state (STOPSTATE) */ 1492 tc358743_set_csi(sd); 1493 } 1494 1495 return 0; 1496 } 1497 1498 /* --------------- PAD OPS --------------- */ 1499 1500 static int tc358743_enum_mbus_code(struct v4l2_subdev *sd, 1501 struct v4l2_subdev_pad_config *cfg, 1502 struct v4l2_subdev_mbus_code_enum *code) 1503 { 1504 switch (code->index) { 1505 case 0: 1506 code->code = MEDIA_BUS_FMT_RGB888_1X24; 1507 break; 1508 case 1: 1509 code->code = MEDIA_BUS_FMT_UYVY8_1X16; 1510 break; 1511 default: 1512 return -EINVAL; 1513 } 1514 return 0; 1515 } 1516 1517 static int tc358743_get_fmt(struct v4l2_subdev *sd, 1518 struct v4l2_subdev_pad_config *cfg, 1519 struct v4l2_subdev_format *format) 1520 { 1521 struct tc358743_state *state = to_state(sd); 1522 u8 vi_rep = i2c_rd8(sd, VI_REP); 1523 1524 if (format->pad != 0) 1525 return -EINVAL; 1526 1527 format->format.code = state->mbus_fmt_code; 1528 format->format.width = state->timings.bt.width; 1529 format->format.height = state->timings.bt.height; 1530 format->format.field = V4L2_FIELD_NONE; 1531 1532 switch (vi_rep & MASK_VOUT_COLOR_SEL) { 1533 case MASK_VOUT_COLOR_RGB_FULL: 1534 case MASK_VOUT_COLOR_RGB_LIMITED: 1535 format->format.colorspace = V4L2_COLORSPACE_SRGB; 1536 break; 1537 case MASK_VOUT_COLOR_601_YCBCR_LIMITED: 1538 case MASK_VOUT_COLOR_601_YCBCR_FULL: 1539 format->format.colorspace = V4L2_COLORSPACE_SMPTE170M; 1540 break; 1541 case MASK_VOUT_COLOR_709_YCBCR_FULL: 1542 case MASK_VOUT_COLOR_709_YCBCR_LIMITED: 1543 format->format.colorspace = V4L2_COLORSPACE_REC709; 1544 break; 1545 default: 1546 format->format.colorspace = 0; 1547 break; 1548 } 1549 1550 return 0; 1551 } 1552 1553 static int tc358743_set_fmt(struct v4l2_subdev *sd, 1554 struct v4l2_subdev_pad_config *cfg, 1555 struct v4l2_subdev_format *format) 1556 { 1557 struct tc358743_state *state = to_state(sd); 1558 1559 u32 code = format->format.code; /* is overwritten by get_fmt */ 1560 int ret = tc358743_get_fmt(sd, cfg, format); 1561 1562 format->format.code = code; 1563 1564 if (ret) 1565 return ret; 1566 1567 switch (code) { 1568 case MEDIA_BUS_FMT_RGB888_1X24: 1569 case MEDIA_BUS_FMT_UYVY8_1X16: 1570 break; 1571 default: 1572 return -EINVAL; 1573 } 1574 1575 if (format->which == V4L2_SUBDEV_FORMAT_TRY) 1576 return 0; 1577 1578 state->mbus_fmt_code = format->format.code; 1579 1580 enable_stream(sd, false); 1581 tc358743_set_pll(sd); 1582 tc358743_set_csi(sd); 1583 tc358743_set_csi_color_space(sd); 1584 1585 return 0; 1586 } 1587 1588 static int tc358743_g_edid(struct v4l2_subdev *sd, 1589 struct v4l2_subdev_edid *edid) 1590 { 1591 struct tc358743_state *state = to_state(sd); 1592 1593 memset(edid->reserved, 0, sizeof(edid->reserved)); 1594 1595 if (edid->pad != 0) 1596 return -EINVAL; 1597 1598 if (edid->start_block == 0 && edid->blocks == 0) { 1599 edid->blocks = state->edid_blocks_written; 1600 return 0; 1601 } 1602 1603 if (state->edid_blocks_written == 0) 1604 return -ENODATA; 1605 1606 if (edid->start_block >= state->edid_blocks_written || 1607 edid->blocks == 0) 1608 return -EINVAL; 1609 1610 if (edid->start_block + edid->blocks > state->edid_blocks_written) 1611 edid->blocks = state->edid_blocks_written - edid->start_block; 1612 1613 i2c_rd(sd, EDID_RAM + (edid->start_block * EDID_BLOCK_SIZE), edid->edid, 1614 edid->blocks * EDID_BLOCK_SIZE); 1615 1616 return 0; 1617 } 1618 1619 static int tc358743_s_edid(struct v4l2_subdev *sd, 1620 struct v4l2_subdev_edid *edid) 1621 { 1622 struct tc358743_state *state = to_state(sd); 1623 u16 edid_len = edid->blocks * EDID_BLOCK_SIZE; 1624 int i; 1625 1626 v4l2_dbg(2, debug, sd, "%s, pad %d, start block %d, blocks %d\n", 1627 __func__, edid->pad, edid->start_block, edid->blocks); 1628 1629 memset(edid->reserved, 0, sizeof(edid->reserved)); 1630 1631 if (edid->pad != 0) 1632 return -EINVAL; 1633 1634 if (edid->start_block != 0) 1635 return -EINVAL; 1636 1637 if (edid->blocks > EDID_NUM_BLOCKS_MAX) { 1638 edid->blocks = EDID_NUM_BLOCKS_MAX; 1639 return -E2BIG; 1640 } 1641 1642 tc358743_disable_edid(sd); 1643 1644 i2c_wr8(sd, EDID_LEN1, edid_len & 0xff); 1645 i2c_wr8(sd, EDID_LEN2, edid_len >> 8); 1646 1647 if (edid->blocks == 0) { 1648 state->edid_blocks_written = 0; 1649 return 0; 1650 } 1651 1652 for (i = 0; i < edid_len; i += EDID_BLOCK_SIZE) 1653 i2c_wr(sd, EDID_RAM + i, edid->edid + i, EDID_BLOCK_SIZE); 1654 1655 state->edid_blocks_written = edid->blocks; 1656 1657 if (tx_5v_power_present(sd)) 1658 tc358743_enable_edid(sd); 1659 1660 return 0; 1661 } 1662 1663 /* -------------------------------------------------------------------------- */ 1664 1665 static const struct v4l2_subdev_core_ops tc358743_core_ops = { 1666 .log_status = tc358743_log_status, 1667 #ifdef CONFIG_VIDEO_ADV_DEBUG 1668 .g_register = tc358743_g_register, 1669 .s_register = tc358743_s_register, 1670 #endif 1671 .interrupt_service_routine = tc358743_isr, 1672 .subscribe_event = tc358743_subscribe_event, 1673 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 1674 }; 1675 1676 static const struct v4l2_subdev_video_ops tc358743_video_ops = { 1677 .g_input_status = tc358743_g_input_status, 1678 .s_dv_timings = tc358743_s_dv_timings, 1679 .g_dv_timings = tc358743_g_dv_timings, 1680 .query_dv_timings = tc358743_query_dv_timings, 1681 .g_mbus_config = tc358743_g_mbus_config, 1682 .s_stream = tc358743_s_stream, 1683 }; 1684 1685 static const struct v4l2_subdev_pad_ops tc358743_pad_ops = { 1686 .enum_mbus_code = tc358743_enum_mbus_code, 1687 .set_fmt = tc358743_set_fmt, 1688 .get_fmt = tc358743_get_fmt, 1689 .get_edid = tc358743_g_edid, 1690 .set_edid = tc358743_s_edid, 1691 .enum_dv_timings = tc358743_enum_dv_timings, 1692 .dv_timings_cap = tc358743_dv_timings_cap, 1693 }; 1694 1695 static const struct v4l2_subdev_ops tc358743_ops = { 1696 .core = &tc358743_core_ops, 1697 .video = &tc358743_video_ops, 1698 .pad = &tc358743_pad_ops, 1699 }; 1700 1701 /* --------------- CUSTOM CTRLS --------------- */ 1702 1703 static const struct v4l2_ctrl_config tc358743_ctrl_audio_sampling_rate = { 1704 .id = TC358743_CID_AUDIO_SAMPLING_RATE, 1705 .name = "Audio sampling rate", 1706 .type = V4L2_CTRL_TYPE_INTEGER, 1707 .min = 0, 1708 .max = 768000, 1709 .step = 1, 1710 .def = 0, 1711 .flags = V4L2_CTRL_FLAG_READ_ONLY, 1712 }; 1713 1714 static const struct v4l2_ctrl_config tc358743_ctrl_audio_present = { 1715 .id = TC358743_CID_AUDIO_PRESENT, 1716 .name = "Audio present", 1717 .type = V4L2_CTRL_TYPE_BOOLEAN, 1718 .min = 0, 1719 .max = 1, 1720 .step = 1, 1721 .def = 0, 1722 .flags = V4L2_CTRL_FLAG_READ_ONLY, 1723 }; 1724 1725 /* --------------- PROBE / REMOVE --------------- */ 1726 1727 #ifdef CONFIG_OF 1728 static void tc358743_gpio_reset(struct tc358743_state *state) 1729 { 1730 usleep_range(5000, 10000); 1731 gpiod_set_value(state->reset_gpio, 1); 1732 usleep_range(1000, 2000); 1733 gpiod_set_value(state->reset_gpio, 0); 1734 msleep(20); 1735 } 1736 1737 static int tc358743_probe_of(struct tc358743_state *state) 1738 { 1739 struct device *dev = &state->i2c_client->dev; 1740 struct v4l2_fwnode_endpoint *endpoint; 1741 struct device_node *ep; 1742 struct clk *refclk; 1743 u32 bps_pr_lane; 1744 int ret = -EINVAL; 1745 1746 refclk = devm_clk_get(dev, "refclk"); 1747 if (IS_ERR(refclk)) { 1748 if (PTR_ERR(refclk) != -EPROBE_DEFER) 1749 dev_err(dev, "failed to get refclk: %ld\n", 1750 PTR_ERR(refclk)); 1751 return PTR_ERR(refclk); 1752 } 1753 1754 ep = of_graph_get_next_endpoint(dev->of_node, NULL); 1755 if (!ep) { 1756 dev_err(dev, "missing endpoint node\n"); 1757 return -EINVAL; 1758 } 1759 1760 endpoint = v4l2_fwnode_endpoint_alloc_parse(of_fwnode_handle(ep)); 1761 if (IS_ERR(endpoint)) { 1762 dev_err(dev, "failed to parse endpoint\n"); 1763 return PTR_ERR(endpoint); 1764 } 1765 1766 if (endpoint->bus_type != V4L2_MBUS_CSI2 || 1767 endpoint->bus.mipi_csi2.num_data_lanes == 0 || 1768 endpoint->nr_of_link_frequencies == 0) { 1769 dev_err(dev, "missing CSI-2 properties in endpoint\n"); 1770 goto free_endpoint; 1771 } 1772 1773 state->bus = endpoint->bus.mipi_csi2; 1774 1775 ret = clk_prepare_enable(refclk); 1776 if (ret) { 1777 dev_err(dev, "Failed! to enable clock\n"); 1778 goto free_endpoint; 1779 } 1780 1781 state->pdata.refclk_hz = clk_get_rate(refclk); 1782 state->pdata.ddc5v_delay = DDC5V_DELAY_100_MS; 1783 state->pdata.enable_hdcp = false; 1784 /* A FIFO level of 16 should be enough for 2-lane 720p60 at 594 MHz. */ 1785 state->pdata.fifo_level = 16; 1786 /* 1787 * The PLL input clock is obtained by dividing refclk by pll_prd. 1788 * It must be between 6 MHz and 40 MHz, lower frequency is better. 1789 */ 1790 switch (state->pdata.refclk_hz) { 1791 case 26000000: 1792 case 27000000: 1793 case 42000000: 1794 state->pdata.pll_prd = state->pdata.refclk_hz / 6000000; 1795 break; 1796 default: 1797 dev_err(dev, "unsupported refclk rate: %u Hz\n", 1798 state->pdata.refclk_hz); 1799 goto disable_clk; 1800 } 1801 1802 /* 1803 * The CSI bps per lane must be between 62.5 Mbps and 1 Gbps. 1804 * The default is 594 Mbps for 4-lane 1080p60 or 2-lane 720p60. 1805 */ 1806 bps_pr_lane = 2 * endpoint->link_frequencies[0]; 1807 if (bps_pr_lane < 62500000U || bps_pr_lane > 1000000000U) { 1808 dev_err(dev, "unsupported bps per lane: %u bps\n", bps_pr_lane); 1809 goto disable_clk; 1810 } 1811 1812 /* The CSI speed per lane is refclk / pll_prd * pll_fbd */ 1813 state->pdata.pll_fbd = bps_pr_lane / 1814 state->pdata.refclk_hz * state->pdata.pll_prd; 1815 1816 /* 1817 * FIXME: These timings are from REF_02 for 594 Mbps per lane (297 MHz 1818 * link frequency). In principle it should be possible to calculate 1819 * them based on link frequency and resolution. 1820 */ 1821 if (bps_pr_lane != 594000000U) 1822 dev_warn(dev, "untested bps per lane: %u bps\n", bps_pr_lane); 1823 state->pdata.lineinitcnt = 0xe80; 1824 state->pdata.lptxtimecnt = 0x003; 1825 /* tclk-preparecnt: 3, tclk-zerocnt: 20 */ 1826 state->pdata.tclk_headercnt = 0x1403; 1827 state->pdata.tclk_trailcnt = 0x00; 1828 /* ths-preparecnt: 3, ths-zerocnt: 1 */ 1829 state->pdata.ths_headercnt = 0x0103; 1830 state->pdata.twakeup = 0x4882; 1831 state->pdata.tclk_postcnt = 0x008; 1832 state->pdata.ths_trailcnt = 0x2; 1833 state->pdata.hstxvregcnt = 0; 1834 1835 state->reset_gpio = devm_gpiod_get_optional(dev, "reset", 1836 GPIOD_OUT_LOW); 1837 if (IS_ERR(state->reset_gpio)) { 1838 dev_err(dev, "failed to get reset gpio\n"); 1839 ret = PTR_ERR(state->reset_gpio); 1840 goto disable_clk; 1841 } 1842 1843 if (state->reset_gpio) 1844 tc358743_gpio_reset(state); 1845 1846 ret = 0; 1847 goto free_endpoint; 1848 1849 disable_clk: 1850 clk_disable_unprepare(refclk); 1851 free_endpoint: 1852 v4l2_fwnode_endpoint_free(endpoint); 1853 return ret; 1854 } 1855 #else 1856 static inline int tc358743_probe_of(struct tc358743_state *state) 1857 { 1858 return -ENODEV; 1859 } 1860 #endif 1861 1862 static int tc358743_probe(struct i2c_client *client, 1863 const struct i2c_device_id *id) 1864 { 1865 static struct v4l2_dv_timings default_timing = 1866 V4L2_DV_BT_CEA_640X480P59_94; 1867 struct tc358743_state *state; 1868 struct tc358743_platform_data *pdata = client->dev.platform_data; 1869 struct v4l2_subdev *sd; 1870 int err; 1871 1872 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 1873 return -EIO; 1874 v4l_dbg(1, debug, client, "chip found @ 0x%x (%s)\n", 1875 client->addr << 1, client->adapter->name); 1876 1877 state = devm_kzalloc(&client->dev, sizeof(struct tc358743_state), 1878 GFP_KERNEL); 1879 if (!state) 1880 return -ENOMEM; 1881 1882 state->i2c_client = client; 1883 1884 /* platform data */ 1885 if (pdata) { 1886 state->pdata = *pdata; 1887 state->bus.flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK; 1888 } else { 1889 err = tc358743_probe_of(state); 1890 if (err == -ENODEV) 1891 v4l_err(client, "No platform data!\n"); 1892 if (err) 1893 return err; 1894 } 1895 1896 sd = &state->sd; 1897 v4l2_i2c_subdev_init(sd, client, &tc358743_ops); 1898 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; 1899 1900 /* i2c access */ 1901 if ((i2c_rd16(sd, CHIPID) & MASK_CHIPID) != 0) { 1902 v4l2_info(sd, "not a TC358743 on address 0x%x\n", 1903 client->addr << 1); 1904 return -ENODEV; 1905 } 1906 1907 /* control handlers */ 1908 v4l2_ctrl_handler_init(&state->hdl, 3); 1909 1910 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(&state->hdl, NULL, 1911 V4L2_CID_DV_RX_POWER_PRESENT, 0, 1, 0, 0); 1912 1913 /* custom controls */ 1914 state->audio_sampling_rate_ctrl = v4l2_ctrl_new_custom(&state->hdl, 1915 &tc358743_ctrl_audio_sampling_rate, NULL); 1916 1917 state->audio_present_ctrl = v4l2_ctrl_new_custom(&state->hdl, 1918 &tc358743_ctrl_audio_present, NULL); 1919 1920 sd->ctrl_handler = &state->hdl; 1921 if (state->hdl.error) { 1922 err = state->hdl.error; 1923 goto err_hdl; 1924 } 1925 1926 if (tc358743_update_controls(sd)) { 1927 err = -ENODEV; 1928 goto err_hdl; 1929 } 1930 1931 state->pad.flags = MEDIA_PAD_FL_SOURCE; 1932 err = media_entity_pads_init(&sd->entity, 1, &state->pad); 1933 if (err < 0) 1934 goto err_hdl; 1935 1936 state->mbus_fmt_code = MEDIA_BUS_FMT_RGB888_1X24; 1937 1938 sd->dev = &client->dev; 1939 err = v4l2_async_register_subdev(sd); 1940 if (err < 0) 1941 goto err_hdl; 1942 1943 mutex_init(&state->confctl_mutex); 1944 1945 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, 1946 tc358743_delayed_work_enable_hotplug); 1947 1948 tc358743_initial_setup(sd); 1949 1950 tc358743_s_dv_timings(sd, &default_timing); 1951 1952 tc358743_set_csi_color_space(sd); 1953 1954 tc358743_init_interrupts(sd); 1955 1956 if (state->i2c_client->irq) { 1957 err = devm_request_threaded_irq(&client->dev, 1958 state->i2c_client->irq, 1959 NULL, tc358743_irq_handler, 1960 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 1961 "tc358743", state); 1962 if (err) 1963 goto err_work_queues; 1964 } else { 1965 INIT_WORK(&state->work_i2c_poll, 1966 tc358743_work_i2c_poll); 1967 state->timer.data = (unsigned long)state; 1968 state->timer.function = tc358743_irq_poll_timer; 1969 state->timer.expires = jiffies + 1970 msecs_to_jiffies(POLL_INTERVAL_MS); 1971 add_timer(&state->timer); 1972 } 1973 1974 tc358743_enable_interrupts(sd, tx_5v_power_present(sd)); 1975 i2c_wr16(sd, INTMASK, ~(MASK_HDMI_MSK | MASK_CSI_MSK) & 0xffff); 1976 1977 err = v4l2_ctrl_handler_setup(sd->ctrl_handler); 1978 if (err) 1979 goto err_work_queues; 1980 1981 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, 1982 client->addr << 1, client->adapter->name); 1983 1984 return 0; 1985 1986 err_work_queues: 1987 if (!state->i2c_client->irq) 1988 flush_work(&state->work_i2c_poll); 1989 cancel_delayed_work(&state->delayed_work_enable_hotplug); 1990 mutex_destroy(&state->confctl_mutex); 1991 err_hdl: 1992 media_entity_cleanup(&sd->entity); 1993 v4l2_ctrl_handler_free(&state->hdl); 1994 return err; 1995 } 1996 1997 static int tc358743_remove(struct i2c_client *client) 1998 { 1999 struct v4l2_subdev *sd = i2c_get_clientdata(client); 2000 struct tc358743_state *state = to_state(sd); 2001 2002 if (!state->i2c_client->irq) { 2003 del_timer_sync(&state->timer); 2004 flush_work(&state->work_i2c_poll); 2005 } 2006 cancel_delayed_work(&state->delayed_work_enable_hotplug); 2007 v4l2_async_unregister_subdev(sd); 2008 v4l2_device_unregister_subdev(sd); 2009 mutex_destroy(&state->confctl_mutex); 2010 media_entity_cleanup(&sd->entity); 2011 v4l2_ctrl_handler_free(&state->hdl); 2012 2013 return 0; 2014 } 2015 2016 static const struct i2c_device_id tc358743_id[] = { 2017 {"tc358743", 0}, 2018 {} 2019 }; 2020 2021 MODULE_DEVICE_TABLE(i2c, tc358743_id); 2022 2023 #if IS_ENABLED(CONFIG_OF) 2024 static const struct of_device_id tc358743_of_match[] = { 2025 { .compatible = "toshiba,tc358743" }, 2026 {}, 2027 }; 2028 MODULE_DEVICE_TABLE(of, tc358743_of_match); 2029 #endif 2030 2031 static struct i2c_driver tc358743_driver = { 2032 .driver = { 2033 .name = "tc358743", 2034 .of_match_table = of_match_ptr(tc358743_of_match), 2035 }, 2036 .probe = tc358743_probe, 2037 .remove = tc358743_remove, 2038 .id_table = tc358743_id, 2039 }; 2040 2041 module_i2c_driver(tc358743_driver); 2042