1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * tc358743 - Toshiba HDMI to CSI-2 bridge 4 * 5 * Copyright 2015 Cisco Systems, Inc. and/or its affiliates. All rights 6 * reserved. 7 */ 8 9 /* 10 * References (c = chapter, p = page): 11 * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60 12 * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls 13 */ 14 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/slab.h> 18 #include <linux/i2c.h> 19 #include <linux/clk.h> 20 #include <linux/delay.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/interrupt.h> 23 #include <linux/timer.h> 24 #include <linux/of_graph.h> 25 #include <linux/videodev2.h> 26 #include <linux/workqueue.h> 27 #include <linux/v4l2-dv-timings.h> 28 #include <linux/hdmi.h> 29 #include <media/cec.h> 30 #include <media/v4l2-dv-timings.h> 31 #include <media/v4l2-device.h> 32 #include <media/v4l2-ctrls.h> 33 #include <media/v4l2-event.h> 34 #include <media/v4l2-fwnode.h> 35 #include <media/i2c/tc358743.h> 36 37 #include "tc358743_regs.h" 38 39 static int debug; 40 module_param(debug, int, 0644); 41 MODULE_PARM_DESC(debug, "debug level (0-3)"); 42 43 MODULE_DESCRIPTION("Toshiba TC358743 HDMI to CSI-2 bridge driver"); 44 MODULE_AUTHOR("Ramakrishnan Muthukrishnan <ram@rkrishnan.org>"); 45 MODULE_AUTHOR("Mikhail Khelik <mkhelik@cisco.com>"); 46 MODULE_AUTHOR("Mats Randgaard <matrandg@cisco.com>"); 47 MODULE_LICENSE("GPL"); 48 49 #define EDID_NUM_BLOCKS_MAX 8 50 #define EDID_BLOCK_SIZE 128 51 52 #define I2C_MAX_XFER_SIZE (EDID_BLOCK_SIZE + 2) 53 54 #define POLL_INTERVAL_CEC_MS 10 55 #define POLL_INTERVAL_MS 1000 56 57 static const struct v4l2_dv_timings_cap tc358743_timings_cap = { 58 .type = V4L2_DV_BT_656_1120, 59 /* keep this initialization for compatibility with GCC < 4.4.6 */ 60 .reserved = { 0 }, 61 /* Pixel clock from REF_01 p. 20. Min/max height/width are unknown */ 62 V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 13000000, 165000000, 63 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 64 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, 65 V4L2_DV_BT_CAP_PROGRESSIVE | 66 V4L2_DV_BT_CAP_REDUCED_BLANKING | 67 V4L2_DV_BT_CAP_CUSTOM) 68 }; 69 70 struct tc358743_state { 71 struct tc358743_platform_data pdata; 72 struct v4l2_fwnode_bus_mipi_csi2 bus; 73 struct v4l2_subdev sd; 74 struct media_pad pad; 75 struct v4l2_ctrl_handler hdl; 76 struct i2c_client *i2c_client; 77 /* CONFCTL is modified in ops and tc358743_hdmi_sys_int_handler */ 78 struct mutex confctl_mutex; 79 80 /* controls */ 81 struct v4l2_ctrl *detect_tx_5v_ctrl; 82 struct v4l2_ctrl *audio_sampling_rate_ctrl; 83 struct v4l2_ctrl *audio_present_ctrl; 84 85 struct delayed_work delayed_work_enable_hotplug; 86 87 struct timer_list timer; 88 struct work_struct work_i2c_poll; 89 90 /* edid */ 91 u8 edid_blocks_written; 92 93 struct v4l2_dv_timings timings; 94 u32 mbus_fmt_code; 95 u8 csi_lanes_in_use; 96 97 struct gpio_desc *reset_gpio; 98 99 struct cec_adapter *cec_adap; 100 }; 101 102 static void tc358743_enable_interrupts(struct v4l2_subdev *sd, 103 bool cable_connected); 104 static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd); 105 106 static inline struct tc358743_state *to_state(struct v4l2_subdev *sd) 107 { 108 return container_of(sd, struct tc358743_state, sd); 109 } 110 111 /* --------------- I2C --------------- */ 112 113 static void i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n) 114 { 115 struct tc358743_state *state = to_state(sd); 116 struct i2c_client *client = state->i2c_client; 117 int err; 118 u8 buf[2] = { reg >> 8, reg & 0xff }; 119 struct i2c_msg msgs[] = { 120 { 121 .addr = client->addr, 122 .flags = 0, 123 .len = 2, 124 .buf = buf, 125 }, 126 { 127 .addr = client->addr, 128 .flags = I2C_M_RD, 129 .len = n, 130 .buf = values, 131 }, 132 }; 133 134 err = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); 135 if (err != ARRAY_SIZE(msgs)) { 136 v4l2_err(sd, "%s: reading register 0x%x from 0x%x failed\n", 137 __func__, reg, client->addr); 138 } 139 } 140 141 static void i2c_wr(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n) 142 { 143 struct tc358743_state *state = to_state(sd); 144 struct i2c_client *client = state->i2c_client; 145 int err, i; 146 struct i2c_msg msg; 147 u8 data[I2C_MAX_XFER_SIZE]; 148 149 if ((2 + n) > I2C_MAX_XFER_SIZE) { 150 n = I2C_MAX_XFER_SIZE - 2; 151 v4l2_warn(sd, "i2c wr reg=%04x: len=%d is too big!\n", 152 reg, 2 + n); 153 } 154 155 msg.addr = client->addr; 156 msg.buf = data; 157 msg.len = 2 + n; 158 msg.flags = 0; 159 160 data[0] = reg >> 8; 161 data[1] = reg & 0xff; 162 163 for (i = 0; i < n; i++) 164 data[2 + i] = values[i]; 165 166 err = i2c_transfer(client->adapter, &msg, 1); 167 if (err != 1) { 168 v4l2_err(sd, "%s: writing register 0x%x from 0x%x failed\n", 169 __func__, reg, client->addr); 170 return; 171 } 172 173 if (debug < 3) 174 return; 175 176 switch (n) { 177 case 1: 178 v4l2_info(sd, "I2C write 0x%04x = 0x%02x", 179 reg, data[2]); 180 break; 181 case 2: 182 v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x", 183 reg, data[3], data[2]); 184 break; 185 case 4: 186 v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x%02x%02x", 187 reg, data[5], data[4], data[3], data[2]); 188 break; 189 default: 190 v4l2_info(sd, "I2C write %d bytes from address 0x%04x\n", 191 n, reg); 192 } 193 } 194 195 static noinline u32 i2c_rdreg(struct v4l2_subdev *sd, u16 reg, u32 n) 196 { 197 __le32 val = 0; 198 199 i2c_rd(sd, reg, (u8 __force *)&val, n); 200 201 return le32_to_cpu(val); 202 } 203 204 static noinline void i2c_wrreg(struct v4l2_subdev *sd, u16 reg, u32 val, u32 n) 205 { 206 __le32 raw = cpu_to_le32(val); 207 208 i2c_wr(sd, reg, (u8 __force *)&raw, n); 209 } 210 211 static u8 i2c_rd8(struct v4l2_subdev *sd, u16 reg) 212 { 213 return i2c_rdreg(sd, reg, 1); 214 } 215 216 static void i2c_wr8(struct v4l2_subdev *sd, u16 reg, u8 val) 217 { 218 i2c_wrreg(sd, reg, val, 1); 219 } 220 221 static void i2c_wr8_and_or(struct v4l2_subdev *sd, u16 reg, 222 u8 mask, u8 val) 223 { 224 i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 1) & mask) | val, 1); 225 } 226 227 static u16 i2c_rd16(struct v4l2_subdev *sd, u16 reg) 228 { 229 return i2c_rdreg(sd, reg, 2); 230 } 231 232 static void i2c_wr16(struct v4l2_subdev *sd, u16 reg, u16 val) 233 { 234 i2c_wrreg(sd, reg, val, 2); 235 } 236 237 static void i2c_wr16_and_or(struct v4l2_subdev *sd, u16 reg, u16 mask, u16 val) 238 { 239 i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 2) & mask) | val, 2); 240 } 241 242 static u32 i2c_rd32(struct v4l2_subdev *sd, u16 reg) 243 { 244 return i2c_rdreg(sd, reg, 4); 245 } 246 247 static void i2c_wr32(struct v4l2_subdev *sd, u16 reg, u32 val) 248 { 249 i2c_wrreg(sd, reg, val, 4); 250 } 251 252 /* --------------- STATUS --------------- */ 253 254 static inline bool is_hdmi(struct v4l2_subdev *sd) 255 { 256 return i2c_rd8(sd, SYS_STATUS) & MASK_S_HDMI; 257 } 258 259 static inline bool tx_5v_power_present(struct v4l2_subdev *sd) 260 { 261 return i2c_rd8(sd, SYS_STATUS) & MASK_S_DDC5V; 262 } 263 264 static inline bool no_signal(struct v4l2_subdev *sd) 265 { 266 return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_TMDS); 267 } 268 269 static inline bool no_sync(struct v4l2_subdev *sd) 270 { 271 return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_SYNC); 272 } 273 274 static inline bool audio_present(struct v4l2_subdev *sd) 275 { 276 return i2c_rd8(sd, AU_STATUS0) & MASK_S_A_SAMPLE; 277 } 278 279 static int get_audio_sampling_rate(struct v4l2_subdev *sd) 280 { 281 static const int code_to_rate[] = { 282 44100, 0, 48000, 32000, 22050, 384000, 24000, 352800, 283 88200, 768000, 96000, 705600, 176400, 0, 192000, 0 284 }; 285 286 /* Register FS_SET is not cleared when the cable is disconnected */ 287 if (no_signal(sd)) 288 return 0; 289 290 return code_to_rate[i2c_rd8(sd, FS_SET) & MASK_FS]; 291 } 292 293 /* --------------- TIMINGS --------------- */ 294 295 static inline unsigned fps(const struct v4l2_bt_timings *t) 296 { 297 if (!V4L2_DV_BT_FRAME_HEIGHT(t) || !V4L2_DV_BT_FRAME_WIDTH(t)) 298 return 0; 299 300 return DIV_ROUND_CLOSEST((unsigned)t->pixelclock, 301 V4L2_DV_BT_FRAME_HEIGHT(t) * V4L2_DV_BT_FRAME_WIDTH(t)); 302 } 303 304 static int tc358743_get_detected_timings(struct v4l2_subdev *sd, 305 struct v4l2_dv_timings *timings) 306 { 307 struct v4l2_bt_timings *bt = &timings->bt; 308 unsigned width, height, frame_width, frame_height, frame_interval, fps; 309 310 memset(timings, 0, sizeof(struct v4l2_dv_timings)); 311 312 if (no_signal(sd)) { 313 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); 314 return -ENOLINK; 315 } 316 if (no_sync(sd)) { 317 v4l2_dbg(1, debug, sd, "%s: no sync on signal\n", __func__); 318 return -ENOLCK; 319 } 320 321 timings->type = V4L2_DV_BT_656_1120; 322 bt->interlaced = i2c_rd8(sd, VI_STATUS1) & MASK_S_V_INTERLACE ? 323 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; 324 325 width = ((i2c_rd8(sd, DE_WIDTH_H_HI) & 0x1f) << 8) + 326 i2c_rd8(sd, DE_WIDTH_H_LO); 327 height = ((i2c_rd8(sd, DE_WIDTH_V_HI) & 0x1f) << 8) + 328 i2c_rd8(sd, DE_WIDTH_V_LO); 329 frame_width = ((i2c_rd8(sd, H_SIZE_HI) & 0x1f) << 8) + 330 i2c_rd8(sd, H_SIZE_LO); 331 frame_height = (((i2c_rd8(sd, V_SIZE_HI) & 0x3f) << 8) + 332 i2c_rd8(sd, V_SIZE_LO)) / 2; 333 /* frame interval in milliseconds * 10 334 * Require SYS_FREQ0 and SYS_FREQ1 are precisely set */ 335 frame_interval = ((i2c_rd8(sd, FV_CNT_HI) & 0x3) << 8) + 336 i2c_rd8(sd, FV_CNT_LO); 337 fps = (frame_interval > 0) ? 338 DIV_ROUND_CLOSEST(10000, frame_interval) : 0; 339 340 bt->width = width; 341 bt->height = height; 342 bt->vsync = frame_height - height; 343 bt->hsync = frame_width - width; 344 bt->pixelclock = frame_width * frame_height * fps; 345 if (bt->interlaced == V4L2_DV_INTERLACED) { 346 bt->height *= 2; 347 bt->il_vsync = bt->vsync + 1; 348 bt->pixelclock /= 2; 349 } 350 351 return 0; 352 } 353 354 /* --------------- HOTPLUG / HDCP / EDID --------------- */ 355 356 static void tc358743_delayed_work_enable_hotplug(struct work_struct *work) 357 { 358 struct delayed_work *dwork = to_delayed_work(work); 359 struct tc358743_state *state = container_of(dwork, 360 struct tc358743_state, delayed_work_enable_hotplug); 361 struct v4l2_subdev *sd = &state->sd; 362 363 v4l2_dbg(2, debug, sd, "%s:\n", __func__); 364 365 i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, MASK_HPD_OUT0); 366 } 367 368 static void tc358743_set_hdmi_hdcp(struct v4l2_subdev *sd, bool enable) 369 { 370 v4l2_dbg(2, debug, sd, "%s: %s\n", __func__, enable ? 371 "enable" : "disable"); 372 373 if (enable) { 374 i2c_wr8_and_or(sd, HDCP_REG3, ~KEY_RD_CMD, KEY_RD_CMD); 375 376 i2c_wr8_and_or(sd, HDCP_MODE, ~MASK_MANUAL_AUTHENTICATION, 0); 377 378 i2c_wr8_and_or(sd, HDCP_REG1, 0xff, 379 MASK_AUTH_UNAUTH_SEL_16_FRAMES | 380 MASK_AUTH_UNAUTH_AUTO); 381 382 i2c_wr8_and_or(sd, HDCP_REG2, ~MASK_AUTO_P3_RESET, 383 SET_AUTO_P3_RESET_FRAMES(0x0f)); 384 } else { 385 i2c_wr8_and_or(sd, HDCP_MODE, ~MASK_MANUAL_AUTHENTICATION, 386 MASK_MANUAL_AUTHENTICATION); 387 } 388 } 389 390 static void tc358743_disable_edid(struct v4l2_subdev *sd) 391 { 392 struct tc358743_state *state = to_state(sd); 393 394 v4l2_dbg(2, debug, sd, "%s:\n", __func__); 395 396 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); 397 398 /* DDC access to EDID is also disabled when hotplug is disabled. See 399 * register DDC_CTL */ 400 i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, 0x0); 401 } 402 403 static void tc358743_enable_edid(struct v4l2_subdev *sd) 404 { 405 struct tc358743_state *state = to_state(sd); 406 407 if (state->edid_blocks_written == 0) { 408 v4l2_dbg(2, debug, sd, "%s: no EDID -> no hotplug\n", __func__); 409 tc358743_s_ctrl_detect_tx_5v(sd); 410 return; 411 } 412 413 v4l2_dbg(2, debug, sd, "%s:\n", __func__); 414 415 /* Enable hotplug after 100 ms. DDC access to EDID is also enabled when 416 * hotplug is enabled. See register DDC_CTL */ 417 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 10); 418 419 tc358743_enable_interrupts(sd, true); 420 tc358743_s_ctrl_detect_tx_5v(sd); 421 } 422 423 static void tc358743_erase_bksv(struct v4l2_subdev *sd) 424 { 425 int i; 426 427 for (i = 0; i < 5; i++) 428 i2c_wr8(sd, BKSV + i, 0); 429 } 430 431 /* --------------- AVI infoframe --------------- */ 432 433 static void print_avi_infoframe(struct v4l2_subdev *sd) 434 { 435 struct i2c_client *client = v4l2_get_subdevdata(sd); 436 struct device *dev = &client->dev; 437 union hdmi_infoframe frame; 438 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)]; 439 440 if (!is_hdmi(sd)) { 441 v4l2_info(sd, "DVI-D signal - AVI infoframe not supported\n"); 442 return; 443 } 444 445 i2c_rd(sd, PK_AVI_0HEAD, buffer, HDMI_INFOFRAME_SIZE(AVI)); 446 447 if (hdmi_infoframe_unpack(&frame, buffer, sizeof(buffer)) < 0) { 448 v4l2_err(sd, "%s: unpack of AVI infoframe failed\n", __func__); 449 return; 450 } 451 452 hdmi_infoframe_log(KERN_INFO, dev, &frame); 453 } 454 455 /* --------------- CTRLS --------------- */ 456 457 static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd) 458 { 459 struct tc358743_state *state = to_state(sd); 460 461 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, 462 tx_5v_power_present(sd)); 463 } 464 465 static int tc358743_s_ctrl_audio_sampling_rate(struct v4l2_subdev *sd) 466 { 467 struct tc358743_state *state = to_state(sd); 468 469 return v4l2_ctrl_s_ctrl(state->audio_sampling_rate_ctrl, 470 get_audio_sampling_rate(sd)); 471 } 472 473 static int tc358743_s_ctrl_audio_present(struct v4l2_subdev *sd) 474 { 475 struct tc358743_state *state = to_state(sd); 476 477 return v4l2_ctrl_s_ctrl(state->audio_present_ctrl, 478 audio_present(sd)); 479 } 480 481 static int tc358743_update_controls(struct v4l2_subdev *sd) 482 { 483 int ret = 0; 484 485 ret |= tc358743_s_ctrl_detect_tx_5v(sd); 486 ret |= tc358743_s_ctrl_audio_sampling_rate(sd); 487 ret |= tc358743_s_ctrl_audio_present(sd); 488 489 return ret; 490 } 491 492 /* --------------- INIT --------------- */ 493 494 static void tc358743_reset_phy(struct v4l2_subdev *sd) 495 { 496 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 497 498 i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, 0); 499 i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, MASK_RESET_CTRL); 500 } 501 502 static void tc358743_reset(struct v4l2_subdev *sd, uint16_t mask) 503 { 504 u16 sysctl = i2c_rd16(sd, SYSCTL); 505 506 i2c_wr16(sd, SYSCTL, sysctl | mask); 507 i2c_wr16(sd, SYSCTL, sysctl & ~mask); 508 } 509 510 static inline void tc358743_sleep_mode(struct v4l2_subdev *sd, bool enable) 511 { 512 i2c_wr16_and_or(sd, SYSCTL, ~MASK_SLEEP, 513 enable ? MASK_SLEEP : 0); 514 } 515 516 static inline void enable_stream(struct v4l2_subdev *sd, bool enable) 517 { 518 struct tc358743_state *state = to_state(sd); 519 520 v4l2_dbg(3, debug, sd, "%s: %sable\n", 521 __func__, enable ? "en" : "dis"); 522 523 if (enable) { 524 /* It is critical for CSI receiver to see lane transition 525 * LP11->HS. Set to non-continuous mode to enable clock lane 526 * LP11 state. */ 527 i2c_wr32(sd, TXOPTIONCNTRL, 0); 528 /* Set to continuous mode to trigger LP11->HS transition */ 529 i2c_wr32(sd, TXOPTIONCNTRL, MASK_CONTCLKMODE); 530 /* Unmute video */ 531 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE); 532 } else { 533 /* Mute video so that all data lanes go to LSP11 state. 534 * No data is output to CSI Tx block. */ 535 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE | MASK_VI_MUTE); 536 } 537 538 mutex_lock(&state->confctl_mutex); 539 i2c_wr16_and_or(sd, CONFCTL, ~(MASK_VBUFEN | MASK_ABUFEN), 540 enable ? (MASK_VBUFEN | MASK_ABUFEN) : 0x0); 541 mutex_unlock(&state->confctl_mutex); 542 } 543 544 static void tc358743_set_pll(struct v4l2_subdev *sd) 545 { 546 struct tc358743_state *state = to_state(sd); 547 struct tc358743_platform_data *pdata = &state->pdata; 548 u16 pllctl0 = i2c_rd16(sd, PLLCTL0); 549 u16 pllctl1 = i2c_rd16(sd, PLLCTL1); 550 u16 pllctl0_new = SET_PLL_PRD(pdata->pll_prd) | 551 SET_PLL_FBD(pdata->pll_fbd); 552 u32 hsck = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd; 553 554 v4l2_dbg(2, debug, sd, "%s:\n", __func__); 555 556 /* Only rewrite when needed (new value or disabled), since rewriting 557 * triggers another format change event. */ 558 if ((pllctl0 != pllctl0_new) || ((pllctl1 & MASK_PLL_EN) == 0)) { 559 u16 pll_frs; 560 561 if (hsck > 500000000) 562 pll_frs = 0x0; 563 else if (hsck > 250000000) 564 pll_frs = 0x1; 565 else if (hsck > 125000000) 566 pll_frs = 0x2; 567 else 568 pll_frs = 0x3; 569 570 v4l2_dbg(1, debug, sd, "%s: updating PLL clock\n", __func__); 571 tc358743_sleep_mode(sd, true); 572 i2c_wr16(sd, PLLCTL0, pllctl0_new); 573 i2c_wr16_and_or(sd, PLLCTL1, 574 ~(MASK_PLL_FRS | MASK_RESETB | MASK_PLL_EN), 575 (SET_PLL_FRS(pll_frs) | MASK_RESETB | 576 MASK_PLL_EN)); 577 udelay(10); /* REF_02, Sheet "Source HDMI" */ 578 i2c_wr16_and_or(sd, PLLCTL1, ~MASK_CKEN, MASK_CKEN); 579 tc358743_sleep_mode(sd, false); 580 } 581 } 582 583 static void tc358743_set_ref_clk(struct v4l2_subdev *sd) 584 { 585 struct tc358743_state *state = to_state(sd); 586 struct tc358743_platform_data *pdata = &state->pdata; 587 u32 sys_freq; 588 u32 lockdet_ref; 589 u32 cec_freq; 590 u16 fh_min; 591 u16 fh_max; 592 593 BUG_ON(!(pdata->refclk_hz == 26000000 || 594 pdata->refclk_hz == 27000000 || 595 pdata->refclk_hz == 42000000)); 596 597 sys_freq = pdata->refclk_hz / 10000; 598 i2c_wr8(sd, SYS_FREQ0, sys_freq & 0x00ff); 599 i2c_wr8(sd, SYS_FREQ1, (sys_freq & 0xff00) >> 8); 600 601 i2c_wr8_and_or(sd, PHY_CTL0, ~MASK_PHY_SYSCLK_IND, 602 (pdata->refclk_hz == 42000000) ? 603 MASK_PHY_SYSCLK_IND : 0x0); 604 605 fh_min = pdata->refclk_hz / 100000; 606 i2c_wr8(sd, FH_MIN0, fh_min & 0x00ff); 607 i2c_wr8(sd, FH_MIN1, (fh_min & 0xff00) >> 8); 608 609 fh_max = (fh_min * 66) / 10; 610 i2c_wr8(sd, FH_MAX0, fh_max & 0x00ff); 611 i2c_wr8(sd, FH_MAX1, (fh_max & 0xff00) >> 8); 612 613 lockdet_ref = pdata->refclk_hz / 100; 614 i2c_wr8(sd, LOCKDET_REF0, lockdet_ref & 0x0000ff); 615 i2c_wr8(sd, LOCKDET_REF1, (lockdet_ref & 0x00ff00) >> 8); 616 i2c_wr8(sd, LOCKDET_REF2, (lockdet_ref & 0x0f0000) >> 16); 617 618 i2c_wr8_and_or(sd, NCO_F0_MOD, ~MASK_NCO_F0_MOD, 619 (pdata->refclk_hz == 27000000) ? 620 MASK_NCO_F0_MOD_27MHZ : 0x0); 621 622 /* 623 * Trial and error suggests that the default register value 624 * of 656 is for a 42 MHz reference clock. Use that to derive 625 * a new value based on the actual reference clock. 626 */ 627 cec_freq = (656 * sys_freq) / 4200; 628 i2c_wr16(sd, CECHCLK, cec_freq); 629 i2c_wr16(sd, CECLCLK, cec_freq); 630 } 631 632 static void tc358743_set_csi_color_space(struct v4l2_subdev *sd) 633 { 634 struct tc358743_state *state = to_state(sd); 635 636 switch (state->mbus_fmt_code) { 637 case MEDIA_BUS_FMT_UYVY8_1X16: 638 v4l2_dbg(2, debug, sd, "%s: YCbCr 422 16-bit\n", __func__); 639 i2c_wr8_and_or(sd, VOUT_SET2, 640 ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff, 641 MASK_SEL422 | MASK_VOUT_422FIL_100); 642 i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff, 643 MASK_VOUT_COLOR_601_YCBCR_LIMITED); 644 mutex_lock(&state->confctl_mutex); 645 i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT, 646 MASK_YCBCRFMT_422_8_BIT); 647 mutex_unlock(&state->confctl_mutex); 648 break; 649 case MEDIA_BUS_FMT_RGB888_1X24: 650 v4l2_dbg(2, debug, sd, "%s: RGB 888 24-bit\n", __func__); 651 i2c_wr8_and_or(sd, VOUT_SET2, 652 ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff, 653 0x00); 654 i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff, 655 MASK_VOUT_COLOR_RGB_FULL); 656 mutex_lock(&state->confctl_mutex); 657 i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT, 0); 658 mutex_unlock(&state->confctl_mutex); 659 break; 660 default: 661 v4l2_dbg(2, debug, sd, "%s: Unsupported format code 0x%x\n", 662 __func__, state->mbus_fmt_code); 663 } 664 } 665 666 static unsigned tc358743_num_csi_lanes_needed(struct v4l2_subdev *sd) 667 { 668 struct tc358743_state *state = to_state(sd); 669 struct v4l2_bt_timings *bt = &state->timings.bt; 670 struct tc358743_platform_data *pdata = &state->pdata; 671 u32 bits_pr_pixel = 672 (state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16) ? 16 : 24; 673 u32 bps = bt->width * bt->height * fps(bt) * bits_pr_pixel; 674 u32 bps_pr_lane = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd; 675 676 return DIV_ROUND_UP(bps, bps_pr_lane); 677 } 678 679 static void tc358743_set_csi(struct v4l2_subdev *sd) 680 { 681 struct tc358743_state *state = to_state(sd); 682 struct tc358743_platform_data *pdata = &state->pdata; 683 unsigned lanes = tc358743_num_csi_lanes_needed(sd); 684 685 v4l2_dbg(3, debug, sd, "%s:\n", __func__); 686 687 state->csi_lanes_in_use = lanes; 688 689 tc358743_reset(sd, MASK_CTXRST); 690 691 if (lanes < 1) 692 i2c_wr32(sd, CLW_CNTRL, MASK_CLW_LANEDISABLE); 693 if (lanes < 1) 694 i2c_wr32(sd, D0W_CNTRL, MASK_D0W_LANEDISABLE); 695 if (lanes < 2) 696 i2c_wr32(sd, D1W_CNTRL, MASK_D1W_LANEDISABLE); 697 if (lanes < 3) 698 i2c_wr32(sd, D2W_CNTRL, MASK_D2W_LANEDISABLE); 699 if (lanes < 4) 700 i2c_wr32(sd, D3W_CNTRL, MASK_D3W_LANEDISABLE); 701 702 i2c_wr32(sd, LINEINITCNT, pdata->lineinitcnt); 703 i2c_wr32(sd, LPTXTIMECNT, pdata->lptxtimecnt); 704 i2c_wr32(sd, TCLK_HEADERCNT, pdata->tclk_headercnt); 705 i2c_wr32(sd, TCLK_TRAILCNT, pdata->tclk_trailcnt); 706 i2c_wr32(sd, THS_HEADERCNT, pdata->ths_headercnt); 707 i2c_wr32(sd, TWAKEUP, pdata->twakeup); 708 i2c_wr32(sd, TCLK_POSTCNT, pdata->tclk_postcnt); 709 i2c_wr32(sd, THS_TRAILCNT, pdata->ths_trailcnt); 710 i2c_wr32(sd, HSTXVREGCNT, pdata->hstxvregcnt); 711 712 i2c_wr32(sd, HSTXVREGEN, 713 ((lanes > 0) ? MASK_CLM_HSTXVREGEN : 0x0) | 714 ((lanes > 0) ? MASK_D0M_HSTXVREGEN : 0x0) | 715 ((lanes > 1) ? MASK_D1M_HSTXVREGEN : 0x0) | 716 ((lanes > 2) ? MASK_D2M_HSTXVREGEN : 0x0) | 717 ((lanes > 3) ? MASK_D3M_HSTXVREGEN : 0x0)); 718 719 i2c_wr32(sd, TXOPTIONCNTRL, (state->bus.flags & 720 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) ? MASK_CONTCLKMODE : 0); 721 i2c_wr32(sd, STARTCNTRL, MASK_START); 722 i2c_wr32(sd, CSI_START, MASK_STRT); 723 724 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET | 725 MASK_ADDRESS_CSI_CONTROL | 726 MASK_CSI_MODE | 727 MASK_TXHSMD | 728 ((lanes == 4) ? MASK_NOL_4 : 729 (lanes == 3) ? MASK_NOL_3 : 730 (lanes == 2) ? MASK_NOL_2 : MASK_NOL_1)); 731 732 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET | 733 MASK_ADDRESS_CSI_ERR_INTENA | MASK_TXBRK | MASK_QUNK | 734 MASK_WCER | MASK_INER); 735 736 i2c_wr32(sd, CSI_CONFW, MASK_MODE_CLEAR | 737 MASK_ADDRESS_CSI_ERR_HALT | MASK_TXBRK | MASK_QUNK); 738 739 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET | 740 MASK_ADDRESS_CSI_INT_ENA | MASK_INTER); 741 } 742 743 static void tc358743_set_hdmi_phy(struct v4l2_subdev *sd) 744 { 745 struct tc358743_state *state = to_state(sd); 746 struct tc358743_platform_data *pdata = &state->pdata; 747 748 /* Default settings from REF_02, sheet "Source HDMI" 749 * and custom settings as platform data */ 750 i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, 0x0); 751 i2c_wr8(sd, PHY_CTL1, SET_PHY_AUTO_RST1_US(1600) | 752 SET_FREQ_RANGE_MODE_CYCLES(1)); 753 i2c_wr8_and_or(sd, PHY_CTL2, ~MASK_PHY_AUTO_RSTn, 754 (pdata->hdmi_phy_auto_reset_tmds_detected ? 755 MASK_PHY_AUTO_RST2 : 0) | 756 (pdata->hdmi_phy_auto_reset_tmds_in_range ? 757 MASK_PHY_AUTO_RST3 : 0) | 758 (pdata->hdmi_phy_auto_reset_tmds_valid ? 759 MASK_PHY_AUTO_RST4 : 0)); 760 i2c_wr8(sd, PHY_BIAS, 0x40); 761 i2c_wr8(sd, PHY_CSQ, SET_CSQ_CNT_LEVEL(0x0a)); 762 i2c_wr8(sd, AVM_CTL, 45); 763 i2c_wr8_and_or(sd, HDMI_DET, ~MASK_HDMI_DET_V, 764 pdata->hdmi_detection_delay << 4); 765 i2c_wr8_and_or(sd, HV_RST, ~(MASK_H_PI_RST | MASK_V_PI_RST), 766 (pdata->hdmi_phy_auto_reset_hsync_out_of_range ? 767 MASK_H_PI_RST : 0) | 768 (pdata->hdmi_phy_auto_reset_vsync_out_of_range ? 769 MASK_V_PI_RST : 0)); 770 i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, MASK_ENABLE_PHY); 771 } 772 773 static void tc358743_set_hdmi_audio(struct v4l2_subdev *sd) 774 { 775 struct tc358743_state *state = to_state(sd); 776 777 /* Default settings from REF_02, sheet "Source HDMI" */ 778 i2c_wr8(sd, FORCE_MUTE, 0x00); 779 i2c_wr8(sd, AUTO_CMD0, MASK_AUTO_MUTE7 | MASK_AUTO_MUTE6 | 780 MASK_AUTO_MUTE5 | MASK_AUTO_MUTE4 | 781 MASK_AUTO_MUTE1 | MASK_AUTO_MUTE0); 782 i2c_wr8(sd, AUTO_CMD1, MASK_AUTO_MUTE9); 783 i2c_wr8(sd, AUTO_CMD2, MASK_AUTO_PLAY3 | MASK_AUTO_PLAY2); 784 i2c_wr8(sd, BUFINIT_START, SET_BUFINIT_START_MS(500)); 785 i2c_wr8(sd, FS_MUTE, 0x00); 786 i2c_wr8(sd, FS_IMODE, MASK_NLPCM_SMODE | MASK_FS_SMODE); 787 i2c_wr8(sd, ACR_MODE, MASK_CTS_MODE); 788 i2c_wr8(sd, ACR_MDF0, MASK_ACR_L2MDF_1976_PPM | MASK_ACR_L1MDF_976_PPM); 789 i2c_wr8(sd, ACR_MDF1, MASK_ACR_L3MDF_3906_PPM); 790 i2c_wr8(sd, SDO_MODE1, MASK_SDO_FMT_I2S); 791 i2c_wr8(sd, DIV_MODE, SET_DIV_DLY_MS(100)); 792 793 mutex_lock(&state->confctl_mutex); 794 i2c_wr16_and_or(sd, CONFCTL, 0xffff, MASK_AUDCHNUM_2 | 795 MASK_AUDOUTSEL_I2S | MASK_AUTOINDEX); 796 mutex_unlock(&state->confctl_mutex); 797 } 798 799 static void tc358743_set_hdmi_info_frame_mode(struct v4l2_subdev *sd) 800 { 801 /* Default settings from REF_02, sheet "Source HDMI" */ 802 i2c_wr8(sd, PK_INT_MODE, MASK_ISRC2_INT_MODE | MASK_ISRC_INT_MODE | 803 MASK_ACP_INT_MODE | MASK_VS_INT_MODE | 804 MASK_SPD_INT_MODE | MASK_MS_INT_MODE | 805 MASK_AUD_INT_MODE | MASK_AVI_INT_MODE); 806 i2c_wr8(sd, NO_PKT_LIMIT, 0x2c); 807 i2c_wr8(sd, NO_PKT_CLR, 0x53); 808 i2c_wr8(sd, ERR_PK_LIMIT, 0x01); 809 i2c_wr8(sd, NO_PKT_LIMIT2, 0x30); 810 i2c_wr8(sd, NO_GDB_LIMIT, 0x10); 811 } 812 813 static void tc358743_initial_setup(struct v4l2_subdev *sd) 814 { 815 struct tc358743_state *state = to_state(sd); 816 struct tc358743_platform_data *pdata = &state->pdata; 817 818 /* 819 * IR is not supported by this driver. 820 * CEC is only enabled if needed. 821 */ 822 i2c_wr16_and_or(sd, SYSCTL, ~(MASK_IRRST | MASK_CECRST), 823 (MASK_IRRST | MASK_CECRST)); 824 825 tc358743_reset(sd, MASK_CTXRST | MASK_HDMIRST); 826 #ifdef CONFIG_VIDEO_TC358743_CEC 827 tc358743_reset(sd, MASK_CECRST); 828 #endif 829 tc358743_sleep_mode(sd, false); 830 831 i2c_wr16(sd, FIFOCTL, pdata->fifo_level); 832 833 tc358743_set_ref_clk(sd); 834 835 i2c_wr8_and_or(sd, DDC_CTL, ~MASK_DDC5V_MODE, 836 pdata->ddc5v_delay & MASK_DDC5V_MODE); 837 i2c_wr8_and_or(sd, EDID_MODE, ~MASK_EDID_MODE, MASK_EDID_MODE_E_DDC); 838 839 tc358743_set_hdmi_phy(sd); 840 tc358743_set_hdmi_hdcp(sd, pdata->enable_hdcp); 841 tc358743_set_hdmi_audio(sd); 842 tc358743_set_hdmi_info_frame_mode(sd); 843 844 /* All CE and IT formats are detected as RGB full range in DVI mode */ 845 i2c_wr8_and_or(sd, VI_MODE, ~MASK_RGB_DVI, 0); 846 847 i2c_wr8_and_or(sd, VOUT_SET2, ~MASK_VOUTCOLORMODE, 848 MASK_VOUTCOLORMODE_AUTO); 849 i2c_wr8(sd, VOUT_SET3, MASK_VOUT_EXTCNT); 850 } 851 852 /* --------------- CEC --------------- */ 853 854 #ifdef CONFIG_VIDEO_TC358743_CEC 855 static int tc358743_cec_adap_enable(struct cec_adapter *adap, bool enable) 856 { 857 struct tc358743_state *state = adap->priv; 858 struct v4l2_subdev *sd = &state->sd; 859 860 i2c_wr32(sd, CECIMSK, enable ? MASK_CECTIM | MASK_CECRIM : 0); 861 i2c_wr32(sd, CECICLR, MASK_CECTICLR | MASK_CECRICLR); 862 i2c_wr32(sd, CECEN, enable); 863 if (enable) 864 i2c_wr32(sd, CECREN, MASK_CECREN); 865 return 0; 866 } 867 868 static int tc358743_cec_adap_monitor_all_enable(struct cec_adapter *adap, 869 bool enable) 870 { 871 struct tc358743_state *state = adap->priv; 872 struct v4l2_subdev *sd = &state->sd; 873 u32 reg; 874 875 reg = i2c_rd32(sd, CECRCTL1); 876 if (enable) 877 reg |= MASK_CECOTH; 878 else 879 reg &= ~MASK_CECOTH; 880 i2c_wr32(sd, CECRCTL1, reg); 881 return 0; 882 } 883 884 static int tc358743_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr) 885 { 886 struct tc358743_state *state = adap->priv; 887 struct v4l2_subdev *sd = &state->sd; 888 unsigned int la = 0; 889 890 if (log_addr != CEC_LOG_ADDR_INVALID) { 891 la = i2c_rd32(sd, CECADD); 892 la |= 1 << log_addr; 893 } 894 i2c_wr32(sd, CECADD, la); 895 return 0; 896 } 897 898 static int tc358743_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 899 u32 signal_free_time, struct cec_msg *msg) 900 { 901 struct tc358743_state *state = adap->priv; 902 struct v4l2_subdev *sd = &state->sd; 903 unsigned int i; 904 905 i2c_wr32(sd, CECTCTL, 906 (cec_msg_is_broadcast(msg) ? MASK_CECBRD : 0) | 907 (signal_free_time - 1)); 908 for (i = 0; i < msg->len; i++) 909 i2c_wr32(sd, CECTBUF1 + i * 4, 910 msg->msg[i] | ((i == msg->len - 1) ? MASK_CECTEOM : 0)); 911 i2c_wr32(sd, CECTEN, MASK_CECTEN); 912 return 0; 913 } 914 915 static const struct cec_adap_ops tc358743_cec_adap_ops = { 916 .adap_enable = tc358743_cec_adap_enable, 917 .adap_log_addr = tc358743_cec_adap_log_addr, 918 .adap_transmit = tc358743_cec_adap_transmit, 919 .adap_monitor_all_enable = tc358743_cec_adap_monitor_all_enable, 920 }; 921 922 static void tc358743_cec_handler(struct v4l2_subdev *sd, u16 intstatus, 923 bool *handled) 924 { 925 struct tc358743_state *state = to_state(sd); 926 unsigned int cec_rxint, cec_txint; 927 unsigned int clr = 0; 928 929 cec_rxint = i2c_rd32(sd, CECRSTAT); 930 cec_txint = i2c_rd32(sd, CECTSTAT); 931 932 if (intstatus & MASK_CEC_RINT) 933 clr |= MASK_CECRICLR; 934 if (intstatus & MASK_CEC_TINT) 935 clr |= MASK_CECTICLR; 936 i2c_wr32(sd, CECICLR, clr); 937 938 if ((intstatus & MASK_CEC_TINT) && cec_txint) { 939 if (cec_txint & MASK_CECTIEND) 940 cec_transmit_attempt_done(state->cec_adap, 941 CEC_TX_STATUS_OK); 942 else if (cec_txint & MASK_CECTIAL) 943 cec_transmit_attempt_done(state->cec_adap, 944 CEC_TX_STATUS_ARB_LOST); 945 else if (cec_txint & MASK_CECTIACK) 946 cec_transmit_attempt_done(state->cec_adap, 947 CEC_TX_STATUS_NACK); 948 else if (cec_txint & MASK_CECTIUR) { 949 /* 950 * Not sure when this bit is set. Treat 951 * it as an error for now. 952 */ 953 cec_transmit_attempt_done(state->cec_adap, 954 CEC_TX_STATUS_ERROR); 955 } 956 if (handled) 957 *handled = true; 958 } 959 if ((intstatus & MASK_CEC_RINT) && 960 (cec_rxint & MASK_CECRIEND)) { 961 struct cec_msg msg = {}; 962 unsigned int i; 963 unsigned int v; 964 965 v = i2c_rd32(sd, CECRCTR); 966 msg.len = v & 0x1f; 967 for (i = 0; i < msg.len; i++) { 968 v = i2c_rd32(sd, CECRBUF1 + i * 4); 969 msg.msg[i] = v & 0xff; 970 } 971 cec_received_msg(state->cec_adap, &msg); 972 if (handled) 973 *handled = true; 974 } 975 i2c_wr16(sd, INTSTATUS, 976 intstatus & (MASK_CEC_RINT | MASK_CEC_TINT)); 977 } 978 979 #endif 980 981 /* --------------- IRQ --------------- */ 982 983 static void tc358743_format_change(struct v4l2_subdev *sd) 984 { 985 struct tc358743_state *state = to_state(sd); 986 struct v4l2_dv_timings timings; 987 const struct v4l2_event tc358743_ev_fmt = { 988 .type = V4L2_EVENT_SOURCE_CHANGE, 989 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, 990 }; 991 992 if (tc358743_get_detected_timings(sd, &timings)) { 993 enable_stream(sd, false); 994 995 v4l2_dbg(1, debug, sd, "%s: No signal\n", 996 __func__); 997 } else { 998 if (!v4l2_match_dv_timings(&state->timings, &timings, 0, false)) 999 enable_stream(sd, false); 1000 1001 if (debug) 1002 v4l2_print_dv_timings(sd->name, 1003 "tc358743_format_change: New format: ", 1004 &timings, false); 1005 } 1006 1007 if (sd->devnode) 1008 v4l2_subdev_notify_event(sd, &tc358743_ev_fmt); 1009 } 1010 1011 static void tc358743_init_interrupts(struct v4l2_subdev *sd) 1012 { 1013 u16 i; 1014 1015 /* clear interrupt status registers */ 1016 for (i = SYS_INT; i <= KEY_INT; i++) 1017 i2c_wr8(sd, i, 0xff); 1018 1019 i2c_wr16(sd, INTSTATUS, 0xffff); 1020 } 1021 1022 static void tc358743_enable_interrupts(struct v4l2_subdev *sd, 1023 bool cable_connected) 1024 { 1025 v4l2_dbg(2, debug, sd, "%s: cable connected = %d\n", __func__, 1026 cable_connected); 1027 1028 if (cable_connected) { 1029 i2c_wr8(sd, SYS_INTM, ~(MASK_M_DDC | MASK_M_DVI_DET | 1030 MASK_M_HDMI_DET) & 0xff); 1031 i2c_wr8(sd, CLK_INTM, ~MASK_M_IN_DE_CHG); 1032 i2c_wr8(sd, CBIT_INTM, ~(MASK_M_CBIT_FS | MASK_M_AF_LOCK | 1033 MASK_M_AF_UNLOCK) & 0xff); 1034 i2c_wr8(sd, AUDIO_INTM, ~MASK_M_BUFINIT_END); 1035 i2c_wr8(sd, MISC_INTM, ~MASK_M_SYNC_CHG); 1036 } else { 1037 i2c_wr8(sd, SYS_INTM, ~MASK_M_DDC & 0xff); 1038 i2c_wr8(sd, CLK_INTM, 0xff); 1039 i2c_wr8(sd, CBIT_INTM, 0xff); 1040 i2c_wr8(sd, AUDIO_INTM, 0xff); 1041 i2c_wr8(sd, MISC_INTM, 0xff); 1042 } 1043 } 1044 1045 static void tc358743_hdmi_audio_int_handler(struct v4l2_subdev *sd, 1046 bool *handled) 1047 { 1048 u8 audio_int_mask = i2c_rd8(sd, AUDIO_INTM); 1049 u8 audio_int = i2c_rd8(sd, AUDIO_INT) & ~audio_int_mask; 1050 1051 i2c_wr8(sd, AUDIO_INT, audio_int); 1052 1053 v4l2_dbg(3, debug, sd, "%s: AUDIO_INT = 0x%02x\n", __func__, audio_int); 1054 1055 tc358743_s_ctrl_audio_sampling_rate(sd); 1056 tc358743_s_ctrl_audio_present(sd); 1057 } 1058 1059 static void tc358743_csi_err_int_handler(struct v4l2_subdev *sd, bool *handled) 1060 { 1061 v4l2_err(sd, "%s: CSI_ERR = 0x%x\n", __func__, i2c_rd32(sd, CSI_ERR)); 1062 1063 i2c_wr32(sd, CSI_INT_CLR, MASK_ICRER); 1064 } 1065 1066 static void tc358743_hdmi_misc_int_handler(struct v4l2_subdev *sd, 1067 bool *handled) 1068 { 1069 u8 misc_int_mask = i2c_rd8(sd, MISC_INTM); 1070 u8 misc_int = i2c_rd8(sd, MISC_INT) & ~misc_int_mask; 1071 1072 i2c_wr8(sd, MISC_INT, misc_int); 1073 1074 v4l2_dbg(3, debug, sd, "%s: MISC_INT = 0x%02x\n", __func__, misc_int); 1075 1076 if (misc_int & MASK_I_SYNC_CHG) { 1077 /* Reset the HDMI PHY to try to trigger proper lock on the 1078 * incoming video format. Erase BKSV to prevent that old keys 1079 * are used when a new source is connected. */ 1080 if (no_sync(sd) || no_signal(sd)) { 1081 tc358743_reset_phy(sd); 1082 tc358743_erase_bksv(sd); 1083 } 1084 1085 tc358743_format_change(sd); 1086 1087 misc_int &= ~MASK_I_SYNC_CHG; 1088 if (handled) 1089 *handled = true; 1090 } 1091 1092 if (misc_int) { 1093 v4l2_err(sd, "%s: Unhandled MISC_INT interrupts: 0x%02x\n", 1094 __func__, misc_int); 1095 } 1096 } 1097 1098 static void tc358743_hdmi_cbit_int_handler(struct v4l2_subdev *sd, 1099 bool *handled) 1100 { 1101 u8 cbit_int_mask = i2c_rd8(sd, CBIT_INTM); 1102 u8 cbit_int = i2c_rd8(sd, CBIT_INT) & ~cbit_int_mask; 1103 1104 i2c_wr8(sd, CBIT_INT, cbit_int); 1105 1106 v4l2_dbg(3, debug, sd, "%s: CBIT_INT = 0x%02x\n", __func__, cbit_int); 1107 1108 if (cbit_int & MASK_I_CBIT_FS) { 1109 1110 v4l2_dbg(1, debug, sd, "%s: Audio sample rate changed\n", 1111 __func__); 1112 tc358743_s_ctrl_audio_sampling_rate(sd); 1113 1114 cbit_int &= ~MASK_I_CBIT_FS; 1115 if (handled) 1116 *handled = true; 1117 } 1118 1119 if (cbit_int & (MASK_I_AF_LOCK | MASK_I_AF_UNLOCK)) { 1120 1121 v4l2_dbg(1, debug, sd, "%s: Audio present changed\n", 1122 __func__); 1123 tc358743_s_ctrl_audio_present(sd); 1124 1125 cbit_int &= ~(MASK_I_AF_LOCK | MASK_I_AF_UNLOCK); 1126 if (handled) 1127 *handled = true; 1128 } 1129 1130 if (cbit_int) { 1131 v4l2_err(sd, "%s: Unhandled CBIT_INT interrupts: 0x%02x\n", 1132 __func__, cbit_int); 1133 } 1134 } 1135 1136 static void tc358743_hdmi_clk_int_handler(struct v4l2_subdev *sd, bool *handled) 1137 { 1138 u8 clk_int_mask = i2c_rd8(sd, CLK_INTM); 1139 u8 clk_int = i2c_rd8(sd, CLK_INT) & ~clk_int_mask; 1140 1141 /* Bit 7 and bit 6 are set even when they are masked */ 1142 i2c_wr8(sd, CLK_INT, clk_int | 0x80 | MASK_I_OUT_H_CHG); 1143 1144 v4l2_dbg(3, debug, sd, "%s: CLK_INT = 0x%02x\n", __func__, clk_int); 1145 1146 if (clk_int & (MASK_I_IN_DE_CHG)) { 1147 1148 v4l2_dbg(1, debug, sd, "%s: DE size or position has changed\n", 1149 __func__); 1150 1151 /* If the source switch to a new resolution with the same pixel 1152 * frequency as the existing (e.g. 1080p25 -> 720p50), the 1153 * I_SYNC_CHG interrupt is not always triggered, while the 1154 * I_IN_DE_CHG interrupt seems to work fine. Format change 1155 * notifications are only sent when the signal is stable to 1156 * reduce the number of notifications. */ 1157 if (!no_signal(sd) && !no_sync(sd)) 1158 tc358743_format_change(sd); 1159 1160 clk_int &= ~(MASK_I_IN_DE_CHG); 1161 if (handled) 1162 *handled = true; 1163 } 1164 1165 if (clk_int) { 1166 v4l2_err(sd, "%s: Unhandled CLK_INT interrupts: 0x%02x\n", 1167 __func__, clk_int); 1168 } 1169 } 1170 1171 static void tc358743_hdmi_sys_int_handler(struct v4l2_subdev *sd, bool *handled) 1172 { 1173 struct tc358743_state *state = to_state(sd); 1174 u8 sys_int_mask = i2c_rd8(sd, SYS_INTM); 1175 u8 sys_int = i2c_rd8(sd, SYS_INT) & ~sys_int_mask; 1176 1177 i2c_wr8(sd, SYS_INT, sys_int); 1178 1179 v4l2_dbg(3, debug, sd, "%s: SYS_INT = 0x%02x\n", __func__, sys_int); 1180 1181 if (sys_int & MASK_I_DDC) { 1182 bool tx_5v = tx_5v_power_present(sd); 1183 1184 v4l2_dbg(1, debug, sd, "%s: Tx 5V power present: %s\n", 1185 __func__, tx_5v ? "yes" : "no"); 1186 1187 if (tx_5v) { 1188 tc358743_enable_edid(sd); 1189 } else { 1190 tc358743_enable_interrupts(sd, false); 1191 tc358743_disable_edid(sd); 1192 memset(&state->timings, 0, sizeof(state->timings)); 1193 tc358743_erase_bksv(sd); 1194 tc358743_update_controls(sd); 1195 } 1196 1197 sys_int &= ~MASK_I_DDC; 1198 if (handled) 1199 *handled = true; 1200 } 1201 1202 if (sys_int & MASK_I_DVI) { 1203 v4l2_dbg(1, debug, sd, "%s: HDMI->DVI change detected\n", 1204 __func__); 1205 1206 /* Reset the HDMI PHY to try to trigger proper lock on the 1207 * incoming video format. Erase BKSV to prevent that old keys 1208 * are used when a new source is connected. */ 1209 if (no_sync(sd) || no_signal(sd)) { 1210 tc358743_reset_phy(sd); 1211 tc358743_erase_bksv(sd); 1212 } 1213 1214 sys_int &= ~MASK_I_DVI; 1215 if (handled) 1216 *handled = true; 1217 } 1218 1219 if (sys_int & MASK_I_HDMI) { 1220 v4l2_dbg(1, debug, sd, "%s: DVI->HDMI change detected\n", 1221 __func__); 1222 1223 /* Register is reset in DVI mode (REF_01, c. 6.6.41) */ 1224 i2c_wr8(sd, ANA_CTL, MASK_APPL_PCSX_NORMAL | MASK_ANALOG_ON); 1225 1226 sys_int &= ~MASK_I_HDMI; 1227 if (handled) 1228 *handled = true; 1229 } 1230 1231 if (sys_int) { 1232 v4l2_err(sd, "%s: Unhandled SYS_INT interrupts: 0x%02x\n", 1233 __func__, sys_int); 1234 } 1235 } 1236 1237 /* --------------- CORE OPS --------------- */ 1238 1239 static int tc358743_log_status(struct v4l2_subdev *sd) 1240 { 1241 struct tc358743_state *state = to_state(sd); 1242 struct v4l2_dv_timings timings; 1243 uint8_t hdmi_sys_status = i2c_rd8(sd, SYS_STATUS); 1244 uint16_t sysctl = i2c_rd16(sd, SYSCTL); 1245 u8 vi_status3 = i2c_rd8(sd, VI_STATUS3); 1246 const int deep_color_mode[4] = { 8, 10, 12, 16 }; 1247 static const char * const input_color_space[] = { 1248 "RGB", "YCbCr 601", "opRGB", "YCbCr 709", "NA (4)", 1249 "xvYCC 601", "NA(6)", "xvYCC 709", "NA(8)", "sYCC601", 1250 "NA(10)", "NA(11)", "NA(12)", "opYCC 601"}; 1251 1252 v4l2_info(sd, "-----Chip status-----\n"); 1253 v4l2_info(sd, "Chip ID: 0x%02x\n", 1254 (i2c_rd16(sd, CHIPID) & MASK_CHIPID) >> 8); 1255 v4l2_info(sd, "Chip revision: 0x%02x\n", 1256 i2c_rd16(sd, CHIPID) & MASK_REVID); 1257 v4l2_info(sd, "Reset: IR: %d, CEC: %d, CSI TX: %d, HDMI: %d\n", 1258 !!(sysctl & MASK_IRRST), 1259 !!(sysctl & MASK_CECRST), 1260 !!(sysctl & MASK_CTXRST), 1261 !!(sysctl & MASK_HDMIRST)); 1262 v4l2_info(sd, "Sleep mode: %s\n", sysctl & MASK_SLEEP ? "on" : "off"); 1263 v4l2_info(sd, "Cable detected (+5V power): %s\n", 1264 hdmi_sys_status & MASK_S_DDC5V ? "yes" : "no"); 1265 v4l2_info(sd, "DDC lines enabled: %s\n", 1266 (i2c_rd8(sd, EDID_MODE) & MASK_EDID_MODE_E_DDC) ? 1267 "yes" : "no"); 1268 v4l2_info(sd, "Hotplug enabled: %s\n", 1269 (i2c_rd8(sd, HPD_CTL) & MASK_HPD_OUT0) ? 1270 "yes" : "no"); 1271 v4l2_info(sd, "CEC enabled: %s\n", 1272 (i2c_rd16(sd, CECEN) & MASK_CECEN) ? "yes" : "no"); 1273 v4l2_info(sd, "-----Signal status-----\n"); 1274 v4l2_info(sd, "TMDS signal detected: %s\n", 1275 hdmi_sys_status & MASK_S_TMDS ? "yes" : "no"); 1276 v4l2_info(sd, "Stable sync signal: %s\n", 1277 hdmi_sys_status & MASK_S_SYNC ? "yes" : "no"); 1278 v4l2_info(sd, "PHY PLL locked: %s\n", 1279 hdmi_sys_status & MASK_S_PHY_PLL ? "yes" : "no"); 1280 v4l2_info(sd, "PHY DE detected: %s\n", 1281 hdmi_sys_status & MASK_S_PHY_SCDT ? "yes" : "no"); 1282 1283 if (tc358743_get_detected_timings(sd, &timings)) { 1284 v4l2_info(sd, "No video detected\n"); 1285 } else { 1286 v4l2_print_dv_timings(sd->name, "Detected format: ", &timings, 1287 true); 1288 } 1289 v4l2_print_dv_timings(sd->name, "Configured format: ", &state->timings, 1290 true); 1291 1292 v4l2_info(sd, "-----CSI-TX status-----\n"); 1293 v4l2_info(sd, "Lanes needed: %d\n", 1294 tc358743_num_csi_lanes_needed(sd)); 1295 v4l2_info(sd, "Lanes in use: %d\n", 1296 state->csi_lanes_in_use); 1297 v4l2_info(sd, "Waiting for particular sync signal: %s\n", 1298 (i2c_rd16(sd, CSI_STATUS) & MASK_S_WSYNC) ? 1299 "yes" : "no"); 1300 v4l2_info(sd, "Transmit mode: %s\n", 1301 (i2c_rd16(sd, CSI_STATUS) & MASK_S_TXACT) ? 1302 "yes" : "no"); 1303 v4l2_info(sd, "Receive mode: %s\n", 1304 (i2c_rd16(sd, CSI_STATUS) & MASK_S_RXACT) ? 1305 "yes" : "no"); 1306 v4l2_info(sd, "Stopped: %s\n", 1307 (i2c_rd16(sd, CSI_STATUS) & MASK_S_HLT) ? 1308 "yes" : "no"); 1309 v4l2_info(sd, "Color space: %s\n", 1310 state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16 ? 1311 "YCbCr 422 16-bit" : 1312 state->mbus_fmt_code == MEDIA_BUS_FMT_RGB888_1X24 ? 1313 "RGB 888 24-bit" : "Unsupported"); 1314 1315 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); 1316 v4l2_info(sd, "HDCP encrypted content: %s\n", 1317 hdmi_sys_status & MASK_S_HDCP ? "yes" : "no"); 1318 v4l2_info(sd, "Input color space: %s %s range\n", 1319 input_color_space[(vi_status3 & MASK_S_V_COLOR) >> 1], 1320 (vi_status3 & MASK_LIMITED) ? "limited" : "full"); 1321 if (!is_hdmi(sd)) 1322 return 0; 1323 v4l2_info(sd, "AV Mute: %s\n", hdmi_sys_status & MASK_S_AVMUTE ? "on" : 1324 "off"); 1325 v4l2_info(sd, "Deep color mode: %d-bits per channel\n", 1326 deep_color_mode[(i2c_rd8(sd, VI_STATUS1) & 1327 MASK_S_DEEPCOLOR) >> 2]); 1328 print_avi_infoframe(sd); 1329 1330 return 0; 1331 } 1332 1333 #ifdef CONFIG_VIDEO_ADV_DEBUG 1334 static void tc358743_print_register_map(struct v4l2_subdev *sd) 1335 { 1336 v4l2_info(sd, "0x0000-0x00FF: Global Control Register\n"); 1337 v4l2_info(sd, "0x0100-0x01FF: CSI2-TX PHY Register\n"); 1338 v4l2_info(sd, "0x0200-0x03FF: CSI2-TX PPI Register\n"); 1339 v4l2_info(sd, "0x0400-0x05FF: Reserved\n"); 1340 v4l2_info(sd, "0x0600-0x06FF: CEC Register\n"); 1341 v4l2_info(sd, "0x0700-0x84FF: Reserved\n"); 1342 v4l2_info(sd, "0x8500-0x85FF: HDMIRX System Control Register\n"); 1343 v4l2_info(sd, "0x8600-0x86FF: HDMIRX Audio Control Register\n"); 1344 v4l2_info(sd, "0x8700-0x87FF: HDMIRX InfoFrame packet data Register\n"); 1345 v4l2_info(sd, "0x8800-0x88FF: HDMIRX HDCP Port Register\n"); 1346 v4l2_info(sd, "0x8900-0x89FF: HDMIRX Video Output Port & 3D Register\n"); 1347 v4l2_info(sd, "0x8A00-0x8BFF: Reserved\n"); 1348 v4l2_info(sd, "0x8C00-0x8FFF: HDMIRX EDID-RAM (1024bytes)\n"); 1349 v4l2_info(sd, "0x9000-0x90FF: HDMIRX GBD Extraction Control\n"); 1350 v4l2_info(sd, "0x9100-0x92FF: HDMIRX GBD RAM read\n"); 1351 v4l2_info(sd, "0x9300- : Reserved\n"); 1352 } 1353 1354 static int tc358743_get_reg_size(u16 address) 1355 { 1356 /* REF_01 p. 66-72 */ 1357 if (address <= 0x00ff) 1358 return 2; 1359 else if ((address >= 0x0100) && (address <= 0x06FF)) 1360 return 4; 1361 else if ((address >= 0x0700) && (address <= 0x84ff)) 1362 return 2; 1363 else 1364 return 1; 1365 } 1366 1367 static int tc358743_g_register(struct v4l2_subdev *sd, 1368 struct v4l2_dbg_register *reg) 1369 { 1370 if (reg->reg > 0xffff) { 1371 tc358743_print_register_map(sd); 1372 return -EINVAL; 1373 } 1374 1375 reg->size = tc358743_get_reg_size(reg->reg); 1376 1377 reg->val = i2c_rdreg(sd, reg->reg, reg->size); 1378 1379 return 0; 1380 } 1381 1382 static int tc358743_s_register(struct v4l2_subdev *sd, 1383 const struct v4l2_dbg_register *reg) 1384 { 1385 if (reg->reg > 0xffff) { 1386 tc358743_print_register_map(sd); 1387 return -EINVAL; 1388 } 1389 1390 /* It should not be possible for the user to enable HDCP with a simple 1391 * v4l2-dbg command. 1392 * 1393 * DO NOT REMOVE THIS unless all other issues with HDCP have been 1394 * resolved. 1395 */ 1396 if (reg->reg == HDCP_MODE || 1397 reg->reg == HDCP_REG1 || 1398 reg->reg == HDCP_REG2 || 1399 reg->reg == HDCP_REG3 || 1400 reg->reg == BCAPS) 1401 return 0; 1402 1403 i2c_wrreg(sd, (u16)reg->reg, reg->val, 1404 tc358743_get_reg_size(reg->reg)); 1405 1406 return 0; 1407 } 1408 #endif 1409 1410 static int tc358743_isr(struct v4l2_subdev *sd, u32 status, bool *handled) 1411 { 1412 u16 intstatus = i2c_rd16(sd, INTSTATUS); 1413 1414 v4l2_dbg(1, debug, sd, "%s: IntStatus = 0x%04x\n", __func__, intstatus); 1415 1416 if (intstatus & MASK_HDMI_INT) { 1417 u8 hdmi_int0 = i2c_rd8(sd, HDMI_INT0); 1418 u8 hdmi_int1 = i2c_rd8(sd, HDMI_INT1); 1419 1420 if (hdmi_int0 & MASK_I_MISC) 1421 tc358743_hdmi_misc_int_handler(sd, handled); 1422 if (hdmi_int1 & MASK_I_CBIT) 1423 tc358743_hdmi_cbit_int_handler(sd, handled); 1424 if (hdmi_int1 & MASK_I_CLK) 1425 tc358743_hdmi_clk_int_handler(sd, handled); 1426 if (hdmi_int1 & MASK_I_SYS) 1427 tc358743_hdmi_sys_int_handler(sd, handled); 1428 if (hdmi_int1 & MASK_I_AUD) 1429 tc358743_hdmi_audio_int_handler(sd, handled); 1430 1431 i2c_wr16(sd, INTSTATUS, MASK_HDMI_INT); 1432 intstatus &= ~MASK_HDMI_INT; 1433 } 1434 1435 #ifdef CONFIG_VIDEO_TC358743_CEC 1436 if (intstatus & (MASK_CEC_RINT | MASK_CEC_TINT)) { 1437 tc358743_cec_handler(sd, intstatus, handled); 1438 i2c_wr16(sd, INTSTATUS, 1439 intstatus & (MASK_CEC_RINT | MASK_CEC_TINT)); 1440 intstatus &= ~(MASK_CEC_RINT | MASK_CEC_TINT); 1441 } 1442 #endif 1443 1444 if (intstatus & MASK_CSI_INT) { 1445 u32 csi_int = i2c_rd32(sd, CSI_INT); 1446 1447 if (csi_int & MASK_INTER) 1448 tc358743_csi_err_int_handler(sd, handled); 1449 1450 i2c_wr16(sd, INTSTATUS, MASK_CSI_INT); 1451 } 1452 1453 intstatus = i2c_rd16(sd, INTSTATUS); 1454 if (intstatus) { 1455 v4l2_dbg(1, debug, sd, 1456 "%s: Unhandled IntStatus interrupts: 0x%02x\n", 1457 __func__, intstatus); 1458 } 1459 1460 return 0; 1461 } 1462 1463 static irqreturn_t tc358743_irq_handler(int irq, void *dev_id) 1464 { 1465 struct tc358743_state *state = dev_id; 1466 bool handled = false; 1467 1468 tc358743_isr(&state->sd, 0, &handled); 1469 1470 return handled ? IRQ_HANDLED : IRQ_NONE; 1471 } 1472 1473 static void tc358743_irq_poll_timer(struct timer_list *t) 1474 { 1475 struct tc358743_state *state = from_timer(state, t, timer); 1476 unsigned int msecs; 1477 1478 schedule_work(&state->work_i2c_poll); 1479 /* 1480 * If CEC is present, then we need to poll more frequently, 1481 * otherwise we will miss CEC messages. 1482 */ 1483 msecs = state->cec_adap ? POLL_INTERVAL_CEC_MS : POLL_INTERVAL_MS; 1484 mod_timer(&state->timer, jiffies + msecs_to_jiffies(msecs)); 1485 } 1486 1487 static void tc358743_work_i2c_poll(struct work_struct *work) 1488 { 1489 struct tc358743_state *state = container_of(work, 1490 struct tc358743_state, work_i2c_poll); 1491 bool handled; 1492 1493 tc358743_isr(&state->sd, 0, &handled); 1494 } 1495 1496 static int tc358743_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh, 1497 struct v4l2_event_subscription *sub) 1498 { 1499 switch (sub->type) { 1500 case V4L2_EVENT_SOURCE_CHANGE: 1501 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub); 1502 case V4L2_EVENT_CTRL: 1503 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub); 1504 default: 1505 return -EINVAL; 1506 } 1507 } 1508 1509 /* --------------- VIDEO OPS --------------- */ 1510 1511 static int tc358743_g_input_status(struct v4l2_subdev *sd, u32 *status) 1512 { 1513 *status = 0; 1514 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0; 1515 *status |= no_sync(sd) ? V4L2_IN_ST_NO_SYNC : 0; 1516 1517 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status); 1518 1519 return 0; 1520 } 1521 1522 static int tc358743_s_dv_timings(struct v4l2_subdev *sd, 1523 struct v4l2_dv_timings *timings) 1524 { 1525 struct tc358743_state *state = to_state(sd); 1526 1527 if (!timings) 1528 return -EINVAL; 1529 1530 if (debug) 1531 v4l2_print_dv_timings(sd->name, "tc358743_s_dv_timings: ", 1532 timings, false); 1533 1534 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) { 1535 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__); 1536 return 0; 1537 } 1538 1539 if (!v4l2_valid_dv_timings(timings, 1540 &tc358743_timings_cap, NULL, NULL)) { 1541 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__); 1542 return -ERANGE; 1543 } 1544 1545 state->timings = *timings; 1546 1547 enable_stream(sd, false); 1548 tc358743_set_pll(sd); 1549 tc358743_set_csi(sd); 1550 1551 return 0; 1552 } 1553 1554 static int tc358743_g_dv_timings(struct v4l2_subdev *sd, 1555 struct v4l2_dv_timings *timings) 1556 { 1557 struct tc358743_state *state = to_state(sd); 1558 1559 *timings = state->timings; 1560 1561 return 0; 1562 } 1563 1564 static int tc358743_enum_dv_timings(struct v4l2_subdev *sd, 1565 struct v4l2_enum_dv_timings *timings) 1566 { 1567 if (timings->pad != 0) 1568 return -EINVAL; 1569 1570 return v4l2_enum_dv_timings_cap(timings, 1571 &tc358743_timings_cap, NULL, NULL); 1572 } 1573 1574 static int tc358743_query_dv_timings(struct v4l2_subdev *sd, 1575 struct v4l2_dv_timings *timings) 1576 { 1577 int ret; 1578 1579 ret = tc358743_get_detected_timings(sd, timings); 1580 if (ret) 1581 return ret; 1582 1583 if (debug) 1584 v4l2_print_dv_timings(sd->name, "tc358743_query_dv_timings: ", 1585 timings, false); 1586 1587 if (!v4l2_valid_dv_timings(timings, 1588 &tc358743_timings_cap, NULL, NULL)) { 1589 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__); 1590 return -ERANGE; 1591 } 1592 1593 return 0; 1594 } 1595 1596 static int tc358743_dv_timings_cap(struct v4l2_subdev *sd, 1597 struct v4l2_dv_timings_cap *cap) 1598 { 1599 if (cap->pad != 0) 1600 return -EINVAL; 1601 1602 *cap = tc358743_timings_cap; 1603 1604 return 0; 1605 } 1606 1607 static int tc358743_get_mbus_config(struct v4l2_subdev *sd, 1608 unsigned int pad, 1609 struct v4l2_mbus_config *cfg) 1610 { 1611 struct tc358743_state *state = to_state(sd); 1612 1613 cfg->type = V4L2_MBUS_CSI2_DPHY; 1614 1615 /* Support for non-continuous CSI-2 clock is missing in the driver */ 1616 cfg->flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK; 1617 1618 switch (state->csi_lanes_in_use) { 1619 case 1: 1620 cfg->flags |= V4L2_MBUS_CSI2_1_LANE; 1621 break; 1622 case 2: 1623 cfg->flags |= V4L2_MBUS_CSI2_2_LANE; 1624 break; 1625 case 3: 1626 cfg->flags |= V4L2_MBUS_CSI2_3_LANE; 1627 break; 1628 case 4: 1629 cfg->flags |= V4L2_MBUS_CSI2_4_LANE; 1630 break; 1631 default: 1632 return -EINVAL; 1633 } 1634 1635 return 0; 1636 } 1637 1638 static int tc358743_s_stream(struct v4l2_subdev *sd, int enable) 1639 { 1640 enable_stream(sd, enable); 1641 if (!enable) { 1642 /* Put all lanes in LP-11 state (STOPSTATE) */ 1643 tc358743_set_csi(sd); 1644 } 1645 1646 return 0; 1647 } 1648 1649 /* --------------- PAD OPS --------------- */ 1650 1651 static int tc358743_enum_mbus_code(struct v4l2_subdev *sd, 1652 struct v4l2_subdev_pad_config *cfg, 1653 struct v4l2_subdev_mbus_code_enum *code) 1654 { 1655 switch (code->index) { 1656 case 0: 1657 code->code = MEDIA_BUS_FMT_RGB888_1X24; 1658 break; 1659 case 1: 1660 code->code = MEDIA_BUS_FMT_UYVY8_1X16; 1661 break; 1662 default: 1663 return -EINVAL; 1664 } 1665 return 0; 1666 } 1667 1668 static int tc358743_get_fmt(struct v4l2_subdev *sd, 1669 struct v4l2_subdev_pad_config *cfg, 1670 struct v4l2_subdev_format *format) 1671 { 1672 struct tc358743_state *state = to_state(sd); 1673 u8 vi_rep = i2c_rd8(sd, VI_REP); 1674 1675 if (format->pad != 0) 1676 return -EINVAL; 1677 1678 format->format.code = state->mbus_fmt_code; 1679 format->format.width = state->timings.bt.width; 1680 format->format.height = state->timings.bt.height; 1681 format->format.field = V4L2_FIELD_NONE; 1682 1683 switch (vi_rep & MASK_VOUT_COLOR_SEL) { 1684 case MASK_VOUT_COLOR_RGB_FULL: 1685 case MASK_VOUT_COLOR_RGB_LIMITED: 1686 format->format.colorspace = V4L2_COLORSPACE_SRGB; 1687 break; 1688 case MASK_VOUT_COLOR_601_YCBCR_LIMITED: 1689 case MASK_VOUT_COLOR_601_YCBCR_FULL: 1690 format->format.colorspace = V4L2_COLORSPACE_SMPTE170M; 1691 break; 1692 case MASK_VOUT_COLOR_709_YCBCR_FULL: 1693 case MASK_VOUT_COLOR_709_YCBCR_LIMITED: 1694 format->format.colorspace = V4L2_COLORSPACE_REC709; 1695 break; 1696 default: 1697 format->format.colorspace = 0; 1698 break; 1699 } 1700 1701 return 0; 1702 } 1703 1704 static int tc358743_set_fmt(struct v4l2_subdev *sd, 1705 struct v4l2_subdev_pad_config *cfg, 1706 struct v4l2_subdev_format *format) 1707 { 1708 struct tc358743_state *state = to_state(sd); 1709 1710 u32 code = format->format.code; /* is overwritten by get_fmt */ 1711 int ret = tc358743_get_fmt(sd, cfg, format); 1712 1713 format->format.code = code; 1714 1715 if (ret) 1716 return ret; 1717 1718 switch (code) { 1719 case MEDIA_BUS_FMT_RGB888_1X24: 1720 case MEDIA_BUS_FMT_UYVY8_1X16: 1721 break; 1722 default: 1723 return -EINVAL; 1724 } 1725 1726 if (format->which == V4L2_SUBDEV_FORMAT_TRY) 1727 return 0; 1728 1729 state->mbus_fmt_code = format->format.code; 1730 1731 enable_stream(sd, false); 1732 tc358743_set_pll(sd); 1733 tc358743_set_csi(sd); 1734 tc358743_set_csi_color_space(sd); 1735 1736 return 0; 1737 } 1738 1739 static int tc358743_g_edid(struct v4l2_subdev *sd, 1740 struct v4l2_subdev_edid *edid) 1741 { 1742 struct tc358743_state *state = to_state(sd); 1743 1744 memset(edid->reserved, 0, sizeof(edid->reserved)); 1745 1746 if (edid->pad != 0) 1747 return -EINVAL; 1748 1749 if (edid->start_block == 0 && edid->blocks == 0) { 1750 edid->blocks = state->edid_blocks_written; 1751 return 0; 1752 } 1753 1754 if (state->edid_blocks_written == 0) 1755 return -ENODATA; 1756 1757 if (edid->start_block >= state->edid_blocks_written || 1758 edid->blocks == 0) 1759 return -EINVAL; 1760 1761 if (edid->start_block + edid->blocks > state->edid_blocks_written) 1762 edid->blocks = state->edid_blocks_written - edid->start_block; 1763 1764 i2c_rd(sd, EDID_RAM + (edid->start_block * EDID_BLOCK_SIZE), edid->edid, 1765 edid->blocks * EDID_BLOCK_SIZE); 1766 1767 return 0; 1768 } 1769 1770 static int tc358743_s_edid(struct v4l2_subdev *sd, 1771 struct v4l2_subdev_edid *edid) 1772 { 1773 struct tc358743_state *state = to_state(sd); 1774 u16 edid_len = edid->blocks * EDID_BLOCK_SIZE; 1775 u16 pa; 1776 int err; 1777 int i; 1778 1779 v4l2_dbg(2, debug, sd, "%s, pad %d, start block %d, blocks %d\n", 1780 __func__, edid->pad, edid->start_block, edid->blocks); 1781 1782 memset(edid->reserved, 0, sizeof(edid->reserved)); 1783 1784 if (edid->pad != 0) 1785 return -EINVAL; 1786 1787 if (edid->start_block != 0) 1788 return -EINVAL; 1789 1790 if (edid->blocks > EDID_NUM_BLOCKS_MAX) { 1791 edid->blocks = EDID_NUM_BLOCKS_MAX; 1792 return -E2BIG; 1793 } 1794 pa = cec_get_edid_phys_addr(edid->edid, edid->blocks * 128, NULL); 1795 err = v4l2_phys_addr_validate(pa, &pa, NULL); 1796 if (err) 1797 return err; 1798 1799 cec_phys_addr_invalidate(state->cec_adap); 1800 1801 tc358743_disable_edid(sd); 1802 1803 i2c_wr8(sd, EDID_LEN1, edid_len & 0xff); 1804 i2c_wr8(sd, EDID_LEN2, edid_len >> 8); 1805 1806 if (edid->blocks == 0) { 1807 state->edid_blocks_written = 0; 1808 return 0; 1809 } 1810 1811 for (i = 0; i < edid_len; i += EDID_BLOCK_SIZE) 1812 i2c_wr(sd, EDID_RAM + i, edid->edid + i, EDID_BLOCK_SIZE); 1813 1814 state->edid_blocks_written = edid->blocks; 1815 1816 cec_s_phys_addr(state->cec_adap, pa, false); 1817 1818 if (tx_5v_power_present(sd)) 1819 tc358743_enable_edid(sd); 1820 1821 return 0; 1822 } 1823 1824 /* -------------------------------------------------------------------------- */ 1825 1826 static const struct v4l2_subdev_core_ops tc358743_core_ops = { 1827 .log_status = tc358743_log_status, 1828 #ifdef CONFIG_VIDEO_ADV_DEBUG 1829 .g_register = tc358743_g_register, 1830 .s_register = tc358743_s_register, 1831 #endif 1832 .interrupt_service_routine = tc358743_isr, 1833 .subscribe_event = tc358743_subscribe_event, 1834 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 1835 }; 1836 1837 static const struct v4l2_subdev_video_ops tc358743_video_ops = { 1838 .g_input_status = tc358743_g_input_status, 1839 .s_dv_timings = tc358743_s_dv_timings, 1840 .g_dv_timings = tc358743_g_dv_timings, 1841 .query_dv_timings = tc358743_query_dv_timings, 1842 .s_stream = tc358743_s_stream, 1843 }; 1844 1845 static const struct v4l2_subdev_pad_ops tc358743_pad_ops = { 1846 .enum_mbus_code = tc358743_enum_mbus_code, 1847 .set_fmt = tc358743_set_fmt, 1848 .get_fmt = tc358743_get_fmt, 1849 .get_edid = tc358743_g_edid, 1850 .set_edid = tc358743_s_edid, 1851 .enum_dv_timings = tc358743_enum_dv_timings, 1852 .dv_timings_cap = tc358743_dv_timings_cap, 1853 .get_mbus_config = tc358743_get_mbus_config, 1854 }; 1855 1856 static const struct v4l2_subdev_ops tc358743_ops = { 1857 .core = &tc358743_core_ops, 1858 .video = &tc358743_video_ops, 1859 .pad = &tc358743_pad_ops, 1860 }; 1861 1862 /* --------------- CUSTOM CTRLS --------------- */ 1863 1864 static const struct v4l2_ctrl_config tc358743_ctrl_audio_sampling_rate = { 1865 .id = TC358743_CID_AUDIO_SAMPLING_RATE, 1866 .name = "Audio sampling rate", 1867 .type = V4L2_CTRL_TYPE_INTEGER, 1868 .min = 0, 1869 .max = 768000, 1870 .step = 1, 1871 .def = 0, 1872 .flags = V4L2_CTRL_FLAG_READ_ONLY, 1873 }; 1874 1875 static const struct v4l2_ctrl_config tc358743_ctrl_audio_present = { 1876 .id = TC358743_CID_AUDIO_PRESENT, 1877 .name = "Audio present", 1878 .type = V4L2_CTRL_TYPE_BOOLEAN, 1879 .min = 0, 1880 .max = 1, 1881 .step = 1, 1882 .def = 0, 1883 .flags = V4L2_CTRL_FLAG_READ_ONLY, 1884 }; 1885 1886 /* --------------- PROBE / REMOVE --------------- */ 1887 1888 #ifdef CONFIG_OF 1889 static void tc358743_gpio_reset(struct tc358743_state *state) 1890 { 1891 usleep_range(5000, 10000); 1892 gpiod_set_value(state->reset_gpio, 1); 1893 usleep_range(1000, 2000); 1894 gpiod_set_value(state->reset_gpio, 0); 1895 msleep(20); 1896 } 1897 1898 static int tc358743_probe_of(struct tc358743_state *state) 1899 { 1900 struct device *dev = &state->i2c_client->dev; 1901 struct v4l2_fwnode_endpoint endpoint = { .bus_type = 0 }; 1902 struct device_node *ep; 1903 struct clk *refclk; 1904 u32 bps_pr_lane; 1905 int ret; 1906 1907 refclk = devm_clk_get(dev, "refclk"); 1908 if (IS_ERR(refclk)) { 1909 if (PTR_ERR(refclk) != -EPROBE_DEFER) 1910 dev_err(dev, "failed to get refclk: %ld\n", 1911 PTR_ERR(refclk)); 1912 return PTR_ERR(refclk); 1913 } 1914 1915 ep = of_graph_get_next_endpoint(dev->of_node, NULL); 1916 if (!ep) { 1917 dev_err(dev, "missing endpoint node\n"); 1918 return -EINVAL; 1919 } 1920 1921 ret = v4l2_fwnode_endpoint_alloc_parse(of_fwnode_handle(ep), &endpoint); 1922 if (ret) { 1923 dev_err(dev, "failed to parse endpoint\n"); 1924 goto put_node; 1925 } 1926 1927 if (endpoint.bus_type != V4L2_MBUS_CSI2_DPHY || 1928 endpoint.bus.mipi_csi2.num_data_lanes == 0 || 1929 endpoint.nr_of_link_frequencies == 0) { 1930 dev_err(dev, "missing CSI-2 properties in endpoint\n"); 1931 ret = -EINVAL; 1932 goto free_endpoint; 1933 } 1934 1935 if (endpoint.bus.mipi_csi2.num_data_lanes > 4) { 1936 dev_err(dev, "invalid number of lanes\n"); 1937 ret = -EINVAL; 1938 goto free_endpoint; 1939 } 1940 1941 state->bus = endpoint.bus.mipi_csi2; 1942 1943 ret = clk_prepare_enable(refclk); 1944 if (ret) { 1945 dev_err(dev, "Failed! to enable clock\n"); 1946 goto free_endpoint; 1947 } 1948 1949 state->pdata.refclk_hz = clk_get_rate(refclk); 1950 state->pdata.ddc5v_delay = DDC5V_DELAY_100_MS; 1951 state->pdata.enable_hdcp = false; 1952 /* A FIFO level of 16 should be enough for 2-lane 720p60 at 594 MHz. */ 1953 state->pdata.fifo_level = 16; 1954 /* 1955 * The PLL input clock is obtained by dividing refclk by pll_prd. 1956 * It must be between 6 MHz and 40 MHz, lower frequency is better. 1957 */ 1958 switch (state->pdata.refclk_hz) { 1959 case 26000000: 1960 case 27000000: 1961 case 42000000: 1962 state->pdata.pll_prd = state->pdata.refclk_hz / 6000000; 1963 break; 1964 default: 1965 dev_err(dev, "unsupported refclk rate: %u Hz\n", 1966 state->pdata.refclk_hz); 1967 goto disable_clk; 1968 } 1969 1970 /* 1971 * The CSI bps per lane must be between 62.5 Mbps and 1 Gbps. 1972 * The default is 594 Mbps for 4-lane 1080p60 or 2-lane 720p60. 1973 */ 1974 bps_pr_lane = 2 * endpoint.link_frequencies[0]; 1975 if (bps_pr_lane < 62500000U || bps_pr_lane > 1000000000U) { 1976 dev_err(dev, "unsupported bps per lane: %u bps\n", bps_pr_lane); 1977 goto disable_clk; 1978 } 1979 1980 /* The CSI speed per lane is refclk / pll_prd * pll_fbd */ 1981 state->pdata.pll_fbd = bps_pr_lane / 1982 state->pdata.refclk_hz * state->pdata.pll_prd; 1983 1984 /* 1985 * FIXME: These timings are from REF_02 for 594 Mbps per lane (297 MHz 1986 * link frequency). In principle it should be possible to calculate 1987 * them based on link frequency and resolution. 1988 */ 1989 if (bps_pr_lane != 594000000U) 1990 dev_warn(dev, "untested bps per lane: %u bps\n", bps_pr_lane); 1991 state->pdata.lineinitcnt = 0xe80; 1992 state->pdata.lptxtimecnt = 0x003; 1993 /* tclk-preparecnt: 3, tclk-zerocnt: 20 */ 1994 state->pdata.tclk_headercnt = 0x1403; 1995 state->pdata.tclk_trailcnt = 0x00; 1996 /* ths-preparecnt: 3, ths-zerocnt: 1 */ 1997 state->pdata.ths_headercnt = 0x0103; 1998 state->pdata.twakeup = 0x4882; 1999 state->pdata.tclk_postcnt = 0x008; 2000 state->pdata.ths_trailcnt = 0x2; 2001 state->pdata.hstxvregcnt = 0; 2002 2003 state->reset_gpio = devm_gpiod_get_optional(dev, "reset", 2004 GPIOD_OUT_LOW); 2005 if (IS_ERR(state->reset_gpio)) { 2006 dev_err(dev, "failed to get reset gpio\n"); 2007 ret = PTR_ERR(state->reset_gpio); 2008 goto disable_clk; 2009 } 2010 2011 if (state->reset_gpio) 2012 tc358743_gpio_reset(state); 2013 2014 ret = 0; 2015 goto free_endpoint; 2016 2017 disable_clk: 2018 clk_disable_unprepare(refclk); 2019 free_endpoint: 2020 v4l2_fwnode_endpoint_free(&endpoint); 2021 put_node: 2022 of_node_put(ep); 2023 return ret; 2024 } 2025 #else 2026 static inline int tc358743_probe_of(struct tc358743_state *state) 2027 { 2028 return -ENODEV; 2029 } 2030 #endif 2031 2032 static int tc358743_probe(struct i2c_client *client) 2033 { 2034 static struct v4l2_dv_timings default_timing = 2035 V4L2_DV_BT_CEA_640X480P59_94; 2036 struct tc358743_state *state; 2037 struct tc358743_platform_data *pdata = client->dev.platform_data; 2038 struct v4l2_subdev *sd; 2039 u16 irq_mask = MASK_HDMI_MSK | MASK_CSI_MSK; 2040 int err; 2041 2042 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 2043 return -EIO; 2044 v4l_dbg(1, debug, client, "chip found @ 0x%x (%s)\n", 2045 client->addr << 1, client->adapter->name); 2046 2047 state = devm_kzalloc(&client->dev, sizeof(struct tc358743_state), 2048 GFP_KERNEL); 2049 if (!state) 2050 return -ENOMEM; 2051 2052 state->i2c_client = client; 2053 2054 /* platform data */ 2055 if (pdata) { 2056 state->pdata = *pdata; 2057 state->bus.flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK; 2058 } else { 2059 err = tc358743_probe_of(state); 2060 if (err == -ENODEV) 2061 v4l_err(client, "No platform data!\n"); 2062 if (err) 2063 return err; 2064 } 2065 2066 sd = &state->sd; 2067 v4l2_i2c_subdev_init(sd, client, &tc358743_ops); 2068 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; 2069 2070 /* i2c access */ 2071 if ((i2c_rd16(sd, CHIPID) & MASK_CHIPID) != 0) { 2072 v4l2_info(sd, "not a TC358743 on address 0x%x\n", 2073 client->addr << 1); 2074 return -ENODEV; 2075 } 2076 2077 /* control handlers */ 2078 v4l2_ctrl_handler_init(&state->hdl, 3); 2079 2080 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(&state->hdl, NULL, 2081 V4L2_CID_DV_RX_POWER_PRESENT, 0, 1, 0, 0); 2082 2083 /* custom controls */ 2084 state->audio_sampling_rate_ctrl = v4l2_ctrl_new_custom(&state->hdl, 2085 &tc358743_ctrl_audio_sampling_rate, NULL); 2086 2087 state->audio_present_ctrl = v4l2_ctrl_new_custom(&state->hdl, 2088 &tc358743_ctrl_audio_present, NULL); 2089 2090 sd->ctrl_handler = &state->hdl; 2091 if (state->hdl.error) { 2092 err = state->hdl.error; 2093 goto err_hdl; 2094 } 2095 2096 if (tc358743_update_controls(sd)) { 2097 err = -ENODEV; 2098 goto err_hdl; 2099 } 2100 2101 state->pad.flags = MEDIA_PAD_FL_SOURCE; 2102 sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; 2103 err = media_entity_pads_init(&sd->entity, 1, &state->pad); 2104 if (err < 0) 2105 goto err_hdl; 2106 2107 state->mbus_fmt_code = MEDIA_BUS_FMT_RGB888_1X24; 2108 2109 sd->dev = &client->dev; 2110 err = v4l2_async_register_subdev(sd); 2111 if (err < 0) 2112 goto err_hdl; 2113 2114 mutex_init(&state->confctl_mutex); 2115 2116 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, 2117 tc358743_delayed_work_enable_hotplug); 2118 2119 #ifdef CONFIG_VIDEO_TC358743_CEC 2120 state->cec_adap = cec_allocate_adapter(&tc358743_cec_adap_ops, 2121 state, dev_name(&client->dev), 2122 CEC_CAP_DEFAULTS | CEC_CAP_MONITOR_ALL, CEC_MAX_LOG_ADDRS); 2123 if (IS_ERR(state->cec_adap)) { 2124 err = PTR_ERR(state->cec_adap); 2125 goto err_hdl; 2126 } 2127 irq_mask |= MASK_CEC_RMSK | MASK_CEC_TMSK; 2128 #endif 2129 2130 tc358743_initial_setup(sd); 2131 2132 tc358743_s_dv_timings(sd, &default_timing); 2133 2134 tc358743_set_csi_color_space(sd); 2135 2136 tc358743_init_interrupts(sd); 2137 2138 if (state->i2c_client->irq) { 2139 err = devm_request_threaded_irq(&client->dev, 2140 state->i2c_client->irq, 2141 NULL, tc358743_irq_handler, 2142 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 2143 "tc358743", state); 2144 if (err) 2145 goto err_work_queues; 2146 } else { 2147 INIT_WORK(&state->work_i2c_poll, 2148 tc358743_work_i2c_poll); 2149 timer_setup(&state->timer, tc358743_irq_poll_timer, 0); 2150 state->timer.expires = jiffies + 2151 msecs_to_jiffies(POLL_INTERVAL_MS); 2152 add_timer(&state->timer); 2153 } 2154 2155 err = cec_register_adapter(state->cec_adap, &client->dev); 2156 if (err < 0) { 2157 pr_err("%s: failed to register the cec device\n", __func__); 2158 cec_delete_adapter(state->cec_adap); 2159 state->cec_adap = NULL; 2160 goto err_work_queues; 2161 } 2162 2163 tc358743_enable_interrupts(sd, tx_5v_power_present(sd)); 2164 i2c_wr16(sd, INTMASK, ~irq_mask); 2165 2166 err = v4l2_ctrl_handler_setup(sd->ctrl_handler); 2167 if (err) 2168 goto err_work_queues; 2169 2170 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, 2171 client->addr << 1, client->adapter->name); 2172 2173 return 0; 2174 2175 err_work_queues: 2176 cec_unregister_adapter(state->cec_adap); 2177 if (!state->i2c_client->irq) 2178 flush_work(&state->work_i2c_poll); 2179 cancel_delayed_work(&state->delayed_work_enable_hotplug); 2180 mutex_destroy(&state->confctl_mutex); 2181 err_hdl: 2182 media_entity_cleanup(&sd->entity); 2183 v4l2_ctrl_handler_free(&state->hdl); 2184 return err; 2185 } 2186 2187 static int tc358743_remove(struct i2c_client *client) 2188 { 2189 struct v4l2_subdev *sd = i2c_get_clientdata(client); 2190 struct tc358743_state *state = to_state(sd); 2191 2192 if (!state->i2c_client->irq) { 2193 del_timer_sync(&state->timer); 2194 flush_work(&state->work_i2c_poll); 2195 } 2196 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); 2197 cec_unregister_adapter(state->cec_adap); 2198 v4l2_async_unregister_subdev(sd); 2199 v4l2_device_unregister_subdev(sd); 2200 mutex_destroy(&state->confctl_mutex); 2201 media_entity_cleanup(&sd->entity); 2202 v4l2_ctrl_handler_free(&state->hdl); 2203 2204 return 0; 2205 } 2206 2207 static const struct i2c_device_id tc358743_id[] = { 2208 {"tc358743", 0}, 2209 {} 2210 }; 2211 2212 MODULE_DEVICE_TABLE(i2c, tc358743_id); 2213 2214 #if IS_ENABLED(CONFIG_OF) 2215 static const struct of_device_id tc358743_of_match[] = { 2216 { .compatible = "toshiba,tc358743" }, 2217 {}, 2218 }; 2219 MODULE_DEVICE_TABLE(of, tc358743_of_match); 2220 #endif 2221 2222 static struct i2c_driver tc358743_driver = { 2223 .driver = { 2224 .name = "tc358743", 2225 .of_match_table = of_match_ptr(tc358743_of_match), 2226 }, 2227 .probe_new = tc358743_probe, 2228 .remove = tc358743_remove, 2229 .id_table = tc358743_id, 2230 }; 2231 2232 module_i2c_driver(tc358743_driver); 2233