1 /* 2 * tc358743 - Toshiba HDMI to CSI-2 bridge 3 * 4 * Copyright 2015 Cisco Systems, Inc. and/or its affiliates. All rights 5 * reserved. 6 * 7 * This program is free software; you may redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; version 2 of the License. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 12 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 13 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 15 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 16 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 17 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 18 * SOFTWARE. 19 * 20 */ 21 22 /* 23 * References (c = chapter, p = page): 24 * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60 25 * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls 26 */ 27 28 #include <linux/kernel.h> 29 #include <linux/module.h> 30 #include <linux/slab.h> 31 #include <linux/i2c.h> 32 #include <linux/clk.h> 33 #include <linux/delay.h> 34 #include <linux/gpio/consumer.h> 35 #include <linux/interrupt.h> 36 #include <linux/videodev2.h> 37 #include <linux/workqueue.h> 38 #include <linux/v4l2-dv-timings.h> 39 #include <linux/hdmi.h> 40 #include <media/v4l2-dv-timings.h> 41 #include <media/v4l2-device.h> 42 #include <media/v4l2-ctrls.h> 43 #include <media/v4l2-event.h> 44 #include <media/v4l2-of.h> 45 #include <media/tc358743.h> 46 47 #include "tc358743_regs.h" 48 49 static int debug; 50 module_param(debug, int, 0644); 51 MODULE_PARM_DESC(debug, "debug level (0-3)"); 52 53 MODULE_DESCRIPTION("Toshiba TC358743 HDMI to CSI-2 bridge driver"); 54 MODULE_AUTHOR("Ramakrishnan Muthukrishnan <ram@rkrishnan.org>"); 55 MODULE_AUTHOR("Mikhail Khelik <mkhelik@cisco.com>"); 56 MODULE_AUTHOR("Mats Randgaard <matrandg@cisco.com>"); 57 MODULE_LICENSE("GPL"); 58 59 #define EDID_NUM_BLOCKS_MAX 8 60 #define EDID_BLOCK_SIZE 128 61 62 static const struct v4l2_dv_timings_cap tc358743_timings_cap = { 63 .type = V4L2_DV_BT_656_1120, 64 /* keep this initialization for compatibility with GCC < 4.4.6 */ 65 .reserved = { 0 }, 66 /* Pixel clock from REF_01 p. 20. Min/max height/width are unknown */ 67 V4L2_INIT_BT_TIMINGS(1, 10000, 1, 10000, 0, 165000000, 68 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 69 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, 70 V4L2_DV_BT_CAP_PROGRESSIVE | 71 V4L2_DV_BT_CAP_REDUCED_BLANKING | 72 V4L2_DV_BT_CAP_CUSTOM) 73 }; 74 75 struct tc358743_state { 76 struct tc358743_platform_data pdata; 77 struct v4l2_of_bus_mipi_csi2 bus; 78 struct v4l2_subdev sd; 79 struct media_pad pad; 80 struct v4l2_ctrl_handler hdl; 81 struct i2c_client *i2c_client; 82 /* CONFCTL is modified in ops and tc358743_hdmi_sys_int_handler */ 83 struct mutex confctl_mutex; 84 85 /* controls */ 86 struct v4l2_ctrl *detect_tx_5v_ctrl; 87 struct v4l2_ctrl *audio_sampling_rate_ctrl; 88 struct v4l2_ctrl *audio_present_ctrl; 89 90 /* work queues */ 91 struct workqueue_struct *work_queues; 92 struct delayed_work delayed_work_enable_hotplug; 93 94 /* edid */ 95 u8 edid_blocks_written; 96 97 struct v4l2_dv_timings timings; 98 u32 mbus_fmt_code; 99 100 struct gpio_desc *reset_gpio; 101 }; 102 103 static void tc358743_enable_interrupts(struct v4l2_subdev *sd, 104 bool cable_connected); 105 static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd); 106 107 static inline struct tc358743_state *to_state(struct v4l2_subdev *sd) 108 { 109 return container_of(sd, struct tc358743_state, sd); 110 } 111 112 /* --------------- I2C --------------- */ 113 114 static void i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n) 115 { 116 struct tc358743_state *state = to_state(sd); 117 struct i2c_client *client = state->i2c_client; 118 int err; 119 u8 buf[2] = { reg >> 8, reg & 0xff }; 120 struct i2c_msg msgs[] = { 121 { 122 .addr = client->addr, 123 .flags = 0, 124 .len = 2, 125 .buf = buf, 126 }, 127 { 128 .addr = client->addr, 129 .flags = I2C_M_RD, 130 .len = n, 131 .buf = values, 132 }, 133 }; 134 135 err = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); 136 if (err != ARRAY_SIZE(msgs)) { 137 v4l2_err(sd, "%s: reading register 0x%x from 0x%x failed\n", 138 __func__, reg, client->addr); 139 } 140 } 141 142 static void i2c_wr(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n) 143 { 144 struct tc358743_state *state = to_state(sd); 145 struct i2c_client *client = state->i2c_client; 146 int err, i; 147 struct i2c_msg msg; 148 u8 data[2 + n]; 149 150 msg.addr = client->addr; 151 msg.buf = data; 152 msg.len = 2 + n; 153 msg.flags = 0; 154 155 data[0] = reg >> 8; 156 data[1] = reg & 0xff; 157 158 for (i = 0; i < n; i++) 159 data[2 + i] = values[i]; 160 161 err = i2c_transfer(client->adapter, &msg, 1); 162 if (err != 1) { 163 v4l2_err(sd, "%s: writing register 0x%x from 0x%x failed\n", 164 __func__, reg, client->addr); 165 return; 166 } 167 168 if (debug < 3) 169 return; 170 171 switch (n) { 172 case 1: 173 v4l2_info(sd, "I2C write 0x%04x = 0x%02x", 174 reg, data[2]); 175 break; 176 case 2: 177 v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x", 178 reg, data[3], data[2]); 179 break; 180 case 4: 181 v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x%02x%02x", 182 reg, data[5], data[4], data[3], data[2]); 183 break; 184 default: 185 v4l2_info(sd, "I2C write %d bytes from address 0x%04x\n", 186 n, reg); 187 } 188 } 189 190 static u8 i2c_rd8(struct v4l2_subdev *sd, u16 reg) 191 { 192 u8 val; 193 194 i2c_rd(sd, reg, &val, 1); 195 196 return val; 197 } 198 199 static void i2c_wr8(struct v4l2_subdev *sd, u16 reg, u8 val) 200 { 201 i2c_wr(sd, reg, &val, 1); 202 } 203 204 static void i2c_wr8_and_or(struct v4l2_subdev *sd, u16 reg, 205 u8 mask, u8 val) 206 { 207 i2c_wr8(sd, reg, (i2c_rd8(sd, reg) & mask) | val); 208 } 209 210 static u16 i2c_rd16(struct v4l2_subdev *sd, u16 reg) 211 { 212 u16 val; 213 214 i2c_rd(sd, reg, (u8 *)&val, 2); 215 216 return val; 217 } 218 219 static void i2c_wr16(struct v4l2_subdev *sd, u16 reg, u16 val) 220 { 221 i2c_wr(sd, reg, (u8 *)&val, 2); 222 } 223 224 static void i2c_wr16_and_or(struct v4l2_subdev *sd, u16 reg, u16 mask, u16 val) 225 { 226 i2c_wr16(sd, reg, (i2c_rd16(sd, reg) & mask) | val); 227 } 228 229 static u32 i2c_rd32(struct v4l2_subdev *sd, u16 reg) 230 { 231 u32 val; 232 233 i2c_rd(sd, reg, (u8 *)&val, 4); 234 235 return val; 236 } 237 238 static void i2c_wr32(struct v4l2_subdev *sd, u16 reg, u32 val) 239 { 240 i2c_wr(sd, reg, (u8 *)&val, 4); 241 } 242 243 /* --------------- STATUS --------------- */ 244 245 static inline bool is_hdmi(struct v4l2_subdev *sd) 246 { 247 return i2c_rd8(sd, SYS_STATUS) & MASK_S_HDMI; 248 } 249 250 static inline bool tx_5v_power_present(struct v4l2_subdev *sd) 251 { 252 return i2c_rd8(sd, SYS_STATUS) & MASK_S_DDC5V; 253 } 254 255 static inline bool no_signal(struct v4l2_subdev *sd) 256 { 257 return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_TMDS); 258 } 259 260 static inline bool no_sync(struct v4l2_subdev *sd) 261 { 262 return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_SYNC); 263 } 264 265 static inline bool audio_present(struct v4l2_subdev *sd) 266 { 267 return i2c_rd8(sd, AU_STATUS0) & MASK_S_A_SAMPLE; 268 } 269 270 static int get_audio_sampling_rate(struct v4l2_subdev *sd) 271 { 272 static const int code_to_rate[] = { 273 44100, 0, 48000, 32000, 22050, 384000, 24000, 352800, 274 88200, 768000, 96000, 705600, 176400, 0, 192000, 0 275 }; 276 277 /* Register FS_SET is not cleared when the cable is disconnected */ 278 if (no_signal(sd)) 279 return 0; 280 281 return code_to_rate[i2c_rd8(sd, FS_SET) & MASK_FS]; 282 } 283 284 static unsigned tc358743_num_csi_lanes_in_use(struct v4l2_subdev *sd) 285 { 286 return ((i2c_rd32(sd, CSI_CONTROL) & MASK_NOL) >> 1) + 1; 287 } 288 289 /* --------------- TIMINGS --------------- */ 290 291 static inline unsigned fps(const struct v4l2_bt_timings *t) 292 { 293 if (!V4L2_DV_BT_FRAME_HEIGHT(t) || !V4L2_DV_BT_FRAME_WIDTH(t)) 294 return 0; 295 296 return DIV_ROUND_CLOSEST((unsigned)t->pixelclock, 297 V4L2_DV_BT_FRAME_HEIGHT(t) * V4L2_DV_BT_FRAME_WIDTH(t)); 298 } 299 300 static int tc358743_get_detected_timings(struct v4l2_subdev *sd, 301 struct v4l2_dv_timings *timings) 302 { 303 struct v4l2_bt_timings *bt = &timings->bt; 304 unsigned width, height, frame_width, frame_height, frame_interval, fps; 305 306 memset(timings, 0, sizeof(struct v4l2_dv_timings)); 307 308 if (no_signal(sd)) { 309 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); 310 return -ENOLINK; 311 } 312 if (no_sync(sd)) { 313 v4l2_dbg(1, debug, sd, "%s: no sync on signal\n", __func__); 314 return -ENOLCK; 315 } 316 317 timings->type = V4L2_DV_BT_656_1120; 318 bt->interlaced = i2c_rd8(sd, VI_STATUS1) & MASK_S_V_INTERLACE ? 319 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; 320 321 width = ((i2c_rd8(sd, DE_WIDTH_H_HI) & 0x1f) << 8) + 322 i2c_rd8(sd, DE_WIDTH_H_LO); 323 height = ((i2c_rd8(sd, DE_WIDTH_V_HI) & 0x1f) << 8) + 324 i2c_rd8(sd, DE_WIDTH_V_LO); 325 frame_width = ((i2c_rd8(sd, H_SIZE_HI) & 0x1f) << 8) + 326 i2c_rd8(sd, H_SIZE_LO); 327 frame_height = (((i2c_rd8(sd, V_SIZE_HI) & 0x3f) << 8) + 328 i2c_rd8(sd, V_SIZE_LO)) / 2; 329 /* frame interval in milliseconds * 10 330 * Require SYS_FREQ0 and SYS_FREQ1 are precisely set */ 331 frame_interval = ((i2c_rd8(sd, FV_CNT_HI) & 0x3) << 8) + 332 i2c_rd8(sd, FV_CNT_LO); 333 fps = (frame_interval > 0) ? 334 DIV_ROUND_CLOSEST(10000, frame_interval) : 0; 335 336 bt->width = width; 337 bt->height = height; 338 bt->vsync = frame_height - height; 339 bt->hsync = frame_width - width; 340 bt->pixelclock = frame_width * frame_height * fps; 341 if (bt->interlaced == V4L2_DV_INTERLACED) { 342 bt->height *= 2; 343 bt->il_vsync = bt->vsync + 1; 344 bt->pixelclock /= 2; 345 } 346 347 return 0; 348 } 349 350 /* --------------- HOTPLUG / HDCP / EDID --------------- */ 351 352 static void tc358743_delayed_work_enable_hotplug(struct work_struct *work) 353 { 354 struct delayed_work *dwork = to_delayed_work(work); 355 struct tc358743_state *state = container_of(dwork, 356 struct tc358743_state, delayed_work_enable_hotplug); 357 struct v4l2_subdev *sd = &state->sd; 358 359 v4l2_dbg(2, debug, sd, "%s:\n", __func__); 360 361 i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, MASK_HPD_OUT0); 362 } 363 364 static void tc358743_set_hdmi_hdcp(struct v4l2_subdev *sd, bool enable) 365 { 366 v4l2_dbg(2, debug, sd, "%s: %s\n", __func__, enable ? 367 "enable" : "disable"); 368 369 i2c_wr8_and_or(sd, HDCP_REG1, 370 ~(MASK_AUTH_UNAUTH_SEL | MASK_AUTH_UNAUTH), 371 MASK_AUTH_UNAUTH_SEL_16_FRAMES | MASK_AUTH_UNAUTH_AUTO); 372 373 i2c_wr8_and_or(sd, HDCP_REG2, ~MASK_AUTO_P3_RESET, 374 SET_AUTO_P3_RESET_FRAMES(0x0f)); 375 376 /* HDCP is disabled by configuring the receiver as HDCP repeater. The 377 * repeater mode require software support to work, so HDCP 378 * authentication will fail. 379 */ 380 i2c_wr8_and_or(sd, HDCP_REG3, ~KEY_RD_CMD, enable ? KEY_RD_CMD : 0); 381 i2c_wr8_and_or(sd, HDCP_MODE, ~(MASK_AUTO_CLR | MASK_MODE_RST_TN), 382 enable ? (MASK_AUTO_CLR | MASK_MODE_RST_TN) : 0); 383 384 /* Apple MacBook Pro gen.8 has a bug that makes it freeze every fifth 385 * second when HDCP is disabled, but the MAX_EXCED bit is handled 386 * correctly and HDCP is disabled on the HDMI output. 387 */ 388 i2c_wr8_and_or(sd, BSTATUS1, ~MASK_MAX_EXCED, 389 enable ? 0 : MASK_MAX_EXCED); 390 i2c_wr8_and_or(sd, BCAPS, ~(MASK_REPEATER | MASK_READY), 391 enable ? 0 : MASK_REPEATER | MASK_READY); 392 } 393 394 static void tc358743_disable_edid(struct v4l2_subdev *sd) 395 { 396 struct tc358743_state *state = to_state(sd); 397 398 v4l2_dbg(2, debug, sd, "%s:\n", __func__); 399 400 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); 401 402 /* DDC access to EDID is also disabled when hotplug is disabled. See 403 * register DDC_CTL */ 404 i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, 0x0); 405 } 406 407 static void tc358743_enable_edid(struct v4l2_subdev *sd) 408 { 409 struct tc358743_state *state = to_state(sd); 410 411 if (state->edid_blocks_written == 0) { 412 v4l2_dbg(2, debug, sd, "%s: no EDID -> no hotplug\n", __func__); 413 return; 414 } 415 416 v4l2_dbg(2, debug, sd, "%s:\n", __func__); 417 418 /* Enable hotplug after 100 ms. DDC access to EDID is also enabled when 419 * hotplug is enabled. See register DDC_CTL */ 420 queue_delayed_work(state->work_queues, 421 &state->delayed_work_enable_hotplug, HZ / 10); 422 423 tc358743_enable_interrupts(sd, true); 424 tc358743_s_ctrl_detect_tx_5v(sd); 425 } 426 427 static void tc358743_erase_bksv(struct v4l2_subdev *sd) 428 { 429 int i; 430 431 for (i = 0; i < 5; i++) 432 i2c_wr8(sd, BKSV + i, 0); 433 } 434 435 /* --------------- AVI infoframe --------------- */ 436 437 static void print_avi_infoframe(struct v4l2_subdev *sd) 438 { 439 struct i2c_client *client = v4l2_get_subdevdata(sd); 440 struct device *dev = &client->dev; 441 union hdmi_infoframe frame; 442 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)]; 443 444 if (!is_hdmi(sd)) { 445 v4l2_info(sd, "DVI-D signal - AVI infoframe not supported\n"); 446 return; 447 } 448 449 i2c_rd(sd, PK_AVI_0HEAD, buffer, HDMI_INFOFRAME_SIZE(AVI)); 450 451 if (hdmi_infoframe_unpack(&frame, buffer) < 0) { 452 v4l2_err(sd, "%s: unpack of AVI infoframe failed\n", __func__); 453 return; 454 } 455 456 hdmi_infoframe_log(KERN_INFO, dev, &frame); 457 } 458 459 /* --------------- CTRLS --------------- */ 460 461 static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd) 462 { 463 struct tc358743_state *state = to_state(sd); 464 465 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, 466 tx_5v_power_present(sd)); 467 } 468 469 static int tc358743_s_ctrl_audio_sampling_rate(struct v4l2_subdev *sd) 470 { 471 struct tc358743_state *state = to_state(sd); 472 473 return v4l2_ctrl_s_ctrl(state->audio_sampling_rate_ctrl, 474 get_audio_sampling_rate(sd)); 475 } 476 477 static int tc358743_s_ctrl_audio_present(struct v4l2_subdev *sd) 478 { 479 struct tc358743_state *state = to_state(sd); 480 481 return v4l2_ctrl_s_ctrl(state->audio_present_ctrl, 482 audio_present(sd)); 483 } 484 485 static int tc358743_update_controls(struct v4l2_subdev *sd) 486 { 487 int ret = 0; 488 489 ret |= tc358743_s_ctrl_detect_tx_5v(sd); 490 ret |= tc358743_s_ctrl_audio_sampling_rate(sd); 491 ret |= tc358743_s_ctrl_audio_present(sd); 492 493 return ret; 494 } 495 496 /* --------------- INIT --------------- */ 497 498 static void tc358743_reset_phy(struct v4l2_subdev *sd) 499 { 500 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 501 502 i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, 0); 503 i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, MASK_RESET_CTRL); 504 } 505 506 static void tc358743_reset(struct v4l2_subdev *sd, uint16_t mask) 507 { 508 u16 sysctl = i2c_rd16(sd, SYSCTL); 509 510 i2c_wr16(sd, SYSCTL, sysctl | mask); 511 i2c_wr16(sd, SYSCTL, sysctl & ~mask); 512 } 513 514 static inline void tc358743_sleep_mode(struct v4l2_subdev *sd, bool enable) 515 { 516 i2c_wr16_and_or(sd, SYSCTL, ~MASK_SLEEP, 517 enable ? MASK_SLEEP : 0); 518 } 519 520 static inline void enable_stream(struct v4l2_subdev *sd, bool enable) 521 { 522 struct tc358743_state *state = to_state(sd); 523 524 v4l2_dbg(3, debug, sd, "%s: %sable\n", 525 __func__, enable ? "en" : "dis"); 526 527 if (enable) { 528 /* It is critical for CSI receiver to see lane transition 529 * LP11->HS. Set to non-continuous mode to enable clock lane 530 * LP11 state. */ 531 i2c_wr32(sd, TXOPTIONCNTRL, 0); 532 /* Set to continuous mode to trigger LP11->HS transition */ 533 i2c_wr32(sd, TXOPTIONCNTRL, MASK_CONTCLKMODE); 534 /* Unmute video */ 535 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE); 536 } else { 537 /* Mute video so that all data lanes go to LSP11 state. 538 * No data is output to CSI Tx block. */ 539 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE | MASK_VI_MUTE); 540 } 541 542 mutex_lock(&state->confctl_mutex); 543 i2c_wr16_and_or(sd, CONFCTL, ~(MASK_VBUFEN | MASK_ABUFEN), 544 enable ? (MASK_VBUFEN | MASK_ABUFEN) : 0x0); 545 mutex_unlock(&state->confctl_mutex); 546 } 547 548 static void tc358743_set_pll(struct v4l2_subdev *sd) 549 { 550 struct tc358743_state *state = to_state(sd); 551 struct tc358743_platform_data *pdata = &state->pdata; 552 u16 pllctl0 = i2c_rd16(sd, PLLCTL0); 553 u16 pllctl1 = i2c_rd16(sd, PLLCTL1); 554 u16 pllctl0_new = SET_PLL_PRD(pdata->pll_prd) | 555 SET_PLL_FBD(pdata->pll_fbd); 556 u32 hsck = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd; 557 558 v4l2_dbg(2, debug, sd, "%s:\n", __func__); 559 560 /* Only rewrite when needed (new value or disabled), since rewriting 561 * triggers another format change event. */ 562 if ((pllctl0 != pllctl0_new) || ((pllctl1 & MASK_PLL_EN) == 0)) { 563 u16 pll_frs; 564 565 if (hsck > 500000000) 566 pll_frs = 0x0; 567 else if (hsck > 250000000) 568 pll_frs = 0x1; 569 else if (hsck > 125000000) 570 pll_frs = 0x2; 571 else 572 pll_frs = 0x3; 573 574 v4l2_dbg(1, debug, sd, "%s: updating PLL clock\n", __func__); 575 tc358743_sleep_mode(sd, true); 576 i2c_wr16(sd, PLLCTL0, pllctl0_new); 577 i2c_wr16_and_or(sd, PLLCTL1, 578 ~(MASK_PLL_FRS | MASK_RESETB | MASK_PLL_EN), 579 (SET_PLL_FRS(pll_frs) | MASK_RESETB | 580 MASK_PLL_EN)); 581 udelay(10); /* REF_02, Sheet "Source HDMI" */ 582 i2c_wr16_and_or(sd, PLLCTL1, ~MASK_CKEN, MASK_CKEN); 583 tc358743_sleep_mode(sd, false); 584 } 585 } 586 587 static void tc358743_set_ref_clk(struct v4l2_subdev *sd) 588 { 589 struct tc358743_state *state = to_state(sd); 590 struct tc358743_platform_data *pdata = &state->pdata; 591 u32 sys_freq; 592 u32 lockdet_ref; 593 u16 fh_min; 594 u16 fh_max; 595 596 BUG_ON(!(pdata->refclk_hz == 26000000 || 597 pdata->refclk_hz == 27000000 || 598 pdata->refclk_hz == 42000000)); 599 600 sys_freq = pdata->refclk_hz / 10000; 601 i2c_wr8(sd, SYS_FREQ0, sys_freq & 0x00ff); 602 i2c_wr8(sd, SYS_FREQ1, (sys_freq & 0xff00) >> 8); 603 604 i2c_wr8_and_or(sd, PHY_CTL0, ~MASK_PHY_SYSCLK_IND, 605 (pdata->refclk_hz == 42000000) ? 606 MASK_PHY_SYSCLK_IND : 0x0); 607 608 fh_min = pdata->refclk_hz / 100000; 609 i2c_wr8(sd, FH_MIN0, fh_min & 0x00ff); 610 i2c_wr8(sd, FH_MIN1, (fh_min & 0xff00) >> 8); 611 612 fh_max = (fh_min * 66) / 10; 613 i2c_wr8(sd, FH_MAX0, fh_max & 0x00ff); 614 i2c_wr8(sd, FH_MAX1, (fh_max & 0xff00) >> 8); 615 616 lockdet_ref = pdata->refclk_hz / 100; 617 i2c_wr8(sd, LOCKDET_REF0, lockdet_ref & 0x0000ff); 618 i2c_wr8(sd, LOCKDET_REF1, (lockdet_ref & 0x00ff00) >> 8); 619 i2c_wr8(sd, LOCKDET_REF2, (lockdet_ref & 0x0f0000) >> 16); 620 621 i2c_wr8_and_or(sd, NCO_F0_MOD, ~MASK_NCO_F0_MOD, 622 (pdata->refclk_hz == 27000000) ? 623 MASK_NCO_F0_MOD_27MHZ : 0x0); 624 } 625 626 static void tc358743_set_csi_color_space(struct v4l2_subdev *sd) 627 { 628 struct tc358743_state *state = to_state(sd); 629 630 switch (state->mbus_fmt_code) { 631 case MEDIA_BUS_FMT_UYVY8_1X16: 632 v4l2_dbg(2, debug, sd, "%s: YCbCr 422 16-bit\n", __func__); 633 i2c_wr8_and_or(sd, VOUT_SET2, 634 ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff, 635 MASK_SEL422 | MASK_VOUT_422FIL_100); 636 i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff, 637 MASK_VOUT_COLOR_601_YCBCR_LIMITED); 638 mutex_lock(&state->confctl_mutex); 639 i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT, 640 MASK_YCBCRFMT_422_8_BIT); 641 mutex_unlock(&state->confctl_mutex); 642 break; 643 case MEDIA_BUS_FMT_RGB888_1X24: 644 v4l2_dbg(2, debug, sd, "%s: RGB 888 24-bit\n", __func__); 645 i2c_wr8_and_or(sd, VOUT_SET2, 646 ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff, 647 0x00); 648 i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff, 649 MASK_VOUT_COLOR_RGB_FULL); 650 mutex_lock(&state->confctl_mutex); 651 i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT, 0); 652 mutex_unlock(&state->confctl_mutex); 653 break; 654 default: 655 v4l2_dbg(2, debug, sd, "%s: Unsupported format code 0x%x\n", 656 __func__, state->mbus_fmt_code); 657 } 658 } 659 660 static unsigned tc358743_num_csi_lanes_needed(struct v4l2_subdev *sd) 661 { 662 struct tc358743_state *state = to_state(sd); 663 struct v4l2_bt_timings *bt = &state->timings.bt; 664 struct tc358743_platform_data *pdata = &state->pdata; 665 u32 bits_pr_pixel = 666 (state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16) ? 16 : 24; 667 u32 bps = bt->width * bt->height * fps(bt) * bits_pr_pixel; 668 u32 bps_pr_lane = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd; 669 670 return DIV_ROUND_UP(bps, bps_pr_lane); 671 } 672 673 static void tc358743_set_csi(struct v4l2_subdev *sd) 674 { 675 struct tc358743_state *state = to_state(sd); 676 struct tc358743_platform_data *pdata = &state->pdata; 677 unsigned lanes = tc358743_num_csi_lanes_needed(sd); 678 679 v4l2_dbg(3, debug, sd, "%s:\n", __func__); 680 681 tc358743_reset(sd, MASK_CTXRST); 682 683 if (lanes < 1) 684 i2c_wr32(sd, CLW_CNTRL, MASK_CLW_LANEDISABLE); 685 if (lanes < 1) 686 i2c_wr32(sd, D0W_CNTRL, MASK_D0W_LANEDISABLE); 687 if (lanes < 2) 688 i2c_wr32(sd, D1W_CNTRL, MASK_D1W_LANEDISABLE); 689 if (lanes < 3) 690 i2c_wr32(sd, D2W_CNTRL, MASK_D2W_LANEDISABLE); 691 if (lanes < 4) 692 i2c_wr32(sd, D3W_CNTRL, MASK_D3W_LANEDISABLE); 693 694 i2c_wr32(sd, LINEINITCNT, pdata->lineinitcnt); 695 i2c_wr32(sd, LPTXTIMECNT, pdata->lptxtimecnt); 696 i2c_wr32(sd, TCLK_HEADERCNT, pdata->tclk_headercnt); 697 i2c_wr32(sd, TCLK_TRAILCNT, pdata->tclk_trailcnt); 698 i2c_wr32(sd, THS_HEADERCNT, pdata->ths_headercnt); 699 i2c_wr32(sd, TWAKEUP, pdata->twakeup); 700 i2c_wr32(sd, TCLK_POSTCNT, pdata->tclk_postcnt); 701 i2c_wr32(sd, THS_TRAILCNT, pdata->ths_trailcnt); 702 i2c_wr32(sd, HSTXVREGCNT, pdata->hstxvregcnt); 703 704 i2c_wr32(sd, HSTXVREGEN, 705 ((lanes > 0) ? MASK_CLM_HSTXVREGEN : 0x0) | 706 ((lanes > 0) ? MASK_D0M_HSTXVREGEN : 0x0) | 707 ((lanes > 1) ? MASK_D1M_HSTXVREGEN : 0x0) | 708 ((lanes > 2) ? MASK_D2M_HSTXVREGEN : 0x0) | 709 ((lanes > 3) ? MASK_D3M_HSTXVREGEN : 0x0)); 710 711 i2c_wr32(sd, TXOPTIONCNTRL, (state->bus.flags & 712 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) ? MASK_CONTCLKMODE : 0); 713 i2c_wr32(sd, STARTCNTRL, MASK_START); 714 i2c_wr32(sd, CSI_START, MASK_STRT); 715 716 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET | 717 MASK_ADDRESS_CSI_CONTROL | 718 MASK_CSI_MODE | 719 MASK_TXHSMD | 720 ((lanes == 4) ? MASK_NOL_4 : 721 (lanes == 3) ? MASK_NOL_3 : 722 (lanes == 2) ? MASK_NOL_2 : MASK_NOL_1)); 723 724 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET | 725 MASK_ADDRESS_CSI_ERR_INTENA | MASK_TXBRK | MASK_QUNK | 726 MASK_WCER | MASK_INER); 727 728 i2c_wr32(sd, CSI_CONFW, MASK_MODE_CLEAR | 729 MASK_ADDRESS_CSI_ERR_HALT | MASK_TXBRK | MASK_QUNK); 730 731 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET | 732 MASK_ADDRESS_CSI_INT_ENA | MASK_INTER); 733 } 734 735 static void tc358743_set_hdmi_phy(struct v4l2_subdev *sd) 736 { 737 struct tc358743_state *state = to_state(sd); 738 struct tc358743_platform_data *pdata = &state->pdata; 739 740 /* Default settings from REF_02, sheet "Source HDMI" 741 * and custom settings as platform data */ 742 i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, 0x0); 743 i2c_wr8(sd, PHY_CTL1, SET_PHY_AUTO_RST1_US(1600) | 744 SET_FREQ_RANGE_MODE_CYCLES(1)); 745 i2c_wr8_and_or(sd, PHY_CTL2, ~MASK_PHY_AUTO_RSTn, 746 (pdata->hdmi_phy_auto_reset_tmds_detected ? 747 MASK_PHY_AUTO_RST2 : 0) | 748 (pdata->hdmi_phy_auto_reset_tmds_in_range ? 749 MASK_PHY_AUTO_RST3 : 0) | 750 (pdata->hdmi_phy_auto_reset_tmds_valid ? 751 MASK_PHY_AUTO_RST4 : 0)); 752 i2c_wr8(sd, PHY_BIAS, 0x40); 753 i2c_wr8(sd, PHY_CSQ, SET_CSQ_CNT_LEVEL(0x0a)); 754 i2c_wr8(sd, AVM_CTL, 45); 755 i2c_wr8_and_or(sd, HDMI_DET, ~MASK_HDMI_DET_V, 756 pdata->hdmi_detection_delay << 4); 757 i2c_wr8_and_or(sd, HV_RST, ~(MASK_H_PI_RST | MASK_V_PI_RST), 758 (pdata->hdmi_phy_auto_reset_hsync_out_of_range ? 759 MASK_H_PI_RST : 0) | 760 (pdata->hdmi_phy_auto_reset_vsync_out_of_range ? 761 MASK_V_PI_RST : 0)); 762 i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, MASK_ENABLE_PHY); 763 } 764 765 static void tc358743_set_hdmi_audio(struct v4l2_subdev *sd) 766 { 767 struct tc358743_state *state = to_state(sd); 768 769 /* Default settings from REF_02, sheet "Source HDMI" */ 770 i2c_wr8(sd, FORCE_MUTE, 0x00); 771 i2c_wr8(sd, AUTO_CMD0, MASK_AUTO_MUTE7 | MASK_AUTO_MUTE6 | 772 MASK_AUTO_MUTE5 | MASK_AUTO_MUTE4 | 773 MASK_AUTO_MUTE1 | MASK_AUTO_MUTE0); 774 i2c_wr8(sd, AUTO_CMD1, MASK_AUTO_MUTE9); 775 i2c_wr8(sd, AUTO_CMD2, MASK_AUTO_PLAY3 | MASK_AUTO_PLAY2); 776 i2c_wr8(sd, BUFINIT_START, SET_BUFINIT_START_MS(500)); 777 i2c_wr8(sd, FS_MUTE, 0x00); 778 i2c_wr8(sd, FS_IMODE, MASK_NLPCM_SMODE | MASK_FS_SMODE); 779 i2c_wr8(sd, ACR_MODE, MASK_CTS_MODE); 780 i2c_wr8(sd, ACR_MDF0, MASK_ACR_L2MDF_1976_PPM | MASK_ACR_L1MDF_976_PPM); 781 i2c_wr8(sd, ACR_MDF1, MASK_ACR_L3MDF_3906_PPM); 782 i2c_wr8(sd, SDO_MODE1, MASK_SDO_FMT_I2S); 783 i2c_wr8(sd, DIV_MODE, SET_DIV_DLY_MS(100)); 784 785 mutex_lock(&state->confctl_mutex); 786 i2c_wr16_and_or(sd, CONFCTL, 0xffff, MASK_AUDCHNUM_2 | 787 MASK_AUDOUTSEL_I2S | MASK_AUTOINDEX); 788 mutex_unlock(&state->confctl_mutex); 789 } 790 791 static void tc358743_set_hdmi_info_frame_mode(struct v4l2_subdev *sd) 792 { 793 /* Default settings from REF_02, sheet "Source HDMI" */ 794 i2c_wr8(sd, PK_INT_MODE, MASK_ISRC2_INT_MODE | MASK_ISRC_INT_MODE | 795 MASK_ACP_INT_MODE | MASK_VS_INT_MODE | 796 MASK_SPD_INT_MODE | MASK_MS_INT_MODE | 797 MASK_AUD_INT_MODE | MASK_AVI_INT_MODE); 798 i2c_wr8(sd, NO_PKT_LIMIT, 0x2c); 799 i2c_wr8(sd, NO_PKT_CLR, 0x53); 800 i2c_wr8(sd, ERR_PK_LIMIT, 0x01); 801 i2c_wr8(sd, NO_PKT_LIMIT2, 0x30); 802 i2c_wr8(sd, NO_GDB_LIMIT, 0x10); 803 } 804 805 static void tc358743_initial_setup(struct v4l2_subdev *sd) 806 { 807 struct tc358743_state *state = to_state(sd); 808 struct tc358743_platform_data *pdata = &state->pdata; 809 810 /* CEC and IR are not supported by this driver */ 811 i2c_wr16_and_or(sd, SYSCTL, ~(MASK_CECRST | MASK_IRRST), 812 (MASK_CECRST | MASK_IRRST)); 813 814 tc358743_reset(sd, MASK_CTXRST | MASK_HDMIRST); 815 tc358743_sleep_mode(sd, false); 816 817 i2c_wr16(sd, FIFOCTL, pdata->fifo_level); 818 819 tc358743_set_ref_clk(sd); 820 821 i2c_wr8_and_or(sd, DDC_CTL, ~MASK_DDC5V_MODE, 822 pdata->ddc5v_delay & MASK_DDC5V_MODE); 823 i2c_wr8_and_or(sd, EDID_MODE, ~MASK_EDID_MODE, MASK_EDID_MODE_E_DDC); 824 825 tc358743_set_hdmi_phy(sd); 826 tc358743_set_hdmi_hdcp(sd, pdata->enable_hdcp); 827 tc358743_set_hdmi_audio(sd); 828 tc358743_set_hdmi_info_frame_mode(sd); 829 830 /* All CE and IT formats are detected as RGB full range in DVI mode */ 831 i2c_wr8_and_or(sd, VI_MODE, ~MASK_RGB_DVI, 0); 832 833 i2c_wr8_and_or(sd, VOUT_SET2, ~MASK_VOUTCOLORMODE, 834 MASK_VOUTCOLORMODE_AUTO); 835 i2c_wr8(sd, VOUT_SET3, MASK_VOUT_EXTCNT); 836 } 837 838 /* --------------- IRQ --------------- */ 839 840 static void tc358743_format_change(struct v4l2_subdev *sd) 841 { 842 struct tc358743_state *state = to_state(sd); 843 struct v4l2_dv_timings timings; 844 const struct v4l2_event tc358743_ev_fmt = { 845 .type = V4L2_EVENT_SOURCE_CHANGE, 846 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, 847 }; 848 849 if (tc358743_get_detected_timings(sd, &timings)) { 850 enable_stream(sd, false); 851 852 v4l2_dbg(1, debug, sd, "%s: Format changed. No signal\n", 853 __func__); 854 } else { 855 if (!v4l2_match_dv_timings(&state->timings, &timings, 0)) 856 enable_stream(sd, false); 857 858 v4l2_print_dv_timings(sd->name, 859 "tc358743_format_change: Format changed. New format: ", 860 &timings, false); 861 } 862 863 v4l2_subdev_notify_event(sd, &tc358743_ev_fmt); 864 } 865 866 static void tc358743_init_interrupts(struct v4l2_subdev *sd) 867 { 868 u16 i; 869 870 /* clear interrupt status registers */ 871 for (i = SYS_INT; i <= KEY_INT; i++) 872 i2c_wr8(sd, i, 0xff); 873 874 i2c_wr16(sd, INTSTATUS, 0xffff); 875 } 876 877 static void tc358743_enable_interrupts(struct v4l2_subdev *sd, 878 bool cable_connected) 879 { 880 v4l2_dbg(2, debug, sd, "%s: cable connected = %d\n", __func__, 881 cable_connected); 882 883 if (cable_connected) { 884 i2c_wr8(sd, SYS_INTM, ~(MASK_M_DDC | MASK_M_DVI_DET | 885 MASK_M_HDMI_DET) & 0xff); 886 i2c_wr8(sd, CLK_INTM, ~MASK_M_IN_DE_CHG); 887 i2c_wr8(sd, CBIT_INTM, ~(MASK_M_CBIT_FS | MASK_M_AF_LOCK | 888 MASK_M_AF_UNLOCK) & 0xff); 889 i2c_wr8(sd, AUDIO_INTM, ~MASK_M_BUFINIT_END); 890 i2c_wr8(sd, MISC_INTM, ~MASK_M_SYNC_CHG); 891 } else { 892 i2c_wr8(sd, SYS_INTM, ~MASK_M_DDC & 0xff); 893 i2c_wr8(sd, CLK_INTM, 0xff); 894 i2c_wr8(sd, CBIT_INTM, 0xff); 895 i2c_wr8(sd, AUDIO_INTM, 0xff); 896 i2c_wr8(sd, MISC_INTM, 0xff); 897 } 898 } 899 900 static void tc358743_hdmi_audio_int_handler(struct v4l2_subdev *sd, 901 bool *handled) 902 { 903 u8 audio_int_mask = i2c_rd8(sd, AUDIO_INTM); 904 u8 audio_int = i2c_rd8(sd, AUDIO_INT) & ~audio_int_mask; 905 906 i2c_wr8(sd, AUDIO_INT, audio_int); 907 908 v4l2_dbg(3, debug, sd, "%s: AUDIO_INT = 0x%02x\n", __func__, audio_int); 909 910 tc358743_s_ctrl_audio_sampling_rate(sd); 911 tc358743_s_ctrl_audio_present(sd); 912 } 913 914 static void tc358743_csi_err_int_handler(struct v4l2_subdev *sd, bool *handled) 915 { 916 v4l2_err(sd, "%s: CSI_ERR = 0x%x\n", __func__, i2c_rd32(sd, CSI_ERR)); 917 918 i2c_wr32(sd, CSI_INT_CLR, MASK_ICRER); 919 } 920 921 static void tc358743_hdmi_misc_int_handler(struct v4l2_subdev *sd, 922 bool *handled) 923 { 924 u8 misc_int_mask = i2c_rd8(sd, MISC_INTM); 925 u8 misc_int = i2c_rd8(sd, MISC_INT) & ~misc_int_mask; 926 927 i2c_wr8(sd, MISC_INT, misc_int); 928 929 v4l2_dbg(3, debug, sd, "%s: MISC_INT = 0x%02x\n", __func__, misc_int); 930 931 if (misc_int & MASK_I_SYNC_CHG) { 932 /* Reset the HDMI PHY to try to trigger proper lock on the 933 * incoming video format. Erase BKSV to prevent that old keys 934 * are used when a new source is connected. */ 935 if (no_sync(sd) || no_signal(sd)) { 936 tc358743_reset_phy(sd); 937 tc358743_erase_bksv(sd); 938 } 939 940 tc358743_format_change(sd); 941 942 misc_int &= ~MASK_I_SYNC_CHG; 943 if (handled) 944 *handled = true; 945 } 946 947 if (misc_int) { 948 v4l2_err(sd, "%s: Unhandled MISC_INT interrupts: 0x%02x\n", 949 __func__, misc_int); 950 } 951 } 952 953 static void tc358743_hdmi_cbit_int_handler(struct v4l2_subdev *sd, 954 bool *handled) 955 { 956 u8 cbit_int_mask = i2c_rd8(sd, CBIT_INTM); 957 u8 cbit_int = i2c_rd8(sd, CBIT_INT) & ~cbit_int_mask; 958 959 i2c_wr8(sd, CBIT_INT, cbit_int); 960 961 v4l2_dbg(3, debug, sd, "%s: CBIT_INT = 0x%02x\n", __func__, cbit_int); 962 963 if (cbit_int & MASK_I_CBIT_FS) { 964 965 v4l2_dbg(1, debug, sd, "%s: Audio sample rate changed\n", 966 __func__); 967 tc358743_s_ctrl_audio_sampling_rate(sd); 968 969 cbit_int &= ~MASK_I_CBIT_FS; 970 if (handled) 971 *handled = true; 972 } 973 974 if (cbit_int & (MASK_I_AF_LOCK | MASK_I_AF_UNLOCK)) { 975 976 v4l2_dbg(1, debug, sd, "%s: Audio present changed\n", 977 __func__); 978 tc358743_s_ctrl_audio_present(sd); 979 980 cbit_int &= ~(MASK_I_AF_LOCK | MASK_I_AF_UNLOCK); 981 if (handled) 982 *handled = true; 983 } 984 985 if (cbit_int) { 986 v4l2_err(sd, "%s: Unhandled CBIT_INT interrupts: 0x%02x\n", 987 __func__, cbit_int); 988 } 989 } 990 991 static void tc358743_hdmi_clk_int_handler(struct v4l2_subdev *sd, bool *handled) 992 { 993 u8 clk_int_mask = i2c_rd8(sd, CLK_INTM); 994 u8 clk_int = i2c_rd8(sd, CLK_INT) & ~clk_int_mask; 995 996 /* Bit 7 and bit 6 are set even when they are masked */ 997 i2c_wr8(sd, CLK_INT, clk_int | 0x80 | MASK_I_OUT_H_CHG); 998 999 v4l2_dbg(3, debug, sd, "%s: CLK_INT = 0x%02x\n", __func__, clk_int); 1000 1001 if (clk_int & (MASK_I_IN_DE_CHG)) { 1002 1003 v4l2_dbg(1, debug, sd, "%s: DE size or position has changed\n", 1004 __func__); 1005 1006 /* If the source switch to a new resolution with the same pixel 1007 * frequency as the existing (e.g. 1080p25 -> 720p50), the 1008 * I_SYNC_CHG interrupt is not always triggered, while the 1009 * I_IN_DE_CHG interrupt seems to work fine. Format change 1010 * notifications are only sent when the signal is stable to 1011 * reduce the number of notifications. */ 1012 if (!no_signal(sd) && !no_sync(sd)) 1013 tc358743_format_change(sd); 1014 1015 clk_int &= ~(MASK_I_IN_DE_CHG); 1016 if (handled) 1017 *handled = true; 1018 } 1019 1020 if (clk_int) { 1021 v4l2_err(sd, "%s: Unhandled CLK_INT interrupts: 0x%02x\n", 1022 __func__, clk_int); 1023 } 1024 } 1025 1026 static void tc358743_hdmi_sys_int_handler(struct v4l2_subdev *sd, bool *handled) 1027 { 1028 struct tc358743_state *state = to_state(sd); 1029 u8 sys_int_mask = i2c_rd8(sd, SYS_INTM); 1030 u8 sys_int = i2c_rd8(sd, SYS_INT) & ~sys_int_mask; 1031 1032 i2c_wr8(sd, SYS_INT, sys_int); 1033 1034 v4l2_dbg(3, debug, sd, "%s: SYS_INT = 0x%02x\n", __func__, sys_int); 1035 1036 if (sys_int & MASK_I_DDC) { 1037 bool tx_5v = tx_5v_power_present(sd); 1038 1039 v4l2_dbg(1, debug, sd, "%s: Tx 5V power present: %s\n", 1040 __func__, tx_5v ? "yes" : "no"); 1041 1042 if (tx_5v) { 1043 tc358743_enable_edid(sd); 1044 } else { 1045 tc358743_enable_interrupts(sd, false); 1046 tc358743_disable_edid(sd); 1047 memset(&state->timings, 0, sizeof(state->timings)); 1048 tc358743_erase_bksv(sd); 1049 tc358743_update_controls(sd); 1050 } 1051 1052 sys_int &= ~MASK_I_DDC; 1053 if (handled) 1054 *handled = true; 1055 } 1056 1057 if (sys_int & MASK_I_DVI) { 1058 v4l2_dbg(1, debug, sd, "%s: HDMI->DVI change detected\n", 1059 __func__); 1060 1061 /* Reset the HDMI PHY to try to trigger proper lock on the 1062 * incoming video format. Erase BKSV to prevent that old keys 1063 * are used when a new source is connected. */ 1064 if (no_sync(sd) || no_signal(sd)) { 1065 tc358743_reset_phy(sd); 1066 tc358743_erase_bksv(sd); 1067 } 1068 1069 sys_int &= ~MASK_I_DVI; 1070 if (handled) 1071 *handled = true; 1072 } 1073 1074 if (sys_int & MASK_I_HDMI) { 1075 v4l2_dbg(1, debug, sd, "%s: DVI->HDMI change detected\n", 1076 __func__); 1077 1078 /* Register is reset in DVI mode (REF_01, c. 6.6.41) */ 1079 i2c_wr8(sd, ANA_CTL, MASK_APPL_PCSX_NORMAL | MASK_ANALOG_ON); 1080 1081 sys_int &= ~MASK_I_HDMI; 1082 if (handled) 1083 *handled = true; 1084 } 1085 1086 if (sys_int) { 1087 v4l2_err(sd, "%s: Unhandled SYS_INT interrupts: 0x%02x\n", 1088 __func__, sys_int); 1089 } 1090 } 1091 1092 /* --------------- CORE OPS --------------- */ 1093 1094 static int tc358743_log_status(struct v4l2_subdev *sd) 1095 { 1096 struct tc358743_state *state = to_state(sd); 1097 struct v4l2_dv_timings timings; 1098 uint8_t hdmi_sys_status = i2c_rd8(sd, SYS_STATUS); 1099 uint16_t sysctl = i2c_rd16(sd, SYSCTL); 1100 u8 vi_status3 = i2c_rd8(sd, VI_STATUS3); 1101 const int deep_color_mode[4] = { 8, 10, 12, 16 }; 1102 static const char * const input_color_space[] = { 1103 "RGB", "YCbCr 601", "Adobe RGB", "YCbCr 709", "NA (4)", 1104 "xvYCC 601", "NA(6)", "xvYCC 709", "NA(8)", "sYCC601", 1105 "NA(10)", "NA(11)", "NA(12)", "Adobe YCC 601"}; 1106 1107 v4l2_info(sd, "-----Chip status-----\n"); 1108 v4l2_info(sd, "Chip ID: 0x%02x\n", 1109 (i2c_rd16(sd, CHIPID) & MASK_CHIPID) >> 8); 1110 v4l2_info(sd, "Chip revision: 0x%02x\n", 1111 i2c_rd16(sd, CHIPID) & MASK_REVID); 1112 v4l2_info(sd, "Reset: IR: %d, CEC: %d, CSI TX: %d, HDMI: %d\n", 1113 !!(sysctl & MASK_IRRST), 1114 !!(sysctl & MASK_CECRST), 1115 !!(sysctl & MASK_CTXRST), 1116 !!(sysctl & MASK_HDMIRST)); 1117 v4l2_info(sd, "Sleep mode: %s\n", sysctl & MASK_SLEEP ? "on" : "off"); 1118 v4l2_info(sd, "Cable detected (+5V power): %s\n", 1119 hdmi_sys_status & MASK_S_DDC5V ? "yes" : "no"); 1120 v4l2_info(sd, "DDC lines enabled: %s\n", 1121 (i2c_rd8(sd, EDID_MODE) & MASK_EDID_MODE_E_DDC) ? 1122 "yes" : "no"); 1123 v4l2_info(sd, "Hotplug enabled: %s\n", 1124 (i2c_rd8(sd, HPD_CTL) & MASK_HPD_OUT0) ? 1125 "yes" : "no"); 1126 v4l2_info(sd, "CEC enabled: %s\n", 1127 (i2c_rd16(sd, CECEN) & MASK_CECEN) ? "yes" : "no"); 1128 v4l2_info(sd, "-----Signal status-----\n"); 1129 v4l2_info(sd, "TMDS signal detected: %s\n", 1130 hdmi_sys_status & MASK_S_TMDS ? "yes" : "no"); 1131 v4l2_info(sd, "Stable sync signal: %s\n", 1132 hdmi_sys_status & MASK_S_SYNC ? "yes" : "no"); 1133 v4l2_info(sd, "PHY PLL locked: %s\n", 1134 hdmi_sys_status & MASK_S_PHY_PLL ? "yes" : "no"); 1135 v4l2_info(sd, "PHY DE detected: %s\n", 1136 hdmi_sys_status & MASK_S_PHY_SCDT ? "yes" : "no"); 1137 1138 if (tc358743_get_detected_timings(sd, &timings)) { 1139 v4l2_info(sd, "No video detected\n"); 1140 } else { 1141 v4l2_print_dv_timings(sd->name, "Detected format: ", &timings, 1142 true); 1143 } 1144 v4l2_print_dv_timings(sd->name, "Configured format: ", &state->timings, 1145 true); 1146 1147 v4l2_info(sd, "-----CSI-TX status-----\n"); 1148 v4l2_info(sd, "Lanes needed: %d\n", 1149 tc358743_num_csi_lanes_needed(sd)); 1150 v4l2_info(sd, "Lanes in use: %d\n", 1151 tc358743_num_csi_lanes_in_use(sd)); 1152 v4l2_info(sd, "Waiting for particular sync signal: %s\n", 1153 (i2c_rd16(sd, CSI_STATUS) & MASK_S_WSYNC) ? 1154 "yes" : "no"); 1155 v4l2_info(sd, "Transmit mode: %s\n", 1156 (i2c_rd16(sd, CSI_STATUS) & MASK_S_TXACT) ? 1157 "yes" : "no"); 1158 v4l2_info(sd, "Receive mode: %s\n", 1159 (i2c_rd16(sd, CSI_STATUS) & MASK_S_RXACT) ? 1160 "yes" : "no"); 1161 v4l2_info(sd, "Stopped: %s\n", 1162 (i2c_rd16(sd, CSI_STATUS) & MASK_S_HLT) ? 1163 "yes" : "no"); 1164 v4l2_info(sd, "Color space: %s\n", 1165 state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16 ? 1166 "YCbCr 422 16-bit" : 1167 state->mbus_fmt_code == MEDIA_BUS_FMT_RGB888_1X24 ? 1168 "RGB 888 24-bit" : "Unsupported"); 1169 1170 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); 1171 v4l2_info(sd, "HDCP encrypted content: %s\n", 1172 hdmi_sys_status & MASK_S_HDCP ? "yes" : "no"); 1173 v4l2_info(sd, "Input color space: %s %s range\n", 1174 input_color_space[(vi_status3 & MASK_S_V_COLOR) >> 1], 1175 (vi_status3 & MASK_LIMITED) ? "limited" : "full"); 1176 if (!is_hdmi(sd)) 1177 return 0; 1178 v4l2_info(sd, "AV Mute: %s\n", hdmi_sys_status & MASK_S_AVMUTE ? "on" : 1179 "off"); 1180 v4l2_info(sd, "Deep color mode: %d-bits per channel\n", 1181 deep_color_mode[(i2c_rd8(sd, VI_STATUS1) & 1182 MASK_S_DEEPCOLOR) >> 2]); 1183 print_avi_infoframe(sd); 1184 1185 return 0; 1186 } 1187 1188 #ifdef CONFIG_VIDEO_ADV_DEBUG 1189 static void tc358743_print_register_map(struct v4l2_subdev *sd) 1190 { 1191 v4l2_info(sd, "0x0000–0x00FF: Global Control Register\n"); 1192 v4l2_info(sd, "0x0100–0x01FF: CSI2-TX PHY Register\n"); 1193 v4l2_info(sd, "0x0200–0x03FF: CSI2-TX PPI Register\n"); 1194 v4l2_info(sd, "0x0400–0x05FF: Reserved\n"); 1195 v4l2_info(sd, "0x0600–0x06FF: CEC Register\n"); 1196 v4l2_info(sd, "0x0700–0x84FF: Reserved\n"); 1197 v4l2_info(sd, "0x8500–0x85FF: HDMIRX System Control Register\n"); 1198 v4l2_info(sd, "0x8600–0x86FF: HDMIRX Audio Control Register\n"); 1199 v4l2_info(sd, "0x8700–0x87FF: HDMIRX InfoFrame packet data Register\n"); 1200 v4l2_info(sd, "0x8800–0x88FF: HDMIRX HDCP Port Register\n"); 1201 v4l2_info(sd, "0x8900–0x89FF: HDMIRX Video Output Port & 3D Register\n"); 1202 v4l2_info(sd, "0x8A00–0x8BFF: Reserved\n"); 1203 v4l2_info(sd, "0x8C00–0x8FFF: HDMIRX EDID-RAM (1024bytes)\n"); 1204 v4l2_info(sd, "0x9000–0x90FF: HDMIRX GBD Extraction Control\n"); 1205 v4l2_info(sd, "0x9100–0x92FF: HDMIRX GBD RAM read\n"); 1206 v4l2_info(sd, "0x9300- : Reserved\n"); 1207 } 1208 1209 static int tc358743_get_reg_size(u16 address) 1210 { 1211 /* REF_01 p. 66-72 */ 1212 if (address <= 0x00ff) 1213 return 2; 1214 else if ((address >= 0x0100) && (address <= 0x06FF)) 1215 return 4; 1216 else if ((address >= 0x0700) && (address <= 0x84ff)) 1217 return 2; 1218 else 1219 return 1; 1220 } 1221 1222 static int tc358743_g_register(struct v4l2_subdev *sd, 1223 struct v4l2_dbg_register *reg) 1224 { 1225 if (reg->reg > 0xffff) { 1226 tc358743_print_register_map(sd); 1227 return -EINVAL; 1228 } 1229 1230 reg->size = tc358743_get_reg_size(reg->reg); 1231 1232 i2c_rd(sd, reg->reg, (u8 *)®->val, reg->size); 1233 1234 return 0; 1235 } 1236 1237 static int tc358743_s_register(struct v4l2_subdev *sd, 1238 const struct v4l2_dbg_register *reg) 1239 { 1240 if (reg->reg > 0xffff) { 1241 tc358743_print_register_map(sd); 1242 return -EINVAL; 1243 } 1244 1245 /* It should not be possible for the user to enable HDCP with a simple 1246 * v4l2-dbg command. 1247 * 1248 * DO NOT REMOVE THIS unless all other issues with HDCP have been 1249 * resolved. 1250 */ 1251 if (reg->reg == HDCP_MODE || 1252 reg->reg == HDCP_REG1 || 1253 reg->reg == HDCP_REG2 || 1254 reg->reg == HDCP_REG3 || 1255 reg->reg == BCAPS) 1256 return 0; 1257 1258 i2c_wr(sd, (u16)reg->reg, (u8 *)®->val, 1259 tc358743_get_reg_size(reg->reg)); 1260 1261 return 0; 1262 } 1263 #endif 1264 1265 static int tc358743_isr(struct v4l2_subdev *sd, u32 status, bool *handled) 1266 { 1267 u16 intstatus = i2c_rd16(sd, INTSTATUS); 1268 1269 v4l2_dbg(1, debug, sd, "%s: IntStatus = 0x%04x\n", __func__, intstatus); 1270 1271 if (intstatus & MASK_HDMI_INT) { 1272 u8 hdmi_int0 = i2c_rd8(sd, HDMI_INT0); 1273 u8 hdmi_int1 = i2c_rd8(sd, HDMI_INT1); 1274 1275 if (hdmi_int0 & MASK_I_MISC) 1276 tc358743_hdmi_misc_int_handler(sd, handled); 1277 if (hdmi_int1 & MASK_I_CBIT) 1278 tc358743_hdmi_cbit_int_handler(sd, handled); 1279 if (hdmi_int1 & MASK_I_CLK) 1280 tc358743_hdmi_clk_int_handler(sd, handled); 1281 if (hdmi_int1 & MASK_I_SYS) 1282 tc358743_hdmi_sys_int_handler(sd, handled); 1283 if (hdmi_int1 & MASK_I_AUD) 1284 tc358743_hdmi_audio_int_handler(sd, handled); 1285 1286 i2c_wr16(sd, INTSTATUS, MASK_HDMI_INT); 1287 intstatus &= ~MASK_HDMI_INT; 1288 } 1289 1290 if (intstatus & MASK_CSI_INT) { 1291 u32 csi_int = i2c_rd32(sd, CSI_INT); 1292 1293 if (csi_int & MASK_INTER) 1294 tc358743_csi_err_int_handler(sd, handled); 1295 1296 i2c_wr16(sd, INTSTATUS, MASK_CSI_INT); 1297 intstatus &= ~MASK_CSI_INT; 1298 } 1299 1300 intstatus = i2c_rd16(sd, INTSTATUS); 1301 if (intstatus) { 1302 v4l2_dbg(1, debug, sd, 1303 "%s: Unhandled IntStatus interrupts: 0x%02x\n", 1304 __func__, intstatus); 1305 } 1306 1307 return 0; 1308 } 1309 1310 static irqreturn_t tc358743_irq_handler(int irq, void *dev_id) 1311 { 1312 struct tc358743_state *state = dev_id; 1313 bool handled; 1314 1315 tc358743_isr(&state->sd, 0, &handled); 1316 1317 return handled ? IRQ_HANDLED : IRQ_NONE; 1318 } 1319 1320 static int tc358743_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh, 1321 struct v4l2_event_subscription *sub) 1322 { 1323 switch (sub->type) { 1324 case V4L2_EVENT_SOURCE_CHANGE: 1325 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub); 1326 case V4L2_EVENT_CTRL: 1327 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub); 1328 default: 1329 return -EINVAL; 1330 } 1331 } 1332 1333 /* --------------- VIDEO OPS --------------- */ 1334 1335 static int tc358743_g_input_status(struct v4l2_subdev *sd, u32 *status) 1336 { 1337 *status = 0; 1338 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0; 1339 *status |= no_sync(sd) ? V4L2_IN_ST_NO_SYNC : 0; 1340 1341 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status); 1342 1343 return 0; 1344 } 1345 1346 static int tc358743_s_dv_timings(struct v4l2_subdev *sd, 1347 struct v4l2_dv_timings *timings) 1348 { 1349 struct tc358743_state *state = to_state(sd); 1350 1351 if (!timings) 1352 return -EINVAL; 1353 1354 if (debug) 1355 v4l2_print_dv_timings(sd->name, "tc358743_s_dv_timings: ", 1356 timings, false); 1357 1358 if (v4l2_match_dv_timings(&state->timings, timings, 0)) { 1359 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__); 1360 return 0; 1361 } 1362 1363 if (!v4l2_valid_dv_timings(timings, 1364 &tc358743_timings_cap, NULL, NULL)) { 1365 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__); 1366 return -ERANGE; 1367 } 1368 1369 state->timings = *timings; 1370 1371 enable_stream(sd, false); 1372 tc358743_set_pll(sd); 1373 tc358743_set_csi(sd); 1374 1375 return 0; 1376 } 1377 1378 static int tc358743_g_dv_timings(struct v4l2_subdev *sd, 1379 struct v4l2_dv_timings *timings) 1380 { 1381 struct tc358743_state *state = to_state(sd); 1382 1383 *timings = state->timings; 1384 1385 return 0; 1386 } 1387 1388 static int tc358743_enum_dv_timings(struct v4l2_subdev *sd, 1389 struct v4l2_enum_dv_timings *timings) 1390 { 1391 if (timings->pad != 0) 1392 return -EINVAL; 1393 1394 return v4l2_enum_dv_timings_cap(timings, 1395 &tc358743_timings_cap, NULL, NULL); 1396 } 1397 1398 static int tc358743_query_dv_timings(struct v4l2_subdev *sd, 1399 struct v4l2_dv_timings *timings) 1400 { 1401 int ret; 1402 1403 ret = tc358743_get_detected_timings(sd, timings); 1404 if (ret) 1405 return ret; 1406 1407 if (debug) 1408 v4l2_print_dv_timings(sd->name, "tc358743_query_dv_timings: ", 1409 timings, false); 1410 1411 if (!v4l2_valid_dv_timings(timings, 1412 &tc358743_timings_cap, NULL, NULL)) { 1413 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__); 1414 return -ERANGE; 1415 } 1416 1417 return 0; 1418 } 1419 1420 static int tc358743_dv_timings_cap(struct v4l2_subdev *sd, 1421 struct v4l2_dv_timings_cap *cap) 1422 { 1423 if (cap->pad != 0) 1424 return -EINVAL; 1425 1426 *cap = tc358743_timings_cap; 1427 1428 return 0; 1429 } 1430 1431 static int tc358743_g_mbus_config(struct v4l2_subdev *sd, 1432 struct v4l2_mbus_config *cfg) 1433 { 1434 cfg->type = V4L2_MBUS_CSI2; 1435 1436 /* Support for non-continuous CSI-2 clock is missing in the driver */ 1437 cfg->flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK; 1438 1439 switch (tc358743_num_csi_lanes_in_use(sd)) { 1440 case 1: 1441 cfg->flags |= V4L2_MBUS_CSI2_1_LANE; 1442 break; 1443 case 2: 1444 cfg->flags |= V4L2_MBUS_CSI2_2_LANE; 1445 break; 1446 case 3: 1447 cfg->flags |= V4L2_MBUS_CSI2_3_LANE; 1448 break; 1449 case 4: 1450 cfg->flags |= V4L2_MBUS_CSI2_4_LANE; 1451 break; 1452 default: 1453 return -EINVAL; 1454 } 1455 1456 return 0; 1457 } 1458 1459 static int tc358743_s_stream(struct v4l2_subdev *sd, int enable) 1460 { 1461 enable_stream(sd, enable); 1462 1463 return 0; 1464 } 1465 1466 /* --------------- PAD OPS --------------- */ 1467 1468 static int tc358743_get_fmt(struct v4l2_subdev *sd, 1469 struct v4l2_subdev_pad_config *cfg, 1470 struct v4l2_subdev_format *format) 1471 { 1472 struct tc358743_state *state = to_state(sd); 1473 u8 vi_rep = i2c_rd8(sd, VI_REP); 1474 1475 if (format->pad != 0) 1476 return -EINVAL; 1477 1478 format->format.code = state->mbus_fmt_code; 1479 format->format.width = state->timings.bt.width; 1480 format->format.height = state->timings.bt.height; 1481 format->format.field = V4L2_FIELD_NONE; 1482 1483 switch (vi_rep & MASK_VOUT_COLOR_SEL) { 1484 case MASK_VOUT_COLOR_RGB_FULL: 1485 case MASK_VOUT_COLOR_RGB_LIMITED: 1486 format->format.colorspace = V4L2_COLORSPACE_SRGB; 1487 break; 1488 case MASK_VOUT_COLOR_601_YCBCR_LIMITED: 1489 case MASK_VOUT_COLOR_601_YCBCR_FULL: 1490 format->format.colorspace = V4L2_COLORSPACE_SMPTE170M; 1491 break; 1492 case MASK_VOUT_COLOR_709_YCBCR_FULL: 1493 case MASK_VOUT_COLOR_709_YCBCR_LIMITED: 1494 format->format.colorspace = V4L2_COLORSPACE_REC709; 1495 break; 1496 default: 1497 format->format.colorspace = 0; 1498 break; 1499 } 1500 1501 return 0; 1502 } 1503 1504 static int tc358743_set_fmt(struct v4l2_subdev *sd, 1505 struct v4l2_subdev_pad_config *cfg, 1506 struct v4l2_subdev_format *format) 1507 { 1508 struct tc358743_state *state = to_state(sd); 1509 1510 u32 code = format->format.code; /* is overwritten by get_fmt */ 1511 int ret = tc358743_get_fmt(sd, cfg, format); 1512 1513 format->format.code = code; 1514 1515 if (ret) 1516 return ret; 1517 1518 switch (code) { 1519 case MEDIA_BUS_FMT_RGB888_1X24: 1520 case MEDIA_BUS_FMT_UYVY8_1X16: 1521 break; 1522 default: 1523 return -EINVAL; 1524 } 1525 1526 if (format->which == V4L2_SUBDEV_FORMAT_TRY) 1527 return 0; 1528 1529 state->mbus_fmt_code = format->format.code; 1530 1531 enable_stream(sd, false); 1532 tc358743_set_pll(sd); 1533 tc358743_set_csi(sd); 1534 tc358743_set_csi_color_space(sd); 1535 1536 return 0; 1537 } 1538 1539 static int tc358743_g_edid(struct v4l2_subdev *sd, 1540 struct v4l2_subdev_edid *edid) 1541 { 1542 struct tc358743_state *state = to_state(sd); 1543 1544 if (edid->pad != 0) 1545 return -EINVAL; 1546 1547 if (edid->start_block == 0 && edid->blocks == 0) { 1548 edid->blocks = state->edid_blocks_written; 1549 return 0; 1550 } 1551 1552 if (state->edid_blocks_written == 0) 1553 return -ENODATA; 1554 1555 if (edid->start_block >= state->edid_blocks_written || 1556 edid->blocks == 0) 1557 return -EINVAL; 1558 1559 if (edid->start_block + edid->blocks > state->edid_blocks_written) 1560 edid->blocks = state->edid_blocks_written - edid->start_block; 1561 1562 i2c_rd(sd, EDID_RAM + (edid->start_block * EDID_BLOCK_SIZE), edid->edid, 1563 edid->blocks * EDID_BLOCK_SIZE); 1564 1565 return 0; 1566 } 1567 1568 static int tc358743_s_edid(struct v4l2_subdev *sd, 1569 struct v4l2_subdev_edid *edid) 1570 { 1571 struct tc358743_state *state = to_state(sd); 1572 u16 edid_len = edid->blocks * EDID_BLOCK_SIZE; 1573 1574 v4l2_dbg(2, debug, sd, "%s, pad %d, start block %d, blocks %d\n", 1575 __func__, edid->pad, edid->start_block, edid->blocks); 1576 1577 if (edid->pad != 0) 1578 return -EINVAL; 1579 1580 if (edid->start_block != 0) 1581 return -EINVAL; 1582 1583 if (edid->blocks > EDID_NUM_BLOCKS_MAX) { 1584 edid->blocks = EDID_NUM_BLOCKS_MAX; 1585 return -E2BIG; 1586 } 1587 1588 tc358743_disable_edid(sd); 1589 1590 i2c_wr8(sd, EDID_LEN1, edid_len & 0xff); 1591 i2c_wr8(sd, EDID_LEN2, edid_len >> 8); 1592 1593 if (edid->blocks == 0) { 1594 state->edid_blocks_written = 0; 1595 return 0; 1596 } 1597 1598 i2c_wr(sd, EDID_RAM, edid->edid, edid_len); 1599 1600 state->edid_blocks_written = edid->blocks; 1601 1602 if (tx_5v_power_present(sd)) 1603 tc358743_enable_edid(sd); 1604 1605 return 0; 1606 } 1607 1608 /* -------------------------------------------------------------------------- */ 1609 1610 static const struct v4l2_subdev_core_ops tc358743_core_ops = { 1611 .log_status = tc358743_log_status, 1612 #ifdef CONFIG_VIDEO_ADV_DEBUG 1613 .g_register = tc358743_g_register, 1614 .s_register = tc358743_s_register, 1615 #endif 1616 .interrupt_service_routine = tc358743_isr, 1617 .subscribe_event = tc358743_subscribe_event, 1618 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 1619 }; 1620 1621 static const struct v4l2_subdev_video_ops tc358743_video_ops = { 1622 .g_input_status = tc358743_g_input_status, 1623 .s_dv_timings = tc358743_s_dv_timings, 1624 .g_dv_timings = tc358743_g_dv_timings, 1625 .query_dv_timings = tc358743_query_dv_timings, 1626 .g_mbus_config = tc358743_g_mbus_config, 1627 .s_stream = tc358743_s_stream, 1628 }; 1629 1630 static const struct v4l2_subdev_pad_ops tc358743_pad_ops = { 1631 .set_fmt = tc358743_set_fmt, 1632 .get_fmt = tc358743_get_fmt, 1633 .get_edid = tc358743_g_edid, 1634 .set_edid = tc358743_s_edid, 1635 .enum_dv_timings = tc358743_enum_dv_timings, 1636 .dv_timings_cap = tc358743_dv_timings_cap, 1637 }; 1638 1639 static const struct v4l2_subdev_ops tc358743_ops = { 1640 .core = &tc358743_core_ops, 1641 .video = &tc358743_video_ops, 1642 .pad = &tc358743_pad_ops, 1643 }; 1644 1645 /* --------------- CUSTOM CTRLS --------------- */ 1646 1647 static const struct v4l2_ctrl_config tc358743_ctrl_audio_sampling_rate = { 1648 .id = TC358743_CID_AUDIO_SAMPLING_RATE, 1649 .name = "Audio sampling rate", 1650 .type = V4L2_CTRL_TYPE_INTEGER, 1651 .min = 0, 1652 .max = 768000, 1653 .step = 1, 1654 .def = 0, 1655 .flags = V4L2_CTRL_FLAG_READ_ONLY, 1656 }; 1657 1658 static const struct v4l2_ctrl_config tc358743_ctrl_audio_present = { 1659 .id = TC358743_CID_AUDIO_PRESENT, 1660 .name = "Audio present", 1661 .type = V4L2_CTRL_TYPE_BOOLEAN, 1662 .min = 0, 1663 .max = 1, 1664 .step = 1, 1665 .def = 0, 1666 .flags = V4L2_CTRL_FLAG_READ_ONLY, 1667 }; 1668 1669 /* --------------- PROBE / REMOVE --------------- */ 1670 1671 #ifdef CONFIG_OF 1672 static void tc358743_gpio_reset(struct tc358743_state *state) 1673 { 1674 gpiod_set_value(state->reset_gpio, 0); 1675 usleep_range(5000, 10000); 1676 gpiod_set_value(state->reset_gpio, 1); 1677 usleep_range(1000, 2000); 1678 gpiod_set_value(state->reset_gpio, 0); 1679 msleep(20); 1680 } 1681 1682 static int tc358743_probe_of(struct tc358743_state *state) 1683 { 1684 struct device *dev = &state->i2c_client->dev; 1685 struct v4l2_of_endpoint *endpoint; 1686 struct device_node *ep; 1687 struct clk *refclk; 1688 u32 bps_pr_lane; 1689 int ret = -EINVAL; 1690 1691 refclk = devm_clk_get(dev, "refclk"); 1692 if (IS_ERR(refclk)) { 1693 if (PTR_ERR(refclk) != -EPROBE_DEFER) 1694 dev_err(dev, "failed to get refclk: %ld\n", 1695 PTR_ERR(refclk)); 1696 return PTR_ERR(refclk); 1697 } 1698 1699 ep = of_graph_get_next_endpoint(dev->of_node, NULL); 1700 if (!ep) { 1701 dev_err(dev, "missing endpoint node\n"); 1702 return -EINVAL; 1703 } 1704 1705 endpoint = v4l2_of_alloc_parse_endpoint(ep); 1706 if (IS_ERR(endpoint)) { 1707 dev_err(dev, "failed to parse endpoint\n"); 1708 return PTR_ERR(endpoint); 1709 } 1710 1711 if (endpoint->bus_type != V4L2_MBUS_CSI2 || 1712 endpoint->bus.mipi_csi2.num_data_lanes == 0 || 1713 endpoint->nr_of_link_frequencies == 0) { 1714 dev_err(dev, "missing CSI-2 properties in endpoint\n"); 1715 goto free_endpoint; 1716 } 1717 1718 state->bus = endpoint->bus.mipi_csi2; 1719 1720 clk_prepare_enable(refclk); 1721 1722 state->pdata.refclk_hz = clk_get_rate(refclk); 1723 state->pdata.ddc5v_delay = DDC5V_DELAY_100_MS; 1724 state->pdata.enable_hdcp = false; 1725 /* A FIFO level of 16 should be enough for 2-lane 720p60 at 594 MHz. */ 1726 state->pdata.fifo_level = 16; 1727 /* 1728 * The PLL input clock is obtained by dividing refclk by pll_prd. 1729 * It must be between 6 MHz and 40 MHz, lower frequency is better. 1730 */ 1731 switch (state->pdata.refclk_hz) { 1732 case 26000000: 1733 case 27000000: 1734 case 42000000: 1735 state->pdata.pll_prd = state->pdata.refclk_hz / 6000000; 1736 break; 1737 default: 1738 dev_err(dev, "unsupported refclk rate: %u Hz\n", 1739 state->pdata.refclk_hz); 1740 goto disable_clk; 1741 } 1742 1743 /* 1744 * The CSI bps per lane must be between 62.5 Mbps and 1 Gbps. 1745 * The default is 594 Mbps for 4-lane 1080p60 or 2-lane 720p60. 1746 */ 1747 bps_pr_lane = 2 * endpoint->link_frequencies[0]; 1748 if (bps_pr_lane < 62500000U || bps_pr_lane > 1000000000U) { 1749 dev_err(dev, "unsupported bps per lane: %u bps\n", bps_pr_lane); 1750 goto disable_clk; 1751 } 1752 1753 /* The CSI speed per lane is refclk / pll_prd * pll_fbd */ 1754 state->pdata.pll_fbd = bps_pr_lane / 1755 state->pdata.refclk_hz * state->pdata.pll_prd; 1756 1757 /* 1758 * FIXME: These timings are from REF_02 for 594 Mbps per lane (297 MHz 1759 * link frequency). In principle it should be possible to calculate 1760 * them based on link frequency and resolution. 1761 */ 1762 if (bps_pr_lane != 594000000U) 1763 dev_warn(dev, "untested bps per lane: %u bps\n", bps_pr_lane); 1764 state->pdata.lineinitcnt = 0xe80; 1765 state->pdata.lptxtimecnt = 0x003; 1766 /* tclk-preparecnt: 3, tclk-zerocnt: 20 */ 1767 state->pdata.tclk_headercnt = 0x1403; 1768 state->pdata.tclk_trailcnt = 0x00; 1769 /* ths-preparecnt: 3, ths-zerocnt: 1 */ 1770 state->pdata.ths_headercnt = 0x0103; 1771 state->pdata.twakeup = 0x4882; 1772 state->pdata.tclk_postcnt = 0x008; 1773 state->pdata.ths_trailcnt = 0x2; 1774 state->pdata.hstxvregcnt = 0; 1775 1776 state->reset_gpio = devm_gpiod_get(dev, "reset"); 1777 if (IS_ERR(state->reset_gpio)) { 1778 dev_err(dev, "failed to get reset gpio\n"); 1779 ret = PTR_ERR(state->reset_gpio); 1780 goto disable_clk; 1781 } 1782 1783 tc358743_gpio_reset(state); 1784 1785 ret = 0; 1786 goto free_endpoint; 1787 1788 disable_clk: 1789 clk_disable_unprepare(refclk); 1790 free_endpoint: 1791 v4l2_of_free_endpoint(endpoint); 1792 return ret; 1793 } 1794 #else 1795 static inline int tc358743_probe_of(struct tc358743_state *state) 1796 { 1797 return -ENODEV; 1798 } 1799 #endif 1800 1801 static int tc358743_probe(struct i2c_client *client, 1802 const struct i2c_device_id *id) 1803 { 1804 static struct v4l2_dv_timings default_timing = 1805 V4L2_DV_BT_CEA_640X480P59_94; 1806 struct tc358743_state *state; 1807 struct tc358743_platform_data *pdata = client->dev.platform_data; 1808 struct v4l2_subdev *sd; 1809 int err; 1810 1811 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 1812 return -EIO; 1813 v4l_dbg(1, debug, client, "chip found @ 0x%x (%s)\n", 1814 client->addr << 1, client->adapter->name); 1815 1816 state = devm_kzalloc(&client->dev, sizeof(struct tc358743_state), 1817 GFP_KERNEL); 1818 if (!state) 1819 return -ENOMEM; 1820 1821 state->i2c_client = client; 1822 1823 /* platform data */ 1824 if (pdata) { 1825 state->pdata = *pdata; 1826 state->bus.flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK; 1827 } else { 1828 err = tc358743_probe_of(state); 1829 if (err == -ENODEV) 1830 v4l_err(client, "No platform data!\n"); 1831 if (err) 1832 return err; 1833 } 1834 1835 sd = &state->sd; 1836 v4l2_i2c_subdev_init(sd, client, &tc358743_ops); 1837 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; 1838 1839 /* i2c access */ 1840 if ((i2c_rd16(sd, CHIPID) & MASK_CHIPID) != 0) { 1841 v4l2_info(sd, "not a TC358743 on address 0x%x\n", 1842 client->addr << 1); 1843 return -ENODEV; 1844 } 1845 1846 /* control handlers */ 1847 v4l2_ctrl_handler_init(&state->hdl, 3); 1848 1849 /* private controls */ 1850 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(&state->hdl, NULL, 1851 V4L2_CID_DV_RX_POWER_PRESENT, 0, 1, 0, 0); 1852 1853 /* custom controls */ 1854 state->audio_sampling_rate_ctrl = v4l2_ctrl_new_custom(&state->hdl, 1855 &tc358743_ctrl_audio_sampling_rate, NULL); 1856 1857 state->audio_present_ctrl = v4l2_ctrl_new_custom(&state->hdl, 1858 &tc358743_ctrl_audio_present, NULL); 1859 1860 sd->ctrl_handler = &state->hdl; 1861 if (state->hdl.error) { 1862 err = state->hdl.error; 1863 goto err_hdl; 1864 } 1865 1866 if (tc358743_update_controls(sd)) { 1867 err = -ENODEV; 1868 goto err_hdl; 1869 } 1870 1871 /* work queues */ 1872 state->work_queues = create_singlethread_workqueue(client->name); 1873 if (!state->work_queues) { 1874 v4l2_err(sd, "Could not create work queue\n"); 1875 err = -ENOMEM; 1876 goto err_hdl; 1877 } 1878 1879 state->pad.flags = MEDIA_PAD_FL_SOURCE; 1880 err = media_entity_init(&sd->entity, 1, &state->pad, 0); 1881 if (err < 0) 1882 goto err_hdl; 1883 1884 sd->dev = &client->dev; 1885 err = v4l2_async_register_subdev(sd); 1886 if (err < 0) 1887 goto err_hdl; 1888 1889 mutex_init(&state->confctl_mutex); 1890 1891 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, 1892 tc358743_delayed_work_enable_hotplug); 1893 1894 tc358743_initial_setup(sd); 1895 1896 tc358743_s_dv_timings(sd, &default_timing); 1897 1898 state->mbus_fmt_code = MEDIA_BUS_FMT_RGB888_1X24; 1899 tc358743_set_csi_color_space(sd); 1900 1901 tc358743_init_interrupts(sd); 1902 1903 if (state->i2c_client->irq) { 1904 err = devm_request_threaded_irq(&client->dev, 1905 state->i2c_client->irq, 1906 NULL, tc358743_irq_handler, 1907 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 1908 "tc358743", state); 1909 if (err) 1910 goto err_work_queues; 1911 } 1912 1913 tc358743_enable_interrupts(sd, tx_5v_power_present(sd)); 1914 i2c_wr16(sd, INTMASK, ~(MASK_HDMI_MSK | MASK_CSI_MSK) & 0xffff); 1915 1916 err = v4l2_ctrl_handler_setup(sd->ctrl_handler); 1917 if (err) 1918 goto err_work_queues; 1919 1920 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, 1921 client->addr << 1, client->adapter->name); 1922 1923 return 0; 1924 1925 err_work_queues: 1926 cancel_delayed_work(&state->delayed_work_enable_hotplug); 1927 destroy_workqueue(state->work_queues); 1928 mutex_destroy(&state->confctl_mutex); 1929 err_hdl: 1930 media_entity_cleanup(&sd->entity); 1931 v4l2_ctrl_handler_free(&state->hdl); 1932 return err; 1933 } 1934 1935 static int tc358743_remove(struct i2c_client *client) 1936 { 1937 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1938 struct tc358743_state *state = to_state(sd); 1939 1940 cancel_delayed_work(&state->delayed_work_enable_hotplug); 1941 destroy_workqueue(state->work_queues); 1942 v4l2_async_unregister_subdev(sd); 1943 v4l2_device_unregister_subdev(sd); 1944 mutex_destroy(&state->confctl_mutex); 1945 media_entity_cleanup(&sd->entity); 1946 v4l2_ctrl_handler_free(&state->hdl); 1947 1948 return 0; 1949 } 1950 1951 static struct i2c_device_id tc358743_id[] = { 1952 {"tc358743", 0}, 1953 {} 1954 }; 1955 1956 MODULE_DEVICE_TABLE(i2c, tc358743_id); 1957 1958 static struct i2c_driver tc358743_driver = { 1959 .driver = { 1960 .owner = THIS_MODULE, 1961 .name = "tc358743", 1962 }, 1963 .probe = tc358743_probe, 1964 .remove = tc358743_remove, 1965 .id_table = tc358743_id, 1966 }; 1967 1968 module_i2c_driver(tc358743_driver); 1969