1 /* 2 * tc358743 - Toshiba HDMI to CSI-2 bridge 3 * 4 * Copyright 2015 Cisco Systems, Inc. and/or its affiliates. All rights 5 * reserved. 6 * 7 * This program is free software; you may redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; version 2 of the License. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 12 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 13 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 15 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 16 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 17 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 18 * SOFTWARE. 19 * 20 */ 21 22 /* 23 * References (c = chapter, p = page): 24 * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60 25 * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls 26 */ 27 28 #include <linux/kernel.h> 29 #include <linux/module.h> 30 #include <linux/slab.h> 31 #include <linux/i2c.h> 32 #include <linux/clk.h> 33 #include <linux/delay.h> 34 #include <linux/gpio/consumer.h> 35 #include <linux/interrupt.h> 36 #include <linux/videodev2.h> 37 #include <linux/workqueue.h> 38 #include <linux/v4l2-dv-timings.h> 39 #include <linux/hdmi.h> 40 #include <media/v4l2-dv-timings.h> 41 #include <media/v4l2-device.h> 42 #include <media/v4l2-ctrls.h> 43 #include <media/v4l2-event.h> 44 #include <media/v4l2-of.h> 45 #include <media/i2c/tc358743.h> 46 47 #include "tc358743_regs.h" 48 49 static int debug; 50 module_param(debug, int, 0644); 51 MODULE_PARM_DESC(debug, "debug level (0-3)"); 52 53 MODULE_DESCRIPTION("Toshiba TC358743 HDMI to CSI-2 bridge driver"); 54 MODULE_AUTHOR("Ramakrishnan Muthukrishnan <ram@rkrishnan.org>"); 55 MODULE_AUTHOR("Mikhail Khelik <mkhelik@cisco.com>"); 56 MODULE_AUTHOR("Mats Randgaard <matrandg@cisco.com>"); 57 MODULE_LICENSE("GPL"); 58 59 #define EDID_NUM_BLOCKS_MAX 8 60 #define EDID_BLOCK_SIZE 128 61 62 #define I2C_MAX_XFER_SIZE (EDID_BLOCK_SIZE + 2) 63 64 static const struct v4l2_dv_timings_cap tc358743_timings_cap = { 65 .type = V4L2_DV_BT_656_1120, 66 /* keep this initialization for compatibility with GCC < 4.4.6 */ 67 .reserved = { 0 }, 68 /* Pixel clock from REF_01 p. 20. Min/max height/width are unknown */ 69 V4L2_INIT_BT_TIMINGS(1, 10000, 1, 10000, 0, 165000000, 70 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 71 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, 72 V4L2_DV_BT_CAP_PROGRESSIVE | 73 V4L2_DV_BT_CAP_REDUCED_BLANKING | 74 V4L2_DV_BT_CAP_CUSTOM) 75 }; 76 77 struct tc358743_state { 78 struct tc358743_platform_data pdata; 79 struct v4l2_of_bus_mipi_csi2 bus; 80 struct v4l2_subdev sd; 81 struct media_pad pad; 82 struct v4l2_ctrl_handler hdl; 83 struct i2c_client *i2c_client; 84 /* CONFCTL is modified in ops and tc358743_hdmi_sys_int_handler */ 85 struct mutex confctl_mutex; 86 87 /* controls */ 88 struct v4l2_ctrl *detect_tx_5v_ctrl; 89 struct v4l2_ctrl *audio_sampling_rate_ctrl; 90 struct v4l2_ctrl *audio_present_ctrl; 91 92 /* work queues */ 93 struct workqueue_struct *work_queues; 94 struct delayed_work delayed_work_enable_hotplug; 95 96 /* edid */ 97 u8 edid_blocks_written; 98 99 struct v4l2_dv_timings timings; 100 u32 mbus_fmt_code; 101 102 struct gpio_desc *reset_gpio; 103 }; 104 105 static void tc358743_enable_interrupts(struct v4l2_subdev *sd, 106 bool cable_connected); 107 static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd); 108 109 static inline struct tc358743_state *to_state(struct v4l2_subdev *sd) 110 { 111 return container_of(sd, struct tc358743_state, sd); 112 } 113 114 /* --------------- I2C --------------- */ 115 116 static void i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n) 117 { 118 struct tc358743_state *state = to_state(sd); 119 struct i2c_client *client = state->i2c_client; 120 int err; 121 u8 buf[2] = { reg >> 8, reg & 0xff }; 122 struct i2c_msg msgs[] = { 123 { 124 .addr = client->addr, 125 .flags = 0, 126 .len = 2, 127 .buf = buf, 128 }, 129 { 130 .addr = client->addr, 131 .flags = I2C_M_RD, 132 .len = n, 133 .buf = values, 134 }, 135 }; 136 137 err = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); 138 if (err != ARRAY_SIZE(msgs)) { 139 v4l2_err(sd, "%s: reading register 0x%x from 0x%x failed\n", 140 __func__, reg, client->addr); 141 } 142 } 143 144 static void i2c_wr(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n) 145 { 146 struct tc358743_state *state = to_state(sd); 147 struct i2c_client *client = state->i2c_client; 148 int err, i; 149 struct i2c_msg msg; 150 u8 data[I2C_MAX_XFER_SIZE]; 151 152 if ((2 + n) > I2C_MAX_XFER_SIZE) { 153 n = I2C_MAX_XFER_SIZE - 2; 154 v4l2_warn(sd, "i2c wr reg=%04x: len=%d is too big!\n", 155 reg, 2 + n); 156 } 157 158 msg.addr = client->addr; 159 msg.buf = data; 160 msg.len = 2 + n; 161 msg.flags = 0; 162 163 data[0] = reg >> 8; 164 data[1] = reg & 0xff; 165 166 for (i = 0; i < n; i++) 167 data[2 + i] = values[i]; 168 169 err = i2c_transfer(client->adapter, &msg, 1); 170 if (err != 1) { 171 v4l2_err(sd, "%s: writing register 0x%x from 0x%x failed\n", 172 __func__, reg, client->addr); 173 return; 174 } 175 176 if (debug < 3) 177 return; 178 179 switch (n) { 180 case 1: 181 v4l2_info(sd, "I2C write 0x%04x = 0x%02x", 182 reg, data[2]); 183 break; 184 case 2: 185 v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x", 186 reg, data[3], data[2]); 187 break; 188 case 4: 189 v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x%02x%02x", 190 reg, data[5], data[4], data[3], data[2]); 191 break; 192 default: 193 v4l2_info(sd, "I2C write %d bytes from address 0x%04x\n", 194 n, reg); 195 } 196 } 197 198 static u8 i2c_rd8(struct v4l2_subdev *sd, u16 reg) 199 { 200 u8 val; 201 202 i2c_rd(sd, reg, &val, 1); 203 204 return val; 205 } 206 207 static void i2c_wr8(struct v4l2_subdev *sd, u16 reg, u8 val) 208 { 209 i2c_wr(sd, reg, &val, 1); 210 } 211 212 static void i2c_wr8_and_or(struct v4l2_subdev *sd, u16 reg, 213 u8 mask, u8 val) 214 { 215 i2c_wr8(sd, reg, (i2c_rd8(sd, reg) & mask) | val); 216 } 217 218 static u16 i2c_rd16(struct v4l2_subdev *sd, u16 reg) 219 { 220 u16 val; 221 222 i2c_rd(sd, reg, (u8 *)&val, 2); 223 224 return val; 225 } 226 227 static void i2c_wr16(struct v4l2_subdev *sd, u16 reg, u16 val) 228 { 229 i2c_wr(sd, reg, (u8 *)&val, 2); 230 } 231 232 static void i2c_wr16_and_or(struct v4l2_subdev *sd, u16 reg, u16 mask, u16 val) 233 { 234 i2c_wr16(sd, reg, (i2c_rd16(sd, reg) & mask) | val); 235 } 236 237 static u32 i2c_rd32(struct v4l2_subdev *sd, u16 reg) 238 { 239 u32 val; 240 241 i2c_rd(sd, reg, (u8 *)&val, 4); 242 243 return val; 244 } 245 246 static void i2c_wr32(struct v4l2_subdev *sd, u16 reg, u32 val) 247 { 248 i2c_wr(sd, reg, (u8 *)&val, 4); 249 } 250 251 /* --------------- STATUS --------------- */ 252 253 static inline bool is_hdmi(struct v4l2_subdev *sd) 254 { 255 return i2c_rd8(sd, SYS_STATUS) & MASK_S_HDMI; 256 } 257 258 static inline bool tx_5v_power_present(struct v4l2_subdev *sd) 259 { 260 return i2c_rd8(sd, SYS_STATUS) & MASK_S_DDC5V; 261 } 262 263 static inline bool no_signal(struct v4l2_subdev *sd) 264 { 265 return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_TMDS); 266 } 267 268 static inline bool no_sync(struct v4l2_subdev *sd) 269 { 270 return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_SYNC); 271 } 272 273 static inline bool audio_present(struct v4l2_subdev *sd) 274 { 275 return i2c_rd8(sd, AU_STATUS0) & MASK_S_A_SAMPLE; 276 } 277 278 static int get_audio_sampling_rate(struct v4l2_subdev *sd) 279 { 280 static const int code_to_rate[] = { 281 44100, 0, 48000, 32000, 22050, 384000, 24000, 352800, 282 88200, 768000, 96000, 705600, 176400, 0, 192000, 0 283 }; 284 285 /* Register FS_SET is not cleared when the cable is disconnected */ 286 if (no_signal(sd)) 287 return 0; 288 289 return code_to_rate[i2c_rd8(sd, FS_SET) & MASK_FS]; 290 } 291 292 static unsigned tc358743_num_csi_lanes_in_use(struct v4l2_subdev *sd) 293 { 294 return ((i2c_rd32(sd, CSI_CONTROL) & MASK_NOL) >> 1) + 1; 295 } 296 297 /* --------------- TIMINGS --------------- */ 298 299 static inline unsigned fps(const struct v4l2_bt_timings *t) 300 { 301 if (!V4L2_DV_BT_FRAME_HEIGHT(t) || !V4L2_DV_BT_FRAME_WIDTH(t)) 302 return 0; 303 304 return DIV_ROUND_CLOSEST((unsigned)t->pixelclock, 305 V4L2_DV_BT_FRAME_HEIGHT(t) * V4L2_DV_BT_FRAME_WIDTH(t)); 306 } 307 308 static int tc358743_get_detected_timings(struct v4l2_subdev *sd, 309 struct v4l2_dv_timings *timings) 310 { 311 struct v4l2_bt_timings *bt = &timings->bt; 312 unsigned width, height, frame_width, frame_height, frame_interval, fps; 313 314 memset(timings, 0, sizeof(struct v4l2_dv_timings)); 315 316 if (no_signal(sd)) { 317 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); 318 return -ENOLINK; 319 } 320 if (no_sync(sd)) { 321 v4l2_dbg(1, debug, sd, "%s: no sync on signal\n", __func__); 322 return -ENOLCK; 323 } 324 325 timings->type = V4L2_DV_BT_656_1120; 326 bt->interlaced = i2c_rd8(sd, VI_STATUS1) & MASK_S_V_INTERLACE ? 327 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; 328 329 width = ((i2c_rd8(sd, DE_WIDTH_H_HI) & 0x1f) << 8) + 330 i2c_rd8(sd, DE_WIDTH_H_LO); 331 height = ((i2c_rd8(sd, DE_WIDTH_V_HI) & 0x1f) << 8) + 332 i2c_rd8(sd, DE_WIDTH_V_LO); 333 frame_width = ((i2c_rd8(sd, H_SIZE_HI) & 0x1f) << 8) + 334 i2c_rd8(sd, H_SIZE_LO); 335 frame_height = (((i2c_rd8(sd, V_SIZE_HI) & 0x3f) << 8) + 336 i2c_rd8(sd, V_SIZE_LO)) / 2; 337 /* frame interval in milliseconds * 10 338 * Require SYS_FREQ0 and SYS_FREQ1 are precisely set */ 339 frame_interval = ((i2c_rd8(sd, FV_CNT_HI) & 0x3) << 8) + 340 i2c_rd8(sd, FV_CNT_LO); 341 fps = (frame_interval > 0) ? 342 DIV_ROUND_CLOSEST(10000, frame_interval) : 0; 343 344 bt->width = width; 345 bt->height = height; 346 bt->vsync = frame_height - height; 347 bt->hsync = frame_width - width; 348 bt->pixelclock = frame_width * frame_height * fps; 349 if (bt->interlaced == V4L2_DV_INTERLACED) { 350 bt->height *= 2; 351 bt->il_vsync = bt->vsync + 1; 352 bt->pixelclock /= 2; 353 } 354 355 return 0; 356 } 357 358 /* --------------- HOTPLUG / HDCP / EDID --------------- */ 359 360 static void tc358743_delayed_work_enable_hotplug(struct work_struct *work) 361 { 362 struct delayed_work *dwork = to_delayed_work(work); 363 struct tc358743_state *state = container_of(dwork, 364 struct tc358743_state, delayed_work_enable_hotplug); 365 struct v4l2_subdev *sd = &state->sd; 366 367 v4l2_dbg(2, debug, sd, "%s:\n", __func__); 368 369 i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, MASK_HPD_OUT0); 370 } 371 372 static void tc358743_set_hdmi_hdcp(struct v4l2_subdev *sd, bool enable) 373 { 374 v4l2_dbg(2, debug, sd, "%s: %s\n", __func__, enable ? 375 "enable" : "disable"); 376 377 i2c_wr8_and_or(sd, HDCP_REG1, 378 ~(MASK_AUTH_UNAUTH_SEL | MASK_AUTH_UNAUTH), 379 MASK_AUTH_UNAUTH_SEL_16_FRAMES | MASK_AUTH_UNAUTH_AUTO); 380 381 i2c_wr8_and_or(sd, HDCP_REG2, ~MASK_AUTO_P3_RESET, 382 SET_AUTO_P3_RESET_FRAMES(0x0f)); 383 384 /* HDCP is disabled by configuring the receiver as HDCP repeater. The 385 * repeater mode require software support to work, so HDCP 386 * authentication will fail. 387 */ 388 i2c_wr8_and_or(sd, HDCP_REG3, ~KEY_RD_CMD, enable ? KEY_RD_CMD : 0); 389 i2c_wr8_and_or(sd, HDCP_MODE, ~(MASK_AUTO_CLR | MASK_MODE_RST_TN), 390 enable ? (MASK_AUTO_CLR | MASK_MODE_RST_TN) : 0); 391 392 /* Apple MacBook Pro gen.8 has a bug that makes it freeze every fifth 393 * second when HDCP is disabled, but the MAX_EXCED bit is handled 394 * correctly and HDCP is disabled on the HDMI output. 395 */ 396 i2c_wr8_and_or(sd, BSTATUS1, ~MASK_MAX_EXCED, 397 enable ? 0 : MASK_MAX_EXCED); 398 i2c_wr8_and_or(sd, BCAPS, ~(MASK_REPEATER | MASK_READY), 399 enable ? 0 : MASK_REPEATER | MASK_READY); 400 } 401 402 static void tc358743_disable_edid(struct v4l2_subdev *sd) 403 { 404 struct tc358743_state *state = to_state(sd); 405 406 v4l2_dbg(2, debug, sd, "%s:\n", __func__); 407 408 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); 409 410 /* DDC access to EDID is also disabled when hotplug is disabled. See 411 * register DDC_CTL */ 412 i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, 0x0); 413 } 414 415 static void tc358743_enable_edid(struct v4l2_subdev *sd) 416 { 417 struct tc358743_state *state = to_state(sd); 418 419 if (state->edid_blocks_written == 0) { 420 v4l2_dbg(2, debug, sd, "%s: no EDID -> no hotplug\n", __func__); 421 return; 422 } 423 424 v4l2_dbg(2, debug, sd, "%s:\n", __func__); 425 426 /* Enable hotplug after 100 ms. DDC access to EDID is also enabled when 427 * hotplug is enabled. See register DDC_CTL */ 428 queue_delayed_work(state->work_queues, 429 &state->delayed_work_enable_hotplug, HZ / 10); 430 431 tc358743_enable_interrupts(sd, true); 432 tc358743_s_ctrl_detect_tx_5v(sd); 433 } 434 435 static void tc358743_erase_bksv(struct v4l2_subdev *sd) 436 { 437 int i; 438 439 for (i = 0; i < 5; i++) 440 i2c_wr8(sd, BKSV + i, 0); 441 } 442 443 /* --------------- AVI infoframe --------------- */ 444 445 static void print_avi_infoframe(struct v4l2_subdev *sd) 446 { 447 struct i2c_client *client = v4l2_get_subdevdata(sd); 448 struct device *dev = &client->dev; 449 union hdmi_infoframe frame; 450 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)]; 451 452 if (!is_hdmi(sd)) { 453 v4l2_info(sd, "DVI-D signal - AVI infoframe not supported\n"); 454 return; 455 } 456 457 i2c_rd(sd, PK_AVI_0HEAD, buffer, HDMI_INFOFRAME_SIZE(AVI)); 458 459 if (hdmi_infoframe_unpack(&frame, buffer) < 0) { 460 v4l2_err(sd, "%s: unpack of AVI infoframe failed\n", __func__); 461 return; 462 } 463 464 hdmi_infoframe_log(KERN_INFO, dev, &frame); 465 } 466 467 /* --------------- CTRLS --------------- */ 468 469 static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd) 470 { 471 struct tc358743_state *state = to_state(sd); 472 473 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, 474 tx_5v_power_present(sd)); 475 } 476 477 static int tc358743_s_ctrl_audio_sampling_rate(struct v4l2_subdev *sd) 478 { 479 struct tc358743_state *state = to_state(sd); 480 481 return v4l2_ctrl_s_ctrl(state->audio_sampling_rate_ctrl, 482 get_audio_sampling_rate(sd)); 483 } 484 485 static int tc358743_s_ctrl_audio_present(struct v4l2_subdev *sd) 486 { 487 struct tc358743_state *state = to_state(sd); 488 489 return v4l2_ctrl_s_ctrl(state->audio_present_ctrl, 490 audio_present(sd)); 491 } 492 493 static int tc358743_update_controls(struct v4l2_subdev *sd) 494 { 495 int ret = 0; 496 497 ret |= tc358743_s_ctrl_detect_tx_5v(sd); 498 ret |= tc358743_s_ctrl_audio_sampling_rate(sd); 499 ret |= tc358743_s_ctrl_audio_present(sd); 500 501 return ret; 502 } 503 504 /* --------------- INIT --------------- */ 505 506 static void tc358743_reset_phy(struct v4l2_subdev *sd) 507 { 508 v4l2_dbg(1, debug, sd, "%s:\n", __func__); 509 510 i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, 0); 511 i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, MASK_RESET_CTRL); 512 } 513 514 static void tc358743_reset(struct v4l2_subdev *sd, uint16_t mask) 515 { 516 u16 sysctl = i2c_rd16(sd, SYSCTL); 517 518 i2c_wr16(sd, SYSCTL, sysctl | mask); 519 i2c_wr16(sd, SYSCTL, sysctl & ~mask); 520 } 521 522 static inline void tc358743_sleep_mode(struct v4l2_subdev *sd, bool enable) 523 { 524 i2c_wr16_and_or(sd, SYSCTL, ~MASK_SLEEP, 525 enable ? MASK_SLEEP : 0); 526 } 527 528 static inline void enable_stream(struct v4l2_subdev *sd, bool enable) 529 { 530 struct tc358743_state *state = to_state(sd); 531 532 v4l2_dbg(3, debug, sd, "%s: %sable\n", 533 __func__, enable ? "en" : "dis"); 534 535 if (enable) { 536 /* It is critical for CSI receiver to see lane transition 537 * LP11->HS. Set to non-continuous mode to enable clock lane 538 * LP11 state. */ 539 i2c_wr32(sd, TXOPTIONCNTRL, 0); 540 /* Set to continuous mode to trigger LP11->HS transition */ 541 i2c_wr32(sd, TXOPTIONCNTRL, MASK_CONTCLKMODE); 542 /* Unmute video */ 543 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE); 544 } else { 545 /* Mute video so that all data lanes go to LSP11 state. 546 * No data is output to CSI Tx block. */ 547 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE | MASK_VI_MUTE); 548 } 549 550 mutex_lock(&state->confctl_mutex); 551 i2c_wr16_and_or(sd, CONFCTL, ~(MASK_VBUFEN | MASK_ABUFEN), 552 enable ? (MASK_VBUFEN | MASK_ABUFEN) : 0x0); 553 mutex_unlock(&state->confctl_mutex); 554 } 555 556 static void tc358743_set_pll(struct v4l2_subdev *sd) 557 { 558 struct tc358743_state *state = to_state(sd); 559 struct tc358743_platform_data *pdata = &state->pdata; 560 u16 pllctl0 = i2c_rd16(sd, PLLCTL0); 561 u16 pllctl1 = i2c_rd16(sd, PLLCTL1); 562 u16 pllctl0_new = SET_PLL_PRD(pdata->pll_prd) | 563 SET_PLL_FBD(pdata->pll_fbd); 564 u32 hsck = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd; 565 566 v4l2_dbg(2, debug, sd, "%s:\n", __func__); 567 568 /* Only rewrite when needed (new value or disabled), since rewriting 569 * triggers another format change event. */ 570 if ((pllctl0 != pllctl0_new) || ((pllctl1 & MASK_PLL_EN) == 0)) { 571 u16 pll_frs; 572 573 if (hsck > 500000000) 574 pll_frs = 0x0; 575 else if (hsck > 250000000) 576 pll_frs = 0x1; 577 else if (hsck > 125000000) 578 pll_frs = 0x2; 579 else 580 pll_frs = 0x3; 581 582 v4l2_dbg(1, debug, sd, "%s: updating PLL clock\n", __func__); 583 tc358743_sleep_mode(sd, true); 584 i2c_wr16(sd, PLLCTL0, pllctl0_new); 585 i2c_wr16_and_or(sd, PLLCTL1, 586 ~(MASK_PLL_FRS | MASK_RESETB | MASK_PLL_EN), 587 (SET_PLL_FRS(pll_frs) | MASK_RESETB | 588 MASK_PLL_EN)); 589 udelay(10); /* REF_02, Sheet "Source HDMI" */ 590 i2c_wr16_and_or(sd, PLLCTL1, ~MASK_CKEN, MASK_CKEN); 591 tc358743_sleep_mode(sd, false); 592 } 593 } 594 595 static void tc358743_set_ref_clk(struct v4l2_subdev *sd) 596 { 597 struct tc358743_state *state = to_state(sd); 598 struct tc358743_platform_data *pdata = &state->pdata; 599 u32 sys_freq; 600 u32 lockdet_ref; 601 u16 fh_min; 602 u16 fh_max; 603 604 BUG_ON(!(pdata->refclk_hz == 26000000 || 605 pdata->refclk_hz == 27000000 || 606 pdata->refclk_hz == 42000000)); 607 608 sys_freq = pdata->refclk_hz / 10000; 609 i2c_wr8(sd, SYS_FREQ0, sys_freq & 0x00ff); 610 i2c_wr8(sd, SYS_FREQ1, (sys_freq & 0xff00) >> 8); 611 612 i2c_wr8_and_or(sd, PHY_CTL0, ~MASK_PHY_SYSCLK_IND, 613 (pdata->refclk_hz == 42000000) ? 614 MASK_PHY_SYSCLK_IND : 0x0); 615 616 fh_min = pdata->refclk_hz / 100000; 617 i2c_wr8(sd, FH_MIN0, fh_min & 0x00ff); 618 i2c_wr8(sd, FH_MIN1, (fh_min & 0xff00) >> 8); 619 620 fh_max = (fh_min * 66) / 10; 621 i2c_wr8(sd, FH_MAX0, fh_max & 0x00ff); 622 i2c_wr8(sd, FH_MAX1, (fh_max & 0xff00) >> 8); 623 624 lockdet_ref = pdata->refclk_hz / 100; 625 i2c_wr8(sd, LOCKDET_REF0, lockdet_ref & 0x0000ff); 626 i2c_wr8(sd, LOCKDET_REF1, (lockdet_ref & 0x00ff00) >> 8); 627 i2c_wr8(sd, LOCKDET_REF2, (lockdet_ref & 0x0f0000) >> 16); 628 629 i2c_wr8_and_or(sd, NCO_F0_MOD, ~MASK_NCO_F0_MOD, 630 (pdata->refclk_hz == 27000000) ? 631 MASK_NCO_F0_MOD_27MHZ : 0x0); 632 } 633 634 static void tc358743_set_csi_color_space(struct v4l2_subdev *sd) 635 { 636 struct tc358743_state *state = to_state(sd); 637 638 switch (state->mbus_fmt_code) { 639 case MEDIA_BUS_FMT_UYVY8_1X16: 640 v4l2_dbg(2, debug, sd, "%s: YCbCr 422 16-bit\n", __func__); 641 i2c_wr8_and_or(sd, VOUT_SET2, 642 ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff, 643 MASK_SEL422 | MASK_VOUT_422FIL_100); 644 i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff, 645 MASK_VOUT_COLOR_601_YCBCR_LIMITED); 646 mutex_lock(&state->confctl_mutex); 647 i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT, 648 MASK_YCBCRFMT_422_8_BIT); 649 mutex_unlock(&state->confctl_mutex); 650 break; 651 case MEDIA_BUS_FMT_RGB888_1X24: 652 v4l2_dbg(2, debug, sd, "%s: RGB 888 24-bit\n", __func__); 653 i2c_wr8_and_or(sd, VOUT_SET2, 654 ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff, 655 0x00); 656 i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff, 657 MASK_VOUT_COLOR_RGB_FULL); 658 mutex_lock(&state->confctl_mutex); 659 i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT, 0); 660 mutex_unlock(&state->confctl_mutex); 661 break; 662 default: 663 v4l2_dbg(2, debug, sd, "%s: Unsupported format code 0x%x\n", 664 __func__, state->mbus_fmt_code); 665 } 666 } 667 668 static unsigned tc358743_num_csi_lanes_needed(struct v4l2_subdev *sd) 669 { 670 struct tc358743_state *state = to_state(sd); 671 struct v4l2_bt_timings *bt = &state->timings.bt; 672 struct tc358743_platform_data *pdata = &state->pdata; 673 u32 bits_pr_pixel = 674 (state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16) ? 16 : 24; 675 u32 bps = bt->width * bt->height * fps(bt) * bits_pr_pixel; 676 u32 bps_pr_lane = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd; 677 678 return DIV_ROUND_UP(bps, bps_pr_lane); 679 } 680 681 static void tc358743_set_csi(struct v4l2_subdev *sd) 682 { 683 struct tc358743_state *state = to_state(sd); 684 struct tc358743_platform_data *pdata = &state->pdata; 685 unsigned lanes = tc358743_num_csi_lanes_needed(sd); 686 687 v4l2_dbg(3, debug, sd, "%s:\n", __func__); 688 689 tc358743_reset(sd, MASK_CTXRST); 690 691 if (lanes < 1) 692 i2c_wr32(sd, CLW_CNTRL, MASK_CLW_LANEDISABLE); 693 if (lanes < 1) 694 i2c_wr32(sd, D0W_CNTRL, MASK_D0W_LANEDISABLE); 695 if (lanes < 2) 696 i2c_wr32(sd, D1W_CNTRL, MASK_D1W_LANEDISABLE); 697 if (lanes < 3) 698 i2c_wr32(sd, D2W_CNTRL, MASK_D2W_LANEDISABLE); 699 if (lanes < 4) 700 i2c_wr32(sd, D3W_CNTRL, MASK_D3W_LANEDISABLE); 701 702 i2c_wr32(sd, LINEINITCNT, pdata->lineinitcnt); 703 i2c_wr32(sd, LPTXTIMECNT, pdata->lptxtimecnt); 704 i2c_wr32(sd, TCLK_HEADERCNT, pdata->tclk_headercnt); 705 i2c_wr32(sd, TCLK_TRAILCNT, pdata->tclk_trailcnt); 706 i2c_wr32(sd, THS_HEADERCNT, pdata->ths_headercnt); 707 i2c_wr32(sd, TWAKEUP, pdata->twakeup); 708 i2c_wr32(sd, TCLK_POSTCNT, pdata->tclk_postcnt); 709 i2c_wr32(sd, THS_TRAILCNT, pdata->ths_trailcnt); 710 i2c_wr32(sd, HSTXVREGCNT, pdata->hstxvregcnt); 711 712 i2c_wr32(sd, HSTXVREGEN, 713 ((lanes > 0) ? MASK_CLM_HSTXVREGEN : 0x0) | 714 ((lanes > 0) ? MASK_D0M_HSTXVREGEN : 0x0) | 715 ((lanes > 1) ? MASK_D1M_HSTXVREGEN : 0x0) | 716 ((lanes > 2) ? MASK_D2M_HSTXVREGEN : 0x0) | 717 ((lanes > 3) ? MASK_D3M_HSTXVREGEN : 0x0)); 718 719 i2c_wr32(sd, TXOPTIONCNTRL, (state->bus.flags & 720 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) ? MASK_CONTCLKMODE : 0); 721 i2c_wr32(sd, STARTCNTRL, MASK_START); 722 i2c_wr32(sd, CSI_START, MASK_STRT); 723 724 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET | 725 MASK_ADDRESS_CSI_CONTROL | 726 MASK_CSI_MODE | 727 MASK_TXHSMD | 728 ((lanes == 4) ? MASK_NOL_4 : 729 (lanes == 3) ? MASK_NOL_3 : 730 (lanes == 2) ? MASK_NOL_2 : MASK_NOL_1)); 731 732 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET | 733 MASK_ADDRESS_CSI_ERR_INTENA | MASK_TXBRK | MASK_QUNK | 734 MASK_WCER | MASK_INER); 735 736 i2c_wr32(sd, CSI_CONFW, MASK_MODE_CLEAR | 737 MASK_ADDRESS_CSI_ERR_HALT | MASK_TXBRK | MASK_QUNK); 738 739 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET | 740 MASK_ADDRESS_CSI_INT_ENA | MASK_INTER); 741 } 742 743 static void tc358743_set_hdmi_phy(struct v4l2_subdev *sd) 744 { 745 struct tc358743_state *state = to_state(sd); 746 struct tc358743_platform_data *pdata = &state->pdata; 747 748 /* Default settings from REF_02, sheet "Source HDMI" 749 * and custom settings as platform data */ 750 i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, 0x0); 751 i2c_wr8(sd, PHY_CTL1, SET_PHY_AUTO_RST1_US(1600) | 752 SET_FREQ_RANGE_MODE_CYCLES(1)); 753 i2c_wr8_and_or(sd, PHY_CTL2, ~MASK_PHY_AUTO_RSTn, 754 (pdata->hdmi_phy_auto_reset_tmds_detected ? 755 MASK_PHY_AUTO_RST2 : 0) | 756 (pdata->hdmi_phy_auto_reset_tmds_in_range ? 757 MASK_PHY_AUTO_RST3 : 0) | 758 (pdata->hdmi_phy_auto_reset_tmds_valid ? 759 MASK_PHY_AUTO_RST4 : 0)); 760 i2c_wr8(sd, PHY_BIAS, 0x40); 761 i2c_wr8(sd, PHY_CSQ, SET_CSQ_CNT_LEVEL(0x0a)); 762 i2c_wr8(sd, AVM_CTL, 45); 763 i2c_wr8_and_or(sd, HDMI_DET, ~MASK_HDMI_DET_V, 764 pdata->hdmi_detection_delay << 4); 765 i2c_wr8_and_or(sd, HV_RST, ~(MASK_H_PI_RST | MASK_V_PI_RST), 766 (pdata->hdmi_phy_auto_reset_hsync_out_of_range ? 767 MASK_H_PI_RST : 0) | 768 (pdata->hdmi_phy_auto_reset_vsync_out_of_range ? 769 MASK_V_PI_RST : 0)); 770 i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, MASK_ENABLE_PHY); 771 } 772 773 static void tc358743_set_hdmi_audio(struct v4l2_subdev *sd) 774 { 775 struct tc358743_state *state = to_state(sd); 776 777 /* Default settings from REF_02, sheet "Source HDMI" */ 778 i2c_wr8(sd, FORCE_MUTE, 0x00); 779 i2c_wr8(sd, AUTO_CMD0, MASK_AUTO_MUTE7 | MASK_AUTO_MUTE6 | 780 MASK_AUTO_MUTE5 | MASK_AUTO_MUTE4 | 781 MASK_AUTO_MUTE1 | MASK_AUTO_MUTE0); 782 i2c_wr8(sd, AUTO_CMD1, MASK_AUTO_MUTE9); 783 i2c_wr8(sd, AUTO_CMD2, MASK_AUTO_PLAY3 | MASK_AUTO_PLAY2); 784 i2c_wr8(sd, BUFINIT_START, SET_BUFINIT_START_MS(500)); 785 i2c_wr8(sd, FS_MUTE, 0x00); 786 i2c_wr8(sd, FS_IMODE, MASK_NLPCM_SMODE | MASK_FS_SMODE); 787 i2c_wr8(sd, ACR_MODE, MASK_CTS_MODE); 788 i2c_wr8(sd, ACR_MDF0, MASK_ACR_L2MDF_1976_PPM | MASK_ACR_L1MDF_976_PPM); 789 i2c_wr8(sd, ACR_MDF1, MASK_ACR_L3MDF_3906_PPM); 790 i2c_wr8(sd, SDO_MODE1, MASK_SDO_FMT_I2S); 791 i2c_wr8(sd, DIV_MODE, SET_DIV_DLY_MS(100)); 792 793 mutex_lock(&state->confctl_mutex); 794 i2c_wr16_and_or(sd, CONFCTL, 0xffff, MASK_AUDCHNUM_2 | 795 MASK_AUDOUTSEL_I2S | MASK_AUTOINDEX); 796 mutex_unlock(&state->confctl_mutex); 797 } 798 799 static void tc358743_set_hdmi_info_frame_mode(struct v4l2_subdev *sd) 800 { 801 /* Default settings from REF_02, sheet "Source HDMI" */ 802 i2c_wr8(sd, PK_INT_MODE, MASK_ISRC2_INT_MODE | MASK_ISRC_INT_MODE | 803 MASK_ACP_INT_MODE | MASK_VS_INT_MODE | 804 MASK_SPD_INT_MODE | MASK_MS_INT_MODE | 805 MASK_AUD_INT_MODE | MASK_AVI_INT_MODE); 806 i2c_wr8(sd, NO_PKT_LIMIT, 0x2c); 807 i2c_wr8(sd, NO_PKT_CLR, 0x53); 808 i2c_wr8(sd, ERR_PK_LIMIT, 0x01); 809 i2c_wr8(sd, NO_PKT_LIMIT2, 0x30); 810 i2c_wr8(sd, NO_GDB_LIMIT, 0x10); 811 } 812 813 static void tc358743_initial_setup(struct v4l2_subdev *sd) 814 { 815 struct tc358743_state *state = to_state(sd); 816 struct tc358743_platform_data *pdata = &state->pdata; 817 818 /* CEC and IR are not supported by this driver */ 819 i2c_wr16_and_or(sd, SYSCTL, ~(MASK_CECRST | MASK_IRRST), 820 (MASK_CECRST | MASK_IRRST)); 821 822 tc358743_reset(sd, MASK_CTXRST | MASK_HDMIRST); 823 tc358743_sleep_mode(sd, false); 824 825 i2c_wr16(sd, FIFOCTL, pdata->fifo_level); 826 827 tc358743_set_ref_clk(sd); 828 829 i2c_wr8_and_or(sd, DDC_CTL, ~MASK_DDC5V_MODE, 830 pdata->ddc5v_delay & MASK_DDC5V_MODE); 831 i2c_wr8_and_or(sd, EDID_MODE, ~MASK_EDID_MODE, MASK_EDID_MODE_E_DDC); 832 833 tc358743_set_hdmi_phy(sd); 834 tc358743_set_hdmi_hdcp(sd, pdata->enable_hdcp); 835 tc358743_set_hdmi_audio(sd); 836 tc358743_set_hdmi_info_frame_mode(sd); 837 838 /* All CE and IT formats are detected as RGB full range in DVI mode */ 839 i2c_wr8_and_or(sd, VI_MODE, ~MASK_RGB_DVI, 0); 840 841 i2c_wr8_and_or(sd, VOUT_SET2, ~MASK_VOUTCOLORMODE, 842 MASK_VOUTCOLORMODE_AUTO); 843 i2c_wr8(sd, VOUT_SET3, MASK_VOUT_EXTCNT); 844 } 845 846 /* --------------- IRQ --------------- */ 847 848 static void tc358743_format_change(struct v4l2_subdev *sd) 849 { 850 struct tc358743_state *state = to_state(sd); 851 struct v4l2_dv_timings timings; 852 const struct v4l2_event tc358743_ev_fmt = { 853 .type = V4L2_EVENT_SOURCE_CHANGE, 854 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, 855 }; 856 857 if (tc358743_get_detected_timings(sd, &timings)) { 858 enable_stream(sd, false); 859 860 v4l2_dbg(1, debug, sd, "%s: No signal\n", 861 __func__); 862 } else { 863 if (!v4l2_match_dv_timings(&state->timings, &timings, 0, false)) 864 enable_stream(sd, false); 865 866 if (debug) 867 v4l2_print_dv_timings(sd->name, 868 "tc358743_format_change: New format: ", 869 &timings, false); 870 } 871 872 if (sd->devnode) 873 v4l2_subdev_notify_event(sd, &tc358743_ev_fmt); 874 } 875 876 static void tc358743_init_interrupts(struct v4l2_subdev *sd) 877 { 878 u16 i; 879 880 /* clear interrupt status registers */ 881 for (i = SYS_INT; i <= KEY_INT; i++) 882 i2c_wr8(sd, i, 0xff); 883 884 i2c_wr16(sd, INTSTATUS, 0xffff); 885 } 886 887 static void tc358743_enable_interrupts(struct v4l2_subdev *sd, 888 bool cable_connected) 889 { 890 v4l2_dbg(2, debug, sd, "%s: cable connected = %d\n", __func__, 891 cable_connected); 892 893 if (cable_connected) { 894 i2c_wr8(sd, SYS_INTM, ~(MASK_M_DDC | MASK_M_DVI_DET | 895 MASK_M_HDMI_DET) & 0xff); 896 i2c_wr8(sd, CLK_INTM, ~MASK_M_IN_DE_CHG); 897 i2c_wr8(sd, CBIT_INTM, ~(MASK_M_CBIT_FS | MASK_M_AF_LOCK | 898 MASK_M_AF_UNLOCK) & 0xff); 899 i2c_wr8(sd, AUDIO_INTM, ~MASK_M_BUFINIT_END); 900 i2c_wr8(sd, MISC_INTM, ~MASK_M_SYNC_CHG); 901 } else { 902 i2c_wr8(sd, SYS_INTM, ~MASK_M_DDC & 0xff); 903 i2c_wr8(sd, CLK_INTM, 0xff); 904 i2c_wr8(sd, CBIT_INTM, 0xff); 905 i2c_wr8(sd, AUDIO_INTM, 0xff); 906 i2c_wr8(sd, MISC_INTM, 0xff); 907 } 908 } 909 910 static void tc358743_hdmi_audio_int_handler(struct v4l2_subdev *sd, 911 bool *handled) 912 { 913 u8 audio_int_mask = i2c_rd8(sd, AUDIO_INTM); 914 u8 audio_int = i2c_rd8(sd, AUDIO_INT) & ~audio_int_mask; 915 916 i2c_wr8(sd, AUDIO_INT, audio_int); 917 918 v4l2_dbg(3, debug, sd, "%s: AUDIO_INT = 0x%02x\n", __func__, audio_int); 919 920 tc358743_s_ctrl_audio_sampling_rate(sd); 921 tc358743_s_ctrl_audio_present(sd); 922 } 923 924 static void tc358743_csi_err_int_handler(struct v4l2_subdev *sd, bool *handled) 925 { 926 v4l2_err(sd, "%s: CSI_ERR = 0x%x\n", __func__, i2c_rd32(sd, CSI_ERR)); 927 928 i2c_wr32(sd, CSI_INT_CLR, MASK_ICRER); 929 } 930 931 static void tc358743_hdmi_misc_int_handler(struct v4l2_subdev *sd, 932 bool *handled) 933 { 934 u8 misc_int_mask = i2c_rd8(sd, MISC_INTM); 935 u8 misc_int = i2c_rd8(sd, MISC_INT) & ~misc_int_mask; 936 937 i2c_wr8(sd, MISC_INT, misc_int); 938 939 v4l2_dbg(3, debug, sd, "%s: MISC_INT = 0x%02x\n", __func__, misc_int); 940 941 if (misc_int & MASK_I_SYNC_CHG) { 942 /* Reset the HDMI PHY to try to trigger proper lock on the 943 * incoming video format. Erase BKSV to prevent that old keys 944 * are used when a new source is connected. */ 945 if (no_sync(sd) || no_signal(sd)) { 946 tc358743_reset_phy(sd); 947 tc358743_erase_bksv(sd); 948 } 949 950 tc358743_format_change(sd); 951 952 misc_int &= ~MASK_I_SYNC_CHG; 953 if (handled) 954 *handled = true; 955 } 956 957 if (misc_int) { 958 v4l2_err(sd, "%s: Unhandled MISC_INT interrupts: 0x%02x\n", 959 __func__, misc_int); 960 } 961 } 962 963 static void tc358743_hdmi_cbit_int_handler(struct v4l2_subdev *sd, 964 bool *handled) 965 { 966 u8 cbit_int_mask = i2c_rd8(sd, CBIT_INTM); 967 u8 cbit_int = i2c_rd8(sd, CBIT_INT) & ~cbit_int_mask; 968 969 i2c_wr8(sd, CBIT_INT, cbit_int); 970 971 v4l2_dbg(3, debug, sd, "%s: CBIT_INT = 0x%02x\n", __func__, cbit_int); 972 973 if (cbit_int & MASK_I_CBIT_FS) { 974 975 v4l2_dbg(1, debug, sd, "%s: Audio sample rate changed\n", 976 __func__); 977 tc358743_s_ctrl_audio_sampling_rate(sd); 978 979 cbit_int &= ~MASK_I_CBIT_FS; 980 if (handled) 981 *handled = true; 982 } 983 984 if (cbit_int & (MASK_I_AF_LOCK | MASK_I_AF_UNLOCK)) { 985 986 v4l2_dbg(1, debug, sd, "%s: Audio present changed\n", 987 __func__); 988 tc358743_s_ctrl_audio_present(sd); 989 990 cbit_int &= ~(MASK_I_AF_LOCK | MASK_I_AF_UNLOCK); 991 if (handled) 992 *handled = true; 993 } 994 995 if (cbit_int) { 996 v4l2_err(sd, "%s: Unhandled CBIT_INT interrupts: 0x%02x\n", 997 __func__, cbit_int); 998 } 999 } 1000 1001 static void tc358743_hdmi_clk_int_handler(struct v4l2_subdev *sd, bool *handled) 1002 { 1003 u8 clk_int_mask = i2c_rd8(sd, CLK_INTM); 1004 u8 clk_int = i2c_rd8(sd, CLK_INT) & ~clk_int_mask; 1005 1006 /* Bit 7 and bit 6 are set even when they are masked */ 1007 i2c_wr8(sd, CLK_INT, clk_int | 0x80 | MASK_I_OUT_H_CHG); 1008 1009 v4l2_dbg(3, debug, sd, "%s: CLK_INT = 0x%02x\n", __func__, clk_int); 1010 1011 if (clk_int & (MASK_I_IN_DE_CHG)) { 1012 1013 v4l2_dbg(1, debug, sd, "%s: DE size or position has changed\n", 1014 __func__); 1015 1016 /* If the source switch to a new resolution with the same pixel 1017 * frequency as the existing (e.g. 1080p25 -> 720p50), the 1018 * I_SYNC_CHG interrupt is not always triggered, while the 1019 * I_IN_DE_CHG interrupt seems to work fine. Format change 1020 * notifications are only sent when the signal is stable to 1021 * reduce the number of notifications. */ 1022 if (!no_signal(sd) && !no_sync(sd)) 1023 tc358743_format_change(sd); 1024 1025 clk_int &= ~(MASK_I_IN_DE_CHG); 1026 if (handled) 1027 *handled = true; 1028 } 1029 1030 if (clk_int) { 1031 v4l2_err(sd, "%s: Unhandled CLK_INT interrupts: 0x%02x\n", 1032 __func__, clk_int); 1033 } 1034 } 1035 1036 static void tc358743_hdmi_sys_int_handler(struct v4l2_subdev *sd, bool *handled) 1037 { 1038 struct tc358743_state *state = to_state(sd); 1039 u8 sys_int_mask = i2c_rd8(sd, SYS_INTM); 1040 u8 sys_int = i2c_rd8(sd, SYS_INT) & ~sys_int_mask; 1041 1042 i2c_wr8(sd, SYS_INT, sys_int); 1043 1044 v4l2_dbg(3, debug, sd, "%s: SYS_INT = 0x%02x\n", __func__, sys_int); 1045 1046 if (sys_int & MASK_I_DDC) { 1047 bool tx_5v = tx_5v_power_present(sd); 1048 1049 v4l2_dbg(1, debug, sd, "%s: Tx 5V power present: %s\n", 1050 __func__, tx_5v ? "yes" : "no"); 1051 1052 if (tx_5v) { 1053 tc358743_enable_edid(sd); 1054 } else { 1055 tc358743_enable_interrupts(sd, false); 1056 tc358743_disable_edid(sd); 1057 memset(&state->timings, 0, sizeof(state->timings)); 1058 tc358743_erase_bksv(sd); 1059 tc358743_update_controls(sd); 1060 } 1061 1062 sys_int &= ~MASK_I_DDC; 1063 if (handled) 1064 *handled = true; 1065 } 1066 1067 if (sys_int & MASK_I_DVI) { 1068 v4l2_dbg(1, debug, sd, "%s: HDMI->DVI change detected\n", 1069 __func__); 1070 1071 /* Reset the HDMI PHY to try to trigger proper lock on the 1072 * incoming video format. Erase BKSV to prevent that old keys 1073 * are used when a new source is connected. */ 1074 if (no_sync(sd) || no_signal(sd)) { 1075 tc358743_reset_phy(sd); 1076 tc358743_erase_bksv(sd); 1077 } 1078 1079 sys_int &= ~MASK_I_DVI; 1080 if (handled) 1081 *handled = true; 1082 } 1083 1084 if (sys_int & MASK_I_HDMI) { 1085 v4l2_dbg(1, debug, sd, "%s: DVI->HDMI change detected\n", 1086 __func__); 1087 1088 /* Register is reset in DVI mode (REF_01, c. 6.6.41) */ 1089 i2c_wr8(sd, ANA_CTL, MASK_APPL_PCSX_NORMAL | MASK_ANALOG_ON); 1090 1091 sys_int &= ~MASK_I_HDMI; 1092 if (handled) 1093 *handled = true; 1094 } 1095 1096 if (sys_int) { 1097 v4l2_err(sd, "%s: Unhandled SYS_INT interrupts: 0x%02x\n", 1098 __func__, sys_int); 1099 } 1100 } 1101 1102 /* --------------- CORE OPS --------------- */ 1103 1104 static int tc358743_log_status(struct v4l2_subdev *sd) 1105 { 1106 struct tc358743_state *state = to_state(sd); 1107 struct v4l2_dv_timings timings; 1108 uint8_t hdmi_sys_status = i2c_rd8(sd, SYS_STATUS); 1109 uint16_t sysctl = i2c_rd16(sd, SYSCTL); 1110 u8 vi_status3 = i2c_rd8(sd, VI_STATUS3); 1111 const int deep_color_mode[4] = { 8, 10, 12, 16 }; 1112 static const char * const input_color_space[] = { 1113 "RGB", "YCbCr 601", "Adobe RGB", "YCbCr 709", "NA (4)", 1114 "xvYCC 601", "NA(6)", "xvYCC 709", "NA(8)", "sYCC601", 1115 "NA(10)", "NA(11)", "NA(12)", "Adobe YCC 601"}; 1116 1117 v4l2_info(sd, "-----Chip status-----\n"); 1118 v4l2_info(sd, "Chip ID: 0x%02x\n", 1119 (i2c_rd16(sd, CHIPID) & MASK_CHIPID) >> 8); 1120 v4l2_info(sd, "Chip revision: 0x%02x\n", 1121 i2c_rd16(sd, CHIPID) & MASK_REVID); 1122 v4l2_info(sd, "Reset: IR: %d, CEC: %d, CSI TX: %d, HDMI: %d\n", 1123 !!(sysctl & MASK_IRRST), 1124 !!(sysctl & MASK_CECRST), 1125 !!(sysctl & MASK_CTXRST), 1126 !!(sysctl & MASK_HDMIRST)); 1127 v4l2_info(sd, "Sleep mode: %s\n", sysctl & MASK_SLEEP ? "on" : "off"); 1128 v4l2_info(sd, "Cable detected (+5V power): %s\n", 1129 hdmi_sys_status & MASK_S_DDC5V ? "yes" : "no"); 1130 v4l2_info(sd, "DDC lines enabled: %s\n", 1131 (i2c_rd8(sd, EDID_MODE) & MASK_EDID_MODE_E_DDC) ? 1132 "yes" : "no"); 1133 v4l2_info(sd, "Hotplug enabled: %s\n", 1134 (i2c_rd8(sd, HPD_CTL) & MASK_HPD_OUT0) ? 1135 "yes" : "no"); 1136 v4l2_info(sd, "CEC enabled: %s\n", 1137 (i2c_rd16(sd, CECEN) & MASK_CECEN) ? "yes" : "no"); 1138 v4l2_info(sd, "-----Signal status-----\n"); 1139 v4l2_info(sd, "TMDS signal detected: %s\n", 1140 hdmi_sys_status & MASK_S_TMDS ? "yes" : "no"); 1141 v4l2_info(sd, "Stable sync signal: %s\n", 1142 hdmi_sys_status & MASK_S_SYNC ? "yes" : "no"); 1143 v4l2_info(sd, "PHY PLL locked: %s\n", 1144 hdmi_sys_status & MASK_S_PHY_PLL ? "yes" : "no"); 1145 v4l2_info(sd, "PHY DE detected: %s\n", 1146 hdmi_sys_status & MASK_S_PHY_SCDT ? "yes" : "no"); 1147 1148 if (tc358743_get_detected_timings(sd, &timings)) { 1149 v4l2_info(sd, "No video detected\n"); 1150 } else { 1151 v4l2_print_dv_timings(sd->name, "Detected format: ", &timings, 1152 true); 1153 } 1154 v4l2_print_dv_timings(sd->name, "Configured format: ", &state->timings, 1155 true); 1156 1157 v4l2_info(sd, "-----CSI-TX status-----\n"); 1158 v4l2_info(sd, "Lanes needed: %d\n", 1159 tc358743_num_csi_lanes_needed(sd)); 1160 v4l2_info(sd, "Lanes in use: %d\n", 1161 tc358743_num_csi_lanes_in_use(sd)); 1162 v4l2_info(sd, "Waiting for particular sync signal: %s\n", 1163 (i2c_rd16(sd, CSI_STATUS) & MASK_S_WSYNC) ? 1164 "yes" : "no"); 1165 v4l2_info(sd, "Transmit mode: %s\n", 1166 (i2c_rd16(sd, CSI_STATUS) & MASK_S_TXACT) ? 1167 "yes" : "no"); 1168 v4l2_info(sd, "Receive mode: %s\n", 1169 (i2c_rd16(sd, CSI_STATUS) & MASK_S_RXACT) ? 1170 "yes" : "no"); 1171 v4l2_info(sd, "Stopped: %s\n", 1172 (i2c_rd16(sd, CSI_STATUS) & MASK_S_HLT) ? 1173 "yes" : "no"); 1174 v4l2_info(sd, "Color space: %s\n", 1175 state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16 ? 1176 "YCbCr 422 16-bit" : 1177 state->mbus_fmt_code == MEDIA_BUS_FMT_RGB888_1X24 ? 1178 "RGB 888 24-bit" : "Unsupported"); 1179 1180 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); 1181 v4l2_info(sd, "HDCP encrypted content: %s\n", 1182 hdmi_sys_status & MASK_S_HDCP ? "yes" : "no"); 1183 v4l2_info(sd, "Input color space: %s %s range\n", 1184 input_color_space[(vi_status3 & MASK_S_V_COLOR) >> 1], 1185 (vi_status3 & MASK_LIMITED) ? "limited" : "full"); 1186 if (!is_hdmi(sd)) 1187 return 0; 1188 v4l2_info(sd, "AV Mute: %s\n", hdmi_sys_status & MASK_S_AVMUTE ? "on" : 1189 "off"); 1190 v4l2_info(sd, "Deep color mode: %d-bits per channel\n", 1191 deep_color_mode[(i2c_rd8(sd, VI_STATUS1) & 1192 MASK_S_DEEPCOLOR) >> 2]); 1193 print_avi_infoframe(sd); 1194 1195 return 0; 1196 } 1197 1198 #ifdef CONFIG_VIDEO_ADV_DEBUG 1199 static void tc358743_print_register_map(struct v4l2_subdev *sd) 1200 { 1201 v4l2_info(sd, "0x0000-0x00FF: Global Control Register\n"); 1202 v4l2_info(sd, "0x0100-0x01FF: CSI2-TX PHY Register\n"); 1203 v4l2_info(sd, "0x0200-0x03FF: CSI2-TX PPI Register\n"); 1204 v4l2_info(sd, "0x0400-0x05FF: Reserved\n"); 1205 v4l2_info(sd, "0x0600-0x06FF: CEC Register\n"); 1206 v4l2_info(sd, "0x0700-0x84FF: Reserved\n"); 1207 v4l2_info(sd, "0x8500-0x85FF: HDMIRX System Control Register\n"); 1208 v4l2_info(sd, "0x8600-0x86FF: HDMIRX Audio Control Register\n"); 1209 v4l2_info(sd, "0x8700-0x87FF: HDMIRX InfoFrame packet data Register\n"); 1210 v4l2_info(sd, "0x8800-0x88FF: HDMIRX HDCP Port Register\n"); 1211 v4l2_info(sd, "0x8900-0x89FF: HDMIRX Video Output Port & 3D Register\n"); 1212 v4l2_info(sd, "0x8A00-0x8BFF: Reserved\n"); 1213 v4l2_info(sd, "0x8C00-0x8FFF: HDMIRX EDID-RAM (1024bytes)\n"); 1214 v4l2_info(sd, "0x9000-0x90FF: HDMIRX GBD Extraction Control\n"); 1215 v4l2_info(sd, "0x9100-0x92FF: HDMIRX GBD RAM read\n"); 1216 v4l2_info(sd, "0x9300- : Reserved\n"); 1217 } 1218 1219 static int tc358743_get_reg_size(u16 address) 1220 { 1221 /* REF_01 p. 66-72 */ 1222 if (address <= 0x00ff) 1223 return 2; 1224 else if ((address >= 0x0100) && (address <= 0x06FF)) 1225 return 4; 1226 else if ((address >= 0x0700) && (address <= 0x84ff)) 1227 return 2; 1228 else 1229 return 1; 1230 } 1231 1232 static int tc358743_g_register(struct v4l2_subdev *sd, 1233 struct v4l2_dbg_register *reg) 1234 { 1235 if (reg->reg > 0xffff) { 1236 tc358743_print_register_map(sd); 1237 return -EINVAL; 1238 } 1239 1240 reg->size = tc358743_get_reg_size(reg->reg); 1241 1242 i2c_rd(sd, reg->reg, (u8 *)®->val, reg->size); 1243 1244 return 0; 1245 } 1246 1247 static int tc358743_s_register(struct v4l2_subdev *sd, 1248 const struct v4l2_dbg_register *reg) 1249 { 1250 if (reg->reg > 0xffff) { 1251 tc358743_print_register_map(sd); 1252 return -EINVAL; 1253 } 1254 1255 /* It should not be possible for the user to enable HDCP with a simple 1256 * v4l2-dbg command. 1257 * 1258 * DO NOT REMOVE THIS unless all other issues with HDCP have been 1259 * resolved. 1260 */ 1261 if (reg->reg == HDCP_MODE || 1262 reg->reg == HDCP_REG1 || 1263 reg->reg == HDCP_REG2 || 1264 reg->reg == HDCP_REG3 || 1265 reg->reg == BCAPS) 1266 return 0; 1267 1268 i2c_wr(sd, (u16)reg->reg, (u8 *)®->val, 1269 tc358743_get_reg_size(reg->reg)); 1270 1271 return 0; 1272 } 1273 #endif 1274 1275 static int tc358743_isr(struct v4l2_subdev *sd, u32 status, bool *handled) 1276 { 1277 u16 intstatus = i2c_rd16(sd, INTSTATUS); 1278 1279 v4l2_dbg(1, debug, sd, "%s: IntStatus = 0x%04x\n", __func__, intstatus); 1280 1281 if (intstatus & MASK_HDMI_INT) { 1282 u8 hdmi_int0 = i2c_rd8(sd, HDMI_INT0); 1283 u8 hdmi_int1 = i2c_rd8(sd, HDMI_INT1); 1284 1285 if (hdmi_int0 & MASK_I_MISC) 1286 tc358743_hdmi_misc_int_handler(sd, handled); 1287 if (hdmi_int1 & MASK_I_CBIT) 1288 tc358743_hdmi_cbit_int_handler(sd, handled); 1289 if (hdmi_int1 & MASK_I_CLK) 1290 tc358743_hdmi_clk_int_handler(sd, handled); 1291 if (hdmi_int1 & MASK_I_SYS) 1292 tc358743_hdmi_sys_int_handler(sd, handled); 1293 if (hdmi_int1 & MASK_I_AUD) 1294 tc358743_hdmi_audio_int_handler(sd, handled); 1295 1296 i2c_wr16(sd, INTSTATUS, MASK_HDMI_INT); 1297 intstatus &= ~MASK_HDMI_INT; 1298 } 1299 1300 if (intstatus & MASK_CSI_INT) { 1301 u32 csi_int = i2c_rd32(sd, CSI_INT); 1302 1303 if (csi_int & MASK_INTER) 1304 tc358743_csi_err_int_handler(sd, handled); 1305 1306 i2c_wr16(sd, INTSTATUS, MASK_CSI_INT); 1307 intstatus &= ~MASK_CSI_INT; 1308 } 1309 1310 intstatus = i2c_rd16(sd, INTSTATUS); 1311 if (intstatus) { 1312 v4l2_dbg(1, debug, sd, 1313 "%s: Unhandled IntStatus interrupts: 0x%02x\n", 1314 __func__, intstatus); 1315 } 1316 1317 return 0; 1318 } 1319 1320 static irqreturn_t tc358743_irq_handler(int irq, void *dev_id) 1321 { 1322 struct tc358743_state *state = dev_id; 1323 bool handled; 1324 1325 tc358743_isr(&state->sd, 0, &handled); 1326 1327 return handled ? IRQ_HANDLED : IRQ_NONE; 1328 } 1329 1330 static int tc358743_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh, 1331 struct v4l2_event_subscription *sub) 1332 { 1333 switch (sub->type) { 1334 case V4L2_EVENT_SOURCE_CHANGE: 1335 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub); 1336 case V4L2_EVENT_CTRL: 1337 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub); 1338 default: 1339 return -EINVAL; 1340 } 1341 } 1342 1343 /* --------------- VIDEO OPS --------------- */ 1344 1345 static int tc358743_g_input_status(struct v4l2_subdev *sd, u32 *status) 1346 { 1347 *status = 0; 1348 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0; 1349 *status |= no_sync(sd) ? V4L2_IN_ST_NO_SYNC : 0; 1350 1351 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status); 1352 1353 return 0; 1354 } 1355 1356 static int tc358743_s_dv_timings(struct v4l2_subdev *sd, 1357 struct v4l2_dv_timings *timings) 1358 { 1359 struct tc358743_state *state = to_state(sd); 1360 1361 if (!timings) 1362 return -EINVAL; 1363 1364 if (debug) 1365 v4l2_print_dv_timings(sd->name, "tc358743_s_dv_timings: ", 1366 timings, false); 1367 1368 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) { 1369 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__); 1370 return 0; 1371 } 1372 1373 if (!v4l2_valid_dv_timings(timings, 1374 &tc358743_timings_cap, NULL, NULL)) { 1375 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__); 1376 return -ERANGE; 1377 } 1378 1379 state->timings = *timings; 1380 1381 enable_stream(sd, false); 1382 tc358743_set_pll(sd); 1383 tc358743_set_csi(sd); 1384 1385 return 0; 1386 } 1387 1388 static int tc358743_g_dv_timings(struct v4l2_subdev *sd, 1389 struct v4l2_dv_timings *timings) 1390 { 1391 struct tc358743_state *state = to_state(sd); 1392 1393 *timings = state->timings; 1394 1395 return 0; 1396 } 1397 1398 static int tc358743_enum_dv_timings(struct v4l2_subdev *sd, 1399 struct v4l2_enum_dv_timings *timings) 1400 { 1401 if (timings->pad != 0) 1402 return -EINVAL; 1403 1404 return v4l2_enum_dv_timings_cap(timings, 1405 &tc358743_timings_cap, NULL, NULL); 1406 } 1407 1408 static int tc358743_query_dv_timings(struct v4l2_subdev *sd, 1409 struct v4l2_dv_timings *timings) 1410 { 1411 int ret; 1412 1413 ret = tc358743_get_detected_timings(sd, timings); 1414 if (ret) 1415 return ret; 1416 1417 if (debug) 1418 v4l2_print_dv_timings(sd->name, "tc358743_query_dv_timings: ", 1419 timings, false); 1420 1421 if (!v4l2_valid_dv_timings(timings, 1422 &tc358743_timings_cap, NULL, NULL)) { 1423 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__); 1424 return -ERANGE; 1425 } 1426 1427 return 0; 1428 } 1429 1430 static int tc358743_dv_timings_cap(struct v4l2_subdev *sd, 1431 struct v4l2_dv_timings_cap *cap) 1432 { 1433 if (cap->pad != 0) 1434 return -EINVAL; 1435 1436 *cap = tc358743_timings_cap; 1437 1438 return 0; 1439 } 1440 1441 static int tc358743_g_mbus_config(struct v4l2_subdev *sd, 1442 struct v4l2_mbus_config *cfg) 1443 { 1444 cfg->type = V4L2_MBUS_CSI2; 1445 1446 /* Support for non-continuous CSI-2 clock is missing in the driver */ 1447 cfg->flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK; 1448 1449 switch (tc358743_num_csi_lanes_in_use(sd)) { 1450 case 1: 1451 cfg->flags |= V4L2_MBUS_CSI2_1_LANE; 1452 break; 1453 case 2: 1454 cfg->flags |= V4L2_MBUS_CSI2_2_LANE; 1455 break; 1456 case 3: 1457 cfg->flags |= V4L2_MBUS_CSI2_3_LANE; 1458 break; 1459 case 4: 1460 cfg->flags |= V4L2_MBUS_CSI2_4_LANE; 1461 break; 1462 default: 1463 return -EINVAL; 1464 } 1465 1466 return 0; 1467 } 1468 1469 static int tc358743_s_stream(struct v4l2_subdev *sd, int enable) 1470 { 1471 enable_stream(sd, enable); 1472 1473 return 0; 1474 } 1475 1476 /* --------------- PAD OPS --------------- */ 1477 1478 static int tc358743_get_fmt(struct v4l2_subdev *sd, 1479 struct v4l2_subdev_pad_config *cfg, 1480 struct v4l2_subdev_format *format) 1481 { 1482 struct tc358743_state *state = to_state(sd); 1483 u8 vi_rep = i2c_rd8(sd, VI_REP); 1484 1485 if (format->pad != 0) 1486 return -EINVAL; 1487 1488 format->format.code = state->mbus_fmt_code; 1489 format->format.width = state->timings.bt.width; 1490 format->format.height = state->timings.bt.height; 1491 format->format.field = V4L2_FIELD_NONE; 1492 1493 switch (vi_rep & MASK_VOUT_COLOR_SEL) { 1494 case MASK_VOUT_COLOR_RGB_FULL: 1495 case MASK_VOUT_COLOR_RGB_LIMITED: 1496 format->format.colorspace = V4L2_COLORSPACE_SRGB; 1497 break; 1498 case MASK_VOUT_COLOR_601_YCBCR_LIMITED: 1499 case MASK_VOUT_COLOR_601_YCBCR_FULL: 1500 format->format.colorspace = V4L2_COLORSPACE_SMPTE170M; 1501 break; 1502 case MASK_VOUT_COLOR_709_YCBCR_FULL: 1503 case MASK_VOUT_COLOR_709_YCBCR_LIMITED: 1504 format->format.colorspace = V4L2_COLORSPACE_REC709; 1505 break; 1506 default: 1507 format->format.colorspace = 0; 1508 break; 1509 } 1510 1511 return 0; 1512 } 1513 1514 static int tc358743_set_fmt(struct v4l2_subdev *sd, 1515 struct v4l2_subdev_pad_config *cfg, 1516 struct v4l2_subdev_format *format) 1517 { 1518 struct tc358743_state *state = to_state(sd); 1519 1520 u32 code = format->format.code; /* is overwritten by get_fmt */ 1521 int ret = tc358743_get_fmt(sd, cfg, format); 1522 1523 format->format.code = code; 1524 1525 if (ret) 1526 return ret; 1527 1528 switch (code) { 1529 case MEDIA_BUS_FMT_RGB888_1X24: 1530 case MEDIA_BUS_FMT_UYVY8_1X16: 1531 break; 1532 default: 1533 return -EINVAL; 1534 } 1535 1536 if (format->which == V4L2_SUBDEV_FORMAT_TRY) 1537 return 0; 1538 1539 state->mbus_fmt_code = format->format.code; 1540 1541 enable_stream(sd, false); 1542 tc358743_set_pll(sd); 1543 tc358743_set_csi(sd); 1544 tc358743_set_csi_color_space(sd); 1545 1546 return 0; 1547 } 1548 1549 static int tc358743_g_edid(struct v4l2_subdev *sd, 1550 struct v4l2_subdev_edid *edid) 1551 { 1552 struct tc358743_state *state = to_state(sd); 1553 1554 if (edid->pad != 0) 1555 return -EINVAL; 1556 1557 if (edid->start_block == 0 && edid->blocks == 0) { 1558 edid->blocks = state->edid_blocks_written; 1559 return 0; 1560 } 1561 1562 if (state->edid_blocks_written == 0) 1563 return -ENODATA; 1564 1565 if (edid->start_block >= state->edid_blocks_written || 1566 edid->blocks == 0) 1567 return -EINVAL; 1568 1569 if (edid->start_block + edid->blocks > state->edid_blocks_written) 1570 edid->blocks = state->edid_blocks_written - edid->start_block; 1571 1572 i2c_rd(sd, EDID_RAM + (edid->start_block * EDID_BLOCK_SIZE), edid->edid, 1573 edid->blocks * EDID_BLOCK_SIZE); 1574 1575 return 0; 1576 } 1577 1578 static int tc358743_s_edid(struct v4l2_subdev *sd, 1579 struct v4l2_subdev_edid *edid) 1580 { 1581 struct tc358743_state *state = to_state(sd); 1582 u16 edid_len = edid->blocks * EDID_BLOCK_SIZE; 1583 int i; 1584 1585 v4l2_dbg(2, debug, sd, "%s, pad %d, start block %d, blocks %d\n", 1586 __func__, edid->pad, edid->start_block, edid->blocks); 1587 1588 if (edid->pad != 0) 1589 return -EINVAL; 1590 1591 if (edid->start_block != 0) 1592 return -EINVAL; 1593 1594 if (edid->blocks > EDID_NUM_BLOCKS_MAX) { 1595 edid->blocks = EDID_NUM_BLOCKS_MAX; 1596 return -E2BIG; 1597 } 1598 1599 tc358743_disable_edid(sd); 1600 1601 i2c_wr8(sd, EDID_LEN1, edid_len & 0xff); 1602 i2c_wr8(sd, EDID_LEN2, edid_len >> 8); 1603 1604 if (edid->blocks == 0) { 1605 state->edid_blocks_written = 0; 1606 return 0; 1607 } 1608 1609 for (i = 0; i < edid_len; i += EDID_BLOCK_SIZE) 1610 i2c_wr(sd, EDID_RAM + i, edid->edid + i, EDID_BLOCK_SIZE); 1611 1612 state->edid_blocks_written = edid->blocks; 1613 1614 if (tx_5v_power_present(sd)) 1615 tc358743_enable_edid(sd); 1616 1617 return 0; 1618 } 1619 1620 /* -------------------------------------------------------------------------- */ 1621 1622 static const struct v4l2_subdev_core_ops tc358743_core_ops = { 1623 .log_status = tc358743_log_status, 1624 #ifdef CONFIG_VIDEO_ADV_DEBUG 1625 .g_register = tc358743_g_register, 1626 .s_register = tc358743_s_register, 1627 #endif 1628 .interrupt_service_routine = tc358743_isr, 1629 .subscribe_event = tc358743_subscribe_event, 1630 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 1631 }; 1632 1633 static const struct v4l2_subdev_video_ops tc358743_video_ops = { 1634 .g_input_status = tc358743_g_input_status, 1635 .s_dv_timings = tc358743_s_dv_timings, 1636 .g_dv_timings = tc358743_g_dv_timings, 1637 .query_dv_timings = tc358743_query_dv_timings, 1638 .g_mbus_config = tc358743_g_mbus_config, 1639 .s_stream = tc358743_s_stream, 1640 }; 1641 1642 static const struct v4l2_subdev_pad_ops tc358743_pad_ops = { 1643 .set_fmt = tc358743_set_fmt, 1644 .get_fmt = tc358743_get_fmt, 1645 .get_edid = tc358743_g_edid, 1646 .set_edid = tc358743_s_edid, 1647 .enum_dv_timings = tc358743_enum_dv_timings, 1648 .dv_timings_cap = tc358743_dv_timings_cap, 1649 }; 1650 1651 static const struct v4l2_subdev_ops tc358743_ops = { 1652 .core = &tc358743_core_ops, 1653 .video = &tc358743_video_ops, 1654 .pad = &tc358743_pad_ops, 1655 }; 1656 1657 /* --------------- CUSTOM CTRLS --------------- */ 1658 1659 static const struct v4l2_ctrl_config tc358743_ctrl_audio_sampling_rate = { 1660 .id = TC358743_CID_AUDIO_SAMPLING_RATE, 1661 .name = "Audio sampling rate", 1662 .type = V4L2_CTRL_TYPE_INTEGER, 1663 .min = 0, 1664 .max = 768000, 1665 .step = 1, 1666 .def = 0, 1667 .flags = V4L2_CTRL_FLAG_READ_ONLY, 1668 }; 1669 1670 static const struct v4l2_ctrl_config tc358743_ctrl_audio_present = { 1671 .id = TC358743_CID_AUDIO_PRESENT, 1672 .name = "Audio present", 1673 .type = V4L2_CTRL_TYPE_BOOLEAN, 1674 .min = 0, 1675 .max = 1, 1676 .step = 1, 1677 .def = 0, 1678 .flags = V4L2_CTRL_FLAG_READ_ONLY, 1679 }; 1680 1681 /* --------------- PROBE / REMOVE --------------- */ 1682 1683 #ifdef CONFIG_OF 1684 static void tc358743_gpio_reset(struct tc358743_state *state) 1685 { 1686 usleep_range(5000, 10000); 1687 gpiod_set_value(state->reset_gpio, 1); 1688 usleep_range(1000, 2000); 1689 gpiod_set_value(state->reset_gpio, 0); 1690 msleep(20); 1691 } 1692 1693 static int tc358743_probe_of(struct tc358743_state *state) 1694 { 1695 struct device *dev = &state->i2c_client->dev; 1696 struct v4l2_of_endpoint *endpoint; 1697 struct device_node *ep; 1698 struct clk *refclk; 1699 u32 bps_pr_lane; 1700 int ret = -EINVAL; 1701 1702 refclk = devm_clk_get(dev, "refclk"); 1703 if (IS_ERR(refclk)) { 1704 if (PTR_ERR(refclk) != -EPROBE_DEFER) 1705 dev_err(dev, "failed to get refclk: %ld\n", 1706 PTR_ERR(refclk)); 1707 return PTR_ERR(refclk); 1708 } 1709 1710 ep = of_graph_get_next_endpoint(dev->of_node, NULL); 1711 if (!ep) { 1712 dev_err(dev, "missing endpoint node\n"); 1713 return -EINVAL; 1714 } 1715 1716 endpoint = v4l2_of_alloc_parse_endpoint(ep); 1717 if (IS_ERR(endpoint)) { 1718 dev_err(dev, "failed to parse endpoint\n"); 1719 return PTR_ERR(endpoint); 1720 } 1721 1722 if (endpoint->bus_type != V4L2_MBUS_CSI2 || 1723 endpoint->bus.mipi_csi2.num_data_lanes == 0 || 1724 endpoint->nr_of_link_frequencies == 0) { 1725 dev_err(dev, "missing CSI-2 properties in endpoint\n"); 1726 goto free_endpoint; 1727 } 1728 1729 state->bus = endpoint->bus.mipi_csi2; 1730 1731 clk_prepare_enable(refclk); 1732 1733 state->pdata.refclk_hz = clk_get_rate(refclk); 1734 state->pdata.ddc5v_delay = DDC5V_DELAY_100_MS; 1735 state->pdata.enable_hdcp = false; 1736 /* A FIFO level of 16 should be enough for 2-lane 720p60 at 594 MHz. */ 1737 state->pdata.fifo_level = 16; 1738 /* 1739 * The PLL input clock is obtained by dividing refclk by pll_prd. 1740 * It must be between 6 MHz and 40 MHz, lower frequency is better. 1741 */ 1742 switch (state->pdata.refclk_hz) { 1743 case 26000000: 1744 case 27000000: 1745 case 42000000: 1746 state->pdata.pll_prd = state->pdata.refclk_hz / 6000000; 1747 break; 1748 default: 1749 dev_err(dev, "unsupported refclk rate: %u Hz\n", 1750 state->pdata.refclk_hz); 1751 goto disable_clk; 1752 } 1753 1754 /* 1755 * The CSI bps per lane must be between 62.5 Mbps and 1 Gbps. 1756 * The default is 594 Mbps for 4-lane 1080p60 or 2-lane 720p60. 1757 */ 1758 bps_pr_lane = 2 * endpoint->link_frequencies[0]; 1759 if (bps_pr_lane < 62500000U || bps_pr_lane > 1000000000U) { 1760 dev_err(dev, "unsupported bps per lane: %u bps\n", bps_pr_lane); 1761 goto disable_clk; 1762 } 1763 1764 /* The CSI speed per lane is refclk / pll_prd * pll_fbd */ 1765 state->pdata.pll_fbd = bps_pr_lane / 1766 state->pdata.refclk_hz * state->pdata.pll_prd; 1767 1768 /* 1769 * FIXME: These timings are from REF_02 for 594 Mbps per lane (297 MHz 1770 * link frequency). In principle it should be possible to calculate 1771 * them based on link frequency and resolution. 1772 */ 1773 if (bps_pr_lane != 594000000U) 1774 dev_warn(dev, "untested bps per lane: %u bps\n", bps_pr_lane); 1775 state->pdata.lineinitcnt = 0xe80; 1776 state->pdata.lptxtimecnt = 0x003; 1777 /* tclk-preparecnt: 3, tclk-zerocnt: 20 */ 1778 state->pdata.tclk_headercnt = 0x1403; 1779 state->pdata.tclk_trailcnt = 0x00; 1780 /* ths-preparecnt: 3, ths-zerocnt: 1 */ 1781 state->pdata.ths_headercnt = 0x0103; 1782 state->pdata.twakeup = 0x4882; 1783 state->pdata.tclk_postcnt = 0x008; 1784 state->pdata.ths_trailcnt = 0x2; 1785 state->pdata.hstxvregcnt = 0; 1786 1787 state->reset_gpio = devm_gpiod_get_optional(dev, "reset", 1788 GPIOD_OUT_LOW); 1789 if (IS_ERR(state->reset_gpio)) { 1790 dev_err(dev, "failed to get reset gpio\n"); 1791 ret = PTR_ERR(state->reset_gpio); 1792 goto disable_clk; 1793 } 1794 1795 if (state->reset_gpio) 1796 tc358743_gpio_reset(state); 1797 1798 ret = 0; 1799 goto free_endpoint; 1800 1801 disable_clk: 1802 clk_disable_unprepare(refclk); 1803 free_endpoint: 1804 v4l2_of_free_endpoint(endpoint); 1805 return ret; 1806 } 1807 #else 1808 static inline int tc358743_probe_of(struct tc358743_state *state) 1809 { 1810 return -ENODEV; 1811 } 1812 #endif 1813 1814 static int tc358743_probe(struct i2c_client *client, 1815 const struct i2c_device_id *id) 1816 { 1817 static struct v4l2_dv_timings default_timing = 1818 V4L2_DV_BT_CEA_640X480P59_94; 1819 struct tc358743_state *state; 1820 struct tc358743_platform_data *pdata = client->dev.platform_data; 1821 struct v4l2_subdev *sd; 1822 int err; 1823 1824 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 1825 return -EIO; 1826 v4l_dbg(1, debug, client, "chip found @ 0x%x (%s)\n", 1827 client->addr << 1, client->adapter->name); 1828 1829 state = devm_kzalloc(&client->dev, sizeof(struct tc358743_state), 1830 GFP_KERNEL); 1831 if (!state) 1832 return -ENOMEM; 1833 1834 state->i2c_client = client; 1835 1836 /* platform data */ 1837 if (pdata) { 1838 state->pdata = *pdata; 1839 state->bus.flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK; 1840 } else { 1841 err = tc358743_probe_of(state); 1842 if (err == -ENODEV) 1843 v4l_err(client, "No platform data!\n"); 1844 if (err) 1845 return err; 1846 } 1847 1848 sd = &state->sd; 1849 v4l2_i2c_subdev_init(sd, client, &tc358743_ops); 1850 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; 1851 1852 /* i2c access */ 1853 if ((i2c_rd16(sd, CHIPID) & MASK_CHIPID) != 0) { 1854 v4l2_info(sd, "not a TC358743 on address 0x%x\n", 1855 client->addr << 1); 1856 return -ENODEV; 1857 } 1858 1859 /* control handlers */ 1860 v4l2_ctrl_handler_init(&state->hdl, 3); 1861 1862 /* private controls */ 1863 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(&state->hdl, NULL, 1864 V4L2_CID_DV_RX_POWER_PRESENT, 0, 1, 0, 0); 1865 1866 /* custom controls */ 1867 state->audio_sampling_rate_ctrl = v4l2_ctrl_new_custom(&state->hdl, 1868 &tc358743_ctrl_audio_sampling_rate, NULL); 1869 1870 state->audio_present_ctrl = v4l2_ctrl_new_custom(&state->hdl, 1871 &tc358743_ctrl_audio_present, NULL); 1872 1873 sd->ctrl_handler = &state->hdl; 1874 if (state->hdl.error) { 1875 err = state->hdl.error; 1876 goto err_hdl; 1877 } 1878 1879 if (tc358743_update_controls(sd)) { 1880 err = -ENODEV; 1881 goto err_hdl; 1882 } 1883 1884 /* work queues */ 1885 state->work_queues = create_singlethread_workqueue(client->name); 1886 if (!state->work_queues) { 1887 v4l2_err(sd, "Could not create work queue\n"); 1888 err = -ENOMEM; 1889 goto err_hdl; 1890 } 1891 1892 state->pad.flags = MEDIA_PAD_FL_SOURCE; 1893 err = media_entity_pads_init(&sd->entity, 1, &state->pad); 1894 if (err < 0) 1895 goto err_hdl; 1896 1897 sd->dev = &client->dev; 1898 err = v4l2_async_register_subdev(sd); 1899 if (err < 0) 1900 goto err_hdl; 1901 1902 mutex_init(&state->confctl_mutex); 1903 1904 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, 1905 tc358743_delayed_work_enable_hotplug); 1906 1907 tc358743_initial_setup(sd); 1908 1909 tc358743_s_dv_timings(sd, &default_timing); 1910 1911 state->mbus_fmt_code = MEDIA_BUS_FMT_RGB888_1X24; 1912 tc358743_set_csi_color_space(sd); 1913 1914 tc358743_init_interrupts(sd); 1915 1916 if (state->i2c_client->irq) { 1917 err = devm_request_threaded_irq(&client->dev, 1918 state->i2c_client->irq, 1919 NULL, tc358743_irq_handler, 1920 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 1921 "tc358743", state); 1922 if (err) 1923 goto err_work_queues; 1924 } 1925 1926 tc358743_enable_interrupts(sd, tx_5v_power_present(sd)); 1927 i2c_wr16(sd, INTMASK, ~(MASK_HDMI_MSK | MASK_CSI_MSK) & 0xffff); 1928 1929 err = v4l2_ctrl_handler_setup(sd->ctrl_handler); 1930 if (err) 1931 goto err_work_queues; 1932 1933 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, 1934 client->addr << 1, client->adapter->name); 1935 1936 return 0; 1937 1938 err_work_queues: 1939 cancel_delayed_work(&state->delayed_work_enable_hotplug); 1940 destroy_workqueue(state->work_queues); 1941 mutex_destroy(&state->confctl_mutex); 1942 err_hdl: 1943 media_entity_cleanup(&sd->entity); 1944 v4l2_ctrl_handler_free(&state->hdl); 1945 return err; 1946 } 1947 1948 static int tc358743_remove(struct i2c_client *client) 1949 { 1950 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1951 struct tc358743_state *state = to_state(sd); 1952 1953 cancel_delayed_work(&state->delayed_work_enable_hotplug); 1954 destroy_workqueue(state->work_queues); 1955 v4l2_async_unregister_subdev(sd); 1956 v4l2_device_unregister_subdev(sd); 1957 mutex_destroy(&state->confctl_mutex); 1958 media_entity_cleanup(&sd->entity); 1959 v4l2_ctrl_handler_free(&state->hdl); 1960 1961 return 0; 1962 } 1963 1964 static struct i2c_device_id tc358743_id[] = { 1965 {"tc358743", 0}, 1966 {} 1967 }; 1968 1969 MODULE_DEVICE_TABLE(i2c, tc358743_id); 1970 1971 static struct i2c_driver tc358743_driver = { 1972 .driver = { 1973 .name = "tc358743", 1974 }, 1975 .probe = tc358743_probe, 1976 .remove = tc358743_remove, 1977 .id_table = tc358743_id, 1978 }; 1979 1980 module_i2c_driver(tc358743_driver); 1981