1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * IMI RDACM21 GMSL Camera Driver 4 * 5 * Copyright (C) 2017-2020 Jacopo Mondi 6 * Copyright (C) 2017-2019 Kieran Bingham 7 * Copyright (C) 2017-2019 Laurent Pinchart 8 * Copyright (C) 2017-2019 Niklas Söderlund 9 * Copyright (C) 2016 Renesas Electronics Corporation 10 * Copyright (C) 2015 Cogent Embedded, Inc. 11 */ 12 13 #include <linux/delay.h> 14 #include <linux/fwnode.h> 15 #include <linux/init.h> 16 #include <linux/i2c.h> 17 #include <linux/module.h> 18 #include <linux/slab.h> 19 #include <linux/videodev2.h> 20 21 #include <media/v4l2-async.h> 22 #include <media/v4l2-ctrls.h> 23 #include <media/v4l2-subdev.h> 24 #include "max9271.h" 25 26 #define MAX9271_RESET_CYCLES 10 27 28 #define OV490_I2C_ADDRESS 0x24 29 30 #define OV490_PAGE_HIGH_REG 0xfffd 31 #define OV490_PAGE_LOW_REG 0xfffe 32 33 /* 34 * The SCCB slave handling is undocumented; the registers naming scheme is 35 * totally arbitrary. 36 */ 37 #define OV490_SCCB_SLAVE_WRITE 0x00 38 #define OV490_SCCB_SLAVE_READ 0x01 39 #define OV490_SCCB_SLAVE0_DIR 0x80195000 40 #define OV490_SCCB_SLAVE0_ADDR_HIGH 0x80195001 41 #define OV490_SCCB_SLAVE0_ADDR_LOW 0x80195002 42 43 #define OV490_DVP_CTRL3 0x80286009 44 45 #define OV490_ODS_CTRL_FRAME_OUTPUT_EN 0x0c 46 #define OV490_ODS_CTRL 0x8029d000 47 48 #define OV490_HOST_CMD 0x808000c0 49 #define OV490_HOST_CMD_TRIGGER 0xc1 50 51 #define OV490_ID_VAL 0x0490 52 #define OV490_ID(_p, _v) ((((_p) & 0xff) << 8) | ((_v) & 0xff)) 53 #define OV490_PID 0x8080300a 54 #define OV490_VER 0x8080300b 55 #define OV490_PID_TIMEOUT 20 56 #define OV490_OUTPUT_EN_TIMEOUT 300 57 58 #define OV490_GPIO0 BIT(0) 59 #define OV490_SPWDN0 BIT(0) 60 #define OV490_GPIO_SEL0 0x80800050 61 #define OV490_GPIO_SEL1 0x80800051 62 #define OV490_GPIO_DIRECTION0 0x80800054 63 #define OV490_GPIO_DIRECTION1 0x80800055 64 #define OV490_GPIO_OUTPUT_VALUE0 0x80800058 65 #define OV490_GPIO_OUTPUT_VALUE1 0x80800059 66 67 #define OV490_ISP_HSIZE_LOW 0x80820060 68 #define OV490_ISP_HSIZE_HIGH 0x80820061 69 #define OV490_ISP_VSIZE_LOW 0x80820062 70 #define OV490_ISP_VSIZE_HIGH 0x80820063 71 72 #define OV10640_ID_HIGH 0xa6 73 #define OV10640_CHIP_ID 0x300a 74 #define OV10640_PIXEL_RATE 55000000 75 76 struct rdacm21_device { 77 struct device *dev; 78 struct max9271_device serializer; 79 struct i2c_client *isp; 80 struct v4l2_subdev sd; 81 struct media_pad pad; 82 struct v4l2_mbus_framefmt fmt; 83 struct v4l2_ctrl_handler ctrls; 84 u32 addrs[2]; 85 u16 last_page; 86 }; 87 88 static inline struct rdacm21_device *sd_to_rdacm21(struct v4l2_subdev *sd) 89 { 90 return container_of(sd, struct rdacm21_device, sd); 91 } 92 93 static const struct ov490_reg { 94 u16 reg; 95 u8 val; 96 } ov490_regs_wizard[] = { 97 {0xfffd, 0x80}, 98 {0xfffe, 0x82}, 99 {0x0071, 0x11}, 100 {0x0075, 0x11}, 101 {0xfffe, 0x29}, 102 {0x6010, 0x01}, 103 /* 104 * OV490 EMB line disable in YUV and RAW data, 105 * NOTE: EMB line is still used in ISP and sensor 106 */ 107 {0xe000, 0x14}, 108 {0xfffe, 0x28}, 109 {0x6000, 0x04}, 110 {0x6004, 0x00}, 111 /* 112 * PCLK polarity - useless due to silicon bug. 113 * Use 0x808000bb register instead. 114 */ 115 {0x6008, 0x00}, 116 {0xfffe, 0x80}, 117 {0x0091, 0x00}, 118 /* bit[3]=0 - PCLK polarity workaround. */ 119 {0x00bb, 0x1d}, 120 /* Ov490 FSIN: app_fsin_from_fsync */ 121 {0xfffe, 0x85}, 122 {0x0008, 0x00}, 123 {0x0009, 0x01}, 124 /* FSIN0 source. */ 125 {0x000A, 0x05}, 126 {0x000B, 0x00}, 127 /* FSIN0 delay. */ 128 {0x0030, 0x02}, 129 {0x0031, 0x00}, 130 {0x0032, 0x00}, 131 {0x0033, 0x00}, 132 /* FSIN1 delay. */ 133 {0x0038, 0x02}, 134 {0x0039, 0x00}, 135 {0x003A, 0x00}, 136 {0x003B, 0x00}, 137 /* FSIN0 length. */ 138 {0x0070, 0x2C}, 139 {0x0071, 0x01}, 140 {0x0072, 0x00}, 141 {0x0073, 0x00}, 142 /* FSIN1 length. */ 143 {0x0074, 0x64}, 144 {0x0075, 0x00}, 145 {0x0076, 0x00}, 146 {0x0077, 0x00}, 147 {0x0000, 0x14}, 148 {0x0001, 0x00}, 149 {0x0002, 0x00}, 150 {0x0003, 0x00}, 151 /* 152 * Load fsin0,load fsin1,load other, 153 * It will be cleared automatically. 154 */ 155 {0x0004, 0x32}, 156 {0x0005, 0x00}, 157 {0x0006, 0x00}, 158 {0x0007, 0x00}, 159 {0xfffe, 0x80}, 160 /* Sensor FSIN. */ 161 {0x0081, 0x00}, 162 /* ov10640 FSIN enable */ 163 {0xfffe, 0x19}, 164 {0x5000, 0x00}, 165 {0x5001, 0x30}, 166 {0x5002, 0x8c}, 167 {0x5003, 0xb2}, 168 {0xfffe, 0x80}, 169 {0x00c0, 0xc1}, 170 /* ov10640 HFLIP=1 by default */ 171 {0xfffe, 0x19}, 172 {0x5000, 0x01}, 173 {0x5001, 0x00}, 174 {0xfffe, 0x80}, 175 {0x00c0, 0xdc}, 176 }; 177 178 static int ov490_read(struct rdacm21_device *dev, u16 reg, u8 *val) 179 { 180 u8 buf[2] = { reg >> 8, reg }; 181 int ret; 182 183 ret = i2c_master_send(dev->isp, buf, 2); 184 if (ret == 2) 185 ret = i2c_master_recv(dev->isp, val, 1); 186 187 if (ret < 0) { 188 dev_dbg(dev->dev, "%s: register 0x%04x read failed (%d)\n", 189 __func__, reg, ret); 190 return ret; 191 } 192 193 return 0; 194 } 195 196 static int ov490_write(struct rdacm21_device *dev, u16 reg, u8 val) 197 { 198 u8 buf[3] = { reg >> 8, reg, val }; 199 int ret; 200 201 ret = i2c_master_send(dev->isp, buf, 3); 202 if (ret < 0) { 203 dev_err(dev->dev, "%s: register 0x%04x write failed (%d)\n", 204 __func__, reg, ret); 205 return ret; 206 } 207 208 return 0; 209 } 210 211 static int ov490_set_page(struct rdacm21_device *dev, u16 page) 212 { 213 u8 page_high = page >> 8; 214 u8 page_low = page; 215 int ret; 216 217 if (page == dev->last_page) 218 return 0; 219 220 if (page_high != (dev->last_page >> 8)) { 221 ret = ov490_write(dev, OV490_PAGE_HIGH_REG, page_high); 222 if (ret) 223 return ret; 224 } 225 226 if (page_low != (u8)dev->last_page) { 227 ret = ov490_write(dev, OV490_PAGE_LOW_REG, page_low); 228 if (ret) 229 return ret; 230 } 231 232 dev->last_page = page; 233 usleep_range(100, 150); 234 235 return 0; 236 } 237 238 static int ov490_read_reg(struct rdacm21_device *dev, u32 reg, u8 *val) 239 { 240 int ret; 241 242 ret = ov490_set_page(dev, reg >> 16); 243 if (ret) 244 return ret; 245 246 ret = ov490_read(dev, (u16)reg, val); 247 if (ret) 248 return ret; 249 250 dev_dbg(dev->dev, "%s: 0x%08x = 0x%02x\n", __func__, reg, *val); 251 252 return 0; 253 } 254 255 static int ov490_write_reg(struct rdacm21_device *dev, u32 reg, u8 val) 256 { 257 int ret; 258 259 ret = ov490_set_page(dev, reg >> 16); 260 if (ret) 261 return ret; 262 263 ret = ov490_write(dev, (u16)reg, val); 264 if (ret) 265 return ret; 266 267 dev_dbg(dev->dev, "%s: 0x%08x = 0x%02x\n", __func__, reg, val); 268 269 return 0; 270 } 271 272 static int rdacm21_s_stream(struct v4l2_subdev *sd, int enable) 273 { 274 struct rdacm21_device *dev = sd_to_rdacm21(sd); 275 276 /* 277 * Enable serial link now that the ISP provides a valid pixel clock 278 * to start serializing video data on the GMSL link. 279 */ 280 return max9271_set_serial_link(&dev->serializer, enable); 281 } 282 283 static int rdacm21_enum_mbus_code(struct v4l2_subdev *sd, 284 struct v4l2_subdev_pad_config *cfg, 285 struct v4l2_subdev_mbus_code_enum *code) 286 { 287 if (code->pad || code->index > 0) 288 return -EINVAL; 289 290 code->code = MEDIA_BUS_FMT_YUYV8_1X16; 291 292 return 0; 293 } 294 295 static int rdacm21_get_fmt(struct v4l2_subdev *sd, 296 struct v4l2_subdev_pad_config *cfg, 297 struct v4l2_subdev_format *format) 298 { 299 struct v4l2_mbus_framefmt *mf = &format->format; 300 struct rdacm21_device *dev = sd_to_rdacm21(sd); 301 302 if (format->pad) 303 return -EINVAL; 304 305 mf->width = dev->fmt.width; 306 mf->height = dev->fmt.height; 307 mf->code = MEDIA_BUS_FMT_YUYV8_1X16; 308 mf->colorspace = V4L2_COLORSPACE_SRGB; 309 mf->field = V4L2_FIELD_NONE; 310 mf->ycbcr_enc = V4L2_YCBCR_ENC_601; 311 mf->quantization = V4L2_QUANTIZATION_FULL_RANGE; 312 mf->xfer_func = V4L2_XFER_FUNC_NONE; 313 314 return 0; 315 } 316 317 static const struct v4l2_subdev_video_ops rdacm21_video_ops = { 318 .s_stream = rdacm21_s_stream, 319 }; 320 321 static const struct v4l2_subdev_pad_ops rdacm21_subdev_pad_ops = { 322 .enum_mbus_code = rdacm21_enum_mbus_code, 323 .get_fmt = rdacm21_get_fmt, 324 .set_fmt = rdacm21_get_fmt, 325 }; 326 327 static const struct v4l2_subdev_ops rdacm21_subdev_ops = { 328 .video = &rdacm21_video_ops, 329 .pad = &rdacm21_subdev_pad_ops, 330 }; 331 332 static int ov10640_initialize(struct rdacm21_device *dev) 333 { 334 u8 val; 335 336 /* Power-up OV10640 by setting RESETB and PWDNB pins high. */ 337 ov490_write_reg(dev, OV490_GPIO_SEL0, OV490_GPIO0); 338 ov490_write_reg(dev, OV490_GPIO_SEL1, OV490_SPWDN0); 339 ov490_write_reg(dev, OV490_GPIO_DIRECTION0, OV490_GPIO0); 340 ov490_write_reg(dev, OV490_GPIO_DIRECTION1, OV490_SPWDN0); 341 ov490_write_reg(dev, OV490_GPIO_OUTPUT_VALUE0, OV490_GPIO0); 342 ov490_write_reg(dev, OV490_GPIO_OUTPUT_VALUE0, OV490_SPWDN0); 343 usleep_range(3000, 5000); 344 345 /* Read OV10640 ID to test communications. */ 346 ov490_write_reg(dev, OV490_SCCB_SLAVE0_DIR, OV490_SCCB_SLAVE_READ); 347 ov490_write_reg(dev, OV490_SCCB_SLAVE0_ADDR_HIGH, OV10640_CHIP_ID >> 8); 348 ov490_write_reg(dev, OV490_SCCB_SLAVE0_ADDR_LOW, (u8)OV10640_CHIP_ID); 349 350 /* Trigger SCCB slave transaction and give it some time to complete. */ 351 ov490_write_reg(dev, OV490_HOST_CMD, OV490_HOST_CMD_TRIGGER); 352 usleep_range(1000, 1500); 353 354 ov490_read_reg(dev, OV490_SCCB_SLAVE0_DIR, &val); 355 if (val != OV10640_ID_HIGH) { 356 dev_err(dev->dev, "OV10640 ID mismatch: (0x%02x)\n", val); 357 return -ENODEV; 358 } 359 360 dev_dbg(dev->dev, "OV10640 ID = 0x%2x\n", val); 361 362 return 0; 363 } 364 365 static int ov490_initialize(struct rdacm21_device *dev) 366 { 367 u8 pid, ver, val; 368 unsigned int i; 369 int ret; 370 371 /* 372 * Read OV490 Id to test communications. Give it up to 40msec to 373 * exit from reset. 374 */ 375 for (i = 0; i < OV490_PID_TIMEOUT; ++i) { 376 ret = ov490_read_reg(dev, OV490_PID, &pid); 377 if (ret == 0) 378 break; 379 usleep_range(1000, 2000); 380 } 381 if (i == OV490_PID_TIMEOUT) { 382 dev_err(dev->dev, "OV490 PID read failed (%d)\n", ret); 383 return ret; 384 } 385 386 ret = ov490_read_reg(dev, OV490_VER, &ver); 387 if (ret < 0) 388 return ret; 389 390 if (OV490_ID(pid, ver) != OV490_ID_VAL) { 391 dev_err(dev->dev, "OV490 ID mismatch (0x%04x)\n", 392 OV490_ID(pid, ver)); 393 return -ENODEV; 394 } 395 396 /* Wait for firmware boot by reading streamon status. */ 397 for (i = 0; i < OV490_OUTPUT_EN_TIMEOUT; ++i) { 398 ov490_read_reg(dev, OV490_ODS_CTRL, &val); 399 if (val == OV490_ODS_CTRL_FRAME_OUTPUT_EN) 400 break; 401 usleep_range(1000, 2000); 402 } 403 if (i == OV490_OUTPUT_EN_TIMEOUT) { 404 dev_err(dev->dev, "Timeout waiting for firmware boot\n"); 405 return -ENODEV; 406 } 407 408 ret = ov10640_initialize(dev); 409 if (ret) 410 return ret; 411 412 /* Program OV490 with register-value table. */ 413 for (i = 0; i < ARRAY_SIZE(ov490_regs_wizard); ++i) { 414 ret = ov490_write(dev, ov490_regs_wizard[i].reg, 415 ov490_regs_wizard[i].val); 416 if (ret < 0) { 417 dev_err(dev->dev, 418 "%s: register %u (0x%04x) write failed (%d)\n", 419 __func__, i, ov490_regs_wizard[i].reg, ret); 420 421 return -EIO; 422 } 423 424 usleep_range(100, 150); 425 } 426 427 /* 428 * The ISP is programmed with the content of a serial flash memory. 429 * Read the firmware configuration to reflect it through the V4L2 APIs. 430 */ 431 ov490_read_reg(dev, OV490_ISP_HSIZE_HIGH, &val); 432 dev->fmt.width = (val & 0xf) << 8; 433 ov490_read_reg(dev, OV490_ISP_HSIZE_LOW, &val); 434 dev->fmt.width |= (val & 0xff); 435 436 ov490_read_reg(dev, OV490_ISP_VSIZE_HIGH, &val); 437 dev->fmt.height = (val & 0xf) << 8; 438 ov490_read_reg(dev, OV490_ISP_VSIZE_LOW, &val); 439 dev->fmt.height |= val & 0xff; 440 441 /* Set bus width to 12 bits with [0:11] ordering. */ 442 ov490_write_reg(dev, OV490_DVP_CTRL3, 0x10); 443 444 dev_info(dev->dev, "Identified RDACM21 camera module\n"); 445 446 return 0; 447 } 448 449 static int rdacm21_initialize(struct rdacm21_device *dev) 450 { 451 int ret; 452 453 /* Verify communication with the MAX9271: ping to wakeup. */ 454 dev->serializer.client->addr = MAX9271_DEFAULT_ADDR; 455 i2c_smbus_read_byte(dev->serializer.client); 456 usleep_range(3000, 5000); 457 458 /* Enable reverse channel and disable the serial link. */ 459 ret = max9271_set_serial_link(&dev->serializer, false); 460 if (ret) 461 return ret; 462 463 /* Configure I2C bus at 105Kbps speed and configure GMSL. */ 464 ret = max9271_configure_i2c(&dev->serializer, 465 MAX9271_I2CSLVSH_469NS_234NS | 466 MAX9271_I2CSLVTO_1024US | 467 MAX9271_I2CMSTBT_105KBPS); 468 if (ret) 469 return ret; 470 471 ret = max9271_verify_id(&dev->serializer); 472 if (ret) 473 return ret; 474 475 /* Enable GPIO1 and hold OV490 in reset during max9271 configuration. */ 476 ret = max9271_enable_gpios(&dev->serializer, MAX9271_GPIO1OUT); 477 if (ret) 478 return ret; 479 480 ret = max9271_clear_gpios(&dev->serializer, MAX9271_GPIO1OUT); 481 if (ret) 482 return ret; 483 484 ret = max9271_configure_gmsl_link(&dev->serializer); 485 if (ret) 486 return ret; 487 488 ret = max9271_set_address(&dev->serializer, dev->addrs[0]); 489 if (ret) 490 return ret; 491 dev->serializer.client->addr = dev->addrs[0]; 492 493 ret = max9271_set_translation(&dev->serializer, dev->addrs[1], 494 OV490_I2C_ADDRESS); 495 if (ret) 496 return ret; 497 dev->isp->addr = dev->addrs[1]; 498 499 /* Release OV490 from reset and initialize it. */ 500 ret = max9271_set_gpios(&dev->serializer, MAX9271_GPIO1OUT); 501 if (ret) 502 return ret; 503 usleep_range(3000, 5000); 504 505 ret = ov490_initialize(dev); 506 if (ret) 507 return ret; 508 509 /* 510 * Set reverse channel high threshold to increase noise immunity. 511 * 512 * This should be compensated by increasing the reverse channel 513 * amplitude on the remote deserializer side. 514 */ 515 return max9271_set_high_threshold(&dev->serializer, true); 516 } 517 518 static int rdacm21_probe(struct i2c_client *client) 519 { 520 struct rdacm21_device *dev; 521 struct fwnode_handle *ep; 522 int ret; 523 524 dev = devm_kzalloc(&client->dev, sizeof(*dev), GFP_KERNEL); 525 if (!dev) 526 return -ENOMEM; 527 dev->dev = &client->dev; 528 dev->serializer.client = client; 529 530 ret = of_property_read_u32_array(client->dev.of_node, "reg", 531 dev->addrs, 2); 532 if (ret < 0) { 533 dev_err(dev->dev, "Invalid DT reg property: %d\n", ret); 534 return -EINVAL; 535 } 536 537 /* Create the dummy I2C client for the sensor. */ 538 dev->isp = i2c_new_dummy_device(client->adapter, OV490_I2C_ADDRESS); 539 if (IS_ERR(dev->isp)) 540 return PTR_ERR(dev->isp); 541 542 ret = rdacm21_initialize(dev); 543 if (ret < 0) 544 goto error; 545 546 /* Initialize and register the subdevice. */ 547 v4l2_i2c_subdev_init(&dev->sd, client, &rdacm21_subdev_ops); 548 dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 549 550 v4l2_ctrl_handler_init(&dev->ctrls, 1); 551 v4l2_ctrl_new_std(&dev->ctrls, NULL, V4L2_CID_PIXEL_RATE, 552 OV10640_PIXEL_RATE, OV10640_PIXEL_RATE, 1, 553 OV10640_PIXEL_RATE); 554 dev->sd.ctrl_handler = &dev->ctrls; 555 556 ret = dev->ctrls.error; 557 if (ret) 558 goto error_free_ctrls; 559 560 dev->pad.flags = MEDIA_PAD_FL_SOURCE; 561 dev->sd.entity.flags |= MEDIA_ENT_F_CAM_SENSOR; 562 ret = media_entity_pads_init(&dev->sd.entity, 1, &dev->pad); 563 if (ret < 0) 564 goto error_free_ctrls; 565 566 ep = fwnode_graph_get_next_endpoint(dev_fwnode(&client->dev), NULL); 567 if (!ep) { 568 dev_err(&client->dev, 569 "Unable to get endpoint in node %pOF\n", 570 client->dev.of_node); 571 ret = -ENOENT; 572 goto error_free_ctrls; 573 } 574 dev->sd.fwnode = ep; 575 576 ret = v4l2_async_register_subdev(&dev->sd); 577 if (ret) 578 goto error_put_node; 579 580 return 0; 581 582 error_put_node: 583 fwnode_handle_put(dev->sd.fwnode); 584 error_free_ctrls: 585 v4l2_ctrl_handler_free(&dev->ctrls); 586 error: 587 i2c_unregister_device(dev->isp); 588 589 return ret; 590 } 591 592 static int rdacm21_remove(struct i2c_client *client) 593 { 594 struct rdacm21_device *dev = sd_to_rdacm21(i2c_get_clientdata(client)); 595 596 v4l2_async_unregister_subdev(&dev->sd); 597 v4l2_ctrl_handler_free(&dev->ctrls); 598 i2c_unregister_device(dev->isp); 599 fwnode_handle_put(dev->sd.fwnode); 600 601 return 0; 602 } 603 604 static const struct of_device_id rdacm21_of_ids[] = { 605 { .compatible = "imi,rdacm21" }, 606 { } 607 }; 608 MODULE_DEVICE_TABLE(of, rdacm21_of_ids); 609 610 static struct i2c_driver rdacm21_i2c_driver = { 611 .driver = { 612 .name = "rdacm21", 613 .of_match_table = rdacm21_of_ids, 614 }, 615 .probe_new = rdacm21_probe, 616 .remove = rdacm21_remove, 617 }; 618 619 module_i2c_driver(rdacm21_i2c_driver); 620 621 MODULE_DESCRIPTION("GMSL Camera driver for RDACM21"); 622 MODULE_AUTHOR("Jacopo Mondi"); 623 MODULE_LICENSE("GPL v2"); 624