1 /* 2 * OmniVision OV96xx Camera Header File 3 * 4 * Copyright (C) 2009 Marek Vasut <marek.vasut@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef __DRIVERS_MEDIA_VIDEO_OV9640_H__ 12 #define __DRIVERS_MEDIA_VIDEO_OV9640_H__ 13 14 /* Register definitions */ 15 #define OV9640_GAIN 0x00 16 #define OV9640_BLUE 0x01 17 #define OV9640_RED 0x02 18 #define OV9640_VFER 0x03 19 #define OV9640_COM1 0x04 20 #define OV9640_BAVE 0x05 21 #define OV9640_GEAVE 0x06 22 #define OV9640_RSID 0x07 23 #define OV9640_RAVE 0x08 24 #define OV9640_COM2 0x09 25 #define OV9640_PID 0x0a 26 #define OV9640_VER 0x0b 27 #define OV9640_COM3 0x0c 28 #define OV9640_COM4 0x0d 29 #define OV9640_COM5 0x0e 30 #define OV9640_COM6 0x0f 31 #define OV9640_AECH 0x10 32 #define OV9640_CLKRC 0x11 33 #define OV9640_COM7 0x12 34 #define OV9640_COM8 0x13 35 #define OV9640_COM9 0x14 36 #define OV9640_COM10 0x15 37 /* 0x16 - RESERVED */ 38 #define OV9640_HSTART 0x17 39 #define OV9640_HSTOP 0x18 40 #define OV9640_VSTART 0x19 41 #define OV9640_VSTOP 0x1a 42 #define OV9640_PSHFT 0x1b 43 #define OV9640_MIDH 0x1c 44 #define OV9640_MIDL 0x1d 45 #define OV9640_MVFP 0x1e 46 #define OV9640_LAEC 0x1f 47 #define OV9640_BOS 0x20 48 #define OV9640_GBOS 0x21 49 #define OV9640_GROS 0x22 50 #define OV9640_ROS 0x23 51 #define OV9640_AEW 0x24 52 #define OV9640_AEB 0x25 53 #define OV9640_VPT 0x26 54 #define OV9640_BBIAS 0x27 55 #define OV9640_GBBIAS 0x28 56 /* 0x29 - RESERVED */ 57 #define OV9640_EXHCH 0x2a 58 #define OV9640_EXHCL 0x2b 59 #define OV9640_RBIAS 0x2c 60 #define OV9640_ADVFL 0x2d 61 #define OV9640_ADVFH 0x2e 62 #define OV9640_YAVE 0x2f 63 #define OV9640_HSYST 0x30 64 #define OV9640_HSYEN 0x31 65 #define OV9640_HREF 0x32 66 #define OV9640_CHLF 0x33 67 #define OV9640_ARBLM 0x34 68 /* 0x35..0x36 - RESERVED */ 69 #define OV9640_ADC 0x37 70 #define OV9640_ACOM 0x38 71 #define OV9640_OFON 0x39 72 #define OV9640_TSLB 0x3a 73 #define OV9640_COM11 0x3b 74 #define OV9640_COM12 0x3c 75 #define OV9640_COM13 0x3d 76 #define OV9640_COM14 0x3e 77 #define OV9640_EDGE 0x3f 78 #define OV9640_COM15 0x40 79 #define OV9640_COM16 0x41 80 #define OV9640_COM17 0x42 81 /* 0x43..0x4e - RESERVED */ 82 #define OV9640_MTX1 0x4f 83 #define OV9640_MTX2 0x50 84 #define OV9640_MTX3 0x51 85 #define OV9640_MTX4 0x52 86 #define OV9640_MTX5 0x53 87 #define OV9640_MTX6 0x54 88 #define OV9640_MTX7 0x55 89 #define OV9640_MTX8 0x56 90 #define OV9640_MTX9 0x57 91 #define OV9640_MTXS 0x58 92 /* 0x59..0x61 - RESERVED */ 93 #define OV9640_LCC1 0x62 94 #define OV9640_LCC2 0x63 95 #define OV9640_LCC3 0x64 96 #define OV9640_LCC4 0x65 97 #define OV9640_LCC5 0x66 98 #define OV9640_MANU 0x67 99 #define OV9640_MANV 0x68 100 #define OV9640_HV 0x69 101 #define OV9640_MBD 0x6a 102 #define OV9640_DBLV 0x6b 103 #define OV9640_GSP 0x6c /* ... till 0x7b */ 104 #define OV9640_GST 0x7c /* ... till 0x8a */ 105 106 #define OV9640_CLKRC_DPLL_EN 0x80 107 #define OV9640_CLKRC_DIRECT 0x40 108 #define OV9640_CLKRC_DIV(x) ((x) & 0x3f) 109 110 #define OV9640_PSHFT_VAL(x) ((x) & 0xff) 111 112 #define OV9640_ACOM_2X_ANALOG 0x80 113 #define OV9640_ACOM_RSVD 0x12 114 115 #define OV9640_MVFP_V 0x10 116 #define OV9640_MVFP_H 0x20 117 118 #define OV9640_COM1_HREF_NOSKIP 0x00 119 #define OV9640_COM1_HREF_2SKIP 0x04 120 #define OV9640_COM1_HREF_3SKIP 0x08 121 #define OV9640_COM1_QQFMT 0x20 122 123 #define OV9640_COM2_SSM 0x10 124 125 #define OV9640_COM3_VP 0x04 126 127 #define OV9640_COM4_QQ_VP 0x80 128 #define OV9640_COM4_RSVD 0x40 129 130 #define OV9640_COM5_SYSCLK 0x80 131 #define OV9640_COM5_LONGEXP 0x01 132 133 #define OV9640_COM6_OPT_BLC 0x40 134 #define OV9640_COM6_ADBLC_BIAS 0x08 135 #define OV9640_COM6_FMT_RST 0x82 136 #define OV9640_COM6_ADBLC_OPTEN 0x01 137 138 #define OV9640_COM7_RAW_RGB 0x01 139 #define OV9640_COM7_RGB 0x04 140 #define OV9640_COM7_QCIF 0x08 141 #define OV9640_COM7_QVGA 0x10 142 #define OV9640_COM7_CIF 0x20 143 #define OV9640_COM7_VGA 0x40 144 #define OV9640_COM7_SCCB_RESET 0x80 145 146 #define OV9640_TSLB_YVYU_YUYV 0x04 147 #define OV9640_TSLB_YUYV_UYVY 0x08 148 149 #define OV9640_COM12_YUV_AVG 0x04 150 #define OV9640_COM12_RSVD 0x40 151 152 #define OV9640_COM13_GAMMA_NONE 0x00 153 #define OV9640_COM13_GAMMA_Y 0x40 154 #define OV9640_COM13_GAMMA_RAW 0x80 155 #define OV9640_COM13_RGB_AVG 0x20 156 #define OV9640_COM13_MATRIX_EN 0x10 157 #define OV9640_COM13_Y_DELAY_EN 0x08 158 #define OV9640_COM13_YUV_DLY(x) ((x) & 0x07) 159 160 #define OV9640_COM15_OR_00FF 0x00 161 #define OV9640_COM15_OR_01FE 0x40 162 #define OV9640_COM15_OR_10F0 0xc0 163 #define OV9640_COM15_RGB_NORM 0x00 164 #define OV9640_COM15_RGB_565 0x10 165 #define OV9640_COM15_RGB_555 0x30 166 167 #define OV9640_COM16_RB_AVG 0x01 168 169 /* IDs */ 170 #define OV9640_V2 0x9648 171 #define OV9640_V3 0x9649 172 #define VERSION(pid, ver) (((pid) << 8) | ((ver) & 0xFF)) 173 174 /* supported resolutions */ 175 enum { 176 W_QQCIF = 88, 177 W_QQVGA = 160, 178 W_QCIF = 176, 179 W_QVGA = 320, 180 W_CIF = 352, 181 W_VGA = 640, 182 W_SXGA = 1280 183 }; 184 #define H_SXGA 960 185 186 /* Misc. structures */ 187 struct ov9640_reg_alt { 188 u8 com7; 189 u8 com12; 190 u8 com13; 191 u8 com15; 192 }; 193 194 struct ov9640_reg { 195 u8 reg; 196 u8 val; 197 }; 198 199 struct ov9640_priv { 200 struct v4l2_subdev subdev; 201 struct v4l2_ctrl_handler hdl; 202 struct v4l2_clk *clk; 203 204 int model; 205 int revision; 206 }; 207 208 #endif /* __DRIVERS_MEDIA_VIDEO_OV9640_H__ */ 209