1f8de593dSPetr Cvek /* SPDX-License-Identifier: GPL-2.0 */ 257b0ad9eSPetr Cvek /* 357b0ad9eSPetr Cvek * OmniVision OV96xx Camera Header File 457b0ad9eSPetr Cvek * 557b0ad9eSPetr Cvek * Copyright (C) 2009 Marek Vasut <marek.vasut@gmail.com> 657b0ad9eSPetr Cvek */ 757b0ad9eSPetr Cvek 857b0ad9eSPetr Cvek #ifndef __DRIVERS_MEDIA_VIDEO_OV9640_H__ 957b0ad9eSPetr Cvek #define __DRIVERS_MEDIA_VIDEO_OV9640_H__ 1057b0ad9eSPetr Cvek 1157b0ad9eSPetr Cvek /* Register definitions */ 1257b0ad9eSPetr Cvek #define OV9640_GAIN 0x00 1357b0ad9eSPetr Cvek #define OV9640_BLUE 0x01 1457b0ad9eSPetr Cvek #define OV9640_RED 0x02 1557b0ad9eSPetr Cvek #define OV9640_VFER 0x03 1657b0ad9eSPetr Cvek #define OV9640_COM1 0x04 1757b0ad9eSPetr Cvek #define OV9640_BAVE 0x05 1857b0ad9eSPetr Cvek #define OV9640_GEAVE 0x06 1957b0ad9eSPetr Cvek #define OV9640_RSID 0x07 2057b0ad9eSPetr Cvek #define OV9640_RAVE 0x08 2157b0ad9eSPetr Cvek #define OV9640_COM2 0x09 2257b0ad9eSPetr Cvek #define OV9640_PID 0x0a 2357b0ad9eSPetr Cvek #define OV9640_VER 0x0b 2457b0ad9eSPetr Cvek #define OV9640_COM3 0x0c 2557b0ad9eSPetr Cvek #define OV9640_COM4 0x0d 2657b0ad9eSPetr Cvek #define OV9640_COM5 0x0e 2757b0ad9eSPetr Cvek #define OV9640_COM6 0x0f 2857b0ad9eSPetr Cvek #define OV9640_AECH 0x10 2957b0ad9eSPetr Cvek #define OV9640_CLKRC 0x11 3057b0ad9eSPetr Cvek #define OV9640_COM7 0x12 3157b0ad9eSPetr Cvek #define OV9640_COM8 0x13 3257b0ad9eSPetr Cvek #define OV9640_COM9 0x14 3357b0ad9eSPetr Cvek #define OV9640_COM10 0x15 3457b0ad9eSPetr Cvek /* 0x16 - RESERVED */ 3557b0ad9eSPetr Cvek #define OV9640_HSTART 0x17 3657b0ad9eSPetr Cvek #define OV9640_HSTOP 0x18 3757b0ad9eSPetr Cvek #define OV9640_VSTART 0x19 3857b0ad9eSPetr Cvek #define OV9640_VSTOP 0x1a 3957b0ad9eSPetr Cvek #define OV9640_PSHFT 0x1b 4057b0ad9eSPetr Cvek #define OV9640_MIDH 0x1c 4157b0ad9eSPetr Cvek #define OV9640_MIDL 0x1d 4257b0ad9eSPetr Cvek #define OV9640_MVFP 0x1e 4357b0ad9eSPetr Cvek #define OV9640_LAEC 0x1f 4457b0ad9eSPetr Cvek #define OV9640_BOS 0x20 4557b0ad9eSPetr Cvek #define OV9640_GBOS 0x21 4657b0ad9eSPetr Cvek #define OV9640_GROS 0x22 4757b0ad9eSPetr Cvek #define OV9640_ROS 0x23 4857b0ad9eSPetr Cvek #define OV9640_AEW 0x24 4957b0ad9eSPetr Cvek #define OV9640_AEB 0x25 5057b0ad9eSPetr Cvek #define OV9640_VPT 0x26 5157b0ad9eSPetr Cvek #define OV9640_BBIAS 0x27 5257b0ad9eSPetr Cvek #define OV9640_GBBIAS 0x28 5357b0ad9eSPetr Cvek /* 0x29 - RESERVED */ 5457b0ad9eSPetr Cvek #define OV9640_EXHCH 0x2a 5557b0ad9eSPetr Cvek #define OV9640_EXHCL 0x2b 5657b0ad9eSPetr Cvek #define OV9640_RBIAS 0x2c 5757b0ad9eSPetr Cvek #define OV9640_ADVFL 0x2d 5857b0ad9eSPetr Cvek #define OV9640_ADVFH 0x2e 5957b0ad9eSPetr Cvek #define OV9640_YAVE 0x2f 6057b0ad9eSPetr Cvek #define OV9640_HSYST 0x30 6157b0ad9eSPetr Cvek #define OV9640_HSYEN 0x31 6257b0ad9eSPetr Cvek #define OV9640_HREF 0x32 6357b0ad9eSPetr Cvek #define OV9640_CHLF 0x33 6457b0ad9eSPetr Cvek #define OV9640_ARBLM 0x34 6557b0ad9eSPetr Cvek /* 0x35..0x36 - RESERVED */ 6657b0ad9eSPetr Cvek #define OV9640_ADC 0x37 6757b0ad9eSPetr Cvek #define OV9640_ACOM 0x38 6857b0ad9eSPetr Cvek #define OV9640_OFON 0x39 6957b0ad9eSPetr Cvek #define OV9640_TSLB 0x3a 7057b0ad9eSPetr Cvek #define OV9640_COM11 0x3b 7157b0ad9eSPetr Cvek #define OV9640_COM12 0x3c 7257b0ad9eSPetr Cvek #define OV9640_COM13 0x3d 7357b0ad9eSPetr Cvek #define OV9640_COM14 0x3e 7457b0ad9eSPetr Cvek #define OV9640_EDGE 0x3f 7557b0ad9eSPetr Cvek #define OV9640_COM15 0x40 7657b0ad9eSPetr Cvek #define OV9640_COM16 0x41 7757b0ad9eSPetr Cvek #define OV9640_COM17 0x42 7857b0ad9eSPetr Cvek /* 0x43..0x4e - RESERVED */ 7957b0ad9eSPetr Cvek #define OV9640_MTX1 0x4f 8057b0ad9eSPetr Cvek #define OV9640_MTX2 0x50 8157b0ad9eSPetr Cvek #define OV9640_MTX3 0x51 8257b0ad9eSPetr Cvek #define OV9640_MTX4 0x52 8357b0ad9eSPetr Cvek #define OV9640_MTX5 0x53 8457b0ad9eSPetr Cvek #define OV9640_MTX6 0x54 8557b0ad9eSPetr Cvek #define OV9640_MTX7 0x55 8657b0ad9eSPetr Cvek #define OV9640_MTX8 0x56 8757b0ad9eSPetr Cvek #define OV9640_MTX9 0x57 8857b0ad9eSPetr Cvek #define OV9640_MTXS 0x58 8957b0ad9eSPetr Cvek /* 0x59..0x61 - RESERVED */ 9057b0ad9eSPetr Cvek #define OV9640_LCC1 0x62 9157b0ad9eSPetr Cvek #define OV9640_LCC2 0x63 9257b0ad9eSPetr Cvek #define OV9640_LCC3 0x64 9357b0ad9eSPetr Cvek #define OV9640_LCC4 0x65 9457b0ad9eSPetr Cvek #define OV9640_LCC5 0x66 9557b0ad9eSPetr Cvek #define OV9640_MANU 0x67 9657b0ad9eSPetr Cvek #define OV9640_MANV 0x68 9757b0ad9eSPetr Cvek #define OV9640_HV 0x69 9857b0ad9eSPetr Cvek #define OV9640_MBD 0x6a 9957b0ad9eSPetr Cvek #define OV9640_DBLV 0x6b 10057b0ad9eSPetr Cvek #define OV9640_GSP 0x6c /* ... till 0x7b */ 10157b0ad9eSPetr Cvek #define OV9640_GST 0x7c /* ... till 0x8a */ 10257b0ad9eSPetr Cvek 10357b0ad9eSPetr Cvek #define OV9640_CLKRC_DPLL_EN 0x80 10457b0ad9eSPetr Cvek #define OV9640_CLKRC_DIRECT 0x40 10557b0ad9eSPetr Cvek #define OV9640_CLKRC_DIV(x) ((x) & 0x3f) 10657b0ad9eSPetr Cvek 10757b0ad9eSPetr Cvek #define OV9640_PSHFT_VAL(x) ((x) & 0xff) 10857b0ad9eSPetr Cvek 10957b0ad9eSPetr Cvek #define OV9640_ACOM_2X_ANALOG 0x80 11057b0ad9eSPetr Cvek #define OV9640_ACOM_RSVD 0x12 11157b0ad9eSPetr Cvek 11257b0ad9eSPetr Cvek #define OV9640_MVFP_V 0x10 11357b0ad9eSPetr Cvek #define OV9640_MVFP_H 0x20 11457b0ad9eSPetr Cvek 11557b0ad9eSPetr Cvek #define OV9640_COM1_HREF_NOSKIP 0x00 11657b0ad9eSPetr Cvek #define OV9640_COM1_HREF_2SKIP 0x04 11757b0ad9eSPetr Cvek #define OV9640_COM1_HREF_3SKIP 0x08 11857b0ad9eSPetr Cvek #define OV9640_COM1_QQFMT 0x20 11957b0ad9eSPetr Cvek 12057b0ad9eSPetr Cvek #define OV9640_COM2_SSM 0x10 12157b0ad9eSPetr Cvek 12257b0ad9eSPetr Cvek #define OV9640_COM3_VP 0x04 12357b0ad9eSPetr Cvek 12457b0ad9eSPetr Cvek #define OV9640_COM4_QQ_VP 0x80 12557b0ad9eSPetr Cvek #define OV9640_COM4_RSVD 0x40 12657b0ad9eSPetr Cvek 12757b0ad9eSPetr Cvek #define OV9640_COM5_SYSCLK 0x80 12857b0ad9eSPetr Cvek #define OV9640_COM5_LONGEXP 0x01 12957b0ad9eSPetr Cvek 13057b0ad9eSPetr Cvek #define OV9640_COM6_OPT_BLC 0x40 13157b0ad9eSPetr Cvek #define OV9640_COM6_ADBLC_BIAS 0x08 13257b0ad9eSPetr Cvek #define OV9640_COM6_FMT_RST 0x82 13357b0ad9eSPetr Cvek #define OV9640_COM6_ADBLC_OPTEN 0x01 13457b0ad9eSPetr Cvek 13557b0ad9eSPetr Cvek #define OV9640_COM7_RAW_RGB 0x01 13657b0ad9eSPetr Cvek #define OV9640_COM7_RGB 0x04 13757b0ad9eSPetr Cvek #define OV9640_COM7_QCIF 0x08 13857b0ad9eSPetr Cvek #define OV9640_COM7_QVGA 0x10 13957b0ad9eSPetr Cvek #define OV9640_COM7_CIF 0x20 14057b0ad9eSPetr Cvek #define OV9640_COM7_VGA 0x40 14157b0ad9eSPetr Cvek #define OV9640_COM7_SCCB_RESET 0x80 14257b0ad9eSPetr Cvek 14357b0ad9eSPetr Cvek #define OV9640_TSLB_YVYU_YUYV 0x04 14457b0ad9eSPetr Cvek #define OV9640_TSLB_YUYV_UYVY 0x08 14557b0ad9eSPetr Cvek 14657b0ad9eSPetr Cvek #define OV9640_COM12_YUV_AVG 0x04 14757b0ad9eSPetr Cvek #define OV9640_COM12_RSVD 0x40 14857b0ad9eSPetr Cvek 14957b0ad9eSPetr Cvek #define OV9640_COM13_GAMMA_NONE 0x00 15057b0ad9eSPetr Cvek #define OV9640_COM13_GAMMA_Y 0x40 15157b0ad9eSPetr Cvek #define OV9640_COM13_GAMMA_RAW 0x80 15257b0ad9eSPetr Cvek #define OV9640_COM13_RGB_AVG 0x20 15357b0ad9eSPetr Cvek #define OV9640_COM13_MATRIX_EN 0x10 15457b0ad9eSPetr Cvek #define OV9640_COM13_Y_DELAY_EN 0x08 15557b0ad9eSPetr Cvek #define OV9640_COM13_YUV_DLY(x) ((x) & 0x07) 15657b0ad9eSPetr Cvek 15757b0ad9eSPetr Cvek #define OV9640_COM15_OR_00FF 0x00 15857b0ad9eSPetr Cvek #define OV9640_COM15_OR_01FE 0x40 15957b0ad9eSPetr Cvek #define OV9640_COM15_OR_10F0 0xc0 16057b0ad9eSPetr Cvek #define OV9640_COM15_RGB_NORM 0x00 16157b0ad9eSPetr Cvek #define OV9640_COM15_RGB_565 0x10 16257b0ad9eSPetr Cvek #define OV9640_COM15_RGB_555 0x30 16357b0ad9eSPetr Cvek 16457b0ad9eSPetr Cvek #define OV9640_COM16_RB_AVG 0x01 16557b0ad9eSPetr Cvek 16657b0ad9eSPetr Cvek /* IDs */ 16757b0ad9eSPetr Cvek #define OV9640_V2 0x9648 16857b0ad9eSPetr Cvek #define OV9640_V3 0x9649 16957b0ad9eSPetr Cvek #define VERSION(pid, ver) (((pid) << 8) | ((ver) & 0xFF)) 17057b0ad9eSPetr Cvek 17157b0ad9eSPetr Cvek /* supported resolutions */ 17257b0ad9eSPetr Cvek enum { 17357b0ad9eSPetr Cvek W_QQCIF = 88, 17457b0ad9eSPetr Cvek W_QQVGA = 160, 17557b0ad9eSPetr Cvek W_QCIF = 176, 17657b0ad9eSPetr Cvek W_QVGA = 320, 17757b0ad9eSPetr Cvek W_CIF = 352, 17857b0ad9eSPetr Cvek W_VGA = 640, 17957b0ad9eSPetr Cvek W_SXGA = 1280 18057b0ad9eSPetr Cvek }; 18157b0ad9eSPetr Cvek #define H_SXGA 960 18257b0ad9eSPetr Cvek 18357b0ad9eSPetr Cvek /* Misc. structures */ 18457b0ad9eSPetr Cvek struct ov9640_reg_alt { 18557b0ad9eSPetr Cvek u8 com7; 18657b0ad9eSPetr Cvek u8 com12; 18757b0ad9eSPetr Cvek u8 com13; 18857b0ad9eSPetr Cvek u8 com15; 18957b0ad9eSPetr Cvek }; 19057b0ad9eSPetr Cvek 19157b0ad9eSPetr Cvek struct ov9640_reg { 19257b0ad9eSPetr Cvek u8 reg; 19357b0ad9eSPetr Cvek u8 val; 19457b0ad9eSPetr Cvek }; 19557b0ad9eSPetr Cvek 19657b0ad9eSPetr Cvek struct ov9640_priv { 19757b0ad9eSPetr Cvek struct v4l2_subdev subdev; 19857b0ad9eSPetr Cvek struct v4l2_ctrl_handler hdl; 199*8de14b3aSEzequiel Garcia struct clk *clk; 2009f7e55d2SPetr Cvek struct gpio_desc *gpio_power; 2019f7e55d2SPetr Cvek struct gpio_desc *gpio_reset; 20257b0ad9eSPetr Cvek 20357b0ad9eSPetr Cvek int model; 20457b0ad9eSPetr Cvek int revision; 20557b0ad9eSPetr Cvek }; 20657b0ad9eSPetr Cvek 20757b0ad9eSPetr Cvek #endif /* __DRIVERS_MEDIA_VIDEO_OV9640_H__ */ 208