1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright 2020 Kévin L'hôpital <kevin.lhopital@bootlin.com> 4 * Copyright 2020 Bootlin 5 * Author: Paul Kocialkowski <paul.kocialkowski@bootlin.com> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/device.h> 11 #include <linux/i2c.h> 12 #include <linux/mod_devicetable.h> 13 #include <linux/module.h> 14 #include <linux/of_graph.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regulator/consumer.h> 17 #include <linux/videodev2.h> 18 #include <media/v4l2-ctrls.h> 19 #include <media/v4l2-device.h> 20 #include <media/v4l2-fwnode.h> 21 #include <media/v4l2-image-sizes.h> 22 #include <media/v4l2-mediabus.h> 23 24 /* Register definitions */ 25 26 /* System */ 27 28 #define OV8865_SW_STANDBY_REG 0x100 29 #define OV8865_SW_STANDBY_STREAM_ON BIT(0) 30 31 #define OV8865_SW_RESET_REG 0x103 32 #define OV8865_SW_RESET_RESET BIT(0) 33 34 #define OV8865_PLL_CTRL0_REG 0x300 35 #define OV8865_PLL_CTRL0_PRE_DIV(v) ((v) & GENMASK(2, 0)) 36 #define OV8865_PLL_CTRL1_REG 0x301 37 #define OV8865_PLL_CTRL1_MUL_H(v) (((v) & GENMASK(9, 8)) >> 8) 38 #define OV8865_PLL_CTRL2_REG 0x302 39 #define OV8865_PLL_CTRL2_MUL_L(v) ((v) & GENMASK(7, 0)) 40 #define OV8865_PLL_CTRL3_REG 0x303 41 #define OV8865_PLL_CTRL3_M_DIV(v) (((v) - 1) & GENMASK(3, 0)) 42 #define OV8865_PLL_CTRL4_REG 0x304 43 #define OV8865_PLL_CTRL4_MIPI_DIV(v) ((v) & GENMASK(1, 0)) 44 #define OV8865_PLL_CTRL5_REG 0x305 45 #define OV8865_PLL_CTRL5_SYS_PRE_DIV(v) ((v) & GENMASK(1, 0)) 46 #define OV8865_PLL_CTRL6_REG 0x306 47 #define OV8865_PLL_CTRL6_SYS_DIV(v) (((v) - 1) & BIT(0)) 48 49 #define OV8865_PLL_CTRL8_REG 0x308 50 #define OV8865_PLL_CTRL9_REG 0x309 51 #define OV8865_PLL_CTRLA_REG 0x30a 52 #define OV8865_PLL_CTRLA_PRE_DIV_HALF(v) (((v) - 1) & BIT(0)) 53 #define OV8865_PLL_CTRLB_REG 0x30b 54 #define OV8865_PLL_CTRLB_PRE_DIV(v) ((v) & GENMASK(2, 0)) 55 #define OV8865_PLL_CTRLC_REG 0x30c 56 #define OV8865_PLL_CTRLC_MUL_H(v) (((v) & GENMASK(9, 8)) >> 8) 57 #define OV8865_PLL_CTRLD_REG 0x30d 58 #define OV8865_PLL_CTRLD_MUL_L(v) ((v) & GENMASK(7, 0)) 59 #define OV8865_PLL_CTRLE_REG 0x30e 60 #define OV8865_PLL_CTRLE_SYS_DIV(v) ((v) & GENMASK(2, 0)) 61 #define OV8865_PLL_CTRLF_REG 0x30f 62 #define OV8865_PLL_CTRLF_SYS_PRE_DIV(v) (((v) - 1) & GENMASK(3, 0)) 63 #define OV8865_PLL_CTRL10_REG 0x310 64 #define OV8865_PLL_CTRL11_REG 0x311 65 #define OV8865_PLL_CTRL12_REG 0x312 66 #define OV8865_PLL_CTRL12_PRE_DIV_HALF(v) ((((v) - 1) << 4) & BIT(4)) 67 #define OV8865_PLL_CTRL12_DAC_DIV(v) (((v) - 1) & GENMASK(3, 0)) 68 69 #define OV8865_PLL_CTRL1B_REG 0x31b 70 #define OV8865_PLL_CTRL1C_REG 0x31c 71 72 #define OV8865_PLL_CTRL1E_REG 0x31e 73 #define OV8865_PLL_CTRL1E_PLL1_NO_LAT BIT(3) 74 75 #define OV8865_PAD_OEN0_REG 0x3000 76 77 #define OV8865_PAD_OEN2_REG 0x3002 78 79 #define OV8865_CLK_RST5_REG 0x3005 80 81 #define OV8865_CHIP_ID_HH_REG 0x300a 82 #define OV8865_CHIP_ID_HH_VALUE 0x00 83 #define OV8865_CHIP_ID_H_REG 0x300b 84 #define OV8865_CHIP_ID_H_VALUE 0x88 85 #define OV8865_CHIP_ID_L_REG 0x300c 86 #define OV8865_CHIP_ID_L_VALUE 0x65 87 #define OV8865_PAD_OUT2_REG 0x300d 88 89 #define OV8865_PAD_SEL2_REG 0x3010 90 #define OV8865_PAD_PK_REG 0x3011 91 #define OV8865_PAD_PK_DRIVE_STRENGTH_1X (0 << 5) 92 #define OV8865_PAD_PK_DRIVE_STRENGTH_2X (1 << 5) 93 #define OV8865_PAD_PK_DRIVE_STRENGTH_3X (2 << 5) 94 #define OV8865_PAD_PK_DRIVE_STRENGTH_4X (3 << 5) 95 96 #define OV8865_PUMP_CLK_DIV_REG 0x3015 97 #define OV8865_PUMP_CLK_DIV_PUMP_N(v) (((v) << 4) & GENMASK(6, 4)) 98 #define OV8865_PUMP_CLK_DIV_PUMP_P(v) ((v) & GENMASK(2, 0)) 99 100 #define OV8865_MIPI_SC_CTRL0_REG 0x3018 101 #define OV8865_MIPI_SC_CTRL0_LANES(v) ((((v) - 1) << 5) & \ 102 GENMASK(7, 5)) 103 #define OV8865_MIPI_SC_CTRL0_MIPI_EN BIT(4) 104 #define OV8865_MIPI_SC_CTRL0_UNKNOWN BIT(1) 105 #define OV8865_MIPI_SC_CTRL0_LANES_PD_MIPI BIT(0) 106 #define OV8865_MIPI_SC_CTRL1_REG 0x3019 107 #define OV8865_CLK_RST0_REG 0x301a 108 #define OV8865_CLK_RST1_REG 0x301b 109 #define OV8865_CLK_RST2_REG 0x301c 110 #define OV8865_CLK_RST3_REG 0x301d 111 #define OV8865_CLK_RST4_REG 0x301e 112 113 #define OV8865_PCLK_SEL_REG 0x3020 114 #define OV8865_PCLK_SEL_PCLK_DIV_MASK BIT(3) 115 #define OV8865_PCLK_SEL_PCLK_DIV(v) ((((v) - 1) << 3) & BIT(3)) 116 117 #define OV8865_MISC_CTRL_REG 0x3021 118 #define OV8865_MIPI_SC_CTRL2_REG 0x3022 119 #define OV8865_MIPI_SC_CTRL2_CLK_LANES_PD_MIPI BIT(1) 120 #define OV8865_MIPI_SC_CTRL2_PD_MIPI_RST_SYNC BIT(0) 121 122 #define OV8865_MIPI_BIT_SEL_REG 0x3031 123 #define OV8865_MIPI_BIT_SEL(v) (((v) << 0) & GENMASK(4, 0)) 124 #define OV8865_CLK_SEL0_REG 0x3032 125 #define OV8865_CLK_SEL0_PLL1_SYS_SEL(v) (((v) << 7) & BIT(7)) 126 #define OV8865_CLK_SEL1_REG 0x3033 127 #define OV8865_CLK_SEL1_MIPI_EOF BIT(5) 128 #define OV8865_CLK_SEL1_UNKNOWN BIT(2) 129 #define OV8865_CLK_SEL1_PLL_SCLK_SEL_MASK BIT(1) 130 #define OV8865_CLK_SEL1_PLL_SCLK_SEL(v) (((v) << 1) & BIT(1)) 131 132 #define OV8865_SCLK_CTRL_REG 0x3106 133 #define OV8865_SCLK_CTRL_SCLK_DIV(v) (((v) << 4) & GENMASK(7, 4)) 134 #define OV8865_SCLK_CTRL_SCLK_PRE_DIV(v) (((v) << 2) & GENMASK(3, 2)) 135 #define OV8865_SCLK_CTRL_UNKNOWN BIT(0) 136 137 /* Exposure/gain */ 138 139 #define OV8865_EXPOSURE_CTRL_HH_REG 0x3500 140 #define OV8865_EXPOSURE_CTRL_HH(v) (((v) & GENMASK(19, 16)) >> 16) 141 #define OV8865_EXPOSURE_CTRL_H_REG 0x3501 142 #define OV8865_EXPOSURE_CTRL_H(v) (((v) & GENMASK(15, 8)) >> 8) 143 #define OV8865_EXPOSURE_CTRL_L_REG 0x3502 144 #define OV8865_EXPOSURE_CTRL_L(v) ((v) & GENMASK(7, 0)) 145 #define OV8865_EXPOSURE_GAIN_MANUAL_REG 0x3503 146 147 #define OV8865_GAIN_CTRL_H_REG 0x3508 148 #define OV8865_GAIN_CTRL_H(v) (((v) & GENMASK(12, 8)) >> 8) 149 #define OV8865_GAIN_CTRL_L_REG 0x3509 150 #define OV8865_GAIN_CTRL_L(v) ((v) & GENMASK(7, 0)) 151 152 /* Timing */ 153 154 #define OV8865_CROP_START_X_H_REG 0x3800 155 #define OV8865_CROP_START_X_H(v) (((v) & GENMASK(11, 8)) >> 8) 156 #define OV8865_CROP_START_X_L_REG 0x3801 157 #define OV8865_CROP_START_X_L(v) ((v) & GENMASK(7, 0)) 158 #define OV8865_CROP_START_Y_H_REG 0x3802 159 #define OV8865_CROP_START_Y_H(v) (((v) & GENMASK(11, 8)) >> 8) 160 #define OV8865_CROP_START_Y_L_REG 0x3803 161 #define OV8865_CROP_START_Y_L(v) ((v) & GENMASK(7, 0)) 162 #define OV8865_CROP_END_X_H_REG 0x3804 163 #define OV8865_CROP_END_X_H(v) (((v) & GENMASK(11, 8)) >> 8) 164 #define OV8865_CROP_END_X_L_REG 0x3805 165 #define OV8865_CROP_END_X_L(v) ((v) & GENMASK(7, 0)) 166 #define OV8865_CROP_END_Y_H_REG 0x3806 167 #define OV8865_CROP_END_Y_H(v) (((v) & GENMASK(11, 8)) >> 8) 168 #define OV8865_CROP_END_Y_L_REG 0x3807 169 #define OV8865_CROP_END_Y_L(v) ((v) & GENMASK(7, 0)) 170 #define OV8865_OUTPUT_SIZE_X_H_REG 0x3808 171 #define OV8865_OUTPUT_SIZE_X_H(v) (((v) & GENMASK(11, 8)) >> 8) 172 #define OV8865_OUTPUT_SIZE_X_L_REG 0x3809 173 #define OV8865_OUTPUT_SIZE_X_L(v) ((v) & GENMASK(7, 0)) 174 #define OV8865_OUTPUT_SIZE_Y_H_REG 0x380a 175 #define OV8865_OUTPUT_SIZE_Y_H(v) (((v) & GENMASK(11, 8)) >> 8) 176 #define OV8865_OUTPUT_SIZE_Y_L_REG 0x380b 177 #define OV8865_OUTPUT_SIZE_Y_L(v) ((v) & GENMASK(7, 0)) 178 #define OV8865_HTS_H_REG 0x380c 179 #define OV8865_HTS_H(v) (((v) & GENMASK(11, 8)) >> 8) 180 #define OV8865_HTS_L_REG 0x380d 181 #define OV8865_HTS_L(v) ((v) & GENMASK(7, 0)) 182 #define OV8865_VTS_H_REG 0x380e 183 #define OV8865_VTS_H(v) (((v) & GENMASK(11, 8)) >> 8) 184 #define OV8865_VTS_L_REG 0x380f 185 #define OV8865_VTS_L(v) ((v) & GENMASK(7, 0)) 186 #define OV8865_OFFSET_X_H_REG 0x3810 187 #define OV8865_OFFSET_X_H(v) (((v) & GENMASK(15, 8)) >> 8) 188 #define OV8865_OFFSET_X_L_REG 0x3811 189 #define OV8865_OFFSET_X_L(v) ((v) & GENMASK(7, 0)) 190 #define OV8865_OFFSET_Y_H_REG 0x3812 191 #define OV8865_OFFSET_Y_H(v) (((v) & GENMASK(14, 8)) >> 8) 192 #define OV8865_OFFSET_Y_L_REG 0x3813 193 #define OV8865_OFFSET_Y_L(v) ((v) & GENMASK(7, 0)) 194 #define OV8865_INC_X_ODD_REG 0x3814 195 #define OV8865_INC_X_ODD(v) ((v) & GENMASK(4, 0)) 196 #define OV8865_INC_X_EVEN_REG 0x3815 197 #define OV8865_INC_X_EVEN(v) ((v) & GENMASK(4, 0)) 198 #define OV8865_VSYNC_START_H_REG 0x3816 199 #define OV8865_VSYNC_START_H(v) (((v) & GENMASK(15, 8)) >> 8) 200 #define OV8865_VSYNC_START_L_REG 0x3817 201 #define OV8865_VSYNC_START_L(v) ((v) & GENMASK(7, 0)) 202 #define OV8865_VSYNC_END_H_REG 0x3818 203 #define OV8865_VSYNC_END_H(v) (((v) & GENMASK(15, 8)) >> 8) 204 #define OV8865_VSYNC_END_L_REG 0x3819 205 #define OV8865_VSYNC_END_L(v) ((v) & GENMASK(7, 0)) 206 #define OV8865_HSYNC_FIRST_H_REG 0x381a 207 #define OV8865_HSYNC_FIRST_H(v) (((v) & GENMASK(15, 8)) >> 8) 208 #define OV8865_HSYNC_FIRST_L_REG 0x381b 209 #define OV8865_HSYNC_FIRST_L(v) ((v) & GENMASK(7, 0)) 210 211 #define OV8865_FORMAT1_REG 0x3820 212 #define OV8865_FORMAT1_FLIP_VERT_ISP_EN BIT(2) 213 #define OV8865_FORMAT1_FLIP_VERT_SENSOR_EN BIT(1) 214 #define OV8865_FORMAT2_REG 0x3821 215 #define OV8865_FORMAT2_HSYNC_EN BIT(6) 216 #define OV8865_FORMAT2_FST_VBIN_EN BIT(5) 217 #define OV8865_FORMAT2_FST_HBIN_EN BIT(4) 218 #define OV8865_FORMAT2_ISP_HORZ_VAR2_EN BIT(3) 219 #define OV8865_FORMAT2_FLIP_HORZ_ISP_EN BIT(2) 220 #define OV8865_FORMAT2_FLIP_HORZ_SENSOR_EN BIT(1) 221 #define OV8865_FORMAT2_SYNC_HBIN_EN BIT(0) 222 223 #define OV8865_INC_Y_ODD_REG 0x382a 224 #define OV8865_INC_Y_ODD(v) ((v) & GENMASK(4, 0)) 225 #define OV8865_INC_Y_EVEN_REG 0x382b 226 #define OV8865_INC_Y_EVEN(v) ((v) & GENMASK(4, 0)) 227 228 #define OV8865_ABLC_NUM_REG 0x3830 229 #define OV8865_ABLC_NUM(v) ((v) & GENMASK(4, 0)) 230 231 #define OV8865_ZLINE_NUM_REG 0x3836 232 #define OV8865_ZLINE_NUM(v) ((v) & GENMASK(4, 0)) 233 234 #define OV8865_AUTO_SIZE_CTRL_REG 0x3841 235 #define OV8865_AUTO_SIZE_CTRL_OFFSET_Y_REG BIT(5) 236 #define OV8865_AUTO_SIZE_CTRL_OFFSET_X_REG BIT(4) 237 #define OV8865_AUTO_SIZE_CTRL_CROP_END_Y_REG BIT(3) 238 #define OV8865_AUTO_SIZE_CTRL_CROP_END_X_REG BIT(2) 239 #define OV8865_AUTO_SIZE_CTRL_CROP_START_Y_REG BIT(1) 240 #define OV8865_AUTO_SIZE_CTRL_CROP_START_X_REG BIT(0) 241 #define OV8865_AUTO_SIZE_X_OFFSET_H_REG 0x3842 242 #define OV8865_AUTO_SIZE_X_OFFSET_L_REG 0x3843 243 #define OV8865_AUTO_SIZE_Y_OFFSET_H_REG 0x3844 244 #define OV8865_AUTO_SIZE_Y_OFFSET_L_REG 0x3845 245 #define OV8865_AUTO_SIZE_BOUNDARIES_REG 0x3846 246 #define OV8865_AUTO_SIZE_BOUNDARIES_Y(v) (((v) << 4) & GENMASK(7, 4)) 247 #define OV8865_AUTO_SIZE_BOUNDARIES_X(v) ((v) & GENMASK(3, 0)) 248 249 /* PSRAM */ 250 251 #define OV8865_PSRAM_CTRL8_REG 0x3f08 252 253 /* Black Level */ 254 255 #define OV8865_BLC_CTRL0_REG 0x4000 256 #define OV8865_BLC_CTRL0_TRIG_RANGE_EN BIT(7) 257 #define OV8865_BLC_CTRL0_TRIG_FORMAT_EN BIT(6) 258 #define OV8865_BLC_CTRL0_TRIG_GAIN_EN BIT(5) 259 #define OV8865_BLC_CTRL0_TRIG_EXPOSURE_EN BIT(4) 260 #define OV8865_BLC_CTRL0_TRIG_MANUAL_EN BIT(3) 261 #define OV8865_BLC_CTRL0_FREEZE_EN BIT(2) 262 #define OV8865_BLC_CTRL0_ALWAYS_EN BIT(1) 263 #define OV8865_BLC_CTRL0_FILTER_EN BIT(0) 264 #define OV8865_BLC_CTRL1_REG 0x4001 265 #define OV8865_BLC_CTRL1_DITHER_EN BIT(7) 266 #define OV8865_BLC_CTRL1_ZERO_LINE_DIFF_EN BIT(6) 267 #define OV8865_BLC_CTRL1_COL_SHIFT_256 (0 << 4) 268 #define OV8865_BLC_CTRL1_COL_SHIFT_128 (1 << 4) 269 #define OV8865_BLC_CTRL1_COL_SHIFT_64 (2 << 4) 270 #define OV8865_BLC_CTRL1_COL_SHIFT_32 (3 << 4) 271 #define OV8865_BLC_CTRL1_OFFSET_LIMIT_EN BIT(2) 272 #define OV8865_BLC_CTRL1_COLUMN_CANCEL_EN BIT(1) 273 #define OV8865_BLC_CTRL2_REG 0x4002 274 #define OV8865_BLC_CTRL3_REG 0x4003 275 #define OV8865_BLC_CTRL4_REG 0x4004 276 #define OV8865_BLC_CTRL5_REG 0x4005 277 #define OV8865_BLC_CTRL6_REG 0x4006 278 #define OV8865_BLC_CTRL7_REG 0x4007 279 #define OV8865_BLC_CTRL8_REG 0x4008 280 #define OV8865_BLC_CTRL9_REG 0x4009 281 #define OV8865_BLC_CTRLA_REG 0x400a 282 #define OV8865_BLC_CTRLB_REG 0x400b 283 #define OV8865_BLC_CTRLC_REG 0x400c 284 #define OV8865_BLC_CTRLD_REG 0x400d 285 #define OV8865_BLC_CTRLD_OFFSET_TRIGGER(v) ((v) & GENMASK(7, 0)) 286 287 #define OV8865_BLC_CTRL1F_REG 0x401f 288 #define OV8865_BLC_CTRL1F_RB_REVERSE BIT(3) 289 #define OV8865_BLC_CTRL1F_INTERPOL_X_EN BIT(2) 290 #define OV8865_BLC_CTRL1F_INTERPOL_Y_EN BIT(1) 291 292 #define OV8865_BLC_ANCHOR_LEFT_START_H_REG 0x4020 293 #define OV8865_BLC_ANCHOR_LEFT_START_H(v) (((v) & GENMASK(11, 8)) >> 8) 294 #define OV8865_BLC_ANCHOR_LEFT_START_L_REG 0x4021 295 #define OV8865_BLC_ANCHOR_LEFT_START_L(v) ((v) & GENMASK(7, 0)) 296 #define OV8865_BLC_ANCHOR_LEFT_END_H_REG 0x4022 297 #define OV8865_BLC_ANCHOR_LEFT_END_H(v) (((v) & GENMASK(11, 8)) >> 8) 298 #define OV8865_BLC_ANCHOR_LEFT_END_L_REG 0x4023 299 #define OV8865_BLC_ANCHOR_LEFT_END_L(v) ((v) & GENMASK(7, 0)) 300 #define OV8865_BLC_ANCHOR_RIGHT_START_H_REG 0x4024 301 #define OV8865_BLC_ANCHOR_RIGHT_START_H(v) (((v) & GENMASK(11, 8)) >> 8) 302 #define OV8865_BLC_ANCHOR_RIGHT_START_L_REG 0x4025 303 #define OV8865_BLC_ANCHOR_RIGHT_START_L(v) ((v) & GENMASK(7, 0)) 304 #define OV8865_BLC_ANCHOR_RIGHT_END_H_REG 0x4026 305 #define OV8865_BLC_ANCHOR_RIGHT_END_H(v) (((v) & GENMASK(11, 8)) >> 8) 306 #define OV8865_BLC_ANCHOR_RIGHT_END_L_REG 0x4027 307 #define OV8865_BLC_ANCHOR_RIGHT_END_L(v) ((v) & GENMASK(7, 0)) 308 309 #define OV8865_BLC_TOP_ZLINE_START_REG 0x4028 310 #define OV8865_BLC_TOP_ZLINE_START(v) ((v) & GENMASK(5, 0)) 311 #define OV8865_BLC_TOP_ZLINE_NUM_REG 0x4029 312 #define OV8865_BLC_TOP_ZLINE_NUM(v) ((v) & GENMASK(4, 0)) 313 #define OV8865_BLC_TOP_BLKLINE_START_REG 0x402a 314 #define OV8865_BLC_TOP_BLKLINE_START(v) ((v) & GENMASK(5, 0)) 315 #define OV8865_BLC_TOP_BLKLINE_NUM_REG 0x402b 316 #define OV8865_BLC_TOP_BLKLINE_NUM(v) ((v) & GENMASK(4, 0)) 317 #define OV8865_BLC_BOT_ZLINE_START_REG 0x402c 318 #define OV8865_BLC_BOT_ZLINE_START(v) ((v) & GENMASK(5, 0)) 319 #define OV8865_BLC_BOT_ZLINE_NUM_REG 0x402d 320 #define OV8865_BLC_BOT_ZLINE_NUM(v) ((v) & GENMASK(4, 0)) 321 #define OV8865_BLC_BOT_BLKLINE_START_REG 0x402e 322 #define OV8865_BLC_BOT_BLKLINE_START(v) ((v) & GENMASK(5, 0)) 323 #define OV8865_BLC_BOT_BLKLINE_NUM_REG 0x402f 324 #define OV8865_BLC_BOT_BLKLINE_NUM(v) ((v) & GENMASK(4, 0)) 325 326 #define OV8865_BLC_OFFSET_LIMIT_REG 0x4034 327 #define OV8865_BLC_OFFSET_LIMIT(v) ((v) & GENMASK(7, 0)) 328 329 /* VFIFO */ 330 331 #define OV8865_VFIFO_READ_START_H_REG 0x4600 332 #define OV8865_VFIFO_READ_START_H(v) (((v) & GENMASK(15, 8)) >> 8) 333 #define OV8865_VFIFO_READ_START_L_REG 0x4601 334 #define OV8865_VFIFO_READ_START_L(v) ((v) & GENMASK(7, 0)) 335 336 /* MIPI */ 337 338 #define OV8865_MIPI_CTRL0_REG 0x4800 339 #define OV8865_MIPI_CTRL1_REG 0x4801 340 #define OV8865_MIPI_CTRL2_REG 0x4802 341 #define OV8865_MIPI_CTRL3_REG 0x4803 342 #define OV8865_MIPI_CTRL4_REG 0x4804 343 #define OV8865_MIPI_CTRL5_REG 0x4805 344 #define OV8865_MIPI_CTRL6_REG 0x4806 345 #define OV8865_MIPI_CTRL7_REG 0x4807 346 #define OV8865_MIPI_CTRL8_REG 0x4808 347 348 #define OV8865_MIPI_FCNT_MAX_H_REG 0x4810 349 #define OV8865_MIPI_FCNT_MAX_L_REG 0x4811 350 351 #define OV8865_MIPI_CTRL13_REG 0x4813 352 #define OV8865_MIPI_CTRL14_REG 0x4814 353 #define OV8865_MIPI_CTRL15_REG 0x4815 354 #define OV8865_MIPI_EMBEDDED_DT_REG 0x4816 355 356 #define OV8865_MIPI_HS_ZERO_MIN_H_REG 0x4818 357 #define OV8865_MIPI_HS_ZERO_MIN_L_REG 0x4819 358 #define OV8865_MIPI_HS_TRAIL_MIN_H_REG 0x481a 359 #define OV8865_MIPI_HS_TRAIL_MIN_L_REG 0x481b 360 #define OV8865_MIPI_CLK_ZERO_MIN_H_REG 0x481c 361 #define OV8865_MIPI_CLK_ZERO_MIN_L_REG 0x481d 362 #define OV8865_MIPI_CLK_PREPARE_MAX_REG 0x481e 363 #define OV8865_MIPI_CLK_PREPARE_MIN_REG 0x481f 364 #define OV8865_MIPI_CLK_POST_MIN_H_REG 0x4820 365 #define OV8865_MIPI_CLK_POST_MIN_L_REG 0x4821 366 #define OV8865_MIPI_CLK_TRAIL_MIN_H_REG 0x4822 367 #define OV8865_MIPI_CLK_TRAIL_MIN_L_REG 0x4823 368 #define OV8865_MIPI_LPX_P_MIN_H_REG 0x4824 369 #define OV8865_MIPI_LPX_P_MIN_L_REG 0x4825 370 #define OV8865_MIPI_HS_PREPARE_MIN_REG 0x4826 371 #define OV8865_MIPI_HS_PREPARE_MAX_REG 0x4827 372 #define OV8865_MIPI_HS_EXIT_MIN_H_REG 0x4828 373 #define OV8865_MIPI_HS_EXIT_MIN_L_REG 0x4829 374 #define OV8865_MIPI_UI_HS_ZERO_MIN_REG 0x482a 375 #define OV8865_MIPI_UI_HS_TRAIL_MIN_REG 0x482b 376 #define OV8865_MIPI_UI_CLK_ZERO_MIN_REG 0x482c 377 #define OV8865_MIPI_UI_CLK_PREPARE_REG 0x482d 378 #define OV8865_MIPI_UI_CLK_POST_MIN_REG 0x482e 379 #define OV8865_MIPI_UI_CLK_TRAIL_MIN_REG 0x482f 380 #define OV8865_MIPI_UI_LPX_P_MIN_REG 0x4830 381 #define OV8865_MIPI_UI_HS_PREPARE_REG 0x4831 382 #define OV8865_MIPI_UI_HS_EXIT_MIN_REG 0x4832 383 #define OV8865_MIPI_PKT_START_SIZE_REG 0x4833 384 385 #define OV8865_MIPI_PCLK_PERIOD_REG 0x4837 386 #define OV8865_MIPI_LP_GPIO0_REG 0x4838 387 #define OV8865_MIPI_LP_GPIO1_REG 0x4839 388 389 #define OV8865_MIPI_CTRL3C_REG 0x483c 390 #define OV8865_MIPI_LP_GPIO4_REG 0x483d 391 392 #define OV8865_MIPI_CTRL4A_REG 0x484a 393 #define OV8865_MIPI_CTRL4B_REG 0x484b 394 #define OV8865_MIPI_CTRL4C_REG 0x484c 395 #define OV8865_MIPI_LANE_TEST_PATTERN_REG 0x484d 396 #define OV8865_MIPI_FRAME_END_DELAY_REG 0x484e 397 #define OV8865_MIPI_CLOCK_TEST_PATTERN_REG 0x484f 398 #define OV8865_MIPI_LANE_SEL01_REG 0x4850 399 #define OV8865_MIPI_LANE_SEL01_LANE0(v) (((v) << 0) & GENMASK(2, 0)) 400 #define OV8865_MIPI_LANE_SEL01_LANE1(v) (((v) << 4) & GENMASK(6, 4)) 401 #define OV8865_MIPI_LANE_SEL23_REG 0x4851 402 #define OV8865_MIPI_LANE_SEL23_LANE2(v) (((v) << 0) & GENMASK(2, 0)) 403 #define OV8865_MIPI_LANE_SEL23_LANE3(v) (((v) << 4) & GENMASK(6, 4)) 404 405 /* ISP */ 406 407 #define OV8865_ISP_CTRL0_REG 0x5000 408 #define OV8865_ISP_CTRL0_LENC_EN BIT(7) 409 #define OV8865_ISP_CTRL0_WHITE_BALANCE_EN BIT(4) 410 #define OV8865_ISP_CTRL0_DPC_BLACK_EN BIT(2) 411 #define OV8865_ISP_CTRL0_DPC_WHITE_EN BIT(1) 412 #define OV8865_ISP_CTRL1_REG 0x5001 413 #define OV8865_ISP_CTRL1_BLC_EN BIT(0) 414 #define OV8865_ISP_CTRL2_REG 0x5002 415 #define OV8865_ISP_CTRL2_DEBUG BIT(3) 416 #define OV8865_ISP_CTRL2_VARIOPIXEL_EN BIT(2) 417 #define OV8865_ISP_CTRL2_VSYNC_LATCH_EN BIT(0) 418 #define OV8865_ISP_CTRL3_REG 0x5003 419 420 #define OV8865_ISP_GAIN_RED_H_REG 0x5018 421 #define OV8865_ISP_GAIN_RED_H(v) (((v) & GENMASK(13, 6)) >> 6) 422 #define OV8865_ISP_GAIN_RED_L_REG 0x5019 423 #define OV8865_ISP_GAIN_RED_L(v) ((v) & GENMASK(5, 0)) 424 #define OV8865_ISP_GAIN_GREEN_H_REG 0x501a 425 #define OV8865_ISP_GAIN_GREEN_H(v) (((v) & GENMASK(13, 6)) >> 6) 426 #define OV8865_ISP_GAIN_GREEN_L_REG 0x501b 427 #define OV8865_ISP_GAIN_GREEN_L(v) ((v) & GENMASK(5, 0)) 428 #define OV8865_ISP_GAIN_BLUE_H_REG 0x501c 429 #define OV8865_ISP_GAIN_BLUE_H(v) (((v) & GENMASK(13, 6)) >> 6) 430 #define OV8865_ISP_GAIN_BLUE_L_REG 0x501d 431 #define OV8865_ISP_GAIN_BLUE_L(v) ((v) & GENMASK(5, 0)) 432 433 /* VarioPixel */ 434 435 #define OV8865_VAP_CTRL0_REG 0x5900 436 #define OV8865_VAP_CTRL1_REG 0x5901 437 #define OV8865_VAP_CTRL1_HSUB_COEF(v) ((((v) - 1) << 2) & \ 438 GENMASK(3, 2)) 439 #define OV8865_VAP_CTRL1_VSUB_COEF(v) (((v) - 1) & GENMASK(1, 0)) 440 441 /* Pre-DSP */ 442 443 #define OV8865_PRE_CTRL0_REG 0x5e00 444 #define OV8865_PRE_CTRL0_PATTERN_EN BIT(7) 445 #define OV8865_PRE_CTRL0_ROLLING_BAR_EN BIT(6) 446 #define OV8865_PRE_CTRL0_TRANSPARENT_MODE BIT(5) 447 #define OV8865_PRE_CTRL0_SQUARES_BW_MODE BIT(4) 448 #define OV8865_PRE_CTRL0_PATTERN_COLOR_BARS 0 449 #define OV8865_PRE_CTRL0_PATTERN_RANDOM_DATA 1 450 #define OV8865_PRE_CTRL0_PATTERN_COLOR_SQUARES 2 451 #define OV8865_PRE_CTRL0_PATTERN_BLACK 3 452 453 /* Pixel Array */ 454 455 #define OV8865_NATIVE_WIDTH 3296 456 #define OV8865_NATIVE_HEIGHT 2528 457 #define OV8865_ACTIVE_START_TOP 32 458 #define OV8865_ACTIVE_START_LEFT 80 459 #define OV8865_ACTIVE_WIDTH 3264 460 #define OV8865_ACTIVE_HEIGHT 2448 461 462 /* Macros */ 463 464 #define ov8865_subdev_sensor(s) \ 465 container_of(s, struct ov8865_sensor, subdev) 466 467 #define ov8865_ctrl_subdev(c) \ 468 (&container_of((c)->handler, struct ov8865_sensor, \ 469 ctrls.handler)->subdev) 470 471 /* Data structures */ 472 473 struct ov8865_register_value { 474 u16 address; 475 u8 value; 476 unsigned int delay_ms; 477 }; 478 479 /* 480 * PLL1 Clock Tree: 481 * 482 * +-< EXTCLK 483 * | 484 * +-+ pll_pre_div_half (0x30a [0]) 485 * | 486 * +-+ pll_pre_div (0x300 [2:0], special values: 487 * | 0: 1, 1: 1.5, 3: 2.5, 4: 3, 5: 4, 7: 8) 488 * +-+ pll_mul (0x301 [1:0], 0x302 [7:0]) 489 * | 490 * +-+ m_div (0x303 [3:0]) 491 * | | 492 * | +-> PHY_SCLK 493 * | | 494 * | +-+ mipi_div (0x304 [1:0], special values: 0: 4, 1: 5, 2: 6, 3: 8) 495 * | | 496 * | +-+ pclk_div (0x3020 [3]) 497 * | | 498 * | +-> PCLK 499 * | 500 * +-+ sys_pre_div (0x305 [1:0], special values: 0: 3, 1: 4, 2: 5, 3: 6) 501 * | 502 * +-+ sys_div (0x306 [0]) 503 * | 504 * +-+ sys_sel (0x3032 [7], 0: PLL1, 1: PLL2) 505 * | 506 * +-+ sclk_sel (0x3033 [1], 0: sys_sel, 1: PLL2 DAC_CLK) 507 * | 508 * +-+ sclk_pre_div (0x3106 [3:2], special values: 509 * | 0: 1, 1: 2, 2: 4, 3: 1) 510 * | 511 * +-+ sclk_div (0x3106 [7:4], special values: 0: 1) 512 * | 513 * +-> SCLK 514 */ 515 516 struct ov8865_pll1_config { 517 unsigned int pll_pre_div_half; 518 unsigned int pll_pre_div; 519 unsigned int pll_mul; 520 unsigned int m_div; 521 unsigned int mipi_div; 522 unsigned int pclk_div; 523 unsigned int sys_pre_div; 524 unsigned int sys_div; 525 }; 526 527 /* 528 * PLL2 Clock Tree: 529 * 530 * +-< EXTCLK 531 * | 532 * +-+ pll_pre_div_half (0x312 [4]) 533 * | 534 * +-+ pll_pre_div (0x30b [2:0], special values: 535 * | 0: 1, 1: 1.5, 3: 2.5, 4: 3, 5: 4, 7: 8) 536 * +-+ pll_mul (0x30c [1:0], 0x30d [7:0]) 537 * | 538 * +-+ dac_div (0x312 [3:0]) 539 * | | 540 * | +-> DAC_CLK 541 * | 542 * +-+ sys_pre_div (0x30f [3:0]) 543 * | 544 * +-+ sys_div (0x30e [2:0], special values: 545 * | 0: 1, 1: 1.5, 3: 2.5, 4: 3, 5: 3.5, 6: 4, 7:5) 546 * | 547 * +-+ sys_sel (0x3032 [7], 0: PLL1, 1: PLL2) 548 * | 549 * +-+ sclk_sel (0x3033 [1], 0: sys_sel, 1: PLL2 DAC_CLK) 550 * | 551 * +-+ sclk_pre_div (0x3106 [3:2], special values: 552 * | 0: 1, 1: 2, 2: 4, 3: 1) 553 * | 554 * +-+ sclk_div (0x3106 [7:4], special values: 0: 1) 555 * | 556 * +-> SCLK 557 */ 558 559 struct ov8865_pll2_config { 560 unsigned int pll_pre_div_half; 561 unsigned int pll_pre_div; 562 unsigned int pll_mul; 563 unsigned int dac_div; 564 unsigned int sys_pre_div; 565 unsigned int sys_div; 566 }; 567 568 struct ov8865_sclk_config { 569 unsigned int sys_sel; 570 unsigned int sclk_sel; 571 unsigned int sclk_pre_div; 572 unsigned int sclk_div; 573 }; 574 575 struct ov8865_pll_configs { 576 const struct ov8865_pll1_config *pll1_config; 577 const struct ov8865_pll2_config *pll2_config_native; 578 const struct ov8865_pll2_config *pll2_config_binning; 579 }; 580 581 /* Clock rate */ 582 583 enum extclk_rate { 584 OV8865_19_2_MHZ, 585 OV8865_24_MHZ, 586 OV8865_NUM_SUPPORTED_RATES 587 }; 588 589 static const unsigned long supported_extclk_rates[] = { 590 [OV8865_19_2_MHZ] = 19200000, 591 [OV8865_24_MHZ] = 24000000, 592 }; 593 594 /* 595 * General formulas for (array-centered) mode calculation: 596 * - photo_array_width = 3296 597 * - crop_start_x = (photo_array_width - output_size_x) / 2 598 * - crop_end_x = crop_start_x + offset_x + output_size_x - 1 599 * 600 * - photo_array_height = 2480 601 * - crop_start_y = (photo_array_height - output_size_y) / 2 602 * - crop_end_y = crop_start_y + offset_y + output_size_y - 1 603 */ 604 605 struct ov8865_mode { 606 unsigned int crop_start_x; 607 unsigned int offset_x; 608 unsigned int output_size_x; 609 unsigned int crop_end_x; 610 unsigned int hts; 611 612 unsigned int crop_start_y; 613 unsigned int offset_y; 614 unsigned int output_size_y; 615 unsigned int crop_end_y; 616 unsigned int vts; 617 618 /* With auto size, only output and total sizes need to be set. */ 619 bool size_auto; 620 unsigned int size_auto_boundary_x; 621 unsigned int size_auto_boundary_y; 622 623 bool binning_x; 624 bool binning_y; 625 bool variopixel; 626 unsigned int variopixel_hsub_coef; 627 unsigned int variopixel_vsub_coef; 628 629 /* Bits for the format register, used for binning. */ 630 bool sync_hbin; 631 bool horz_var2; 632 633 unsigned int inc_x_odd; 634 unsigned int inc_x_even; 635 unsigned int inc_y_odd; 636 unsigned int inc_y_even; 637 638 unsigned int vfifo_read_start; 639 640 unsigned int ablc_num; 641 unsigned int zline_num; 642 643 unsigned int blc_top_zero_line_start; 644 unsigned int blc_top_zero_line_num; 645 unsigned int blc_top_black_line_start; 646 unsigned int blc_top_black_line_num; 647 648 unsigned int blc_bottom_zero_line_start; 649 unsigned int blc_bottom_zero_line_num; 650 unsigned int blc_bottom_black_line_start; 651 unsigned int blc_bottom_black_line_num; 652 653 u8 blc_col_shift_mask; 654 655 unsigned int blc_anchor_left_start; 656 unsigned int blc_anchor_left_end; 657 unsigned int blc_anchor_right_start; 658 unsigned int blc_anchor_right_end; 659 660 struct v4l2_fract frame_interval; 661 662 bool pll2_binning; 663 664 const struct ov8865_register_value *register_values; 665 unsigned int register_values_count; 666 }; 667 668 struct ov8865_state { 669 const struct ov8865_mode *mode; 670 u32 mbus_code; 671 672 bool streaming; 673 }; 674 675 struct ov8865_ctrls { 676 struct v4l2_ctrl *link_freq; 677 struct v4l2_ctrl *pixel_rate; 678 679 struct v4l2_ctrl_handler handler; 680 }; 681 682 struct ov8865_sensor { 683 struct device *dev; 684 struct i2c_client *i2c_client; 685 struct gpio_desc *reset; 686 struct gpio_desc *powerdown; 687 struct regulator *avdd; 688 struct regulator *dvdd; 689 struct regulator *dovdd; 690 691 unsigned long extclk_rate; 692 const struct ov8865_pll_configs *pll_configs; 693 struct clk *extclk; 694 695 struct v4l2_fwnode_endpoint endpoint; 696 struct v4l2_subdev subdev; 697 struct media_pad pad; 698 699 struct mutex mutex; 700 701 struct ov8865_state state; 702 struct ov8865_ctrls ctrls; 703 }; 704 705 /* Static definitions */ 706 707 /* 708 * PHY_SCLK = 720 MHz 709 * MIPI_PCLK = 90 MHz 710 */ 711 712 static const struct ov8865_pll1_config ov8865_pll1_config_native_19_2mhz = { 713 .pll_pre_div_half = 1, 714 .pll_pre_div = 2, 715 .pll_mul = 75, 716 .m_div = 1, 717 .mipi_div = 3, 718 .pclk_div = 1, 719 .sys_pre_div = 1, 720 .sys_div = 2, 721 }; 722 723 static const struct ov8865_pll1_config ov8865_pll1_config_native_24mhz = { 724 .pll_pre_div_half = 1, 725 .pll_pre_div = 0, 726 .pll_mul = 30, 727 .m_div = 1, 728 .mipi_div = 3, 729 .pclk_div = 1, 730 .sys_pre_div = 1, 731 .sys_div = 2, 732 }; 733 734 /* 735 * DAC_CLK = 360 MHz 736 * SCLK = 144 MHz 737 */ 738 739 static const struct ov8865_pll2_config ov8865_pll2_config_native_19_2mhz = { 740 .pll_pre_div_half = 1, 741 .pll_pre_div = 5, 742 .pll_mul = 75, 743 .dac_div = 1, 744 .sys_pre_div = 1, 745 .sys_div = 3, 746 }; 747 748 static const struct ov8865_pll2_config ov8865_pll2_config_native_24mhz = { 749 .pll_pre_div_half = 1, 750 .pll_pre_div = 0, 751 .pll_mul = 30, 752 .dac_div = 2, 753 .sys_pre_div = 5, 754 .sys_div = 0, 755 }; 756 757 /* 758 * DAC_CLK = 360 MHz 759 * SCLK = 72 MHz 760 */ 761 762 static const struct ov8865_pll2_config ov8865_pll2_config_binning_19_2mhz = { 763 .pll_pre_div_half = 1, 764 .pll_pre_div = 2, 765 .pll_mul = 75, 766 .dac_div = 2, 767 .sys_pre_div = 10, 768 .sys_div = 0, 769 }; 770 771 static const struct ov8865_pll2_config ov8865_pll2_config_binning_24mhz = { 772 .pll_pre_div_half = 1, 773 .pll_pre_div = 0, 774 .pll_mul = 30, 775 .dac_div = 2, 776 .sys_pre_div = 10, 777 .sys_div = 0, 778 }; 779 780 static const struct ov8865_pll_configs ov8865_pll_configs_19_2mhz = { 781 .pll1_config = &ov8865_pll1_config_native_19_2mhz, 782 .pll2_config_native = &ov8865_pll2_config_native_19_2mhz, 783 .pll2_config_binning = &ov8865_pll2_config_binning_19_2mhz, 784 }; 785 786 static const struct ov8865_pll_configs ov8865_pll_configs_24mhz = { 787 .pll1_config = &ov8865_pll1_config_native_24mhz, 788 .pll2_config_native = &ov8865_pll2_config_native_24mhz, 789 .pll2_config_binning = &ov8865_pll2_config_binning_24mhz, 790 }; 791 792 static const struct ov8865_pll_configs *ov8865_pll_configs[] = { 793 &ov8865_pll_configs_19_2mhz, 794 &ov8865_pll_configs_24mhz, 795 }; 796 797 static const struct ov8865_sclk_config ov8865_sclk_config_native = { 798 .sys_sel = 1, 799 .sclk_sel = 0, 800 .sclk_pre_div = 0, 801 .sclk_div = 0, 802 }; 803 804 static const struct ov8865_register_value ov8865_register_values_native[] = { 805 /* Sensor */ 806 807 { 0x3700, 0x48 }, 808 { 0x3701, 0x18 }, 809 { 0x3702, 0x50 }, 810 { 0x3703, 0x32 }, 811 { 0x3704, 0x28 }, 812 { 0x3706, 0x70 }, 813 { 0x3707, 0x08 }, 814 { 0x3708, 0x48 }, 815 { 0x3709, 0x80 }, 816 { 0x370a, 0x01 }, 817 { 0x370b, 0x70 }, 818 { 0x370c, 0x07 }, 819 { 0x3718, 0x14 }, 820 { 0x3712, 0x44 }, 821 { 0x371e, 0x31 }, 822 { 0x371f, 0x7f }, 823 { 0x3720, 0x0a }, 824 { 0x3721, 0x0a }, 825 { 0x3724, 0x04 }, 826 { 0x3725, 0x04 }, 827 { 0x3726, 0x0c }, 828 { 0x3728, 0x0a }, 829 { 0x3729, 0x03 }, 830 { 0x372a, 0x06 }, 831 { 0x372b, 0xa6 }, 832 { 0x372c, 0xa6 }, 833 { 0x372d, 0xa6 }, 834 { 0x372e, 0x0c }, 835 { 0x372f, 0x20 }, 836 { 0x3730, 0x02 }, 837 { 0x3731, 0x0c }, 838 { 0x3732, 0x28 }, 839 { 0x3736, 0x30 }, 840 { 0x373a, 0x04 }, 841 { 0x373b, 0x18 }, 842 { 0x373c, 0x14 }, 843 { 0x373e, 0x06 }, 844 { 0x375a, 0x0c }, 845 { 0x375b, 0x26 }, 846 { 0x375d, 0x04 }, 847 { 0x375f, 0x28 }, 848 { 0x3767, 0x1e }, 849 { 0x3772, 0x46 }, 850 { 0x3773, 0x04 }, 851 { 0x3774, 0x2c }, 852 { 0x3775, 0x13 }, 853 { 0x3776, 0x10 }, 854 { 0x37a0, 0x88 }, 855 { 0x37a1, 0x7a }, 856 { 0x37a2, 0x7a }, 857 { 0x37a3, 0x02 }, 858 { 0x37a5, 0x09 }, 859 { 0x37a7, 0x88 }, 860 { 0x37a8, 0xb0 }, 861 { 0x37a9, 0xb0 }, 862 { 0x37aa, 0x88 }, 863 { 0x37ab, 0x5c }, 864 { 0x37ac, 0x5c }, 865 { 0x37ad, 0x55 }, 866 { 0x37ae, 0x19 }, 867 { 0x37af, 0x19 }, 868 { 0x37b3, 0x84 }, 869 { 0x37b4, 0x84 }, 870 { 0x37b5, 0x66 }, 871 872 /* PSRAM */ 873 874 { OV8865_PSRAM_CTRL8_REG, 0x16 }, 875 876 /* ADC Sync */ 877 878 { 0x4500, 0x68 }, 879 }; 880 881 static const struct ov8865_register_value ov8865_register_values_binning[] = { 882 /* Sensor */ 883 884 { 0x3700, 0x24 }, 885 { 0x3701, 0x0c }, 886 { 0x3702, 0x28 }, 887 { 0x3703, 0x19 }, 888 { 0x3704, 0x14 }, 889 { 0x3706, 0x38 }, 890 { 0x3707, 0x04 }, 891 { 0x3708, 0x24 }, 892 { 0x3709, 0x40 }, 893 { 0x370a, 0x00 }, 894 { 0x370b, 0xb8 }, 895 { 0x370c, 0x04 }, 896 { 0x3718, 0x12 }, 897 { 0x3712, 0x42 }, 898 { 0x371e, 0x19 }, 899 { 0x371f, 0x40 }, 900 { 0x3720, 0x05 }, 901 { 0x3721, 0x05 }, 902 { 0x3724, 0x02 }, 903 { 0x3725, 0x02 }, 904 { 0x3726, 0x06 }, 905 { 0x3728, 0x05 }, 906 { 0x3729, 0x02 }, 907 { 0x372a, 0x03 }, 908 { 0x372b, 0x53 }, 909 { 0x372c, 0xa3 }, 910 { 0x372d, 0x53 }, 911 { 0x372e, 0x06 }, 912 { 0x372f, 0x10 }, 913 { 0x3730, 0x01 }, 914 { 0x3731, 0x06 }, 915 { 0x3732, 0x14 }, 916 { 0x3736, 0x20 }, 917 { 0x373a, 0x02 }, 918 { 0x373b, 0x0c }, 919 { 0x373c, 0x0a }, 920 { 0x373e, 0x03 }, 921 { 0x375a, 0x06 }, 922 { 0x375b, 0x13 }, 923 { 0x375d, 0x02 }, 924 { 0x375f, 0x14 }, 925 { 0x3767, 0x1c }, 926 { 0x3772, 0x23 }, 927 { 0x3773, 0x02 }, 928 { 0x3774, 0x16 }, 929 { 0x3775, 0x12 }, 930 { 0x3776, 0x08 }, 931 { 0x37a0, 0x44 }, 932 { 0x37a1, 0x3d }, 933 { 0x37a2, 0x3d }, 934 { 0x37a3, 0x01 }, 935 { 0x37a5, 0x08 }, 936 { 0x37a7, 0x44 }, 937 { 0x37a8, 0x58 }, 938 { 0x37a9, 0x58 }, 939 { 0x37aa, 0x44 }, 940 { 0x37ab, 0x2e }, 941 { 0x37ac, 0x2e }, 942 { 0x37ad, 0x33 }, 943 { 0x37ae, 0x0d }, 944 { 0x37af, 0x0d }, 945 { 0x37b3, 0x42 }, 946 { 0x37b4, 0x42 }, 947 { 0x37b5, 0x33 }, 948 949 /* PSRAM */ 950 951 { OV8865_PSRAM_CTRL8_REG, 0x0b }, 952 953 /* ADC Sync */ 954 955 { 0x4500, 0x40 }, 956 }; 957 958 static const struct ov8865_mode ov8865_modes[] = { 959 /* 3264x2448 */ 960 { 961 /* Horizontal */ 962 .output_size_x = 3264, 963 .hts = 1944, 964 965 /* Vertical */ 966 .output_size_y = 2448, 967 .vts = 2470, 968 969 .size_auto = true, 970 .size_auto_boundary_x = 8, 971 .size_auto_boundary_y = 4, 972 973 /* Subsample increase */ 974 .inc_x_odd = 1, 975 .inc_x_even = 1, 976 .inc_y_odd = 1, 977 .inc_y_even = 1, 978 979 /* VFIFO */ 980 .vfifo_read_start = 16, 981 982 .ablc_num = 4, 983 .zline_num = 1, 984 985 /* Black Level */ 986 987 .blc_top_zero_line_start = 0, 988 .blc_top_zero_line_num = 2, 989 .blc_top_black_line_start = 4, 990 .blc_top_black_line_num = 4, 991 992 .blc_bottom_zero_line_start = 2, 993 .blc_bottom_zero_line_num = 2, 994 .blc_bottom_black_line_start = 8, 995 .blc_bottom_black_line_num = 2, 996 997 .blc_anchor_left_start = 576, 998 .blc_anchor_left_end = 831, 999 .blc_anchor_right_start = 1984, 1000 .blc_anchor_right_end = 2239, 1001 1002 /* Frame Interval */ 1003 .frame_interval = { 1, 30 }, 1004 1005 /* PLL */ 1006 .pll2_binning = false, 1007 1008 /* Registers */ 1009 .register_values = ov8865_register_values_native, 1010 .register_values_count = 1011 ARRAY_SIZE(ov8865_register_values_native), 1012 }, 1013 /* 3264x1836 */ 1014 { 1015 /* Horizontal */ 1016 .output_size_x = 3264, 1017 .hts = 2582, 1018 1019 /* Vertical */ 1020 .output_size_y = 1836, 1021 .vts = 2002, 1022 1023 .size_auto = true, 1024 .size_auto_boundary_x = 8, 1025 .size_auto_boundary_y = 4, 1026 1027 /* Subsample increase */ 1028 .inc_x_odd = 1, 1029 .inc_x_even = 1, 1030 .inc_y_odd = 1, 1031 .inc_y_even = 1, 1032 1033 /* VFIFO */ 1034 .vfifo_read_start = 16, 1035 1036 .ablc_num = 4, 1037 .zline_num = 1, 1038 1039 /* Black Level */ 1040 1041 .blc_top_zero_line_start = 0, 1042 .blc_top_zero_line_num = 2, 1043 .blc_top_black_line_start = 4, 1044 .blc_top_black_line_num = 4, 1045 1046 .blc_bottom_zero_line_start = 2, 1047 .blc_bottom_zero_line_num = 2, 1048 .blc_bottom_black_line_start = 8, 1049 .blc_bottom_black_line_num = 2, 1050 1051 .blc_anchor_left_start = 576, 1052 .blc_anchor_left_end = 831, 1053 .blc_anchor_right_start = 1984, 1054 .blc_anchor_right_end = 2239, 1055 1056 /* Frame Interval */ 1057 .frame_interval = { 1, 30 }, 1058 1059 /* PLL */ 1060 .pll2_binning = false, 1061 1062 /* Registers */ 1063 .register_values = ov8865_register_values_native, 1064 .register_values_count = 1065 ARRAY_SIZE(ov8865_register_values_native), 1066 }, 1067 /* 1632x1224 */ 1068 { 1069 /* Horizontal */ 1070 .output_size_x = 1632, 1071 .hts = 1923, 1072 1073 /* Vertical */ 1074 .output_size_y = 1224, 1075 .vts = 1248, 1076 1077 .size_auto = true, 1078 .size_auto_boundary_x = 8, 1079 .size_auto_boundary_y = 8, 1080 1081 /* Subsample increase */ 1082 .inc_x_odd = 3, 1083 .inc_x_even = 1, 1084 .inc_y_odd = 3, 1085 .inc_y_even = 1, 1086 1087 /* Binning */ 1088 .binning_y = true, 1089 .sync_hbin = true, 1090 1091 /* VFIFO */ 1092 .vfifo_read_start = 116, 1093 1094 .ablc_num = 8, 1095 .zline_num = 2, 1096 1097 /* Black Level */ 1098 1099 .blc_top_zero_line_start = 0, 1100 .blc_top_zero_line_num = 2, 1101 .blc_top_black_line_start = 4, 1102 .blc_top_black_line_num = 4, 1103 1104 .blc_bottom_zero_line_start = 2, 1105 .blc_bottom_zero_line_num = 2, 1106 .blc_bottom_black_line_start = 8, 1107 .blc_bottom_black_line_num = 2, 1108 1109 .blc_anchor_left_start = 288, 1110 .blc_anchor_left_end = 415, 1111 .blc_anchor_right_start = 992, 1112 .blc_anchor_right_end = 1119, 1113 1114 /* Frame Interval */ 1115 .frame_interval = { 1, 30 }, 1116 1117 /* PLL */ 1118 .pll2_binning = true, 1119 1120 /* Registers */ 1121 .register_values = ov8865_register_values_binning, 1122 .register_values_count = 1123 ARRAY_SIZE(ov8865_register_values_binning), 1124 }, 1125 /* 800x600 (SVGA) */ 1126 { 1127 /* Horizontal */ 1128 .output_size_x = 800, 1129 .hts = 1250, 1130 1131 /* Vertical */ 1132 .output_size_y = 600, 1133 .vts = 640, 1134 1135 .size_auto = true, 1136 .size_auto_boundary_x = 8, 1137 .size_auto_boundary_y = 8, 1138 1139 /* Subsample increase */ 1140 .inc_x_odd = 3, 1141 .inc_x_even = 1, 1142 .inc_y_odd = 5, 1143 .inc_y_even = 3, 1144 1145 /* Binning */ 1146 .binning_y = true, 1147 .variopixel = true, 1148 .variopixel_hsub_coef = 2, 1149 .variopixel_vsub_coef = 1, 1150 .sync_hbin = true, 1151 .horz_var2 = true, 1152 1153 /* VFIFO */ 1154 .vfifo_read_start = 80, 1155 1156 .ablc_num = 8, 1157 .zline_num = 2, 1158 1159 /* Black Level */ 1160 1161 .blc_top_zero_line_start = 0, 1162 .blc_top_zero_line_num = 2, 1163 .blc_top_black_line_start = 2, 1164 .blc_top_black_line_num = 2, 1165 1166 .blc_bottom_zero_line_start = 0, 1167 .blc_bottom_zero_line_num = 0, 1168 .blc_bottom_black_line_start = 4, 1169 .blc_bottom_black_line_num = 2, 1170 1171 .blc_col_shift_mask = OV8865_BLC_CTRL1_COL_SHIFT_128, 1172 1173 .blc_anchor_left_start = 288, 1174 .blc_anchor_left_end = 415, 1175 .blc_anchor_right_start = 992, 1176 .blc_anchor_right_end = 1119, 1177 1178 /* Frame Interval */ 1179 .frame_interval = { 1, 90 }, 1180 1181 /* PLL */ 1182 .pll2_binning = true, 1183 1184 /* Registers */ 1185 .register_values = ov8865_register_values_binning, 1186 .register_values_count = 1187 ARRAY_SIZE(ov8865_register_values_binning), 1188 }, 1189 }; 1190 1191 static const u32 ov8865_mbus_codes[] = { 1192 MEDIA_BUS_FMT_SBGGR10_1X10, 1193 }; 1194 1195 static const struct ov8865_register_value ov8865_init_sequence[] = { 1196 /* Analog */ 1197 1198 { 0x3604, 0x04 }, 1199 { 0x3602, 0x30 }, 1200 { 0x3605, 0x00 }, 1201 { 0x3607, 0x20 }, 1202 { 0x3608, 0x11 }, 1203 { 0x3609, 0x68 }, 1204 { 0x360a, 0x40 }, 1205 { 0x360c, 0xdd }, 1206 { 0x360e, 0x0c }, 1207 { 0x3610, 0x07 }, 1208 { 0x3612, 0x86 }, 1209 { 0x3613, 0x58 }, 1210 { 0x3614, 0x28 }, 1211 { 0x3617, 0x40 }, 1212 { 0x3618, 0x5a }, 1213 { 0x3619, 0x9b }, 1214 { 0x361c, 0x00 }, 1215 { 0x361d, 0x60 }, 1216 { 0x3631, 0x60 }, 1217 { 0x3633, 0x10 }, 1218 { 0x3634, 0x10 }, 1219 { 0x3635, 0x10 }, 1220 { 0x3636, 0x10 }, 1221 { 0x3638, 0xff }, 1222 { 0x3641, 0x55 }, 1223 { 0x3646, 0x86 }, 1224 { 0x3647, 0x27 }, 1225 { 0x364a, 0x1b }, 1226 1227 /* Sensor */ 1228 1229 { 0x3700, 0x24 }, 1230 { 0x3701, 0x0c }, 1231 { 0x3702, 0x28 }, 1232 { 0x3703, 0x19 }, 1233 { 0x3704, 0x14 }, 1234 { 0x3705, 0x00 }, 1235 { 0x3706, 0x38 }, 1236 { 0x3707, 0x04 }, 1237 { 0x3708, 0x24 }, 1238 { 0x3709, 0x40 }, 1239 { 0x370a, 0x00 }, 1240 { 0x370b, 0xb8 }, 1241 { 0x370c, 0x04 }, 1242 { 0x3718, 0x12 }, 1243 { 0x3719, 0x31 }, 1244 { 0x3712, 0x42 }, 1245 { 0x3714, 0x12 }, 1246 { 0x371e, 0x19 }, 1247 { 0x371f, 0x40 }, 1248 { 0x3720, 0x05 }, 1249 { 0x3721, 0x05 }, 1250 { 0x3724, 0x02 }, 1251 { 0x3725, 0x02 }, 1252 { 0x3726, 0x06 }, 1253 { 0x3728, 0x05 }, 1254 { 0x3729, 0x02 }, 1255 { 0x372a, 0x03 }, 1256 { 0x372b, 0x53 }, 1257 { 0x372c, 0xa3 }, 1258 { 0x372d, 0x53 }, 1259 { 0x372e, 0x06 }, 1260 { 0x372f, 0x10 }, 1261 { 0x3730, 0x01 }, 1262 { 0x3731, 0x06 }, 1263 { 0x3732, 0x14 }, 1264 { 0x3733, 0x10 }, 1265 { 0x3734, 0x40 }, 1266 { 0x3736, 0x20 }, 1267 { 0x373a, 0x02 }, 1268 { 0x373b, 0x0c }, 1269 { 0x373c, 0x0a }, 1270 { 0x373e, 0x03 }, 1271 { 0x3755, 0x40 }, 1272 { 0x3758, 0x00 }, 1273 { 0x3759, 0x4c }, 1274 { 0x375a, 0x06 }, 1275 { 0x375b, 0x13 }, 1276 { 0x375c, 0x40 }, 1277 { 0x375d, 0x02 }, 1278 { 0x375e, 0x00 }, 1279 { 0x375f, 0x14 }, 1280 { 0x3767, 0x1c }, 1281 { 0x3768, 0x04 }, 1282 { 0x3769, 0x20 }, 1283 { 0x376c, 0xc0 }, 1284 { 0x376d, 0xc0 }, 1285 { 0x376a, 0x08 }, 1286 { 0x3761, 0x00 }, 1287 { 0x3762, 0x00 }, 1288 { 0x3763, 0x00 }, 1289 { 0x3766, 0xff }, 1290 { 0x376b, 0x42 }, 1291 { 0x3772, 0x23 }, 1292 { 0x3773, 0x02 }, 1293 { 0x3774, 0x16 }, 1294 { 0x3775, 0x12 }, 1295 { 0x3776, 0x08 }, 1296 { 0x37a0, 0x44 }, 1297 { 0x37a1, 0x3d }, 1298 { 0x37a2, 0x3d }, 1299 { 0x37a3, 0x01 }, 1300 { 0x37a4, 0x00 }, 1301 { 0x37a5, 0x08 }, 1302 { 0x37a6, 0x00 }, 1303 { 0x37a7, 0x44 }, 1304 { 0x37a8, 0x58 }, 1305 { 0x37a9, 0x58 }, 1306 { 0x3760, 0x00 }, 1307 { 0x376f, 0x01 }, 1308 { 0x37aa, 0x44 }, 1309 { 0x37ab, 0x2e }, 1310 { 0x37ac, 0x2e }, 1311 { 0x37ad, 0x33 }, 1312 { 0x37ae, 0x0d }, 1313 { 0x37af, 0x0d }, 1314 { 0x37b0, 0x00 }, 1315 { 0x37b1, 0x00 }, 1316 { 0x37b2, 0x00 }, 1317 { 0x37b3, 0x42 }, 1318 { 0x37b4, 0x42 }, 1319 { 0x37b5, 0x33 }, 1320 { 0x37b6, 0x00 }, 1321 { 0x37b7, 0x00 }, 1322 { 0x37b8, 0x00 }, 1323 { 0x37b9, 0xff }, 1324 1325 /* ADC Sync */ 1326 1327 { 0x4503, 0x10 }, 1328 }; 1329 1330 static const s64 ov8865_link_freq_menu[] = { 1331 360000000, 1332 }; 1333 1334 static const char *const ov8865_test_pattern_menu[] = { 1335 "Disabled", 1336 "Random data", 1337 "Color bars", 1338 "Color bars with rolling bar", 1339 "Color squares", 1340 "Color squares with rolling bar" 1341 }; 1342 1343 static const u8 ov8865_test_pattern_bits[] = { 1344 0, 1345 OV8865_PRE_CTRL0_PATTERN_EN | OV8865_PRE_CTRL0_PATTERN_RANDOM_DATA, 1346 OV8865_PRE_CTRL0_PATTERN_EN | OV8865_PRE_CTRL0_PATTERN_COLOR_BARS, 1347 OV8865_PRE_CTRL0_PATTERN_EN | OV8865_PRE_CTRL0_ROLLING_BAR_EN | 1348 OV8865_PRE_CTRL0_PATTERN_COLOR_BARS, 1349 OV8865_PRE_CTRL0_PATTERN_EN | OV8865_PRE_CTRL0_PATTERN_COLOR_SQUARES, 1350 OV8865_PRE_CTRL0_PATTERN_EN | OV8865_PRE_CTRL0_ROLLING_BAR_EN | 1351 OV8865_PRE_CTRL0_PATTERN_COLOR_SQUARES, 1352 }; 1353 1354 /* Input/Output */ 1355 1356 static int ov8865_read(struct ov8865_sensor *sensor, u16 address, u8 *value) 1357 { 1358 unsigned char data[2] = { address >> 8, address & 0xff }; 1359 struct i2c_client *client = sensor->i2c_client; 1360 int ret; 1361 1362 ret = i2c_master_send(client, data, sizeof(data)); 1363 if (ret < 0) { 1364 dev_dbg(&client->dev, "i2c send error at address %#04x\n", 1365 address); 1366 return ret; 1367 } 1368 1369 ret = i2c_master_recv(client, value, 1); 1370 if (ret < 0) { 1371 dev_dbg(&client->dev, "i2c recv error at address %#04x\n", 1372 address); 1373 return ret; 1374 } 1375 1376 return 0; 1377 } 1378 1379 static int ov8865_write(struct ov8865_sensor *sensor, u16 address, u8 value) 1380 { 1381 unsigned char data[3] = { address >> 8, address & 0xff, value }; 1382 struct i2c_client *client = sensor->i2c_client; 1383 int ret; 1384 1385 ret = i2c_master_send(client, data, sizeof(data)); 1386 if (ret < 0) { 1387 dev_dbg(&client->dev, "i2c send error at address %#04x\n", 1388 address); 1389 return ret; 1390 } 1391 1392 return 0; 1393 } 1394 1395 static int ov8865_write_sequence(struct ov8865_sensor *sensor, 1396 const struct ov8865_register_value *sequence, 1397 unsigned int sequence_count) 1398 { 1399 unsigned int i; 1400 int ret = 0; 1401 1402 for (i = 0; i < sequence_count; i++) { 1403 ret = ov8865_write(sensor, sequence[i].address, 1404 sequence[i].value); 1405 if (ret) 1406 break; 1407 1408 if (sequence[i].delay_ms) 1409 msleep(sequence[i].delay_ms); 1410 } 1411 1412 return ret; 1413 } 1414 1415 static int ov8865_update_bits(struct ov8865_sensor *sensor, u16 address, 1416 u8 mask, u8 bits) 1417 { 1418 u8 value = 0; 1419 int ret; 1420 1421 ret = ov8865_read(sensor, address, &value); 1422 if (ret) 1423 return ret; 1424 1425 value &= ~mask; 1426 value |= bits; 1427 1428 return ov8865_write(sensor, address, value); 1429 } 1430 1431 /* Sensor */ 1432 1433 static int ov8865_sw_reset(struct ov8865_sensor *sensor) 1434 { 1435 return ov8865_write(sensor, OV8865_SW_RESET_REG, OV8865_SW_RESET_RESET); 1436 } 1437 1438 static int ov8865_sw_standby(struct ov8865_sensor *sensor, int standby) 1439 { 1440 u8 value = 0; 1441 1442 if (!standby) 1443 value = OV8865_SW_STANDBY_STREAM_ON; 1444 1445 return ov8865_write(sensor, OV8865_SW_STANDBY_REG, value); 1446 } 1447 1448 static int ov8865_chip_id_check(struct ov8865_sensor *sensor) 1449 { 1450 u16 regs[] = { OV8865_CHIP_ID_HH_REG, OV8865_CHIP_ID_H_REG, 1451 OV8865_CHIP_ID_L_REG }; 1452 u8 values[] = { OV8865_CHIP_ID_HH_VALUE, OV8865_CHIP_ID_H_VALUE, 1453 OV8865_CHIP_ID_L_VALUE }; 1454 unsigned int i; 1455 u8 value; 1456 int ret; 1457 1458 for (i = 0; i < ARRAY_SIZE(regs); i++) { 1459 ret = ov8865_read(sensor, regs[i], &value); 1460 if (ret < 0) 1461 return ret; 1462 1463 if (value != values[i]) { 1464 dev_err(sensor->dev, 1465 "chip id value mismatch: %#x instead of %#x\n", 1466 value, values[i]); 1467 return -EINVAL; 1468 } 1469 } 1470 1471 return 0; 1472 } 1473 1474 static int ov8865_charge_pump_configure(struct ov8865_sensor *sensor) 1475 { 1476 return ov8865_write(sensor, OV8865_PUMP_CLK_DIV_REG, 1477 OV8865_PUMP_CLK_DIV_PUMP_P(1)); 1478 } 1479 1480 static int ov8865_mipi_configure(struct ov8865_sensor *sensor) 1481 { 1482 struct v4l2_fwnode_bus_mipi_csi2 *bus_mipi_csi2 = 1483 &sensor->endpoint.bus.mipi_csi2; 1484 unsigned int lanes_count = bus_mipi_csi2->num_data_lanes; 1485 int ret; 1486 1487 ret = ov8865_write(sensor, OV8865_MIPI_SC_CTRL0_REG, 1488 OV8865_MIPI_SC_CTRL0_LANES(lanes_count) | 1489 OV8865_MIPI_SC_CTRL0_MIPI_EN | 1490 OV8865_MIPI_SC_CTRL0_UNKNOWN); 1491 if (ret) 1492 return ret; 1493 1494 ret = ov8865_write(sensor, OV8865_MIPI_SC_CTRL2_REG, 1495 OV8865_MIPI_SC_CTRL2_PD_MIPI_RST_SYNC); 1496 if (ret) 1497 return ret; 1498 1499 if (lanes_count >= 2) { 1500 ret = ov8865_write(sensor, OV8865_MIPI_LANE_SEL01_REG, 1501 OV8865_MIPI_LANE_SEL01_LANE0(0) | 1502 OV8865_MIPI_LANE_SEL01_LANE1(1)); 1503 if (ret) 1504 return ret; 1505 } 1506 1507 if (lanes_count >= 4) { 1508 ret = ov8865_write(sensor, OV8865_MIPI_LANE_SEL23_REG, 1509 OV8865_MIPI_LANE_SEL23_LANE2(2) | 1510 OV8865_MIPI_LANE_SEL23_LANE3(3)); 1511 if (ret) 1512 return ret; 1513 } 1514 1515 ret = ov8865_update_bits(sensor, OV8865_CLK_SEL1_REG, 1516 OV8865_CLK_SEL1_MIPI_EOF, 1517 OV8865_CLK_SEL1_MIPI_EOF); 1518 if (ret) 1519 return ret; 1520 1521 /* 1522 * This value might need to change depending on PCLK rate, 1523 * but it's unclear how. This value seems to generally work 1524 * while the default value was found to cause transmission errors. 1525 */ 1526 return ov8865_write(sensor, OV8865_MIPI_PCLK_PERIOD_REG, 0x16); 1527 } 1528 1529 static int ov8865_black_level_configure(struct ov8865_sensor *sensor) 1530 { 1531 int ret; 1532 1533 /* Trigger BLC on relevant events and enable filter. */ 1534 ret = ov8865_write(sensor, OV8865_BLC_CTRL0_REG, 1535 OV8865_BLC_CTRL0_TRIG_RANGE_EN | 1536 OV8865_BLC_CTRL0_TRIG_FORMAT_EN | 1537 OV8865_BLC_CTRL0_TRIG_GAIN_EN | 1538 OV8865_BLC_CTRL0_TRIG_EXPOSURE_EN | 1539 OV8865_BLC_CTRL0_FILTER_EN); 1540 if (ret) 1541 return ret; 1542 1543 /* Lower BLC offset trigger threshold. */ 1544 ret = ov8865_write(sensor, OV8865_BLC_CTRLD_REG, 1545 OV8865_BLC_CTRLD_OFFSET_TRIGGER(16)); 1546 if (ret) 1547 return ret; 1548 1549 ret = ov8865_write(sensor, OV8865_BLC_CTRL1F_REG, 0); 1550 if (ret) 1551 return ret; 1552 1553 /* Increase BLC offset maximum limit. */ 1554 return ov8865_write(sensor, OV8865_BLC_OFFSET_LIMIT_REG, 1555 OV8865_BLC_OFFSET_LIMIT(63)); 1556 } 1557 1558 static int ov8865_isp_configure(struct ov8865_sensor *sensor) 1559 { 1560 int ret; 1561 1562 /* Disable lens correction. */ 1563 ret = ov8865_write(sensor, OV8865_ISP_CTRL0_REG, 1564 OV8865_ISP_CTRL0_WHITE_BALANCE_EN | 1565 OV8865_ISP_CTRL0_DPC_BLACK_EN | 1566 OV8865_ISP_CTRL0_DPC_WHITE_EN); 1567 if (ret) 1568 return ret; 1569 1570 return ov8865_write(sensor, OV8865_ISP_CTRL1_REG, 1571 OV8865_ISP_CTRL1_BLC_EN); 1572 } 1573 1574 static unsigned long ov8865_mode_pll1_rate(struct ov8865_sensor *sensor, 1575 const struct ov8865_mode *mode) 1576 { 1577 const struct ov8865_pll1_config *config; 1578 unsigned long pll1_rate; 1579 1580 config = sensor->pll_configs->pll1_config; 1581 pll1_rate = sensor->extclk_rate * config->pll_mul / config->pll_pre_div_half; 1582 1583 switch (config->pll_pre_div) { 1584 case 0: 1585 break; 1586 case 1: 1587 pll1_rate *= 3; 1588 pll1_rate /= 2; 1589 break; 1590 case 3: 1591 pll1_rate *= 5; 1592 pll1_rate /= 2; 1593 break; 1594 case 4: 1595 pll1_rate /= 3; 1596 break; 1597 case 5: 1598 pll1_rate /= 4; 1599 break; 1600 case 7: 1601 pll1_rate /= 8; 1602 break; 1603 default: 1604 pll1_rate /= config->pll_pre_div; 1605 break; 1606 } 1607 1608 return pll1_rate; 1609 } 1610 1611 static int ov8865_mode_pll1_configure(struct ov8865_sensor *sensor, 1612 const struct ov8865_mode *mode, 1613 u32 mbus_code) 1614 { 1615 const struct ov8865_pll1_config *config; 1616 u8 value; 1617 int ret; 1618 1619 config = sensor->pll_configs->pll1_config; 1620 1621 switch (mbus_code) { 1622 case MEDIA_BUS_FMT_SBGGR10_1X10: 1623 value = OV8865_MIPI_BIT_SEL(10); 1624 break; 1625 default: 1626 return -EINVAL; 1627 } 1628 1629 ret = ov8865_write(sensor, OV8865_MIPI_BIT_SEL_REG, value); 1630 if (ret) 1631 return ret; 1632 1633 ret = ov8865_write(sensor, OV8865_PLL_CTRLA_REG, 1634 OV8865_PLL_CTRLA_PRE_DIV_HALF(config->pll_pre_div_half)); 1635 if (ret) 1636 return ret; 1637 1638 ret = ov8865_write(sensor, OV8865_PLL_CTRL0_REG, 1639 OV8865_PLL_CTRL0_PRE_DIV(config->pll_pre_div)); 1640 if (ret) 1641 return ret; 1642 1643 ret = ov8865_write(sensor, OV8865_PLL_CTRL1_REG, 1644 OV8865_PLL_CTRL1_MUL_H(config->pll_mul)); 1645 if (ret) 1646 return ret; 1647 1648 ret = ov8865_write(sensor, OV8865_PLL_CTRL2_REG, 1649 OV8865_PLL_CTRL2_MUL_L(config->pll_mul)); 1650 if (ret) 1651 return ret; 1652 1653 ret = ov8865_write(sensor, OV8865_PLL_CTRL3_REG, 1654 OV8865_PLL_CTRL3_M_DIV(config->m_div)); 1655 if (ret) 1656 return ret; 1657 1658 ret = ov8865_write(sensor, OV8865_PLL_CTRL4_REG, 1659 OV8865_PLL_CTRL4_MIPI_DIV(config->mipi_div)); 1660 if (ret) 1661 return ret; 1662 1663 ret = ov8865_update_bits(sensor, OV8865_PCLK_SEL_REG, 1664 OV8865_PCLK_SEL_PCLK_DIV_MASK, 1665 OV8865_PCLK_SEL_PCLK_DIV(config->pclk_div)); 1666 if (ret) 1667 return ret; 1668 1669 ret = ov8865_write(sensor, OV8865_PLL_CTRL5_REG, 1670 OV8865_PLL_CTRL5_SYS_PRE_DIV(config->sys_pre_div)); 1671 if (ret) 1672 return ret; 1673 1674 ret = ov8865_write(sensor, OV8865_PLL_CTRL6_REG, 1675 OV8865_PLL_CTRL6_SYS_DIV(config->sys_div)); 1676 if (ret) 1677 return ret; 1678 1679 return ov8865_update_bits(sensor, OV8865_PLL_CTRL1E_REG, 1680 OV8865_PLL_CTRL1E_PLL1_NO_LAT, 1681 OV8865_PLL_CTRL1E_PLL1_NO_LAT); 1682 } 1683 1684 static int ov8865_mode_pll2_configure(struct ov8865_sensor *sensor, 1685 const struct ov8865_mode *mode) 1686 { 1687 const struct ov8865_pll2_config *config; 1688 int ret; 1689 1690 config = mode->pll2_binning ? sensor->pll_configs->pll2_config_binning : 1691 sensor->pll_configs->pll2_config_native; 1692 1693 ret = ov8865_write(sensor, OV8865_PLL_CTRL12_REG, 1694 OV8865_PLL_CTRL12_PRE_DIV_HALF(config->pll_pre_div_half) | 1695 OV8865_PLL_CTRL12_DAC_DIV(config->dac_div)); 1696 if (ret) 1697 return ret; 1698 1699 ret = ov8865_write(sensor, OV8865_PLL_CTRLB_REG, 1700 OV8865_PLL_CTRLB_PRE_DIV(config->pll_pre_div)); 1701 if (ret) 1702 return ret; 1703 1704 ret = ov8865_write(sensor, OV8865_PLL_CTRLC_REG, 1705 OV8865_PLL_CTRLC_MUL_H(config->pll_mul)); 1706 if (ret) 1707 return ret; 1708 1709 ret = ov8865_write(sensor, OV8865_PLL_CTRLD_REG, 1710 OV8865_PLL_CTRLD_MUL_L(config->pll_mul)); 1711 if (ret) 1712 return ret; 1713 1714 ret = ov8865_write(sensor, OV8865_PLL_CTRLF_REG, 1715 OV8865_PLL_CTRLF_SYS_PRE_DIV(config->sys_pre_div)); 1716 if (ret) 1717 return ret; 1718 1719 return ov8865_write(sensor, OV8865_PLL_CTRLE_REG, 1720 OV8865_PLL_CTRLE_SYS_DIV(config->sys_div)); 1721 } 1722 1723 static int ov8865_mode_sclk_configure(struct ov8865_sensor *sensor, 1724 const struct ov8865_mode *mode) 1725 { 1726 const struct ov8865_sclk_config *config = &ov8865_sclk_config_native; 1727 int ret; 1728 1729 ret = ov8865_write(sensor, OV8865_CLK_SEL0_REG, 1730 OV8865_CLK_SEL0_PLL1_SYS_SEL(config->sys_sel)); 1731 if (ret) 1732 return ret; 1733 1734 ret = ov8865_update_bits(sensor, OV8865_CLK_SEL1_REG, 1735 OV8865_CLK_SEL1_PLL_SCLK_SEL_MASK, 1736 OV8865_CLK_SEL1_PLL_SCLK_SEL(config->sclk_sel)); 1737 if (ret) 1738 return ret; 1739 1740 return ov8865_write(sensor, OV8865_SCLK_CTRL_REG, 1741 OV8865_SCLK_CTRL_UNKNOWN | 1742 OV8865_SCLK_CTRL_SCLK_DIV(config->sclk_div) | 1743 OV8865_SCLK_CTRL_SCLK_PRE_DIV(config->sclk_pre_div)); 1744 } 1745 1746 static int ov8865_mode_binning_configure(struct ov8865_sensor *sensor, 1747 const struct ov8865_mode *mode) 1748 { 1749 unsigned int variopixel_hsub_coef, variopixel_vsub_coef; 1750 u8 value; 1751 int ret; 1752 1753 ret = ov8865_write(sensor, OV8865_FORMAT1_REG, 0); 1754 if (ret) 1755 return ret; 1756 1757 value = OV8865_FORMAT2_HSYNC_EN; 1758 1759 if (mode->binning_x) 1760 value |= OV8865_FORMAT2_FST_HBIN_EN; 1761 1762 if (mode->binning_y) 1763 value |= OV8865_FORMAT2_FST_VBIN_EN; 1764 1765 if (mode->sync_hbin) 1766 value |= OV8865_FORMAT2_SYNC_HBIN_EN; 1767 1768 if (mode->horz_var2) 1769 value |= OV8865_FORMAT2_ISP_HORZ_VAR2_EN; 1770 1771 ret = ov8865_write(sensor, OV8865_FORMAT2_REG, value); 1772 if (ret) 1773 return ret; 1774 1775 ret = ov8865_update_bits(sensor, OV8865_ISP_CTRL2_REG, 1776 OV8865_ISP_CTRL2_VARIOPIXEL_EN, 1777 mode->variopixel ? 1778 OV8865_ISP_CTRL2_VARIOPIXEL_EN : 0); 1779 if (ret) 1780 return ret; 1781 1782 if (mode->variopixel) { 1783 /* VarioPixel coefs needs to be > 1. */ 1784 variopixel_hsub_coef = mode->variopixel_hsub_coef; 1785 variopixel_vsub_coef = mode->variopixel_vsub_coef; 1786 } else { 1787 variopixel_hsub_coef = 1; 1788 variopixel_vsub_coef = 1; 1789 } 1790 1791 ret = ov8865_write(sensor, OV8865_VAP_CTRL1_REG, 1792 OV8865_VAP_CTRL1_HSUB_COEF(variopixel_hsub_coef) | 1793 OV8865_VAP_CTRL1_VSUB_COEF(variopixel_vsub_coef)); 1794 if (ret) 1795 return ret; 1796 1797 ret = ov8865_write(sensor, OV8865_INC_X_ODD_REG, 1798 OV8865_INC_X_ODD(mode->inc_x_odd)); 1799 if (ret) 1800 return ret; 1801 1802 ret = ov8865_write(sensor, OV8865_INC_X_EVEN_REG, 1803 OV8865_INC_X_EVEN(mode->inc_x_even)); 1804 if (ret) 1805 return ret; 1806 1807 ret = ov8865_write(sensor, OV8865_INC_Y_ODD_REG, 1808 OV8865_INC_Y_ODD(mode->inc_y_odd)); 1809 if (ret) 1810 return ret; 1811 1812 return ov8865_write(sensor, OV8865_INC_Y_EVEN_REG, 1813 OV8865_INC_Y_EVEN(mode->inc_y_even)); 1814 } 1815 1816 static int ov8865_mode_black_level_configure(struct ov8865_sensor *sensor, 1817 const struct ov8865_mode *mode) 1818 { 1819 int ret; 1820 1821 /* Note that a zero value for blc_col_shift_mask is the default 256. */ 1822 ret = ov8865_write(sensor, OV8865_BLC_CTRL1_REG, 1823 mode->blc_col_shift_mask | 1824 OV8865_BLC_CTRL1_OFFSET_LIMIT_EN); 1825 if (ret) 1826 return ret; 1827 1828 /* BLC top zero line */ 1829 1830 ret = ov8865_write(sensor, OV8865_BLC_TOP_ZLINE_START_REG, 1831 OV8865_BLC_TOP_ZLINE_START(mode->blc_top_zero_line_start)); 1832 if (ret) 1833 return ret; 1834 1835 ret = ov8865_write(sensor, OV8865_BLC_TOP_ZLINE_NUM_REG, 1836 OV8865_BLC_TOP_ZLINE_NUM(mode->blc_top_zero_line_num)); 1837 if (ret) 1838 return ret; 1839 1840 /* BLC top black line */ 1841 1842 ret = ov8865_write(sensor, OV8865_BLC_TOP_BLKLINE_START_REG, 1843 OV8865_BLC_TOP_BLKLINE_START(mode->blc_top_black_line_start)); 1844 if (ret) 1845 return ret; 1846 1847 ret = ov8865_write(sensor, OV8865_BLC_TOP_BLKLINE_NUM_REG, 1848 OV8865_BLC_TOP_BLKLINE_NUM(mode->blc_top_black_line_num)); 1849 if (ret) 1850 return ret; 1851 1852 /* BLC bottom zero line */ 1853 1854 ret = ov8865_write(sensor, OV8865_BLC_BOT_ZLINE_START_REG, 1855 OV8865_BLC_BOT_ZLINE_START(mode->blc_bottom_zero_line_start)); 1856 if (ret) 1857 return ret; 1858 1859 ret = ov8865_write(sensor, OV8865_BLC_BOT_ZLINE_NUM_REG, 1860 OV8865_BLC_BOT_ZLINE_NUM(mode->blc_bottom_zero_line_num)); 1861 if (ret) 1862 return ret; 1863 1864 /* BLC bottom black line */ 1865 1866 ret = ov8865_write(sensor, OV8865_BLC_BOT_BLKLINE_START_REG, 1867 OV8865_BLC_BOT_BLKLINE_START(mode->blc_bottom_black_line_start)); 1868 if (ret) 1869 return ret; 1870 1871 ret = ov8865_write(sensor, OV8865_BLC_BOT_BLKLINE_NUM_REG, 1872 OV8865_BLC_BOT_BLKLINE_NUM(mode->blc_bottom_black_line_num)); 1873 if (ret) 1874 return ret; 1875 1876 /* BLC anchor */ 1877 1878 ret = ov8865_write(sensor, OV8865_BLC_ANCHOR_LEFT_START_H_REG, 1879 OV8865_BLC_ANCHOR_LEFT_START_H(mode->blc_anchor_left_start)); 1880 if (ret) 1881 return ret; 1882 1883 ret = ov8865_write(sensor, OV8865_BLC_ANCHOR_LEFT_START_L_REG, 1884 OV8865_BLC_ANCHOR_LEFT_START_L(mode->blc_anchor_left_start)); 1885 if (ret) 1886 return ret; 1887 1888 ret = ov8865_write(sensor, OV8865_BLC_ANCHOR_LEFT_END_H_REG, 1889 OV8865_BLC_ANCHOR_LEFT_END_H(mode->blc_anchor_left_end)); 1890 if (ret) 1891 return ret; 1892 1893 ret = ov8865_write(sensor, OV8865_BLC_ANCHOR_LEFT_END_L_REG, 1894 OV8865_BLC_ANCHOR_LEFT_END_L(mode->blc_anchor_left_end)); 1895 if (ret) 1896 return ret; 1897 1898 ret = ov8865_write(sensor, OV8865_BLC_ANCHOR_RIGHT_START_H_REG, 1899 OV8865_BLC_ANCHOR_RIGHT_START_H(mode->blc_anchor_right_start)); 1900 if (ret) 1901 return ret; 1902 1903 ret = ov8865_write(sensor, OV8865_BLC_ANCHOR_RIGHT_START_L_REG, 1904 OV8865_BLC_ANCHOR_RIGHT_START_L(mode->blc_anchor_right_start)); 1905 if (ret) 1906 return ret; 1907 1908 ret = ov8865_write(sensor, OV8865_BLC_ANCHOR_RIGHT_END_H_REG, 1909 OV8865_BLC_ANCHOR_RIGHT_END_H(mode->blc_anchor_right_end)); 1910 if (ret) 1911 return ret; 1912 1913 return ov8865_write(sensor, OV8865_BLC_ANCHOR_RIGHT_END_L_REG, 1914 OV8865_BLC_ANCHOR_RIGHT_END_L(mode->blc_anchor_right_end)); 1915 } 1916 1917 static int ov8865_mode_configure(struct ov8865_sensor *sensor, 1918 const struct ov8865_mode *mode, u32 mbus_code) 1919 { 1920 int ret; 1921 1922 /* Output Size X */ 1923 1924 ret = ov8865_write(sensor, OV8865_OUTPUT_SIZE_X_H_REG, 1925 OV8865_OUTPUT_SIZE_X_H(mode->output_size_x)); 1926 if (ret) 1927 return ret; 1928 1929 ret = ov8865_write(sensor, OV8865_OUTPUT_SIZE_X_L_REG, 1930 OV8865_OUTPUT_SIZE_X_L(mode->output_size_x)); 1931 if (ret) 1932 return ret; 1933 1934 /* Horizontal Total Size */ 1935 1936 ret = ov8865_write(sensor, OV8865_HTS_H_REG, OV8865_HTS_H(mode->hts)); 1937 if (ret) 1938 return ret; 1939 1940 ret = ov8865_write(sensor, OV8865_HTS_L_REG, OV8865_HTS_L(mode->hts)); 1941 if (ret) 1942 return ret; 1943 1944 /* Output Size Y */ 1945 1946 ret = ov8865_write(sensor, OV8865_OUTPUT_SIZE_Y_H_REG, 1947 OV8865_OUTPUT_SIZE_Y_H(mode->output_size_y)); 1948 if (ret) 1949 return ret; 1950 1951 ret = ov8865_write(sensor, OV8865_OUTPUT_SIZE_Y_L_REG, 1952 OV8865_OUTPUT_SIZE_Y_L(mode->output_size_y)); 1953 if (ret) 1954 return ret; 1955 1956 /* Vertical Total Size */ 1957 1958 ret = ov8865_write(sensor, OV8865_VTS_H_REG, OV8865_VTS_H(mode->vts)); 1959 if (ret) 1960 return ret; 1961 1962 ret = ov8865_write(sensor, OV8865_VTS_L_REG, OV8865_VTS_L(mode->vts)); 1963 if (ret) 1964 return ret; 1965 1966 if (mode->size_auto) { 1967 /* Auto Size */ 1968 1969 ret = ov8865_write(sensor, OV8865_AUTO_SIZE_CTRL_REG, 1970 OV8865_AUTO_SIZE_CTRL_OFFSET_Y_REG | 1971 OV8865_AUTO_SIZE_CTRL_OFFSET_X_REG | 1972 OV8865_AUTO_SIZE_CTRL_CROP_END_Y_REG | 1973 OV8865_AUTO_SIZE_CTRL_CROP_END_X_REG | 1974 OV8865_AUTO_SIZE_CTRL_CROP_START_Y_REG | 1975 OV8865_AUTO_SIZE_CTRL_CROP_START_X_REG); 1976 if (ret) 1977 return ret; 1978 1979 ret = ov8865_write(sensor, OV8865_AUTO_SIZE_BOUNDARIES_REG, 1980 OV8865_AUTO_SIZE_BOUNDARIES_Y(mode->size_auto_boundary_y) | 1981 OV8865_AUTO_SIZE_BOUNDARIES_X(mode->size_auto_boundary_x)); 1982 if (ret) 1983 return ret; 1984 } else { 1985 /* Crop Start X */ 1986 1987 ret = ov8865_write(sensor, OV8865_CROP_START_X_H_REG, 1988 OV8865_CROP_START_X_H(mode->crop_start_x)); 1989 if (ret) 1990 return ret; 1991 1992 ret = ov8865_write(sensor, OV8865_CROP_START_X_L_REG, 1993 OV8865_CROP_START_X_L(mode->crop_start_x)); 1994 if (ret) 1995 return ret; 1996 1997 /* Offset X */ 1998 1999 ret = ov8865_write(sensor, OV8865_OFFSET_X_H_REG, 2000 OV8865_OFFSET_X_H(mode->offset_x)); 2001 if (ret) 2002 return ret; 2003 2004 ret = ov8865_write(sensor, OV8865_OFFSET_X_L_REG, 2005 OV8865_OFFSET_X_L(mode->offset_x)); 2006 if (ret) 2007 return ret; 2008 2009 /* Crop End X */ 2010 2011 ret = ov8865_write(sensor, OV8865_CROP_END_X_H_REG, 2012 OV8865_CROP_END_X_H(mode->crop_end_x)); 2013 if (ret) 2014 return ret; 2015 2016 ret = ov8865_write(sensor, OV8865_CROP_END_X_L_REG, 2017 OV8865_CROP_END_X_L(mode->crop_end_x)); 2018 if (ret) 2019 return ret; 2020 2021 /* Crop Start Y */ 2022 2023 ret = ov8865_write(sensor, OV8865_CROP_START_Y_H_REG, 2024 OV8865_CROP_START_Y_H(mode->crop_start_y)); 2025 if (ret) 2026 return ret; 2027 2028 ret = ov8865_write(sensor, OV8865_CROP_START_Y_L_REG, 2029 OV8865_CROP_START_Y_L(mode->crop_start_y)); 2030 if (ret) 2031 return ret; 2032 2033 /* Offset Y */ 2034 2035 ret = ov8865_write(sensor, OV8865_OFFSET_Y_H_REG, 2036 OV8865_OFFSET_Y_H(mode->offset_y)); 2037 if (ret) 2038 return ret; 2039 2040 ret = ov8865_write(sensor, OV8865_OFFSET_Y_L_REG, 2041 OV8865_OFFSET_Y_L(mode->offset_y)); 2042 if (ret) 2043 return ret; 2044 2045 /* Crop End Y */ 2046 2047 ret = ov8865_write(sensor, OV8865_CROP_END_Y_H_REG, 2048 OV8865_CROP_END_Y_H(mode->crop_end_y)); 2049 if (ret) 2050 return ret; 2051 2052 ret = ov8865_write(sensor, OV8865_CROP_END_Y_L_REG, 2053 OV8865_CROP_END_Y_L(mode->crop_end_y)); 2054 if (ret) 2055 return ret; 2056 } 2057 2058 /* VFIFO */ 2059 2060 ret = ov8865_write(sensor, OV8865_VFIFO_READ_START_H_REG, 2061 OV8865_VFIFO_READ_START_H(mode->vfifo_read_start)); 2062 if (ret) 2063 return ret; 2064 2065 ret = ov8865_write(sensor, OV8865_VFIFO_READ_START_L_REG, 2066 OV8865_VFIFO_READ_START_L(mode->vfifo_read_start)); 2067 if (ret) 2068 return ret; 2069 2070 ret = ov8865_write(sensor, OV8865_ABLC_NUM_REG, 2071 OV8865_ABLC_NUM(mode->ablc_num)); 2072 if (ret) 2073 return ret; 2074 2075 ret = ov8865_write(sensor, OV8865_ZLINE_NUM_REG, 2076 OV8865_ZLINE_NUM(mode->zline_num)); 2077 if (ret) 2078 return ret; 2079 2080 /* Binning */ 2081 2082 ret = ov8865_mode_binning_configure(sensor, mode); 2083 if (ret) 2084 return ret; 2085 2086 /* Black Level */ 2087 2088 ret = ov8865_mode_black_level_configure(sensor, mode); 2089 if (ret) 2090 return ret; 2091 2092 /* PLLs */ 2093 2094 ret = ov8865_mode_pll1_configure(sensor, mode, mbus_code); 2095 if (ret) 2096 return ret; 2097 2098 ret = ov8865_mode_pll2_configure(sensor, mode); 2099 if (ret) 2100 return ret; 2101 2102 ret = ov8865_mode_sclk_configure(sensor, mode); 2103 if (ret) 2104 return ret; 2105 2106 /* Extra registers */ 2107 2108 if (mode->register_values) { 2109 ret = ov8865_write_sequence(sensor, mode->register_values, 2110 mode->register_values_count); 2111 if (ret) 2112 return ret; 2113 } 2114 2115 return 0; 2116 } 2117 2118 static unsigned long ov8865_mode_mipi_clk_rate(struct ov8865_sensor *sensor, 2119 const struct ov8865_mode *mode) 2120 { 2121 const struct ov8865_pll1_config *config; 2122 unsigned long pll1_rate; 2123 2124 config = sensor->pll_configs->pll1_config; 2125 2126 pll1_rate = ov8865_mode_pll1_rate(sensor, mode); 2127 2128 return pll1_rate / config->m_div / 2; 2129 } 2130 2131 /* Exposure */ 2132 2133 static int ov8865_exposure_configure(struct ov8865_sensor *sensor, u32 exposure) 2134 { 2135 int ret; 2136 2137 ret = ov8865_write(sensor, OV8865_EXPOSURE_CTRL_HH_REG, 2138 OV8865_EXPOSURE_CTRL_HH(exposure)); 2139 if (ret) 2140 return ret; 2141 2142 ret = ov8865_write(sensor, OV8865_EXPOSURE_CTRL_H_REG, 2143 OV8865_EXPOSURE_CTRL_H(exposure)); 2144 if (ret) 2145 return ret; 2146 2147 return ov8865_write(sensor, OV8865_EXPOSURE_CTRL_L_REG, 2148 OV8865_EXPOSURE_CTRL_L(exposure)); 2149 } 2150 2151 /* Gain */ 2152 2153 static int ov8865_analog_gain_configure(struct ov8865_sensor *sensor, u32 gain) 2154 { 2155 int ret; 2156 2157 ret = ov8865_write(sensor, OV8865_GAIN_CTRL_H_REG, 2158 OV8865_GAIN_CTRL_H(gain)); 2159 if (ret) 2160 return ret; 2161 2162 return ov8865_write(sensor, OV8865_GAIN_CTRL_L_REG, 2163 OV8865_GAIN_CTRL_L(gain)); 2164 } 2165 2166 /* White Balance */ 2167 2168 static int ov8865_red_balance_configure(struct ov8865_sensor *sensor, 2169 u32 red_balance) 2170 { 2171 int ret; 2172 2173 ret = ov8865_write(sensor, OV8865_ISP_GAIN_RED_H_REG, 2174 OV8865_ISP_GAIN_RED_H(red_balance)); 2175 if (ret) 2176 return ret; 2177 2178 return ov8865_write(sensor, OV8865_ISP_GAIN_RED_L_REG, 2179 OV8865_ISP_GAIN_RED_L(red_balance)); 2180 } 2181 2182 static int ov8865_blue_balance_configure(struct ov8865_sensor *sensor, 2183 u32 blue_balance) 2184 { 2185 int ret; 2186 2187 ret = ov8865_write(sensor, OV8865_ISP_GAIN_BLUE_H_REG, 2188 OV8865_ISP_GAIN_BLUE_H(blue_balance)); 2189 if (ret) 2190 return ret; 2191 2192 return ov8865_write(sensor, OV8865_ISP_GAIN_BLUE_L_REG, 2193 OV8865_ISP_GAIN_BLUE_L(blue_balance)); 2194 } 2195 2196 /* Flip */ 2197 2198 static int ov8865_flip_vert_configure(struct ov8865_sensor *sensor, bool enable) 2199 { 2200 u8 bits = OV8865_FORMAT1_FLIP_VERT_ISP_EN | 2201 OV8865_FORMAT1_FLIP_VERT_SENSOR_EN; 2202 2203 return ov8865_update_bits(sensor, OV8865_FORMAT1_REG, bits, 2204 enable ? bits : 0); 2205 } 2206 2207 static int ov8865_flip_horz_configure(struct ov8865_sensor *sensor, bool enable) 2208 { 2209 u8 bits = OV8865_FORMAT2_FLIP_HORZ_ISP_EN | 2210 OV8865_FORMAT2_FLIP_HORZ_SENSOR_EN; 2211 2212 return ov8865_update_bits(sensor, OV8865_FORMAT2_REG, bits, 2213 enable ? bits : 0); 2214 } 2215 2216 /* Test Pattern */ 2217 2218 static int ov8865_test_pattern_configure(struct ov8865_sensor *sensor, 2219 unsigned int index) 2220 { 2221 if (index >= ARRAY_SIZE(ov8865_test_pattern_bits)) 2222 return -EINVAL; 2223 2224 return ov8865_write(sensor, OV8865_PRE_CTRL0_REG, 2225 ov8865_test_pattern_bits[index]); 2226 } 2227 2228 /* State */ 2229 2230 static int ov8865_state_mipi_configure(struct ov8865_sensor *sensor, 2231 const struct ov8865_mode *mode, 2232 u32 mbus_code) 2233 { 2234 struct ov8865_ctrls *ctrls = &sensor->ctrls; 2235 struct v4l2_fwnode_bus_mipi_csi2 *bus_mipi_csi2 = 2236 &sensor->endpoint.bus.mipi_csi2; 2237 unsigned long mipi_clk_rate; 2238 unsigned int bits_per_sample; 2239 unsigned int lanes_count; 2240 unsigned int i, j; 2241 s64 mipi_pixel_rate; 2242 2243 mipi_clk_rate = ov8865_mode_mipi_clk_rate(sensor, mode); 2244 if (!mipi_clk_rate) 2245 return -EINVAL; 2246 2247 for (i = 0; i < ARRAY_SIZE(ov8865_link_freq_menu); i++) { 2248 s64 freq = ov8865_link_freq_menu[i]; 2249 2250 if (freq == mipi_clk_rate) 2251 break; 2252 } 2253 2254 for (j = 0; j < sensor->endpoint.nr_of_link_frequencies; j++) { 2255 u64 freq = sensor->endpoint.link_frequencies[j]; 2256 2257 if (freq == mipi_clk_rate) 2258 break; 2259 } 2260 2261 if (i == ARRAY_SIZE(ov8865_link_freq_menu)) { 2262 dev_err(sensor->dev, 2263 "failed to find %lu clk rate in link freq\n", 2264 mipi_clk_rate); 2265 } else if (j == sensor->endpoint.nr_of_link_frequencies) { 2266 dev_err(sensor->dev, 2267 "failed to find %lu clk rate in endpoint link-frequencies\n", 2268 mipi_clk_rate); 2269 } else { 2270 __v4l2_ctrl_s_ctrl(ctrls->link_freq, i); 2271 } 2272 2273 switch (mbus_code) { 2274 case MEDIA_BUS_FMT_SBGGR10_1X10: 2275 bits_per_sample = 10; 2276 break; 2277 default: 2278 return -EINVAL; 2279 } 2280 2281 lanes_count = bus_mipi_csi2->num_data_lanes; 2282 mipi_pixel_rate = mipi_clk_rate * 2 * lanes_count / bits_per_sample; 2283 2284 __v4l2_ctrl_s_ctrl_int64(ctrls->pixel_rate, mipi_pixel_rate); 2285 2286 return 0; 2287 } 2288 2289 static int ov8865_state_configure(struct ov8865_sensor *sensor, 2290 const struct ov8865_mode *mode, 2291 u32 mbus_code) 2292 { 2293 int ret; 2294 2295 if (sensor->state.streaming) 2296 return -EBUSY; 2297 2298 /* State will be configured at first power on otherwise. */ 2299 if (pm_runtime_enabled(sensor->dev) && 2300 !pm_runtime_suspended(sensor->dev)) { 2301 ret = ov8865_mode_configure(sensor, mode, mbus_code); 2302 if (ret) 2303 return ret; 2304 } 2305 2306 ret = ov8865_state_mipi_configure(sensor, mode, mbus_code); 2307 if (ret) 2308 return ret; 2309 2310 sensor->state.mode = mode; 2311 sensor->state.mbus_code = mbus_code; 2312 2313 return 0; 2314 } 2315 2316 static int ov8865_state_init(struct ov8865_sensor *sensor) 2317 { 2318 return ov8865_state_configure(sensor, &ov8865_modes[0], 2319 ov8865_mbus_codes[0]); 2320 } 2321 2322 /* Sensor Base */ 2323 2324 static int ov8865_sensor_init(struct ov8865_sensor *sensor) 2325 { 2326 int ret; 2327 2328 ret = ov8865_sw_reset(sensor); 2329 if (ret) { 2330 dev_err(sensor->dev, "failed to perform sw reset\n"); 2331 return ret; 2332 } 2333 2334 ret = ov8865_sw_standby(sensor, 1); 2335 if (ret) { 2336 dev_err(sensor->dev, "failed to set sensor standby\n"); 2337 return ret; 2338 } 2339 2340 ret = ov8865_chip_id_check(sensor); 2341 if (ret) { 2342 dev_err(sensor->dev, "failed to check sensor chip id\n"); 2343 return ret; 2344 } 2345 2346 ret = ov8865_write_sequence(sensor, ov8865_init_sequence, 2347 ARRAY_SIZE(ov8865_init_sequence)); 2348 if (ret) { 2349 dev_err(sensor->dev, "failed to write init sequence\n"); 2350 return ret; 2351 } 2352 2353 ret = ov8865_charge_pump_configure(sensor); 2354 if (ret) { 2355 dev_err(sensor->dev, "failed to configure pad\n"); 2356 return ret; 2357 } 2358 2359 ret = ov8865_mipi_configure(sensor); 2360 if (ret) { 2361 dev_err(sensor->dev, "failed to configure MIPI\n"); 2362 return ret; 2363 } 2364 2365 ret = ov8865_isp_configure(sensor); 2366 if (ret) { 2367 dev_err(sensor->dev, "failed to configure ISP\n"); 2368 return ret; 2369 } 2370 2371 ret = ov8865_black_level_configure(sensor); 2372 if (ret) { 2373 dev_err(sensor->dev, "failed to configure black level\n"); 2374 return ret; 2375 } 2376 2377 /* Configure current mode. */ 2378 ret = ov8865_state_configure(sensor, sensor->state.mode, 2379 sensor->state.mbus_code); 2380 if (ret) { 2381 dev_err(sensor->dev, "failed to configure state\n"); 2382 return ret; 2383 } 2384 2385 return 0; 2386 } 2387 2388 static int ov8865_sensor_power(struct ov8865_sensor *sensor, bool on) 2389 { 2390 /* Keep initialized to zero for disable label. */ 2391 int ret = 0; 2392 2393 if (on) { 2394 gpiod_set_value_cansleep(sensor->reset, 1); 2395 gpiod_set_value_cansleep(sensor->powerdown, 1); 2396 2397 ret = regulator_enable(sensor->dovdd); 2398 if (ret) { 2399 dev_err(sensor->dev, 2400 "failed to enable DOVDD regulator\n"); 2401 goto disable; 2402 } 2403 2404 ret = regulator_enable(sensor->avdd); 2405 if (ret) { 2406 dev_err(sensor->dev, 2407 "failed to enable AVDD regulator\n"); 2408 goto disable; 2409 } 2410 2411 ret = regulator_enable(sensor->dvdd); 2412 if (ret) { 2413 dev_err(sensor->dev, 2414 "failed to enable DVDD regulator\n"); 2415 goto disable; 2416 } 2417 2418 ret = clk_prepare_enable(sensor->extclk); 2419 if (ret) { 2420 dev_err(sensor->dev, "failed to enable EXTCLK clock\n"); 2421 goto disable; 2422 } 2423 2424 gpiod_set_value_cansleep(sensor->reset, 0); 2425 gpiod_set_value_cansleep(sensor->powerdown, 0); 2426 2427 /* Time to enter streaming mode according to power timings. */ 2428 usleep_range(10000, 12000); 2429 } else { 2430 disable: 2431 gpiod_set_value_cansleep(sensor->powerdown, 1); 2432 gpiod_set_value_cansleep(sensor->reset, 1); 2433 2434 clk_disable_unprepare(sensor->extclk); 2435 2436 regulator_disable(sensor->dvdd); 2437 regulator_disable(sensor->avdd); 2438 regulator_disable(sensor->dovdd); 2439 } 2440 2441 return ret; 2442 } 2443 2444 /* Controls */ 2445 2446 static int ov8865_s_ctrl(struct v4l2_ctrl *ctrl) 2447 { 2448 struct v4l2_subdev *subdev = ov8865_ctrl_subdev(ctrl); 2449 struct ov8865_sensor *sensor = ov8865_subdev_sensor(subdev); 2450 unsigned int index; 2451 int ret; 2452 2453 /* Wait for the sensor to be on before setting controls. */ 2454 if (pm_runtime_suspended(sensor->dev)) 2455 return 0; 2456 2457 switch (ctrl->id) { 2458 case V4L2_CID_EXPOSURE: 2459 ret = ov8865_exposure_configure(sensor, ctrl->val); 2460 if (ret) 2461 return ret; 2462 break; 2463 case V4L2_CID_ANALOGUE_GAIN: 2464 ret = ov8865_analog_gain_configure(sensor, ctrl->val); 2465 if (ret) 2466 return ret; 2467 break; 2468 case V4L2_CID_RED_BALANCE: 2469 return ov8865_red_balance_configure(sensor, ctrl->val); 2470 case V4L2_CID_BLUE_BALANCE: 2471 return ov8865_blue_balance_configure(sensor, ctrl->val); 2472 case V4L2_CID_HFLIP: 2473 return ov8865_flip_horz_configure(sensor, !!ctrl->val); 2474 case V4L2_CID_VFLIP: 2475 return ov8865_flip_vert_configure(sensor, !!ctrl->val); 2476 case V4L2_CID_TEST_PATTERN: 2477 index = (unsigned int)ctrl->val; 2478 return ov8865_test_pattern_configure(sensor, index); 2479 default: 2480 return -EINVAL; 2481 } 2482 2483 return 0; 2484 } 2485 2486 static const struct v4l2_ctrl_ops ov8865_ctrl_ops = { 2487 .s_ctrl = ov8865_s_ctrl, 2488 }; 2489 2490 static int ov8865_ctrls_init(struct ov8865_sensor *sensor) 2491 { 2492 struct ov8865_ctrls *ctrls = &sensor->ctrls; 2493 struct v4l2_ctrl_handler *handler = &ctrls->handler; 2494 const struct v4l2_ctrl_ops *ops = &ov8865_ctrl_ops; 2495 int ret; 2496 2497 v4l2_ctrl_handler_init(handler, 32); 2498 2499 /* Use our mutex for ctrl locking. */ 2500 handler->lock = &sensor->mutex; 2501 2502 /* Exposure */ 2503 2504 v4l2_ctrl_new_std(handler, ops, V4L2_CID_EXPOSURE, 16, 1048575, 16, 2505 512); 2506 2507 /* Gain */ 2508 2509 v4l2_ctrl_new_std(handler, ops, V4L2_CID_ANALOGUE_GAIN, 128, 8191, 128, 2510 128); 2511 2512 /* White Balance */ 2513 2514 v4l2_ctrl_new_std(handler, ops, V4L2_CID_RED_BALANCE, 1, 32767, 1, 2515 1024); 2516 2517 v4l2_ctrl_new_std(handler, ops, V4L2_CID_BLUE_BALANCE, 1, 32767, 1, 2518 1024); 2519 2520 /* Flip */ 2521 2522 v4l2_ctrl_new_std(handler, ops, V4L2_CID_HFLIP, 0, 1, 1, 0); 2523 v4l2_ctrl_new_std(handler, ops, V4L2_CID_VFLIP, 0, 1, 1, 0); 2524 2525 /* Test Pattern */ 2526 2527 v4l2_ctrl_new_std_menu_items(handler, ops, V4L2_CID_TEST_PATTERN, 2528 ARRAY_SIZE(ov8865_test_pattern_menu) - 1, 2529 0, 0, ov8865_test_pattern_menu); 2530 2531 /* MIPI CSI-2 */ 2532 2533 ctrls->link_freq = 2534 v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ, 2535 ARRAY_SIZE(ov8865_link_freq_menu) - 1, 2536 0, ov8865_link_freq_menu); 2537 2538 ctrls->pixel_rate = 2539 v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE, 1, 2540 INT_MAX, 1, 1); 2541 2542 if (handler->error) { 2543 ret = handler->error; 2544 goto error_ctrls; 2545 } 2546 2547 ctrls->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 2548 ctrls->pixel_rate->flags |= V4L2_CTRL_FLAG_READ_ONLY; 2549 2550 sensor->subdev.ctrl_handler = handler; 2551 2552 return 0; 2553 2554 error_ctrls: 2555 v4l2_ctrl_handler_free(handler); 2556 2557 return ret; 2558 } 2559 2560 /* Subdev Video Operations */ 2561 2562 static int ov8865_s_stream(struct v4l2_subdev *subdev, int enable) 2563 { 2564 struct ov8865_sensor *sensor = ov8865_subdev_sensor(subdev); 2565 struct ov8865_state *state = &sensor->state; 2566 int ret; 2567 2568 if (enable) { 2569 ret = pm_runtime_resume_and_get(sensor->dev); 2570 if (ret < 0) 2571 return ret; 2572 } 2573 2574 mutex_lock(&sensor->mutex); 2575 ret = ov8865_sw_standby(sensor, !enable); 2576 mutex_unlock(&sensor->mutex); 2577 2578 if (ret) 2579 return ret; 2580 2581 state->streaming = !!enable; 2582 2583 if (!enable) 2584 pm_runtime_put(sensor->dev); 2585 2586 return 0; 2587 } 2588 2589 static int ov8865_g_frame_interval(struct v4l2_subdev *subdev, 2590 struct v4l2_subdev_frame_interval *interval) 2591 { 2592 struct ov8865_sensor *sensor = ov8865_subdev_sensor(subdev); 2593 const struct ov8865_mode *mode; 2594 2595 mutex_lock(&sensor->mutex); 2596 2597 mode = sensor->state.mode; 2598 interval->interval = mode->frame_interval; 2599 2600 mutex_unlock(&sensor->mutex); 2601 2602 return 0; 2603 } 2604 2605 static const struct v4l2_subdev_video_ops ov8865_subdev_video_ops = { 2606 .s_stream = ov8865_s_stream, 2607 .g_frame_interval = ov8865_g_frame_interval, 2608 .s_frame_interval = ov8865_g_frame_interval, 2609 }; 2610 2611 /* Subdev Pad Operations */ 2612 2613 static int ov8865_enum_mbus_code(struct v4l2_subdev *subdev, 2614 struct v4l2_subdev_state *sd_state, 2615 struct v4l2_subdev_mbus_code_enum *code_enum) 2616 { 2617 if (code_enum->index >= ARRAY_SIZE(ov8865_mbus_codes)) 2618 return -EINVAL; 2619 2620 code_enum->code = ov8865_mbus_codes[code_enum->index]; 2621 2622 return 0; 2623 } 2624 2625 static void ov8865_mbus_format_fill(struct v4l2_mbus_framefmt *mbus_format, 2626 u32 mbus_code, 2627 const struct ov8865_mode *mode) 2628 { 2629 mbus_format->width = mode->output_size_x; 2630 mbus_format->height = mode->output_size_y; 2631 mbus_format->code = mbus_code; 2632 2633 mbus_format->field = V4L2_FIELD_NONE; 2634 mbus_format->colorspace = V4L2_COLORSPACE_RAW; 2635 mbus_format->ycbcr_enc = 2636 V4L2_MAP_YCBCR_ENC_DEFAULT(mbus_format->colorspace); 2637 mbus_format->quantization = V4L2_QUANTIZATION_FULL_RANGE; 2638 mbus_format->xfer_func = 2639 V4L2_MAP_XFER_FUNC_DEFAULT(mbus_format->colorspace); 2640 } 2641 2642 static int ov8865_get_fmt(struct v4l2_subdev *subdev, 2643 struct v4l2_subdev_state *sd_state, 2644 struct v4l2_subdev_format *format) 2645 { 2646 struct ov8865_sensor *sensor = ov8865_subdev_sensor(subdev); 2647 struct v4l2_mbus_framefmt *mbus_format = &format->format; 2648 2649 mutex_lock(&sensor->mutex); 2650 2651 if (format->which == V4L2_SUBDEV_FORMAT_TRY) 2652 *mbus_format = *v4l2_subdev_get_try_format(subdev, sd_state, 2653 format->pad); 2654 else 2655 ov8865_mbus_format_fill(mbus_format, sensor->state.mbus_code, 2656 sensor->state.mode); 2657 2658 mutex_unlock(&sensor->mutex); 2659 2660 return 0; 2661 } 2662 2663 static int ov8865_set_fmt(struct v4l2_subdev *subdev, 2664 struct v4l2_subdev_state *sd_state, 2665 struct v4l2_subdev_format *format) 2666 { 2667 struct ov8865_sensor *sensor = ov8865_subdev_sensor(subdev); 2668 struct v4l2_mbus_framefmt *mbus_format = &format->format; 2669 const struct ov8865_mode *mode; 2670 u32 mbus_code = 0; 2671 unsigned int index; 2672 int ret = 0; 2673 2674 mutex_lock(&sensor->mutex); 2675 2676 if (sensor->state.streaming) { 2677 ret = -EBUSY; 2678 goto complete; 2679 } 2680 2681 /* Try to find requested mbus code. */ 2682 for (index = 0; index < ARRAY_SIZE(ov8865_mbus_codes); index++) { 2683 if (ov8865_mbus_codes[index] == mbus_format->code) { 2684 mbus_code = mbus_format->code; 2685 break; 2686 } 2687 } 2688 2689 /* Fallback to default. */ 2690 if (!mbus_code) 2691 mbus_code = ov8865_mbus_codes[0]; 2692 2693 /* Find the mode with nearest dimensions. */ 2694 mode = v4l2_find_nearest_size(ov8865_modes, ARRAY_SIZE(ov8865_modes), 2695 output_size_x, output_size_y, 2696 mbus_format->width, mbus_format->height); 2697 if (!mode) { 2698 ret = -EINVAL; 2699 goto complete; 2700 } 2701 2702 ov8865_mbus_format_fill(mbus_format, mbus_code, mode); 2703 2704 if (format->which == V4L2_SUBDEV_FORMAT_TRY) 2705 *v4l2_subdev_get_try_format(subdev, sd_state, format->pad) = 2706 *mbus_format; 2707 else if (sensor->state.mode != mode || 2708 sensor->state.mbus_code != mbus_code) 2709 ret = ov8865_state_configure(sensor, mode, mbus_code); 2710 2711 complete: 2712 mutex_unlock(&sensor->mutex); 2713 2714 return ret; 2715 } 2716 2717 static int ov8865_enum_frame_size(struct v4l2_subdev *subdev, 2718 struct v4l2_subdev_state *sd_state, 2719 struct v4l2_subdev_frame_size_enum *size_enum) 2720 { 2721 const struct ov8865_mode *mode; 2722 2723 if (size_enum->index >= ARRAY_SIZE(ov8865_modes)) 2724 return -EINVAL; 2725 2726 mode = &ov8865_modes[size_enum->index]; 2727 2728 size_enum->min_width = size_enum->max_width = mode->output_size_x; 2729 size_enum->min_height = size_enum->max_height = mode->output_size_y; 2730 2731 return 0; 2732 } 2733 2734 static int ov8865_enum_frame_interval(struct v4l2_subdev *subdev, 2735 struct v4l2_subdev_state *sd_state, 2736 struct v4l2_subdev_frame_interval_enum *interval_enum) 2737 { 2738 const struct ov8865_mode *mode = NULL; 2739 unsigned int mode_index; 2740 unsigned int interval_index; 2741 2742 if (interval_enum->index > 0) 2743 return -EINVAL; 2744 /* 2745 * Multiple modes with the same dimensions may have different frame 2746 * intervals, so look up each relevant mode. 2747 */ 2748 for (mode_index = 0, interval_index = 0; 2749 mode_index < ARRAY_SIZE(ov8865_modes); mode_index++) { 2750 mode = &ov8865_modes[mode_index]; 2751 2752 if (mode->output_size_x == interval_enum->width && 2753 mode->output_size_y == interval_enum->height) { 2754 if (interval_index == interval_enum->index) 2755 break; 2756 2757 interval_index++; 2758 } 2759 } 2760 2761 if (mode_index == ARRAY_SIZE(ov8865_modes)) 2762 return -EINVAL; 2763 2764 interval_enum->interval = mode->frame_interval; 2765 2766 return 0; 2767 } 2768 2769 static void 2770 __ov8865_get_pad_crop(struct ov8865_sensor *sensor, 2771 struct v4l2_subdev_state *state, unsigned int pad, 2772 enum v4l2_subdev_format_whence which, struct v4l2_rect *r) 2773 { 2774 const struct ov8865_mode *mode = sensor->state.mode; 2775 2776 switch (which) { 2777 case V4L2_SUBDEV_FORMAT_TRY: 2778 *r = *v4l2_subdev_get_try_crop(&sensor->subdev, state, pad); 2779 break; 2780 case V4L2_SUBDEV_FORMAT_ACTIVE: 2781 r->height = mode->output_size_y; 2782 r->width = mode->output_size_x; 2783 r->top = (OV8865_NATIVE_HEIGHT - mode->output_size_y) / 2; 2784 r->left = (OV8865_NATIVE_WIDTH - mode->output_size_x) / 2; 2785 break; 2786 } 2787 } 2788 2789 static int ov8865_get_selection(struct v4l2_subdev *subdev, 2790 struct v4l2_subdev_state *state, 2791 struct v4l2_subdev_selection *sel) 2792 { 2793 struct ov8865_sensor *sensor = ov8865_subdev_sensor(subdev); 2794 2795 switch (sel->target) { 2796 case V4L2_SEL_TGT_CROP: 2797 mutex_lock(&sensor->mutex); 2798 __ov8865_get_pad_crop(sensor, state, sel->pad, 2799 sel->which, &sel->r); 2800 mutex_unlock(&sensor->mutex); 2801 break; 2802 case V4L2_SEL_TGT_NATIVE_SIZE: 2803 sel->r.top = 0; 2804 sel->r.left = 0; 2805 sel->r.width = OV8865_NATIVE_WIDTH; 2806 sel->r.height = OV8865_NATIVE_HEIGHT; 2807 break; 2808 case V4L2_SEL_TGT_CROP_BOUNDS: 2809 case V4L2_SEL_TGT_CROP_DEFAULT: 2810 sel->r.top = OV8865_ACTIVE_START_TOP; 2811 sel->r.left = OV8865_ACTIVE_START_LEFT; 2812 sel->r.width = OV8865_ACTIVE_WIDTH; 2813 sel->r.height = OV8865_ACTIVE_HEIGHT; 2814 break; 2815 default: 2816 return -EINVAL; 2817 } 2818 2819 return 0; 2820 } 2821 2822 static const struct v4l2_subdev_pad_ops ov8865_subdev_pad_ops = { 2823 .enum_mbus_code = ov8865_enum_mbus_code, 2824 .get_fmt = ov8865_get_fmt, 2825 .set_fmt = ov8865_set_fmt, 2826 .enum_frame_size = ov8865_enum_frame_size, 2827 .enum_frame_interval = ov8865_enum_frame_interval, 2828 .get_selection = ov8865_get_selection, 2829 .set_selection = ov8865_get_selection, 2830 }; 2831 2832 static const struct v4l2_subdev_ops ov8865_subdev_ops = { 2833 .video = &ov8865_subdev_video_ops, 2834 .pad = &ov8865_subdev_pad_ops, 2835 }; 2836 2837 static int ov8865_suspend(struct device *dev) 2838 { 2839 struct i2c_client *client = to_i2c_client(dev); 2840 struct v4l2_subdev *subdev = i2c_get_clientdata(client); 2841 struct ov8865_sensor *sensor = ov8865_subdev_sensor(subdev); 2842 struct ov8865_state *state = &sensor->state; 2843 int ret = 0; 2844 2845 mutex_lock(&sensor->mutex); 2846 2847 if (state->streaming) { 2848 ret = ov8865_sw_standby(sensor, true); 2849 if (ret) 2850 goto complete; 2851 } 2852 2853 ret = ov8865_sensor_power(sensor, false); 2854 if (ret) 2855 ov8865_sw_standby(sensor, false); 2856 2857 complete: 2858 mutex_unlock(&sensor->mutex); 2859 2860 return ret; 2861 } 2862 2863 static int ov8865_resume(struct device *dev) 2864 { 2865 struct i2c_client *client = to_i2c_client(dev); 2866 struct v4l2_subdev *subdev = i2c_get_clientdata(client); 2867 struct ov8865_sensor *sensor = ov8865_subdev_sensor(subdev); 2868 struct ov8865_state *state = &sensor->state; 2869 int ret = 0; 2870 2871 mutex_lock(&sensor->mutex); 2872 2873 ret = ov8865_sensor_power(sensor, true); 2874 if (ret) 2875 goto complete; 2876 2877 ret = ov8865_sensor_init(sensor); 2878 if (ret) 2879 goto error_power; 2880 2881 ret = __v4l2_ctrl_handler_setup(&sensor->ctrls.handler); 2882 if (ret) 2883 goto error_power; 2884 2885 if (state->streaming) { 2886 ret = ov8865_sw_standby(sensor, false); 2887 if (ret) 2888 goto error_power; 2889 } 2890 2891 goto complete; 2892 2893 error_power: 2894 ov8865_sensor_power(sensor, false); 2895 2896 complete: 2897 mutex_unlock(&sensor->mutex); 2898 2899 return ret; 2900 } 2901 2902 static int ov8865_probe(struct i2c_client *client) 2903 { 2904 struct device *dev = &client->dev; 2905 struct fwnode_handle *handle; 2906 struct ov8865_sensor *sensor; 2907 struct v4l2_subdev *subdev; 2908 struct media_pad *pad; 2909 unsigned int rate = 0; 2910 unsigned int i; 2911 int ret; 2912 2913 sensor = devm_kzalloc(dev, sizeof(*sensor), GFP_KERNEL); 2914 if (!sensor) 2915 return -ENOMEM; 2916 2917 sensor->dev = dev; 2918 sensor->i2c_client = client; 2919 2920 /* Graph Endpoint */ 2921 2922 handle = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL); 2923 if (!handle) 2924 return -EPROBE_DEFER; 2925 2926 sensor->endpoint.bus_type = V4L2_MBUS_CSI2_DPHY; 2927 2928 ret = v4l2_fwnode_endpoint_alloc_parse(handle, &sensor->endpoint); 2929 fwnode_handle_put(handle); 2930 if (ret) { 2931 dev_err(dev, "failed to parse endpoint node\n"); 2932 return ret; 2933 } 2934 2935 /* GPIOs */ 2936 2937 sensor->powerdown = devm_gpiod_get_optional(dev, "powerdown", 2938 GPIOD_OUT_HIGH); 2939 if (IS_ERR(sensor->powerdown)) { 2940 ret = PTR_ERR(sensor->powerdown); 2941 goto error_endpoint; 2942 } 2943 2944 sensor->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); 2945 if (IS_ERR(sensor->reset)) { 2946 ret = PTR_ERR(sensor->reset); 2947 goto error_endpoint; 2948 } 2949 2950 /* Regulators */ 2951 2952 /* DVDD: digital core */ 2953 sensor->dvdd = devm_regulator_get(dev, "dvdd"); 2954 if (IS_ERR(sensor->dvdd)) { 2955 dev_err(dev, "cannot get DVDD (digital core) regulator\n"); 2956 ret = PTR_ERR(sensor->dvdd); 2957 goto error_endpoint; 2958 } 2959 2960 /* DOVDD: digital I/O */ 2961 sensor->dovdd = devm_regulator_get(dev, "dovdd"); 2962 if (IS_ERR(sensor->dovdd)) { 2963 dev_err(dev, "cannot get DOVDD (digital I/O) regulator\n"); 2964 ret = PTR_ERR(sensor->dovdd); 2965 goto error_endpoint; 2966 } 2967 2968 /* AVDD: analog */ 2969 sensor->avdd = devm_regulator_get(dev, "avdd"); 2970 if (IS_ERR(sensor->avdd)) { 2971 dev_err(dev, "cannot get AVDD (analog) regulator\n"); 2972 ret = PTR_ERR(sensor->avdd); 2973 goto error_endpoint; 2974 } 2975 2976 /* External Clock */ 2977 2978 sensor->extclk = devm_clk_get(dev, NULL); 2979 if (PTR_ERR(sensor->extclk) == -ENOENT) { 2980 dev_info(dev, "no external clock found, continuing...\n"); 2981 sensor->extclk = NULL; 2982 } else if (IS_ERR(sensor->extclk)) { 2983 dev_err(dev, "failed to get external clock\n"); 2984 ret = PTR_ERR(sensor->extclk); 2985 goto error_endpoint; 2986 } 2987 2988 /* 2989 * We could have either a 24MHz or 19.2MHz clock rate from either dt or 2990 * ACPI...but we also need to support the weird IPU3 case which will 2991 * have an external clock AND a clock-frequency property. Check for the 2992 * clock-frequency property and if found, set that rate if we managed 2993 * to acquire a clock. This should cover the ACPI case. If the system 2994 * uses devicetree then the configured rate should already be set, so 2995 * we can just read it. 2996 */ 2997 ret = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency", 2998 &rate); 2999 if (!ret && sensor->extclk) { 3000 ret = clk_set_rate(sensor->extclk, rate); 3001 if (ret) 3002 return dev_err_probe(dev, ret, 3003 "failed to set clock rate\n"); 3004 } else if (ret && !sensor->extclk) { 3005 return dev_err_probe(dev, ret, "invalid clock config\n"); 3006 } 3007 3008 sensor->extclk_rate = rate ? rate : clk_get_rate(sensor->extclk); 3009 3010 for (i = 0; i < ARRAY_SIZE(supported_extclk_rates); i++) { 3011 if (sensor->extclk_rate == supported_extclk_rates[i]) 3012 break; 3013 } 3014 3015 if (i == ARRAY_SIZE(supported_extclk_rates)) { 3016 dev_err(dev, "clock rate %lu Hz is unsupported\n", 3017 sensor->extclk_rate); 3018 ret = -EINVAL; 3019 goto error_endpoint; 3020 } 3021 3022 sensor->pll_configs = ov8865_pll_configs[i]; 3023 3024 /* Subdev, entity and pad */ 3025 3026 subdev = &sensor->subdev; 3027 v4l2_i2c_subdev_init(subdev, client, &ov8865_subdev_ops); 3028 3029 subdev->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 3030 subdev->entity.function = MEDIA_ENT_F_CAM_SENSOR; 3031 3032 pad = &sensor->pad; 3033 pad->flags = MEDIA_PAD_FL_SOURCE; 3034 3035 ret = media_entity_pads_init(&subdev->entity, 1, pad); 3036 if (ret) 3037 goto error_entity; 3038 3039 /* Mutex */ 3040 3041 mutex_init(&sensor->mutex); 3042 3043 /* Sensor */ 3044 3045 ret = ov8865_ctrls_init(sensor); 3046 if (ret) 3047 goto error_mutex; 3048 3049 mutex_lock(&sensor->mutex); 3050 ret = ov8865_state_init(sensor); 3051 mutex_unlock(&sensor->mutex); 3052 if (ret) 3053 goto error_ctrls; 3054 3055 /* Runtime PM */ 3056 3057 pm_runtime_set_suspended(sensor->dev); 3058 pm_runtime_enable(sensor->dev); 3059 3060 /* V4L2 subdev register */ 3061 3062 ret = v4l2_async_register_subdev_sensor(subdev); 3063 if (ret) 3064 goto error_pm; 3065 3066 return 0; 3067 3068 error_pm: 3069 pm_runtime_disable(sensor->dev); 3070 3071 error_ctrls: 3072 v4l2_ctrl_handler_free(&sensor->ctrls.handler); 3073 3074 error_mutex: 3075 mutex_destroy(&sensor->mutex); 3076 3077 error_entity: 3078 media_entity_cleanup(&sensor->subdev.entity); 3079 3080 error_endpoint: 3081 v4l2_fwnode_endpoint_free(&sensor->endpoint); 3082 3083 return ret; 3084 } 3085 3086 static int ov8865_remove(struct i2c_client *client) 3087 { 3088 struct v4l2_subdev *subdev = i2c_get_clientdata(client); 3089 struct ov8865_sensor *sensor = ov8865_subdev_sensor(subdev); 3090 3091 v4l2_async_unregister_subdev(subdev); 3092 pm_runtime_disable(sensor->dev); 3093 v4l2_ctrl_handler_free(&sensor->ctrls.handler); 3094 mutex_destroy(&sensor->mutex); 3095 media_entity_cleanup(&subdev->entity); 3096 3097 v4l2_fwnode_endpoint_free(&sensor->endpoint); 3098 3099 return 0; 3100 } 3101 3102 static const struct dev_pm_ops ov8865_pm_ops = { 3103 SET_RUNTIME_PM_OPS(ov8865_suspend, ov8865_resume, NULL) 3104 }; 3105 3106 static const struct acpi_device_id ov8865_acpi_match[] = { 3107 {"INT347A"}, 3108 { } 3109 }; 3110 MODULE_DEVICE_TABLE(acpi, ov8865_acpi_match); 3111 3112 static const struct of_device_id ov8865_of_match[] = { 3113 { .compatible = "ovti,ov8865" }, 3114 { } 3115 }; 3116 MODULE_DEVICE_TABLE(of, ov8865_of_match); 3117 3118 static struct i2c_driver ov8865_driver = { 3119 .driver = { 3120 .name = "ov8865", 3121 .of_match_table = ov8865_of_match, 3122 .acpi_match_table = ov8865_acpi_match, 3123 .pm = &ov8865_pm_ops, 3124 }, 3125 .probe_new = ov8865_probe, 3126 .remove = ov8865_remove, 3127 }; 3128 3129 module_i2c_driver(ov8865_driver); 3130 3131 MODULE_AUTHOR("Paul Kocialkowski <paul.kocialkowski@bootlin.com>"); 3132 MODULE_DESCRIPTION("V4L2 driver for the OmniVision OV8865 image sensor"); 3133 MODULE_LICENSE("GPL v2"); 3134