1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ov772x Camera Driver 4 * 5 * Copyright (C) 2017 Jacopo Mondi <jacopo+renesas@jmondi.org> 6 * 7 * Copyright (C) 2008 Renesas Solutions Corp. 8 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 9 * 10 * Based on ov7670 and soc_camera_platform driver, 11 * 12 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net> 13 * Copyright (C) 2008 Magnus Damm 14 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> 15 */ 16 17 #include <linux/clk.h> 18 #include <linux/delay.h> 19 #include <linux/gpio/consumer.h> 20 #include <linux/i2c.h> 21 #include <linux/init.h> 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/slab.h> 25 #include <linux/v4l2-mediabus.h> 26 #include <linux/videodev2.h> 27 28 #include <media/i2c/ov772x.h> 29 30 #include <media/v4l2-ctrls.h> 31 #include <media/v4l2-device.h> 32 #include <media/v4l2-image-sizes.h> 33 #include <media/v4l2-subdev.h> 34 35 /* 36 * register offset 37 */ 38 #define GAIN 0x00 /* AGC - Gain control gain setting */ 39 #define BLUE 0x01 /* AWB - Blue channel gain setting */ 40 #define RED 0x02 /* AWB - Red channel gain setting */ 41 #define GREEN 0x03 /* AWB - Green channel gain setting */ 42 #define COM1 0x04 /* Common control 1 */ 43 #define BAVG 0x05 /* U/B Average Level */ 44 #define GAVG 0x06 /* Y/Gb Average Level */ 45 #define RAVG 0x07 /* V/R Average Level */ 46 #define AECH 0x08 /* Exposure Value - AEC MSBs */ 47 #define COM2 0x09 /* Common control 2 */ 48 #define PID 0x0A /* Product ID Number MSB */ 49 #define VER 0x0B /* Product ID Number LSB */ 50 #define COM3 0x0C /* Common control 3 */ 51 #define COM4 0x0D /* Common control 4 */ 52 #define COM5 0x0E /* Common control 5 */ 53 #define COM6 0x0F /* Common control 6 */ 54 #define AEC 0x10 /* Exposure Value */ 55 #define CLKRC 0x11 /* Internal clock */ 56 #define COM7 0x12 /* Common control 7 */ 57 #define COM8 0x13 /* Common control 8 */ 58 #define COM9 0x14 /* Common control 9 */ 59 #define COM10 0x15 /* Common control 10 */ 60 #define REG16 0x16 /* Register 16 */ 61 #define HSTART 0x17 /* Horizontal sensor size */ 62 #define HSIZE 0x18 /* Horizontal frame (HREF column) end high 8-bit */ 63 #define VSTART 0x19 /* Vertical frame (row) start high 8-bit */ 64 #define VSIZE 0x1A /* Vertical sensor size */ 65 #define PSHFT 0x1B /* Data format - pixel delay select */ 66 #define MIDH 0x1C /* Manufacturer ID byte - high */ 67 #define MIDL 0x1D /* Manufacturer ID byte - low */ 68 #define LAEC 0x1F /* Fine AEC value */ 69 #define COM11 0x20 /* Common control 11 */ 70 #define BDBASE 0x22 /* Banding filter Minimum AEC value */ 71 #define DBSTEP 0x23 /* Banding filter Maximum Setp */ 72 #define AEW 0x24 /* AGC/AEC - Stable operating region (upper limit) */ 73 #define AEB 0x25 /* AGC/AEC - Stable operating region (lower limit) */ 74 #define VPT 0x26 /* AGC/AEC Fast mode operating region */ 75 #define REG28 0x28 /* Register 28 */ 76 #define HOUTSIZE 0x29 /* Horizontal data output size MSBs */ 77 #define EXHCH 0x2A /* Dummy pixel insert MSB */ 78 #define EXHCL 0x2B /* Dummy pixel insert LSB */ 79 #define VOUTSIZE 0x2C /* Vertical data output size MSBs */ 80 #define ADVFL 0x2D /* LSB of insert dummy lines in Vertical direction */ 81 #define ADVFH 0x2E /* MSG of insert dummy lines in Vertical direction */ 82 #define YAVE 0x2F /* Y/G Channel Average value */ 83 #define LUMHTH 0x30 /* Histogram AEC/AGC Luminance high level threshold */ 84 #define LUMLTH 0x31 /* Histogram AEC/AGC Luminance low level threshold */ 85 #define HREF 0x32 /* Image start and size control */ 86 #define DM_LNL 0x33 /* Dummy line low 8 bits */ 87 #define DM_LNH 0x34 /* Dummy line high 8 bits */ 88 #define ADOFF_B 0x35 /* AD offset compensation value for B channel */ 89 #define ADOFF_R 0x36 /* AD offset compensation value for R channel */ 90 #define ADOFF_GB 0x37 /* AD offset compensation value for Gb channel */ 91 #define ADOFF_GR 0x38 /* AD offset compensation value for Gr channel */ 92 #define OFF_B 0x39 /* Analog process B channel offset value */ 93 #define OFF_R 0x3A /* Analog process R channel offset value */ 94 #define OFF_GB 0x3B /* Analog process Gb channel offset value */ 95 #define OFF_GR 0x3C /* Analog process Gr channel offset value */ 96 #define COM12 0x3D /* Common control 12 */ 97 #define COM13 0x3E /* Common control 13 */ 98 #define COM14 0x3F /* Common control 14 */ 99 #define COM15 0x40 /* Common control 15*/ 100 #define COM16 0x41 /* Common control 16 */ 101 #define TGT_B 0x42 /* BLC blue channel target value */ 102 #define TGT_R 0x43 /* BLC red channel target value */ 103 #define TGT_GB 0x44 /* BLC Gb channel target value */ 104 #define TGT_GR 0x45 /* BLC Gr channel target value */ 105 /* for ov7720 */ 106 #define LCC0 0x46 /* Lens correction control 0 */ 107 #define LCC1 0x47 /* Lens correction option 1 - X coordinate */ 108 #define LCC2 0x48 /* Lens correction option 2 - Y coordinate */ 109 #define LCC3 0x49 /* Lens correction option 3 */ 110 #define LCC4 0x4A /* Lens correction option 4 - radius of the circular */ 111 #define LCC5 0x4B /* Lens correction option 5 */ 112 #define LCC6 0x4C /* Lens correction option 6 */ 113 /* for ov7725 */ 114 #define LC_CTR 0x46 /* Lens correction control */ 115 #define LC_XC 0x47 /* X coordinate of lens correction center relative */ 116 #define LC_YC 0x48 /* Y coordinate of lens correction center relative */ 117 #define LC_COEF 0x49 /* Lens correction coefficient */ 118 #define LC_RADI 0x4A /* Lens correction radius */ 119 #define LC_COEFB 0x4B /* Lens B channel compensation coefficient */ 120 #define LC_COEFR 0x4C /* Lens R channel compensation coefficient */ 121 122 #define FIXGAIN 0x4D /* Analog fix gain amplifer */ 123 #define AREF0 0x4E /* Sensor reference control */ 124 #define AREF1 0x4F /* Sensor reference current control */ 125 #define AREF2 0x50 /* Analog reference control */ 126 #define AREF3 0x51 /* ADC reference control */ 127 #define AREF4 0x52 /* ADC reference control */ 128 #define AREF5 0x53 /* ADC reference control */ 129 #define AREF6 0x54 /* Analog reference control */ 130 #define AREF7 0x55 /* Analog reference control */ 131 #define UFIX 0x60 /* U channel fixed value output */ 132 #define VFIX 0x61 /* V channel fixed value output */ 133 #define AWBB_BLK 0x62 /* AWB option for advanced AWB */ 134 #define AWB_CTRL0 0x63 /* AWB control byte 0 */ 135 #define DSP_CTRL1 0x64 /* DSP control byte 1 */ 136 #define DSP_CTRL2 0x65 /* DSP control byte 2 */ 137 #define DSP_CTRL3 0x66 /* DSP control byte 3 */ 138 #define DSP_CTRL4 0x67 /* DSP control byte 4 */ 139 #define AWB_BIAS 0x68 /* AWB BLC level clip */ 140 #define AWB_CTRL1 0x69 /* AWB control 1 */ 141 #define AWB_CTRL2 0x6A /* AWB control 2 */ 142 #define AWB_CTRL3 0x6B /* AWB control 3 */ 143 #define AWB_CTRL4 0x6C /* AWB control 4 */ 144 #define AWB_CTRL5 0x6D /* AWB control 5 */ 145 #define AWB_CTRL6 0x6E /* AWB control 6 */ 146 #define AWB_CTRL7 0x6F /* AWB control 7 */ 147 #define AWB_CTRL8 0x70 /* AWB control 8 */ 148 #define AWB_CTRL9 0x71 /* AWB control 9 */ 149 #define AWB_CTRL10 0x72 /* AWB control 10 */ 150 #define AWB_CTRL11 0x73 /* AWB control 11 */ 151 #define AWB_CTRL12 0x74 /* AWB control 12 */ 152 #define AWB_CTRL13 0x75 /* AWB control 13 */ 153 #define AWB_CTRL14 0x76 /* AWB control 14 */ 154 #define AWB_CTRL15 0x77 /* AWB control 15 */ 155 #define AWB_CTRL16 0x78 /* AWB control 16 */ 156 #define AWB_CTRL17 0x79 /* AWB control 17 */ 157 #define AWB_CTRL18 0x7A /* AWB control 18 */ 158 #define AWB_CTRL19 0x7B /* AWB control 19 */ 159 #define AWB_CTRL20 0x7C /* AWB control 20 */ 160 #define AWB_CTRL21 0x7D /* AWB control 21 */ 161 #define GAM1 0x7E /* Gamma Curve 1st segment input end point */ 162 #define GAM2 0x7F /* Gamma Curve 2nd segment input end point */ 163 #define GAM3 0x80 /* Gamma Curve 3rd segment input end point */ 164 #define GAM4 0x81 /* Gamma Curve 4th segment input end point */ 165 #define GAM5 0x82 /* Gamma Curve 5th segment input end point */ 166 #define GAM6 0x83 /* Gamma Curve 6th segment input end point */ 167 #define GAM7 0x84 /* Gamma Curve 7th segment input end point */ 168 #define GAM8 0x85 /* Gamma Curve 8th segment input end point */ 169 #define GAM9 0x86 /* Gamma Curve 9th segment input end point */ 170 #define GAM10 0x87 /* Gamma Curve 10th segment input end point */ 171 #define GAM11 0x88 /* Gamma Curve 11th segment input end point */ 172 #define GAM12 0x89 /* Gamma Curve 12th segment input end point */ 173 #define GAM13 0x8A /* Gamma Curve 13th segment input end point */ 174 #define GAM14 0x8B /* Gamma Curve 14th segment input end point */ 175 #define GAM15 0x8C /* Gamma Curve 15th segment input end point */ 176 #define SLOP 0x8D /* Gamma curve highest segment slope */ 177 #define DNSTH 0x8E /* De-noise threshold */ 178 #define EDGE_STRNGT 0x8F /* Edge strength control when manual mode */ 179 #define EDGE_TRSHLD 0x90 /* Edge threshold control when manual mode */ 180 #define DNSOFF 0x91 /* Auto De-noise threshold control */ 181 #define EDGE_UPPER 0x92 /* Edge strength upper limit when Auto mode */ 182 #define EDGE_LOWER 0x93 /* Edge strength lower limit when Auto mode */ 183 #define MTX1 0x94 /* Matrix coefficient 1 */ 184 #define MTX2 0x95 /* Matrix coefficient 2 */ 185 #define MTX3 0x96 /* Matrix coefficient 3 */ 186 #define MTX4 0x97 /* Matrix coefficient 4 */ 187 #define MTX5 0x98 /* Matrix coefficient 5 */ 188 #define MTX6 0x99 /* Matrix coefficient 6 */ 189 #define MTX_CTRL 0x9A /* Matrix control */ 190 #define BRIGHT 0x9B /* Brightness control */ 191 #define CNTRST 0x9C /* Contrast contrast */ 192 #define CNTRST_CTRL 0x9D /* Contrast contrast center */ 193 #define UVAD_J0 0x9E /* Auto UV adjust contrast 0 */ 194 #define UVAD_J1 0x9F /* Auto UV adjust contrast 1 */ 195 #define SCAL0 0xA0 /* Scaling control 0 */ 196 #define SCAL1 0xA1 /* Scaling control 1 */ 197 #define SCAL2 0xA2 /* Scaling control 2 */ 198 #define FIFODLYM 0xA3 /* FIFO manual mode delay control */ 199 #define FIFODLYA 0xA4 /* FIFO auto mode delay control */ 200 #define SDE 0xA6 /* Special digital effect control */ 201 #define USAT 0xA7 /* U component saturation control */ 202 #define VSAT 0xA8 /* V component saturation control */ 203 /* for ov7720 */ 204 #define HUE0 0xA9 /* Hue control 0 */ 205 #define HUE1 0xAA /* Hue control 1 */ 206 /* for ov7725 */ 207 #define HUECOS 0xA9 /* Cosine value */ 208 #define HUESIN 0xAA /* Sine value */ 209 210 #define SIGN 0xAB /* Sign bit for Hue and contrast */ 211 #define DSPAUTO 0xAC /* DSP auto function ON/OFF control */ 212 213 /* 214 * register detail 215 */ 216 217 /* COM2 */ 218 #define SOFT_SLEEP_MODE 0x10 /* Soft sleep mode */ 219 /* Output drive capability */ 220 #define OCAP_1x 0x00 /* 1x */ 221 #define OCAP_2x 0x01 /* 2x */ 222 #define OCAP_3x 0x02 /* 3x */ 223 #define OCAP_4x 0x03 /* 4x */ 224 225 /* COM3 */ 226 #define SWAP_MASK (SWAP_RGB | SWAP_YUV | SWAP_ML) 227 #define IMG_MASK (VFLIP_IMG | HFLIP_IMG) 228 229 #define VFLIP_IMG 0x80 /* Vertical flip image ON/OFF selection */ 230 #define HFLIP_IMG 0x40 /* Horizontal mirror image ON/OFF selection */ 231 #define SWAP_RGB 0x20 /* Swap B/R output sequence in RGB mode */ 232 #define SWAP_YUV 0x10 /* Swap Y/UV output sequence in YUV mode */ 233 #define SWAP_ML 0x08 /* Swap output MSB/LSB */ 234 /* Tri-state option for output clock */ 235 #define NOTRI_CLOCK 0x04 /* 0: Tri-state at this period */ 236 /* 1: No tri-state at this period */ 237 /* Tri-state option for output data */ 238 #define NOTRI_DATA 0x02 /* 0: Tri-state at this period */ 239 /* 1: No tri-state at this period */ 240 #define SCOLOR_TEST 0x01 /* Sensor color bar test pattern */ 241 242 /* COM4 */ 243 /* PLL frequency control */ 244 #define PLL_BYPASS 0x00 /* 00: Bypass PLL */ 245 #define PLL_4x 0x40 /* 01: PLL 4x */ 246 #define PLL_6x 0x80 /* 10: PLL 6x */ 247 #define PLL_8x 0xc0 /* 11: PLL 8x */ 248 /* AEC evaluate window */ 249 #define AEC_FULL 0x00 /* 00: Full window */ 250 #define AEC_1p2 0x10 /* 01: 1/2 window */ 251 #define AEC_1p4 0x20 /* 10: 1/4 window */ 252 #define AEC_2p3 0x30 /* 11: Low 2/3 window */ 253 #define COM4_RESERVED 0x01 /* Reserved bit */ 254 255 /* COM5 */ 256 #define AFR_ON_OFF 0x80 /* Auto frame rate control ON/OFF selection */ 257 #define AFR_SPPED 0x40 /* Auto frame rate control speed selection */ 258 /* Auto frame rate max rate control */ 259 #define AFR_NO_RATE 0x00 /* No reduction of frame rate */ 260 #define AFR_1p2 0x10 /* Max reduction to 1/2 frame rate */ 261 #define AFR_1p4 0x20 /* Max reduction to 1/4 frame rate */ 262 #define AFR_1p8 0x30 /* Max reduction to 1/8 frame rate */ 263 /* Auto frame rate active point control */ 264 #define AF_2x 0x00 /* Add frame when AGC reaches 2x gain */ 265 #define AF_4x 0x04 /* Add frame when AGC reaches 4x gain */ 266 #define AF_8x 0x08 /* Add frame when AGC reaches 8x gain */ 267 #define AF_16x 0x0c /* Add frame when AGC reaches 16x gain */ 268 /* AEC max step control */ 269 #define AEC_NO_LIMIT 0x01 /* 0 : AEC incease step has limit */ 270 /* 1 : No limit to AEC increase step */ 271 /* CLKRC */ 272 /* Input clock divider register */ 273 #define CLKRC_RESERVED 0x80 /* Reserved bit */ 274 #define CLKRC_DIV(n) ((n) - 1) 275 276 /* COM7 */ 277 /* SCCB Register Reset */ 278 #define SCCB_RESET 0x80 /* 0 : No change */ 279 /* 1 : Resets all registers to default */ 280 /* Resolution selection */ 281 #define SLCT_MASK 0x40 /* Mask of VGA or QVGA */ 282 #define SLCT_VGA 0x00 /* 0 : VGA */ 283 #define SLCT_QVGA 0x40 /* 1 : QVGA */ 284 #define ITU656_ON_OFF 0x20 /* ITU656 protocol ON/OFF selection */ 285 #define SENSOR_RAW 0x10 /* Sensor RAW */ 286 /* RGB output format control */ 287 #define FMT_MASK 0x0c /* Mask of color format */ 288 #define FMT_GBR422 0x00 /* 00 : GBR 4:2:2 */ 289 #define FMT_RGB565 0x04 /* 01 : RGB 565 */ 290 #define FMT_RGB555 0x08 /* 10 : RGB 555 */ 291 #define FMT_RGB444 0x0c /* 11 : RGB 444 */ 292 /* Output format control */ 293 #define OFMT_MASK 0x03 /* Mask of output format */ 294 #define OFMT_YUV 0x00 /* 00 : YUV */ 295 #define OFMT_P_BRAW 0x01 /* 01 : Processed Bayer RAW */ 296 #define OFMT_RGB 0x02 /* 10 : RGB */ 297 #define OFMT_BRAW 0x03 /* 11 : Bayer RAW */ 298 299 /* COM8 */ 300 #define FAST_ALGO 0x80 /* Enable fast AGC/AEC algorithm */ 301 /* AEC Setp size limit */ 302 #define UNLMT_STEP 0x40 /* 0 : Step size is limited */ 303 /* 1 : Unlimited step size */ 304 #define BNDF_ON_OFF 0x20 /* Banding filter ON/OFF */ 305 #define AEC_BND 0x10 /* Enable AEC below banding value */ 306 #define AEC_ON_OFF 0x08 /* Fine AEC ON/OFF control */ 307 #define AGC_ON 0x04 /* AGC Enable */ 308 #define AWB_ON 0x02 /* AWB Enable */ 309 #define AEC_ON 0x01 /* AEC Enable */ 310 311 /* COM9 */ 312 #define BASE_AECAGC 0x80 /* Histogram or average based AEC/AGC */ 313 /* Automatic gain ceiling - maximum AGC value */ 314 #define GAIN_2x 0x00 /* 000 : 2x */ 315 #define GAIN_4x 0x10 /* 001 : 4x */ 316 #define GAIN_8x 0x20 /* 010 : 8x */ 317 #define GAIN_16x 0x30 /* 011 : 16x */ 318 #define GAIN_32x 0x40 /* 100 : 32x */ 319 #define GAIN_64x 0x50 /* 101 : 64x */ 320 #define GAIN_128x 0x60 /* 110 : 128x */ 321 #define DROP_VSYNC 0x04 /* Drop VSYNC output of corrupt frame */ 322 #define DROP_HREF 0x02 /* Drop HREF output of corrupt frame */ 323 324 /* COM11 */ 325 #define SGLF_ON_OFF 0x02 /* Single frame ON/OFF selection */ 326 #define SGLF_TRIG 0x01 /* Single frame transfer trigger */ 327 328 /* HREF */ 329 #define HREF_VSTART_SHIFT 6 /* VSTART LSB */ 330 #define HREF_HSTART_SHIFT 4 /* HSTART 2 LSBs */ 331 #define HREF_VSIZE_SHIFT 2 /* VSIZE LSB */ 332 #define HREF_HSIZE_SHIFT 0 /* HSIZE 2 LSBs */ 333 334 /* EXHCH */ 335 #define EXHCH_VSIZE_SHIFT 2 /* VOUTSIZE LSB */ 336 #define EXHCH_HSIZE_SHIFT 0 /* HOUTSIZE 2 LSBs */ 337 338 /* DSP_CTRL1 */ 339 #define FIFO_ON 0x80 /* FIFO enable/disable selection */ 340 #define UV_ON_OFF 0x40 /* UV adjust function ON/OFF selection */ 341 #define YUV444_2_422 0x20 /* YUV444 to 422 UV channel option selection */ 342 #define CLR_MTRX_ON_OFF 0x10 /* Color matrix ON/OFF selection */ 343 #define INTPLT_ON_OFF 0x08 /* Interpolation ON/OFF selection */ 344 #define GMM_ON_OFF 0x04 /* Gamma function ON/OFF selection */ 345 #define AUTO_BLK_ON_OFF 0x02 /* Black defect auto correction ON/OFF */ 346 #define AUTO_WHT_ON_OFF 0x01 /* White define auto correction ON/OFF */ 347 348 /* DSP_CTRL3 */ 349 #define UV_MASK 0x80 /* UV output sequence option */ 350 #define UV_ON 0x80 /* ON */ 351 #define UV_OFF 0x00 /* OFF */ 352 #define CBAR_MASK 0x20 /* DSP Color bar mask */ 353 #define CBAR_ON 0x20 /* ON */ 354 #define CBAR_OFF 0x00 /* OFF */ 355 356 /* DSP_CTRL4 */ 357 #define DSP_OFMT_YUV 0x00 358 #define DSP_OFMT_RGB 0x00 359 #define DSP_OFMT_RAW8 0x02 360 #define DSP_OFMT_RAW10 0x03 361 362 /* DSPAUTO (DSP Auto Function ON/OFF Control) */ 363 #define AWB_ACTRL 0x80 /* AWB auto threshold control */ 364 #define DENOISE_ACTRL 0x40 /* De-noise auto threshold control */ 365 #define EDGE_ACTRL 0x20 /* Edge enhancement auto strength control */ 366 #define UV_ACTRL 0x10 /* UV adjust auto slope control */ 367 #define SCAL0_ACTRL 0x08 /* Auto scaling factor control */ 368 #define SCAL1_2_ACTRL 0x04 /* Auto scaling factor control */ 369 370 #define OV772X_MAX_WIDTH VGA_WIDTH 371 #define OV772X_MAX_HEIGHT VGA_HEIGHT 372 373 /* 374 * ID 375 */ 376 #define OV7720 0x7720 377 #define OV7725 0x7721 378 #define VERSION(pid, ver) ((pid << 8) | (ver & 0xFF)) 379 380 /* 381 * PLL multipliers 382 */ 383 static struct { 384 unsigned int mult; 385 u8 com4; 386 } ov772x_pll[] = { 387 { 1, PLL_BYPASS, }, 388 { 4, PLL_4x, }, 389 { 6, PLL_6x, }, 390 { 8, PLL_8x, }, 391 }; 392 393 /* 394 * struct 395 */ 396 397 struct ov772x_color_format { 398 u32 code; 399 enum v4l2_colorspace colorspace; 400 u8 dsp3; 401 u8 dsp4; 402 u8 com3; 403 u8 com7; 404 }; 405 406 struct ov772x_win_size { 407 char *name; 408 unsigned char com7_bit; 409 unsigned int sizeimage; 410 struct v4l2_rect rect; 411 }; 412 413 struct ov772x_priv { 414 struct v4l2_subdev subdev; 415 struct v4l2_ctrl_handler hdl; 416 struct clk *clk; 417 struct ov772x_camera_info *info; 418 struct gpio_desc *pwdn_gpio; 419 struct gpio_desc *rstb_gpio; 420 const struct ov772x_color_format *cfmt; 421 const struct ov772x_win_size *win; 422 unsigned short flag_vflip:1; 423 unsigned short flag_hflip:1; 424 /* band_filter = COM8[5] ? 256 - BDBASE : 0 */ 425 unsigned short band_filter; 426 unsigned int fps; 427 }; 428 429 /* 430 * supported color format list 431 */ 432 static const struct ov772x_color_format ov772x_cfmts[] = { 433 { 434 .code = MEDIA_BUS_FMT_YUYV8_2X8, 435 .colorspace = V4L2_COLORSPACE_SRGB, 436 .dsp3 = 0x0, 437 .dsp4 = DSP_OFMT_YUV, 438 .com3 = SWAP_YUV, 439 .com7 = OFMT_YUV, 440 }, 441 { 442 .code = MEDIA_BUS_FMT_YVYU8_2X8, 443 .colorspace = V4L2_COLORSPACE_SRGB, 444 .dsp3 = UV_ON, 445 .dsp4 = DSP_OFMT_YUV, 446 .com3 = SWAP_YUV, 447 .com7 = OFMT_YUV, 448 }, 449 { 450 .code = MEDIA_BUS_FMT_UYVY8_2X8, 451 .colorspace = V4L2_COLORSPACE_SRGB, 452 .dsp3 = 0x0, 453 .dsp4 = DSP_OFMT_YUV, 454 .com3 = 0x0, 455 .com7 = OFMT_YUV, 456 }, 457 { 458 .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE, 459 .colorspace = V4L2_COLORSPACE_SRGB, 460 .dsp3 = 0x0, 461 .dsp4 = DSP_OFMT_YUV, 462 .com3 = SWAP_RGB, 463 .com7 = FMT_RGB555 | OFMT_RGB, 464 }, 465 { 466 .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE, 467 .colorspace = V4L2_COLORSPACE_SRGB, 468 .dsp3 = 0x0, 469 .dsp4 = DSP_OFMT_YUV, 470 .com3 = 0x0, 471 .com7 = FMT_RGB555 | OFMT_RGB, 472 }, 473 { 474 .code = MEDIA_BUS_FMT_RGB565_2X8_LE, 475 .colorspace = V4L2_COLORSPACE_SRGB, 476 .dsp3 = 0x0, 477 .dsp4 = DSP_OFMT_YUV, 478 .com3 = SWAP_RGB, 479 .com7 = FMT_RGB565 | OFMT_RGB, 480 }, 481 { 482 .code = MEDIA_BUS_FMT_RGB565_2X8_BE, 483 .colorspace = V4L2_COLORSPACE_SRGB, 484 .dsp3 = 0x0, 485 .dsp4 = DSP_OFMT_YUV, 486 .com3 = 0x0, 487 .com7 = FMT_RGB565 | OFMT_RGB, 488 }, 489 { 490 /* Setting DSP4 to DSP_OFMT_RAW8 still gives 10-bit output, 491 * regardless of the COM7 value. We can thus only support 10-bit 492 * Bayer until someone figures it out. 493 */ 494 .code = MEDIA_BUS_FMT_SBGGR10_1X10, 495 .colorspace = V4L2_COLORSPACE_SRGB, 496 .dsp3 = 0x0, 497 .dsp4 = DSP_OFMT_RAW10, 498 .com3 = 0x0, 499 .com7 = SENSOR_RAW | OFMT_BRAW, 500 }, 501 }; 502 503 /* 504 * window size list 505 */ 506 507 static const struct ov772x_win_size ov772x_win_sizes[] = { 508 { 509 .name = "VGA", 510 .com7_bit = SLCT_VGA, 511 .sizeimage = 510 * 748, 512 .rect = { 513 .left = 140, 514 .top = 14, 515 .width = VGA_WIDTH, 516 .height = VGA_HEIGHT, 517 }, 518 }, { 519 .name = "QVGA", 520 .com7_bit = SLCT_QVGA, 521 .sizeimage = 278 * 576, 522 .rect = { 523 .left = 252, 524 .top = 6, 525 .width = QVGA_WIDTH, 526 .height = QVGA_HEIGHT, 527 }, 528 }, 529 }; 530 531 /* 532 * frame rate settings lists 533 */ 534 static const unsigned int ov772x_frame_intervals[] = { 5, 10, 15, 20, 30, 60 }; 535 536 /* 537 * general function 538 */ 539 540 static struct ov772x_priv *to_ov772x(struct v4l2_subdev *sd) 541 { 542 return container_of(sd, struct ov772x_priv, subdev); 543 } 544 545 static inline int ov772x_read(struct i2c_client *client, u8 addr) 546 { 547 return i2c_smbus_read_byte_data(client, addr); 548 } 549 550 static inline int ov772x_write(struct i2c_client *client, u8 addr, u8 value) 551 { 552 return i2c_smbus_write_byte_data(client, addr, value); 553 } 554 555 static int ov772x_mask_set(struct i2c_client *client, u8 command, u8 mask, 556 u8 set) 557 { 558 s32 val = ov772x_read(client, command); 559 560 if (val < 0) 561 return val; 562 563 val &= ~mask; 564 val |= set & mask; 565 566 return ov772x_write(client, command, val); 567 } 568 569 static int ov772x_reset(struct i2c_client *client) 570 { 571 int ret; 572 573 ret = ov772x_write(client, COM7, SCCB_RESET); 574 if (ret < 0) 575 return ret; 576 577 usleep_range(1000, 5000); 578 579 return ov772x_mask_set(client, COM2, SOFT_SLEEP_MODE, SOFT_SLEEP_MODE); 580 } 581 582 /* 583 * subdev ops 584 */ 585 586 static int ov772x_s_stream(struct v4l2_subdev *sd, int enable) 587 { 588 struct i2c_client *client = v4l2_get_subdevdata(sd); 589 struct ov772x_priv *priv = to_ov772x(sd); 590 591 if (!enable) { 592 ov772x_mask_set(client, COM2, SOFT_SLEEP_MODE, SOFT_SLEEP_MODE); 593 return 0; 594 } 595 596 ov772x_mask_set(client, COM2, SOFT_SLEEP_MODE, 0); 597 598 dev_dbg(&client->dev, "format %d, win %s\n", 599 priv->cfmt->code, priv->win->name); 600 601 return 0; 602 } 603 604 static int ov772x_set_frame_rate(struct ov772x_priv *priv, 605 struct v4l2_fract *tpf, 606 const struct ov772x_color_format *cfmt, 607 const struct ov772x_win_size *win) 608 { 609 struct i2c_client *client = v4l2_get_subdevdata(&priv->subdev); 610 unsigned long fin = clk_get_rate(priv->clk); 611 unsigned int fps = tpf->numerator ? 612 tpf->denominator / tpf->numerator : 613 tpf->denominator; 614 unsigned int best_diff; 615 unsigned int fsize; 616 unsigned int pclk; 617 unsigned int diff; 618 unsigned int idx; 619 unsigned int i; 620 u8 clkrc = 0; 621 u8 com4 = 0; 622 int ret; 623 624 /* Approximate to the closest supported frame interval. */ 625 best_diff = ~0L; 626 for (i = 0, idx = 0; i < ARRAY_SIZE(ov772x_frame_intervals); i++) { 627 diff = abs(fps - ov772x_frame_intervals[i]); 628 if (diff < best_diff) { 629 idx = i; 630 best_diff = diff; 631 } 632 } 633 fps = ov772x_frame_intervals[idx]; 634 635 /* Use image size (with blankings) to calculate desired pixel clock. */ 636 switch (cfmt->com7 & OFMT_MASK) { 637 case OFMT_BRAW: 638 fsize = win->sizeimage; 639 break; 640 case OFMT_RGB: 641 case OFMT_YUV: 642 default: 643 fsize = win->sizeimage * 2; 644 break; 645 } 646 647 pclk = fps * fsize; 648 649 /* 650 * Pixel clock generation circuit is pretty simple: 651 * 652 * Fin -> [ / CLKRC_div] -> [ * PLL_mult] -> pclk 653 * 654 * Try to approximate the desired pixel clock testing all available 655 * PLL multipliers (1x, 4x, 6x, 8x) and calculate corresponding 656 * divisor with: 657 * 658 * div = PLL_mult * Fin / pclk 659 * 660 * and re-calculate the pixel clock using it: 661 * 662 * pclk = Fin * PLL_mult / CLKRC_div 663 * 664 * Choose the PLL_mult and CLKRC_div pair that gives a pixel clock 665 * closer to the desired one. 666 * 667 * The desired pixel clock is calculated using a known frame size 668 * (blanking included) and FPS. 669 */ 670 best_diff = ~0L; 671 for (i = 0; i < ARRAY_SIZE(ov772x_pll); i++) { 672 unsigned int pll_mult = ov772x_pll[i].mult; 673 unsigned int pll_out = pll_mult * fin; 674 unsigned int t_pclk; 675 unsigned int div; 676 677 if (pll_out < pclk) 678 continue; 679 680 div = DIV_ROUND_CLOSEST(pll_out, pclk); 681 t_pclk = DIV_ROUND_CLOSEST(fin * pll_mult, div); 682 diff = abs(pclk - t_pclk); 683 if (diff < best_diff) { 684 best_diff = diff; 685 clkrc = CLKRC_DIV(div); 686 com4 = ov772x_pll[i].com4; 687 } 688 } 689 690 ret = ov772x_write(client, COM4, com4 | COM4_RESERVED); 691 if (ret < 0) 692 return ret; 693 694 ret = ov772x_write(client, CLKRC, clkrc | CLKRC_RESERVED); 695 if (ret < 0) 696 return ret; 697 698 tpf->numerator = 1; 699 tpf->denominator = fps; 700 priv->fps = tpf->denominator; 701 702 return 0; 703 } 704 705 static int ov772x_g_frame_interval(struct v4l2_subdev *sd, 706 struct v4l2_subdev_frame_interval *ival) 707 { 708 struct ov772x_priv *priv = to_ov772x(sd); 709 struct v4l2_fract *tpf = &ival->interval; 710 711 tpf->numerator = 1; 712 tpf->denominator = priv->fps; 713 714 return 0; 715 } 716 717 static int ov772x_s_frame_interval(struct v4l2_subdev *sd, 718 struct v4l2_subdev_frame_interval *ival) 719 { 720 struct ov772x_priv *priv = to_ov772x(sd); 721 struct v4l2_fract *tpf = &ival->interval; 722 723 return ov772x_set_frame_rate(priv, tpf, priv->cfmt, priv->win); 724 } 725 726 static int ov772x_s_ctrl(struct v4l2_ctrl *ctrl) 727 { 728 struct ov772x_priv *priv = container_of(ctrl->handler, 729 struct ov772x_priv, hdl); 730 struct v4l2_subdev *sd = &priv->subdev; 731 struct i2c_client *client = v4l2_get_subdevdata(sd); 732 int ret = 0; 733 u8 val; 734 735 switch (ctrl->id) { 736 case V4L2_CID_VFLIP: 737 val = ctrl->val ? VFLIP_IMG : 0x00; 738 priv->flag_vflip = ctrl->val; 739 if (priv->info->flags & OV772X_FLAG_VFLIP) 740 val ^= VFLIP_IMG; 741 return ov772x_mask_set(client, COM3, VFLIP_IMG, val); 742 case V4L2_CID_HFLIP: 743 val = ctrl->val ? HFLIP_IMG : 0x00; 744 priv->flag_hflip = ctrl->val; 745 if (priv->info->flags & OV772X_FLAG_HFLIP) 746 val ^= HFLIP_IMG; 747 return ov772x_mask_set(client, COM3, HFLIP_IMG, val); 748 case V4L2_CID_BAND_STOP_FILTER: 749 if (!ctrl->val) { 750 /* Switch the filter off, it is on now */ 751 ret = ov772x_mask_set(client, BDBASE, 0xff, 0xff); 752 if (!ret) 753 ret = ov772x_mask_set(client, COM8, 754 BNDF_ON_OFF, 0); 755 } else { 756 /* Switch the filter on, set AEC low limit */ 757 val = 256 - ctrl->val; 758 ret = ov772x_mask_set(client, COM8, 759 BNDF_ON_OFF, BNDF_ON_OFF); 760 if (!ret) 761 ret = ov772x_mask_set(client, BDBASE, 762 0xff, val); 763 } 764 if (!ret) 765 priv->band_filter = ctrl->val; 766 return ret; 767 } 768 769 return -EINVAL; 770 } 771 772 #ifdef CONFIG_VIDEO_ADV_DEBUG 773 static int ov772x_g_register(struct v4l2_subdev *sd, 774 struct v4l2_dbg_register *reg) 775 { 776 struct i2c_client *client = v4l2_get_subdevdata(sd); 777 int ret; 778 779 reg->size = 1; 780 if (reg->reg > 0xff) 781 return -EINVAL; 782 783 ret = ov772x_read(client, reg->reg); 784 if (ret < 0) 785 return ret; 786 787 reg->val = (__u64)ret; 788 789 return 0; 790 } 791 792 static int ov772x_s_register(struct v4l2_subdev *sd, 793 const struct v4l2_dbg_register *reg) 794 { 795 struct i2c_client *client = v4l2_get_subdevdata(sd); 796 797 if (reg->reg > 0xff || 798 reg->val > 0xff) 799 return -EINVAL; 800 801 return ov772x_write(client, reg->reg, reg->val); 802 } 803 #endif 804 805 static int ov772x_power_on(struct ov772x_priv *priv) 806 { 807 struct i2c_client *client = v4l2_get_subdevdata(&priv->subdev); 808 int ret; 809 810 if (priv->clk) { 811 ret = clk_prepare_enable(priv->clk); 812 if (ret) 813 return ret; 814 } 815 816 if (priv->pwdn_gpio) { 817 gpiod_set_value(priv->pwdn_gpio, 1); 818 usleep_range(500, 1000); 819 } 820 821 /* 822 * FIXME: The reset signal is connected to a shared GPIO on some 823 * platforms (namely the SuperH Migo-R). Until a framework becomes 824 * available to handle this cleanly, request the GPIO temporarily 825 * to avoid conflicts. 826 */ 827 priv->rstb_gpio = gpiod_get_optional(&client->dev, "rstb", 828 GPIOD_OUT_LOW); 829 if (IS_ERR(priv->rstb_gpio)) { 830 dev_info(&client->dev, "Unable to get GPIO \"rstb\""); 831 return PTR_ERR(priv->rstb_gpio); 832 } 833 834 if (priv->rstb_gpio) { 835 gpiod_set_value(priv->rstb_gpio, 1); 836 usleep_range(500, 1000); 837 gpiod_set_value(priv->rstb_gpio, 0); 838 usleep_range(500, 1000); 839 840 gpiod_put(priv->rstb_gpio); 841 } 842 843 return 0; 844 } 845 846 static int ov772x_power_off(struct ov772x_priv *priv) 847 { 848 clk_disable_unprepare(priv->clk); 849 850 if (priv->pwdn_gpio) { 851 gpiod_set_value(priv->pwdn_gpio, 0); 852 usleep_range(500, 1000); 853 } 854 855 return 0; 856 } 857 858 static int ov772x_s_power(struct v4l2_subdev *sd, int on) 859 { 860 struct ov772x_priv *priv = to_ov772x(sd); 861 862 return on ? ov772x_power_on(priv) : 863 ov772x_power_off(priv); 864 } 865 866 static const struct ov772x_win_size *ov772x_select_win(u32 width, u32 height) 867 { 868 const struct ov772x_win_size *win = &ov772x_win_sizes[0]; 869 u32 best_diff = UINT_MAX; 870 unsigned int i; 871 872 for (i = 0; i < ARRAY_SIZE(ov772x_win_sizes); ++i) { 873 u32 diff = abs(width - ov772x_win_sizes[i].rect.width) 874 + abs(height - ov772x_win_sizes[i].rect.height); 875 if (diff < best_diff) { 876 best_diff = diff; 877 win = &ov772x_win_sizes[i]; 878 } 879 } 880 881 return win; 882 } 883 884 static void ov772x_select_params(const struct v4l2_mbus_framefmt *mf, 885 const struct ov772x_color_format **cfmt, 886 const struct ov772x_win_size **win) 887 { 888 unsigned int i; 889 890 /* Select a format. */ 891 *cfmt = &ov772x_cfmts[0]; 892 893 for (i = 0; i < ARRAY_SIZE(ov772x_cfmts); i++) { 894 if (mf->code == ov772x_cfmts[i].code) { 895 *cfmt = &ov772x_cfmts[i]; 896 break; 897 } 898 } 899 900 /* Select a window size. */ 901 *win = ov772x_select_win(mf->width, mf->height); 902 } 903 904 static int ov772x_set_params(struct ov772x_priv *priv, 905 const struct ov772x_color_format *cfmt, 906 const struct ov772x_win_size *win) 907 { 908 struct i2c_client *client = v4l2_get_subdevdata(&priv->subdev); 909 struct v4l2_fract tpf; 910 int ret; 911 u8 val; 912 913 /* Reset hardware. */ 914 ov772x_reset(client); 915 916 /* Edge Ctrl. */ 917 if (priv->info->edgectrl.strength & OV772X_MANUAL_EDGE_CTRL) { 918 /* 919 * Manual Edge Control Mode. 920 * 921 * Edge auto strength bit is set by default. 922 * Remove it when manual mode. 923 */ 924 925 ret = ov772x_mask_set(client, DSPAUTO, EDGE_ACTRL, 0x00); 926 if (ret < 0) 927 goto ov772x_set_fmt_error; 928 929 ret = ov772x_mask_set(client, 930 EDGE_TRSHLD, OV772X_EDGE_THRESHOLD_MASK, 931 priv->info->edgectrl.threshold); 932 if (ret < 0) 933 goto ov772x_set_fmt_error; 934 935 ret = ov772x_mask_set(client, 936 EDGE_STRNGT, OV772X_EDGE_STRENGTH_MASK, 937 priv->info->edgectrl.strength); 938 if (ret < 0) 939 goto ov772x_set_fmt_error; 940 941 } else if (priv->info->edgectrl.upper > priv->info->edgectrl.lower) { 942 /* 943 * Auto Edge Control Mode. 944 * 945 * Set upper and lower limit. 946 */ 947 ret = ov772x_mask_set(client, 948 EDGE_UPPER, OV772X_EDGE_UPPER_MASK, 949 priv->info->edgectrl.upper); 950 if (ret < 0) 951 goto ov772x_set_fmt_error; 952 953 ret = ov772x_mask_set(client, 954 EDGE_LOWER, OV772X_EDGE_LOWER_MASK, 955 priv->info->edgectrl.lower); 956 if (ret < 0) 957 goto ov772x_set_fmt_error; 958 } 959 960 /* Format and window size. */ 961 ret = ov772x_write(client, HSTART, win->rect.left >> 2); 962 if (ret < 0) 963 goto ov772x_set_fmt_error; 964 ret = ov772x_write(client, HSIZE, win->rect.width >> 2); 965 if (ret < 0) 966 goto ov772x_set_fmt_error; 967 ret = ov772x_write(client, VSTART, win->rect.top >> 1); 968 if (ret < 0) 969 goto ov772x_set_fmt_error; 970 ret = ov772x_write(client, VSIZE, win->rect.height >> 1); 971 if (ret < 0) 972 goto ov772x_set_fmt_error; 973 ret = ov772x_write(client, HOUTSIZE, win->rect.width >> 2); 974 if (ret < 0) 975 goto ov772x_set_fmt_error; 976 ret = ov772x_write(client, VOUTSIZE, win->rect.height >> 1); 977 if (ret < 0) 978 goto ov772x_set_fmt_error; 979 ret = ov772x_write(client, HREF, 980 ((win->rect.top & 1) << HREF_VSTART_SHIFT) | 981 ((win->rect.left & 3) << HREF_HSTART_SHIFT) | 982 ((win->rect.height & 1) << HREF_VSIZE_SHIFT) | 983 ((win->rect.width & 3) << HREF_HSIZE_SHIFT)); 984 if (ret < 0) 985 goto ov772x_set_fmt_error; 986 ret = ov772x_write(client, EXHCH, 987 ((win->rect.height & 1) << EXHCH_VSIZE_SHIFT) | 988 ((win->rect.width & 3) << EXHCH_HSIZE_SHIFT)); 989 if (ret < 0) 990 goto ov772x_set_fmt_error; 991 992 /* Set DSP_CTRL3. */ 993 val = cfmt->dsp3; 994 if (val) { 995 ret = ov772x_mask_set(client, 996 DSP_CTRL3, UV_MASK, val); 997 if (ret < 0) 998 goto ov772x_set_fmt_error; 999 } 1000 1001 /* DSP_CTRL4: AEC reference point and DSP output format. */ 1002 if (cfmt->dsp4) { 1003 ret = ov772x_write(client, DSP_CTRL4, cfmt->dsp4); 1004 if (ret < 0) 1005 goto ov772x_set_fmt_error; 1006 } 1007 1008 /* Set COM3. */ 1009 val = cfmt->com3; 1010 if (priv->info->flags & OV772X_FLAG_VFLIP) 1011 val |= VFLIP_IMG; 1012 if (priv->info->flags & OV772X_FLAG_HFLIP) 1013 val |= HFLIP_IMG; 1014 if (priv->flag_vflip) 1015 val ^= VFLIP_IMG; 1016 if (priv->flag_hflip) 1017 val ^= HFLIP_IMG; 1018 1019 ret = ov772x_mask_set(client, 1020 COM3, SWAP_MASK | IMG_MASK, val); 1021 if (ret < 0) 1022 goto ov772x_set_fmt_error; 1023 1024 /* COM7: Sensor resolution and output format control. */ 1025 ret = ov772x_write(client, COM7, win->com7_bit | cfmt->com7); 1026 if (ret < 0) 1027 goto ov772x_set_fmt_error; 1028 1029 /* COM4, CLKRC: Set pixel clock and framerate. */ 1030 tpf.numerator = 1; 1031 tpf.denominator = priv->fps; 1032 ret = ov772x_set_frame_rate(priv, &tpf, cfmt, win); 1033 if (ret < 0) 1034 goto ov772x_set_fmt_error; 1035 1036 /* Set COM8. */ 1037 if (priv->band_filter) { 1038 ret = ov772x_mask_set(client, COM8, BNDF_ON_OFF, 1); 1039 if (!ret) 1040 ret = ov772x_mask_set(client, BDBASE, 1041 0xff, 256 - priv->band_filter); 1042 if (ret < 0) 1043 goto ov772x_set_fmt_error; 1044 } 1045 1046 return ret; 1047 1048 ov772x_set_fmt_error: 1049 1050 ov772x_reset(client); 1051 1052 return ret; 1053 } 1054 1055 static int ov772x_get_selection(struct v4l2_subdev *sd, 1056 struct v4l2_subdev_pad_config *cfg, 1057 struct v4l2_subdev_selection *sel) 1058 { 1059 struct ov772x_priv *priv = to_ov772x(sd); 1060 1061 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE) 1062 return -EINVAL; 1063 1064 sel->r.left = 0; 1065 sel->r.top = 0; 1066 switch (sel->target) { 1067 case V4L2_SEL_TGT_CROP_BOUNDS: 1068 case V4L2_SEL_TGT_CROP_DEFAULT: 1069 case V4L2_SEL_TGT_CROP: 1070 sel->r.width = priv->win->rect.width; 1071 sel->r.height = priv->win->rect.height; 1072 return 0; 1073 default: 1074 return -EINVAL; 1075 } 1076 } 1077 1078 static int ov772x_get_fmt(struct v4l2_subdev *sd, 1079 struct v4l2_subdev_pad_config *cfg, 1080 struct v4l2_subdev_format *format) 1081 { 1082 struct v4l2_mbus_framefmt *mf = &format->format; 1083 struct ov772x_priv *priv = to_ov772x(sd); 1084 1085 if (format->pad) 1086 return -EINVAL; 1087 1088 mf->width = priv->win->rect.width; 1089 mf->height = priv->win->rect.height; 1090 mf->code = priv->cfmt->code; 1091 mf->colorspace = priv->cfmt->colorspace; 1092 mf->field = V4L2_FIELD_NONE; 1093 1094 return 0; 1095 } 1096 1097 static int ov772x_set_fmt(struct v4l2_subdev *sd, 1098 struct v4l2_subdev_pad_config *cfg, 1099 struct v4l2_subdev_format *format) 1100 { 1101 struct ov772x_priv *priv = to_ov772x(sd); 1102 struct v4l2_mbus_framefmt *mf = &format->format; 1103 const struct ov772x_color_format *cfmt; 1104 const struct ov772x_win_size *win; 1105 int ret; 1106 1107 if (format->pad) 1108 return -EINVAL; 1109 1110 ov772x_select_params(mf, &cfmt, &win); 1111 1112 mf->code = cfmt->code; 1113 mf->width = win->rect.width; 1114 mf->height = win->rect.height; 1115 mf->field = V4L2_FIELD_NONE; 1116 mf->colorspace = cfmt->colorspace; 1117 mf->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 1118 mf->quantization = V4L2_QUANTIZATION_DEFAULT; 1119 mf->xfer_func = V4L2_XFER_FUNC_DEFAULT; 1120 1121 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 1122 cfg->try_fmt = *mf; 1123 return 0; 1124 } 1125 1126 ret = ov772x_set_params(priv, cfmt, win); 1127 if (ret < 0) 1128 return ret; 1129 1130 priv->win = win; 1131 priv->cfmt = cfmt; 1132 1133 return 0; 1134 } 1135 1136 static int ov772x_video_probe(struct ov772x_priv *priv) 1137 { 1138 struct i2c_client *client = v4l2_get_subdevdata(&priv->subdev); 1139 u8 pid, ver; 1140 const char *devname; 1141 int ret; 1142 1143 ret = ov772x_s_power(&priv->subdev, 1); 1144 if (ret < 0) 1145 return ret; 1146 1147 /* Check and show product ID and manufacturer ID. */ 1148 pid = ov772x_read(client, PID); 1149 ver = ov772x_read(client, VER); 1150 1151 switch (VERSION(pid, ver)) { 1152 case OV7720: 1153 devname = "ov7720"; 1154 break; 1155 case OV7725: 1156 devname = "ov7725"; 1157 break; 1158 default: 1159 dev_err(&client->dev, 1160 "Product ID error %x:%x\n", pid, ver); 1161 ret = -ENODEV; 1162 goto done; 1163 } 1164 1165 dev_info(&client->dev, 1166 "%s Product ID %0x:%0x Manufacturer ID %x:%x\n", 1167 devname, 1168 pid, 1169 ver, 1170 ov772x_read(client, MIDH), 1171 ov772x_read(client, MIDL)); 1172 ret = v4l2_ctrl_handler_setup(&priv->hdl); 1173 1174 done: 1175 ov772x_s_power(&priv->subdev, 0); 1176 1177 return ret; 1178 } 1179 1180 static const struct v4l2_ctrl_ops ov772x_ctrl_ops = { 1181 .s_ctrl = ov772x_s_ctrl, 1182 }; 1183 1184 static const struct v4l2_subdev_core_ops ov772x_subdev_core_ops = { 1185 #ifdef CONFIG_VIDEO_ADV_DEBUG 1186 .g_register = ov772x_g_register, 1187 .s_register = ov772x_s_register, 1188 #endif 1189 .s_power = ov772x_s_power, 1190 }; 1191 1192 static int ov772x_enum_frame_interval(struct v4l2_subdev *sd, 1193 struct v4l2_subdev_pad_config *cfg, 1194 struct v4l2_subdev_frame_interval_enum *fie) 1195 { 1196 if (fie->pad || fie->index >= ARRAY_SIZE(ov772x_frame_intervals)) 1197 return -EINVAL; 1198 1199 if (fie->width != VGA_WIDTH && fie->width != QVGA_WIDTH) 1200 return -EINVAL; 1201 if (fie->height != VGA_HEIGHT && fie->height != QVGA_HEIGHT) 1202 return -EINVAL; 1203 1204 fie->interval.numerator = 1; 1205 fie->interval.denominator = ov772x_frame_intervals[fie->index]; 1206 1207 return 0; 1208 } 1209 1210 static int ov772x_enum_mbus_code(struct v4l2_subdev *sd, 1211 struct v4l2_subdev_pad_config *cfg, 1212 struct v4l2_subdev_mbus_code_enum *code) 1213 { 1214 if (code->pad || code->index >= ARRAY_SIZE(ov772x_cfmts)) 1215 return -EINVAL; 1216 1217 code->code = ov772x_cfmts[code->index].code; 1218 1219 return 0; 1220 } 1221 1222 static const struct v4l2_subdev_video_ops ov772x_subdev_video_ops = { 1223 .s_stream = ov772x_s_stream, 1224 .s_frame_interval = ov772x_s_frame_interval, 1225 .g_frame_interval = ov772x_g_frame_interval, 1226 }; 1227 1228 static const struct v4l2_subdev_pad_ops ov772x_subdev_pad_ops = { 1229 .enum_frame_interval = ov772x_enum_frame_interval, 1230 .enum_mbus_code = ov772x_enum_mbus_code, 1231 .get_selection = ov772x_get_selection, 1232 .get_fmt = ov772x_get_fmt, 1233 .set_fmt = ov772x_set_fmt, 1234 }; 1235 1236 static const struct v4l2_subdev_ops ov772x_subdev_ops = { 1237 .core = &ov772x_subdev_core_ops, 1238 .video = &ov772x_subdev_video_ops, 1239 .pad = &ov772x_subdev_pad_ops, 1240 }; 1241 1242 /* 1243 * i2c_driver function 1244 */ 1245 1246 static int ov772x_probe(struct i2c_client *client, 1247 const struct i2c_device_id *did) 1248 { 1249 struct ov772x_priv *priv; 1250 struct i2c_adapter *adapter = client->adapter; 1251 int ret; 1252 1253 if (!client->dev.platform_data) { 1254 dev_err(&client->dev, "Missing ov772x platform data\n"); 1255 return -EINVAL; 1256 } 1257 1258 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA | 1259 I2C_FUNC_PROTOCOL_MANGLING)) { 1260 dev_err(&adapter->dev, 1261 "I2C-Adapter doesn't support SMBUS_BYTE_DATA or PROTOCOL_MANGLING\n"); 1262 return -EIO; 1263 } 1264 client->flags |= I2C_CLIENT_SCCB; 1265 1266 priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL); 1267 if (!priv) 1268 return -ENOMEM; 1269 1270 priv->info = client->dev.platform_data; 1271 1272 v4l2_i2c_subdev_init(&priv->subdev, client, &ov772x_subdev_ops); 1273 v4l2_ctrl_handler_init(&priv->hdl, 3); 1274 v4l2_ctrl_new_std(&priv->hdl, &ov772x_ctrl_ops, 1275 V4L2_CID_VFLIP, 0, 1, 1, 0); 1276 v4l2_ctrl_new_std(&priv->hdl, &ov772x_ctrl_ops, 1277 V4L2_CID_HFLIP, 0, 1, 1, 0); 1278 v4l2_ctrl_new_std(&priv->hdl, &ov772x_ctrl_ops, 1279 V4L2_CID_BAND_STOP_FILTER, 0, 256, 1, 0); 1280 priv->subdev.ctrl_handler = &priv->hdl; 1281 if (priv->hdl.error) 1282 return priv->hdl.error; 1283 1284 priv->clk = clk_get(&client->dev, "xclk"); 1285 if (IS_ERR(priv->clk)) { 1286 dev_err(&client->dev, "Unable to get xclk clock\n"); 1287 ret = PTR_ERR(priv->clk); 1288 goto error_ctrl_free; 1289 } 1290 1291 priv->pwdn_gpio = gpiod_get_optional(&client->dev, "pwdn", 1292 GPIOD_OUT_LOW); 1293 if (IS_ERR(priv->pwdn_gpio)) { 1294 dev_info(&client->dev, "Unable to get GPIO \"pwdn\""); 1295 ret = PTR_ERR(priv->pwdn_gpio); 1296 goto error_clk_put; 1297 } 1298 1299 ret = ov772x_video_probe(priv); 1300 if (ret < 0) 1301 goto error_gpio_put; 1302 1303 priv->cfmt = &ov772x_cfmts[0]; 1304 priv->win = &ov772x_win_sizes[0]; 1305 priv->fps = 15; 1306 1307 ret = v4l2_async_register_subdev(&priv->subdev); 1308 if (ret) 1309 goto error_gpio_put; 1310 1311 return 0; 1312 1313 error_gpio_put: 1314 if (priv->pwdn_gpio) 1315 gpiod_put(priv->pwdn_gpio); 1316 error_clk_put: 1317 clk_put(priv->clk); 1318 error_ctrl_free: 1319 v4l2_ctrl_handler_free(&priv->hdl); 1320 1321 return ret; 1322 } 1323 1324 static int ov772x_remove(struct i2c_client *client) 1325 { 1326 struct ov772x_priv *priv = to_ov772x(i2c_get_clientdata(client)); 1327 1328 clk_put(priv->clk); 1329 if (priv->pwdn_gpio) 1330 gpiod_put(priv->pwdn_gpio); 1331 v4l2_async_unregister_subdev(&priv->subdev); 1332 v4l2_ctrl_handler_free(&priv->hdl); 1333 1334 return 0; 1335 } 1336 1337 static const struct i2c_device_id ov772x_id[] = { 1338 { "ov772x", 0 }, 1339 { } 1340 }; 1341 MODULE_DEVICE_TABLE(i2c, ov772x_id); 1342 1343 static struct i2c_driver ov772x_i2c_driver = { 1344 .driver = { 1345 .name = "ov772x", 1346 }, 1347 .probe = ov772x_probe, 1348 .remove = ov772x_remove, 1349 .id_table = ov772x_id, 1350 }; 1351 1352 module_i2c_driver(ov772x_i2c_driver); 1353 1354 MODULE_DESCRIPTION("V4L2 driver for OV772x image sensor"); 1355 MODULE_AUTHOR("Kuninori Morimoto"); 1356 MODULE_LICENSE("GPL v2"); 1357