1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ov772x Camera Driver 4 * 5 * Copyright (C) 2017 Jacopo Mondi <jacopo+renesas@jmondi.org> 6 * 7 * Copyright (C) 2008 Renesas Solutions Corp. 8 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 9 * 10 * Based on ov7670 and soc_camera_platform driver, 11 * 12 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net> 13 * Copyright (C) 2008 Magnus Damm 14 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> 15 */ 16 17 #include <linux/clk.h> 18 #include <linux/delay.h> 19 #include <linux/gpio/consumer.h> 20 #include <linux/i2c.h> 21 #include <linux/init.h> 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/regmap.h> 25 #include <linux/slab.h> 26 #include <linux/v4l2-mediabus.h> 27 #include <linux/videodev2.h> 28 29 #include <media/i2c/ov772x.h> 30 31 #include <media/v4l2-ctrls.h> 32 #include <media/v4l2-device.h> 33 #include <media/v4l2-event.h> 34 #include <media/v4l2-fwnode.h> 35 #include <media/v4l2-image-sizes.h> 36 #include <media/v4l2-subdev.h> 37 38 /* 39 * register offset 40 */ 41 #define GAIN 0x00 /* AGC - Gain control gain setting */ 42 #define BLUE 0x01 /* AWB - Blue channel gain setting */ 43 #define RED 0x02 /* AWB - Red channel gain setting */ 44 #define GREEN 0x03 /* AWB - Green channel gain setting */ 45 #define COM1 0x04 /* Common control 1 */ 46 #define BAVG 0x05 /* U/B Average Level */ 47 #define GAVG 0x06 /* Y/Gb Average Level */ 48 #define RAVG 0x07 /* V/R Average Level */ 49 #define AECH 0x08 /* Exposure Value - AEC MSBs */ 50 #define COM2 0x09 /* Common control 2 */ 51 #define PID 0x0A /* Product ID Number MSB */ 52 #define VER 0x0B /* Product ID Number LSB */ 53 #define COM3 0x0C /* Common control 3 */ 54 #define COM4 0x0D /* Common control 4 */ 55 #define COM5 0x0E /* Common control 5 */ 56 #define COM6 0x0F /* Common control 6 */ 57 #define AEC 0x10 /* Exposure Value */ 58 #define CLKRC 0x11 /* Internal clock */ 59 #define COM7 0x12 /* Common control 7 */ 60 #define COM8 0x13 /* Common control 8 */ 61 #define COM9 0x14 /* Common control 9 */ 62 #define COM10 0x15 /* Common control 10 */ 63 #define REG16 0x16 /* Register 16 */ 64 #define HSTART 0x17 /* Horizontal sensor size */ 65 #define HSIZE 0x18 /* Horizontal frame (HREF column) end high 8-bit */ 66 #define VSTART 0x19 /* Vertical frame (row) start high 8-bit */ 67 #define VSIZE 0x1A /* Vertical sensor size */ 68 #define PSHFT 0x1B /* Data format - pixel delay select */ 69 #define MIDH 0x1C /* Manufacturer ID byte - high */ 70 #define MIDL 0x1D /* Manufacturer ID byte - low */ 71 #define LAEC 0x1F /* Fine AEC value */ 72 #define COM11 0x20 /* Common control 11 */ 73 #define BDBASE 0x22 /* Banding filter Minimum AEC value */ 74 #define DBSTEP 0x23 /* Banding filter Maximum Setp */ 75 #define AEW 0x24 /* AGC/AEC - Stable operating region (upper limit) */ 76 #define AEB 0x25 /* AGC/AEC - Stable operating region (lower limit) */ 77 #define VPT 0x26 /* AGC/AEC Fast mode operating region */ 78 #define REG28 0x28 /* Register 28 */ 79 #define HOUTSIZE 0x29 /* Horizontal data output size MSBs */ 80 #define EXHCH 0x2A /* Dummy pixel insert MSB */ 81 #define EXHCL 0x2B /* Dummy pixel insert LSB */ 82 #define VOUTSIZE 0x2C /* Vertical data output size MSBs */ 83 #define ADVFL 0x2D /* LSB of insert dummy lines in Vertical direction */ 84 #define ADVFH 0x2E /* MSG of insert dummy lines in Vertical direction */ 85 #define YAVE 0x2F /* Y/G Channel Average value */ 86 #define LUMHTH 0x30 /* Histogram AEC/AGC Luminance high level threshold */ 87 #define LUMLTH 0x31 /* Histogram AEC/AGC Luminance low level threshold */ 88 #define HREF 0x32 /* Image start and size control */ 89 #define DM_LNL 0x33 /* Dummy line low 8 bits */ 90 #define DM_LNH 0x34 /* Dummy line high 8 bits */ 91 #define ADOFF_B 0x35 /* AD offset compensation value for B channel */ 92 #define ADOFF_R 0x36 /* AD offset compensation value for R channel */ 93 #define ADOFF_GB 0x37 /* AD offset compensation value for Gb channel */ 94 #define ADOFF_GR 0x38 /* AD offset compensation value for Gr channel */ 95 #define OFF_B 0x39 /* Analog process B channel offset value */ 96 #define OFF_R 0x3A /* Analog process R channel offset value */ 97 #define OFF_GB 0x3B /* Analog process Gb channel offset value */ 98 #define OFF_GR 0x3C /* Analog process Gr channel offset value */ 99 #define COM12 0x3D /* Common control 12 */ 100 #define COM13 0x3E /* Common control 13 */ 101 #define COM14 0x3F /* Common control 14 */ 102 #define COM15 0x40 /* Common control 15*/ 103 #define COM16 0x41 /* Common control 16 */ 104 #define TGT_B 0x42 /* BLC blue channel target value */ 105 #define TGT_R 0x43 /* BLC red channel target value */ 106 #define TGT_GB 0x44 /* BLC Gb channel target value */ 107 #define TGT_GR 0x45 /* BLC Gr channel target value */ 108 /* for ov7720 */ 109 #define LCC0 0x46 /* Lens correction control 0 */ 110 #define LCC1 0x47 /* Lens correction option 1 - X coordinate */ 111 #define LCC2 0x48 /* Lens correction option 2 - Y coordinate */ 112 #define LCC3 0x49 /* Lens correction option 3 */ 113 #define LCC4 0x4A /* Lens correction option 4 - radius of the circular */ 114 #define LCC5 0x4B /* Lens correction option 5 */ 115 #define LCC6 0x4C /* Lens correction option 6 */ 116 /* for ov7725 */ 117 #define LC_CTR 0x46 /* Lens correction control */ 118 #define LC_XC 0x47 /* X coordinate of lens correction center relative */ 119 #define LC_YC 0x48 /* Y coordinate of lens correction center relative */ 120 #define LC_COEF 0x49 /* Lens correction coefficient */ 121 #define LC_RADI 0x4A /* Lens correction radius */ 122 #define LC_COEFB 0x4B /* Lens B channel compensation coefficient */ 123 #define LC_COEFR 0x4C /* Lens R channel compensation coefficient */ 124 125 #define FIXGAIN 0x4D /* Analog fix gain amplifer */ 126 #define AREF0 0x4E /* Sensor reference control */ 127 #define AREF1 0x4F /* Sensor reference current control */ 128 #define AREF2 0x50 /* Analog reference control */ 129 #define AREF3 0x51 /* ADC reference control */ 130 #define AREF4 0x52 /* ADC reference control */ 131 #define AREF5 0x53 /* ADC reference control */ 132 #define AREF6 0x54 /* Analog reference control */ 133 #define AREF7 0x55 /* Analog reference control */ 134 #define UFIX 0x60 /* U channel fixed value output */ 135 #define VFIX 0x61 /* V channel fixed value output */ 136 #define AWBB_BLK 0x62 /* AWB option for advanced AWB */ 137 #define AWB_CTRL0 0x63 /* AWB control byte 0 */ 138 #define DSP_CTRL1 0x64 /* DSP control byte 1 */ 139 #define DSP_CTRL2 0x65 /* DSP control byte 2 */ 140 #define DSP_CTRL3 0x66 /* DSP control byte 3 */ 141 #define DSP_CTRL4 0x67 /* DSP control byte 4 */ 142 #define AWB_BIAS 0x68 /* AWB BLC level clip */ 143 #define AWB_CTRL1 0x69 /* AWB control 1 */ 144 #define AWB_CTRL2 0x6A /* AWB control 2 */ 145 #define AWB_CTRL3 0x6B /* AWB control 3 */ 146 #define AWB_CTRL4 0x6C /* AWB control 4 */ 147 #define AWB_CTRL5 0x6D /* AWB control 5 */ 148 #define AWB_CTRL6 0x6E /* AWB control 6 */ 149 #define AWB_CTRL7 0x6F /* AWB control 7 */ 150 #define AWB_CTRL8 0x70 /* AWB control 8 */ 151 #define AWB_CTRL9 0x71 /* AWB control 9 */ 152 #define AWB_CTRL10 0x72 /* AWB control 10 */ 153 #define AWB_CTRL11 0x73 /* AWB control 11 */ 154 #define AWB_CTRL12 0x74 /* AWB control 12 */ 155 #define AWB_CTRL13 0x75 /* AWB control 13 */ 156 #define AWB_CTRL14 0x76 /* AWB control 14 */ 157 #define AWB_CTRL15 0x77 /* AWB control 15 */ 158 #define AWB_CTRL16 0x78 /* AWB control 16 */ 159 #define AWB_CTRL17 0x79 /* AWB control 17 */ 160 #define AWB_CTRL18 0x7A /* AWB control 18 */ 161 #define AWB_CTRL19 0x7B /* AWB control 19 */ 162 #define AWB_CTRL20 0x7C /* AWB control 20 */ 163 #define AWB_CTRL21 0x7D /* AWB control 21 */ 164 #define GAM1 0x7E /* Gamma Curve 1st segment input end point */ 165 #define GAM2 0x7F /* Gamma Curve 2nd segment input end point */ 166 #define GAM3 0x80 /* Gamma Curve 3rd segment input end point */ 167 #define GAM4 0x81 /* Gamma Curve 4th segment input end point */ 168 #define GAM5 0x82 /* Gamma Curve 5th segment input end point */ 169 #define GAM6 0x83 /* Gamma Curve 6th segment input end point */ 170 #define GAM7 0x84 /* Gamma Curve 7th segment input end point */ 171 #define GAM8 0x85 /* Gamma Curve 8th segment input end point */ 172 #define GAM9 0x86 /* Gamma Curve 9th segment input end point */ 173 #define GAM10 0x87 /* Gamma Curve 10th segment input end point */ 174 #define GAM11 0x88 /* Gamma Curve 11th segment input end point */ 175 #define GAM12 0x89 /* Gamma Curve 12th segment input end point */ 176 #define GAM13 0x8A /* Gamma Curve 13th segment input end point */ 177 #define GAM14 0x8B /* Gamma Curve 14th segment input end point */ 178 #define GAM15 0x8C /* Gamma Curve 15th segment input end point */ 179 #define SLOP 0x8D /* Gamma curve highest segment slope */ 180 #define DNSTH 0x8E /* De-noise threshold */ 181 #define EDGE_STRNGT 0x8F /* Edge strength control when manual mode */ 182 #define EDGE_TRSHLD 0x90 /* Edge threshold control when manual mode */ 183 #define DNSOFF 0x91 /* Auto De-noise threshold control */ 184 #define EDGE_UPPER 0x92 /* Edge strength upper limit when Auto mode */ 185 #define EDGE_LOWER 0x93 /* Edge strength lower limit when Auto mode */ 186 #define MTX1 0x94 /* Matrix coefficient 1 */ 187 #define MTX2 0x95 /* Matrix coefficient 2 */ 188 #define MTX3 0x96 /* Matrix coefficient 3 */ 189 #define MTX4 0x97 /* Matrix coefficient 4 */ 190 #define MTX5 0x98 /* Matrix coefficient 5 */ 191 #define MTX6 0x99 /* Matrix coefficient 6 */ 192 #define MTX_CTRL 0x9A /* Matrix control */ 193 #define BRIGHT 0x9B /* Brightness control */ 194 #define CNTRST 0x9C /* Contrast contrast */ 195 #define CNTRST_CTRL 0x9D /* Contrast contrast center */ 196 #define UVAD_J0 0x9E /* Auto UV adjust contrast 0 */ 197 #define UVAD_J1 0x9F /* Auto UV adjust contrast 1 */ 198 #define SCAL0 0xA0 /* Scaling control 0 */ 199 #define SCAL1 0xA1 /* Scaling control 1 */ 200 #define SCAL2 0xA2 /* Scaling control 2 */ 201 #define FIFODLYM 0xA3 /* FIFO manual mode delay control */ 202 #define FIFODLYA 0xA4 /* FIFO auto mode delay control */ 203 #define SDE 0xA6 /* Special digital effect control */ 204 #define USAT 0xA7 /* U component saturation control */ 205 #define VSAT 0xA8 /* V component saturation control */ 206 /* for ov7720 */ 207 #define HUE0 0xA9 /* Hue control 0 */ 208 #define HUE1 0xAA /* Hue control 1 */ 209 /* for ov7725 */ 210 #define HUECOS 0xA9 /* Cosine value */ 211 #define HUESIN 0xAA /* Sine value */ 212 213 #define SIGN 0xAB /* Sign bit for Hue and contrast */ 214 #define DSPAUTO 0xAC /* DSP auto function ON/OFF control */ 215 216 /* 217 * register detail 218 */ 219 220 /* COM2 */ 221 #define SOFT_SLEEP_MODE 0x10 /* Soft sleep mode */ 222 /* Output drive capability */ 223 #define OCAP_1x 0x00 /* 1x */ 224 #define OCAP_2x 0x01 /* 2x */ 225 #define OCAP_3x 0x02 /* 3x */ 226 #define OCAP_4x 0x03 /* 4x */ 227 228 /* COM3 */ 229 #define SWAP_MASK (SWAP_RGB | SWAP_YUV | SWAP_ML) 230 #define IMG_MASK (VFLIP_IMG | HFLIP_IMG | SCOLOR_TEST) 231 232 #define VFLIP_IMG 0x80 /* Vertical flip image ON/OFF selection */ 233 #define HFLIP_IMG 0x40 /* Horizontal mirror image ON/OFF selection */ 234 #define SWAP_RGB 0x20 /* Swap B/R output sequence in RGB mode */ 235 #define SWAP_YUV 0x10 /* Swap Y/UV output sequence in YUV mode */ 236 #define SWAP_ML 0x08 /* Swap output MSB/LSB */ 237 /* Tri-state option for output clock */ 238 #define NOTRI_CLOCK 0x04 /* 0: Tri-state at this period */ 239 /* 1: No tri-state at this period */ 240 /* Tri-state option for output data */ 241 #define NOTRI_DATA 0x02 /* 0: Tri-state at this period */ 242 /* 1: No tri-state at this period */ 243 #define SCOLOR_TEST 0x01 /* Sensor color bar test pattern */ 244 245 /* COM4 */ 246 /* PLL frequency control */ 247 #define PLL_BYPASS 0x00 /* 00: Bypass PLL */ 248 #define PLL_4x 0x40 /* 01: PLL 4x */ 249 #define PLL_6x 0x80 /* 10: PLL 6x */ 250 #define PLL_8x 0xc0 /* 11: PLL 8x */ 251 /* AEC evaluate window */ 252 #define AEC_FULL 0x00 /* 00: Full window */ 253 #define AEC_1p2 0x10 /* 01: 1/2 window */ 254 #define AEC_1p4 0x20 /* 10: 1/4 window */ 255 #define AEC_2p3 0x30 /* 11: Low 2/3 window */ 256 #define COM4_RESERVED 0x01 /* Reserved bit */ 257 258 /* COM5 */ 259 #define AFR_ON_OFF 0x80 /* Auto frame rate control ON/OFF selection */ 260 #define AFR_SPPED 0x40 /* Auto frame rate control speed selection */ 261 /* Auto frame rate max rate control */ 262 #define AFR_NO_RATE 0x00 /* No reduction of frame rate */ 263 #define AFR_1p2 0x10 /* Max reduction to 1/2 frame rate */ 264 #define AFR_1p4 0x20 /* Max reduction to 1/4 frame rate */ 265 #define AFR_1p8 0x30 /* Max reduction to 1/8 frame rate */ 266 /* Auto frame rate active point control */ 267 #define AF_2x 0x00 /* Add frame when AGC reaches 2x gain */ 268 #define AF_4x 0x04 /* Add frame when AGC reaches 4x gain */ 269 #define AF_8x 0x08 /* Add frame when AGC reaches 8x gain */ 270 #define AF_16x 0x0c /* Add frame when AGC reaches 16x gain */ 271 /* AEC max step control */ 272 #define AEC_NO_LIMIT 0x01 /* 0 : AEC incease step has limit */ 273 /* 1 : No limit to AEC increase step */ 274 /* CLKRC */ 275 /* Input clock divider register */ 276 #define CLKRC_RESERVED 0x80 /* Reserved bit */ 277 #define CLKRC_DIV(n) ((n) - 1) 278 279 /* COM7 */ 280 /* SCCB Register Reset */ 281 #define SCCB_RESET 0x80 /* 0 : No change */ 282 /* 1 : Resets all registers to default */ 283 /* Resolution selection */ 284 #define SLCT_MASK 0x40 /* Mask of VGA or QVGA */ 285 #define SLCT_VGA 0x00 /* 0 : VGA */ 286 #define SLCT_QVGA 0x40 /* 1 : QVGA */ 287 #define ITU656_ON_OFF 0x20 /* ITU656 protocol ON/OFF selection */ 288 #define SENSOR_RAW 0x10 /* Sensor RAW */ 289 /* RGB output format control */ 290 #define FMT_MASK 0x0c /* Mask of color format */ 291 #define FMT_GBR422 0x00 /* 00 : GBR 4:2:2 */ 292 #define FMT_RGB565 0x04 /* 01 : RGB 565 */ 293 #define FMT_RGB555 0x08 /* 10 : RGB 555 */ 294 #define FMT_RGB444 0x0c /* 11 : RGB 444 */ 295 /* Output format control */ 296 #define OFMT_MASK 0x03 /* Mask of output format */ 297 #define OFMT_YUV 0x00 /* 00 : YUV */ 298 #define OFMT_P_BRAW 0x01 /* 01 : Processed Bayer RAW */ 299 #define OFMT_RGB 0x02 /* 10 : RGB */ 300 #define OFMT_BRAW 0x03 /* 11 : Bayer RAW */ 301 302 /* COM8 */ 303 #define FAST_ALGO 0x80 /* Enable fast AGC/AEC algorithm */ 304 /* AEC Setp size limit */ 305 #define UNLMT_STEP 0x40 /* 0 : Step size is limited */ 306 /* 1 : Unlimited step size */ 307 #define BNDF_ON_OFF 0x20 /* Banding filter ON/OFF */ 308 #define AEC_BND 0x10 /* Enable AEC below banding value */ 309 #define AEC_ON_OFF 0x08 /* Fine AEC ON/OFF control */ 310 #define AGC_ON 0x04 /* AGC Enable */ 311 #define AWB_ON 0x02 /* AWB Enable */ 312 #define AEC_ON 0x01 /* AEC Enable */ 313 314 /* COM9 */ 315 #define BASE_AECAGC 0x80 /* Histogram or average based AEC/AGC */ 316 /* Automatic gain ceiling - maximum AGC value */ 317 #define GAIN_2x 0x00 /* 000 : 2x */ 318 #define GAIN_4x 0x10 /* 001 : 4x */ 319 #define GAIN_8x 0x20 /* 010 : 8x */ 320 #define GAIN_16x 0x30 /* 011 : 16x */ 321 #define GAIN_32x 0x40 /* 100 : 32x */ 322 #define GAIN_64x 0x50 /* 101 : 64x */ 323 #define GAIN_128x 0x60 /* 110 : 128x */ 324 #define DROP_VSYNC 0x04 /* Drop VSYNC output of corrupt frame */ 325 #define DROP_HREF 0x02 /* Drop HREF output of corrupt frame */ 326 327 /* COM11 */ 328 #define SGLF_ON_OFF 0x02 /* Single frame ON/OFF selection */ 329 #define SGLF_TRIG 0x01 /* Single frame transfer trigger */ 330 331 /* HREF */ 332 #define HREF_VSTART_SHIFT 6 /* VSTART LSB */ 333 #define HREF_HSTART_SHIFT 4 /* HSTART 2 LSBs */ 334 #define HREF_VSIZE_SHIFT 2 /* VSIZE LSB */ 335 #define HREF_HSIZE_SHIFT 0 /* HSIZE 2 LSBs */ 336 337 /* EXHCH */ 338 #define EXHCH_VSIZE_SHIFT 2 /* VOUTSIZE LSB */ 339 #define EXHCH_HSIZE_SHIFT 0 /* HOUTSIZE 2 LSBs */ 340 341 /* DSP_CTRL1 */ 342 #define FIFO_ON 0x80 /* FIFO enable/disable selection */ 343 #define UV_ON_OFF 0x40 /* UV adjust function ON/OFF selection */ 344 #define YUV444_2_422 0x20 /* YUV444 to 422 UV channel option selection */ 345 #define CLR_MTRX_ON_OFF 0x10 /* Color matrix ON/OFF selection */ 346 #define INTPLT_ON_OFF 0x08 /* Interpolation ON/OFF selection */ 347 #define GMM_ON_OFF 0x04 /* Gamma function ON/OFF selection */ 348 #define AUTO_BLK_ON_OFF 0x02 /* Black defect auto correction ON/OFF */ 349 #define AUTO_WHT_ON_OFF 0x01 /* White define auto correction ON/OFF */ 350 351 /* DSP_CTRL3 */ 352 #define UV_MASK 0x80 /* UV output sequence option */ 353 #define UV_ON 0x80 /* ON */ 354 #define UV_OFF 0x00 /* OFF */ 355 #define CBAR_MASK 0x20 /* DSP Color bar mask */ 356 #define CBAR_ON 0x20 /* ON */ 357 #define CBAR_OFF 0x00 /* OFF */ 358 359 /* DSP_CTRL4 */ 360 #define DSP_OFMT_YUV 0x00 361 #define DSP_OFMT_RGB 0x00 362 #define DSP_OFMT_RAW8 0x02 363 #define DSP_OFMT_RAW10 0x03 364 365 /* DSPAUTO (DSP Auto Function ON/OFF Control) */ 366 #define AWB_ACTRL 0x80 /* AWB auto threshold control */ 367 #define DENOISE_ACTRL 0x40 /* De-noise auto threshold control */ 368 #define EDGE_ACTRL 0x20 /* Edge enhancement auto strength control */ 369 #define UV_ACTRL 0x10 /* UV adjust auto slope control */ 370 #define SCAL0_ACTRL 0x08 /* Auto scaling factor control */ 371 #define SCAL1_2_ACTRL 0x04 /* Auto scaling factor control */ 372 373 #define OV772X_MAX_WIDTH VGA_WIDTH 374 #define OV772X_MAX_HEIGHT VGA_HEIGHT 375 376 /* 377 * ID 378 */ 379 #define OV7720 0x7720 380 #define OV7725 0x7721 381 #define VERSION(pid, ver) ((pid << 8) | (ver & 0xFF)) 382 383 /* 384 * PLL multipliers 385 */ 386 static struct { 387 unsigned int mult; 388 u8 com4; 389 } ov772x_pll[] = { 390 { 1, PLL_BYPASS, }, 391 { 4, PLL_4x, }, 392 { 6, PLL_6x, }, 393 { 8, PLL_8x, }, 394 }; 395 396 /* 397 * struct 398 */ 399 400 struct ov772x_color_format { 401 u32 code; 402 enum v4l2_colorspace colorspace; 403 u8 dsp3; 404 u8 dsp4; 405 u8 com3; 406 u8 com7; 407 }; 408 409 struct ov772x_win_size { 410 char *name; 411 unsigned char com7_bit; 412 unsigned int sizeimage; 413 struct v4l2_rect rect; 414 }; 415 416 struct ov772x_priv { 417 struct v4l2_subdev subdev; 418 struct v4l2_ctrl_handler hdl; 419 struct clk *clk; 420 struct regmap *regmap; 421 struct ov772x_camera_info *info; 422 struct gpio_desc *pwdn_gpio; 423 struct gpio_desc *rstb_gpio; 424 const struct ov772x_color_format *cfmt; 425 const struct ov772x_win_size *win; 426 struct v4l2_ctrl *vflip_ctrl; 427 struct v4l2_ctrl *hflip_ctrl; 428 unsigned int test_pattern; 429 /* band_filter = COM8[5] ? 256 - BDBASE : 0 */ 430 struct v4l2_ctrl *band_filter_ctrl; 431 unsigned int fps; 432 /* lock to protect power_count and streaming */ 433 struct mutex lock; 434 int power_count; 435 int streaming; 436 #ifdef CONFIG_MEDIA_CONTROLLER 437 struct media_pad pad; 438 #endif 439 enum v4l2_mbus_type bus_type; 440 }; 441 442 /* 443 * supported color format list 444 */ 445 static const struct ov772x_color_format ov772x_cfmts[] = { 446 { 447 .code = MEDIA_BUS_FMT_YUYV8_2X8, 448 .colorspace = V4L2_COLORSPACE_SRGB, 449 .dsp3 = 0x0, 450 .dsp4 = DSP_OFMT_YUV, 451 .com3 = SWAP_YUV, 452 .com7 = OFMT_YUV, 453 }, 454 { 455 .code = MEDIA_BUS_FMT_YVYU8_2X8, 456 .colorspace = V4L2_COLORSPACE_SRGB, 457 .dsp3 = UV_ON, 458 .dsp4 = DSP_OFMT_YUV, 459 .com3 = SWAP_YUV, 460 .com7 = OFMT_YUV, 461 }, 462 { 463 .code = MEDIA_BUS_FMT_UYVY8_2X8, 464 .colorspace = V4L2_COLORSPACE_SRGB, 465 .dsp3 = 0x0, 466 .dsp4 = DSP_OFMT_YUV, 467 .com3 = 0x0, 468 .com7 = OFMT_YUV, 469 }, 470 { 471 .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE, 472 .colorspace = V4L2_COLORSPACE_SRGB, 473 .dsp3 = 0x0, 474 .dsp4 = DSP_OFMT_YUV, 475 .com3 = SWAP_RGB, 476 .com7 = FMT_RGB555 | OFMT_RGB, 477 }, 478 { 479 .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE, 480 .colorspace = V4L2_COLORSPACE_SRGB, 481 .dsp3 = 0x0, 482 .dsp4 = DSP_OFMT_YUV, 483 .com3 = 0x0, 484 .com7 = FMT_RGB555 | OFMT_RGB, 485 }, 486 { 487 .code = MEDIA_BUS_FMT_RGB565_2X8_LE, 488 .colorspace = V4L2_COLORSPACE_SRGB, 489 .dsp3 = 0x0, 490 .dsp4 = DSP_OFMT_YUV, 491 .com3 = SWAP_RGB, 492 .com7 = FMT_RGB565 | OFMT_RGB, 493 }, 494 { 495 .code = MEDIA_BUS_FMT_RGB565_2X8_BE, 496 .colorspace = V4L2_COLORSPACE_SRGB, 497 .dsp3 = 0x0, 498 .dsp4 = DSP_OFMT_YUV, 499 .com3 = 0x0, 500 .com7 = FMT_RGB565 | OFMT_RGB, 501 }, 502 { 503 /* Setting DSP4 to DSP_OFMT_RAW8 still gives 10-bit output, 504 * regardless of the COM7 value. We can thus only support 10-bit 505 * Bayer until someone figures it out. 506 */ 507 .code = MEDIA_BUS_FMT_SBGGR10_1X10, 508 .colorspace = V4L2_COLORSPACE_SRGB, 509 .dsp3 = 0x0, 510 .dsp4 = DSP_OFMT_RAW10, 511 .com3 = 0x0, 512 .com7 = SENSOR_RAW | OFMT_BRAW, 513 }, 514 }; 515 516 /* 517 * window size list 518 */ 519 520 static const struct ov772x_win_size ov772x_win_sizes[] = { 521 { 522 .name = "VGA", 523 .com7_bit = SLCT_VGA, 524 .sizeimage = 510 * 748, 525 .rect = { 526 .left = 140, 527 .top = 14, 528 .width = VGA_WIDTH, 529 .height = VGA_HEIGHT, 530 }, 531 }, { 532 .name = "QVGA", 533 .com7_bit = SLCT_QVGA, 534 .sizeimage = 278 * 576, 535 .rect = { 536 .left = 252, 537 .top = 6, 538 .width = QVGA_WIDTH, 539 .height = QVGA_HEIGHT, 540 }, 541 }, 542 }; 543 544 static const char * const ov772x_test_pattern_menu[] = { 545 "Disabled", 546 "Vertical Color Bar Type 1", 547 }; 548 549 /* 550 * frame rate settings lists 551 */ 552 static const unsigned int ov772x_frame_intervals[] = { 5, 10, 15, 20, 30, 60 }; 553 554 /* 555 * general function 556 */ 557 558 static struct ov772x_priv *to_ov772x(struct v4l2_subdev *sd) 559 { 560 return container_of(sd, struct ov772x_priv, subdev); 561 } 562 563 static int ov772x_reset(struct ov772x_priv *priv) 564 { 565 int ret; 566 567 ret = regmap_write(priv->regmap, COM7, SCCB_RESET); 568 if (ret < 0) 569 return ret; 570 571 usleep_range(1000, 5000); 572 573 return regmap_update_bits(priv->regmap, COM2, SOFT_SLEEP_MODE, 574 SOFT_SLEEP_MODE); 575 } 576 577 /* 578 * subdev ops 579 */ 580 581 static int ov772x_s_stream(struct v4l2_subdev *sd, int enable) 582 { 583 struct i2c_client *client = v4l2_get_subdevdata(sd); 584 struct ov772x_priv *priv = to_ov772x(sd); 585 int ret = 0; 586 587 mutex_lock(&priv->lock); 588 589 if (priv->streaming == enable) 590 goto done; 591 592 if (priv->bus_type == V4L2_MBUS_BT656) { 593 ret = regmap_update_bits(priv->regmap, COM7, ITU656_ON_OFF, 594 enable ? 595 ITU656_ON_OFF : ~ITU656_ON_OFF); 596 if (ret) 597 goto done; 598 } 599 600 ret = regmap_update_bits(priv->regmap, COM2, SOFT_SLEEP_MODE, 601 enable ? 0 : SOFT_SLEEP_MODE); 602 if (ret) 603 goto done; 604 605 if (enable) { 606 dev_dbg(&client->dev, "format %d, win %s\n", 607 priv->cfmt->code, priv->win->name); 608 } 609 priv->streaming = enable; 610 611 done: 612 mutex_unlock(&priv->lock); 613 614 return ret; 615 } 616 617 static unsigned int ov772x_select_fps(struct ov772x_priv *priv, 618 struct v4l2_fract *tpf) 619 { 620 unsigned int fps = tpf->numerator ? 621 tpf->denominator / tpf->numerator : 622 tpf->denominator; 623 unsigned int best_diff; 624 unsigned int diff; 625 unsigned int idx; 626 unsigned int i; 627 628 /* Approximate to the closest supported frame interval. */ 629 best_diff = ~0L; 630 for (i = 0, idx = 0; i < ARRAY_SIZE(ov772x_frame_intervals); i++) { 631 diff = abs(fps - ov772x_frame_intervals[i]); 632 if (diff < best_diff) { 633 idx = i; 634 best_diff = diff; 635 } 636 } 637 638 return ov772x_frame_intervals[idx]; 639 } 640 641 static int ov772x_set_frame_rate(struct ov772x_priv *priv, 642 unsigned int fps, 643 const struct ov772x_color_format *cfmt, 644 const struct ov772x_win_size *win) 645 { 646 unsigned long fin = clk_get_rate(priv->clk); 647 unsigned int best_diff; 648 unsigned int fsize; 649 unsigned int pclk; 650 unsigned int diff; 651 unsigned int i; 652 u8 clkrc = 0; 653 u8 com4 = 0; 654 int ret; 655 656 /* Use image size (with blankings) to calculate desired pixel clock. */ 657 switch (cfmt->com7 & OFMT_MASK) { 658 case OFMT_BRAW: 659 fsize = win->sizeimage; 660 break; 661 case OFMT_RGB: 662 case OFMT_YUV: 663 default: 664 fsize = win->sizeimage * 2; 665 break; 666 } 667 668 pclk = fps * fsize; 669 670 /* 671 * Pixel clock generation circuit is pretty simple: 672 * 673 * Fin -> [ / CLKRC_div] -> [ * PLL_mult] -> pclk 674 * 675 * Try to approximate the desired pixel clock testing all available 676 * PLL multipliers (1x, 4x, 6x, 8x) and calculate corresponding 677 * divisor with: 678 * 679 * div = PLL_mult * Fin / pclk 680 * 681 * and re-calculate the pixel clock using it: 682 * 683 * pclk = Fin * PLL_mult / CLKRC_div 684 * 685 * Choose the PLL_mult and CLKRC_div pair that gives a pixel clock 686 * closer to the desired one. 687 * 688 * The desired pixel clock is calculated using a known frame size 689 * (blanking included) and FPS. 690 */ 691 best_diff = ~0L; 692 for (i = 0; i < ARRAY_SIZE(ov772x_pll); i++) { 693 unsigned int pll_mult = ov772x_pll[i].mult; 694 unsigned int pll_out = pll_mult * fin; 695 unsigned int t_pclk; 696 unsigned int div; 697 698 if (pll_out < pclk) 699 continue; 700 701 div = DIV_ROUND_CLOSEST(pll_out, pclk); 702 t_pclk = DIV_ROUND_CLOSEST(fin * pll_mult, div); 703 diff = abs(pclk - t_pclk); 704 if (diff < best_diff) { 705 best_diff = diff; 706 clkrc = CLKRC_DIV(div); 707 com4 = ov772x_pll[i].com4; 708 } 709 } 710 711 ret = regmap_write(priv->regmap, COM4, com4 | COM4_RESERVED); 712 if (ret < 0) 713 return ret; 714 715 ret = regmap_write(priv->regmap, CLKRC, clkrc | CLKRC_RESERVED); 716 if (ret < 0) 717 return ret; 718 719 return 0; 720 } 721 722 static int ov772x_g_frame_interval(struct v4l2_subdev *sd, 723 struct v4l2_subdev_frame_interval *ival) 724 { 725 struct ov772x_priv *priv = to_ov772x(sd); 726 struct v4l2_fract *tpf = &ival->interval; 727 728 tpf->numerator = 1; 729 tpf->denominator = priv->fps; 730 731 return 0; 732 } 733 734 static int ov772x_s_frame_interval(struct v4l2_subdev *sd, 735 struct v4l2_subdev_frame_interval *ival) 736 { 737 struct ov772x_priv *priv = to_ov772x(sd); 738 struct v4l2_fract *tpf = &ival->interval; 739 unsigned int fps; 740 int ret = 0; 741 742 mutex_lock(&priv->lock); 743 744 if (priv->streaming) { 745 ret = -EBUSY; 746 goto error; 747 } 748 749 fps = ov772x_select_fps(priv, tpf); 750 751 /* 752 * If the device is not powered up by the host driver do 753 * not apply any changes to H/W at this time. Instead 754 * the frame rate will be restored right after power-up. 755 */ 756 if (priv->power_count > 0) { 757 ret = ov772x_set_frame_rate(priv, fps, priv->cfmt, priv->win); 758 if (ret) 759 goto error; 760 } 761 762 tpf->numerator = 1; 763 tpf->denominator = fps; 764 priv->fps = fps; 765 766 error: 767 mutex_unlock(&priv->lock); 768 769 return ret; 770 } 771 772 static int ov772x_s_ctrl(struct v4l2_ctrl *ctrl) 773 { 774 struct ov772x_priv *priv = container_of(ctrl->handler, 775 struct ov772x_priv, hdl); 776 struct regmap *regmap = priv->regmap; 777 int ret = 0; 778 u8 val; 779 780 /* v4l2_ctrl_lock() locks our own mutex */ 781 782 /* 783 * If the device is not powered up by the host driver do 784 * not apply any controls to H/W at this time. Instead 785 * the controls will be restored right after power-up. 786 */ 787 if (priv->power_count == 0) 788 return 0; 789 790 switch (ctrl->id) { 791 case V4L2_CID_VFLIP: 792 val = ctrl->val ? VFLIP_IMG : 0x00; 793 if (priv->info && (priv->info->flags & OV772X_FLAG_VFLIP)) 794 val ^= VFLIP_IMG; 795 return regmap_update_bits(regmap, COM3, VFLIP_IMG, val); 796 case V4L2_CID_HFLIP: 797 val = ctrl->val ? HFLIP_IMG : 0x00; 798 if (priv->info && (priv->info->flags & OV772X_FLAG_HFLIP)) 799 val ^= HFLIP_IMG; 800 return regmap_update_bits(regmap, COM3, HFLIP_IMG, val); 801 case V4L2_CID_BAND_STOP_FILTER: 802 if (!ctrl->val) { 803 /* Switch the filter off, it is on now */ 804 ret = regmap_update_bits(regmap, BDBASE, 0xff, 0xff); 805 if (!ret) 806 ret = regmap_update_bits(regmap, COM8, 807 BNDF_ON_OFF, 0); 808 } else { 809 /* Switch the filter on, set AEC low limit */ 810 val = 256 - ctrl->val; 811 ret = regmap_update_bits(regmap, COM8, 812 BNDF_ON_OFF, BNDF_ON_OFF); 813 if (!ret) 814 ret = regmap_update_bits(regmap, BDBASE, 815 0xff, val); 816 } 817 818 return ret; 819 case V4L2_CID_TEST_PATTERN: 820 priv->test_pattern = ctrl->val; 821 return 0; 822 } 823 824 return -EINVAL; 825 } 826 827 #ifdef CONFIG_VIDEO_ADV_DEBUG 828 static int ov772x_g_register(struct v4l2_subdev *sd, 829 struct v4l2_dbg_register *reg) 830 { 831 struct ov772x_priv *priv = to_ov772x(sd); 832 int ret; 833 unsigned int val; 834 835 reg->size = 1; 836 if (reg->reg > 0xff) 837 return -EINVAL; 838 839 ret = regmap_read(priv->regmap, reg->reg, &val); 840 if (ret < 0) 841 return ret; 842 843 reg->val = (__u64)val; 844 845 return 0; 846 } 847 848 static int ov772x_s_register(struct v4l2_subdev *sd, 849 const struct v4l2_dbg_register *reg) 850 { 851 struct ov772x_priv *priv = to_ov772x(sd); 852 853 if (reg->reg > 0xff || 854 reg->val > 0xff) 855 return -EINVAL; 856 857 return regmap_write(priv->regmap, reg->reg, reg->val); 858 } 859 #endif 860 861 static int ov772x_power_on(struct ov772x_priv *priv) 862 { 863 struct i2c_client *client = v4l2_get_subdevdata(&priv->subdev); 864 int ret; 865 866 if (priv->clk) { 867 ret = clk_prepare_enable(priv->clk); 868 if (ret) 869 return ret; 870 } 871 872 if (priv->pwdn_gpio) { 873 gpiod_set_value(priv->pwdn_gpio, 1); 874 usleep_range(500, 1000); 875 } 876 877 /* 878 * FIXME: The reset signal is connected to a shared GPIO on some 879 * platforms (namely the SuperH Migo-R). Until a framework becomes 880 * available to handle this cleanly, request the GPIO temporarily 881 * to avoid conflicts. 882 */ 883 priv->rstb_gpio = gpiod_get_optional(&client->dev, "reset", 884 GPIOD_OUT_LOW); 885 if (IS_ERR(priv->rstb_gpio)) { 886 dev_info(&client->dev, "Unable to get GPIO \"reset\""); 887 clk_disable_unprepare(priv->clk); 888 return PTR_ERR(priv->rstb_gpio); 889 } 890 891 if (priv->rstb_gpio) { 892 gpiod_set_value(priv->rstb_gpio, 1); 893 usleep_range(500, 1000); 894 gpiod_set_value(priv->rstb_gpio, 0); 895 usleep_range(500, 1000); 896 897 gpiod_put(priv->rstb_gpio); 898 } 899 900 return 0; 901 } 902 903 static int ov772x_power_off(struct ov772x_priv *priv) 904 { 905 clk_disable_unprepare(priv->clk); 906 907 if (priv->pwdn_gpio) { 908 gpiod_set_value(priv->pwdn_gpio, 0); 909 usleep_range(500, 1000); 910 } 911 912 return 0; 913 } 914 915 static int ov772x_set_params(struct ov772x_priv *priv, 916 const struct ov772x_color_format *cfmt, 917 const struct ov772x_win_size *win); 918 919 static int ov772x_s_power(struct v4l2_subdev *sd, int on) 920 { 921 struct ov772x_priv *priv = to_ov772x(sd); 922 int ret = 0; 923 924 mutex_lock(&priv->lock); 925 926 /* If the power count is modified from 0 to != 0 or from != 0 to 0, 927 * update the power state. 928 */ 929 if (priv->power_count == !on) { 930 if (on) { 931 ret = ov772x_power_on(priv); 932 /* 933 * Restore the format, the frame rate, and 934 * the controls 935 */ 936 if (!ret) 937 ret = ov772x_set_params(priv, priv->cfmt, 938 priv->win); 939 } else { 940 ret = ov772x_power_off(priv); 941 } 942 } 943 944 if (!ret) { 945 /* Update the power count. */ 946 priv->power_count += on ? 1 : -1; 947 WARN(priv->power_count < 0, "Unbalanced power count\n"); 948 WARN(priv->power_count > 1, "Duplicated s_power call\n"); 949 } 950 951 mutex_unlock(&priv->lock); 952 953 return ret; 954 } 955 956 static const struct ov772x_win_size *ov772x_select_win(u32 width, u32 height) 957 { 958 const struct ov772x_win_size *win = &ov772x_win_sizes[0]; 959 u32 best_diff = UINT_MAX; 960 unsigned int i; 961 962 for (i = 0; i < ARRAY_SIZE(ov772x_win_sizes); ++i) { 963 u32 diff = abs(width - ov772x_win_sizes[i].rect.width) 964 + abs(height - ov772x_win_sizes[i].rect.height); 965 if (diff < best_diff) { 966 best_diff = diff; 967 win = &ov772x_win_sizes[i]; 968 } 969 } 970 971 return win; 972 } 973 974 static void ov772x_select_params(const struct v4l2_mbus_framefmt *mf, 975 const struct ov772x_color_format **cfmt, 976 const struct ov772x_win_size **win) 977 { 978 unsigned int i; 979 980 /* Select a format. */ 981 *cfmt = &ov772x_cfmts[0]; 982 983 for (i = 0; i < ARRAY_SIZE(ov772x_cfmts); i++) { 984 if (mf->code == ov772x_cfmts[i].code) { 985 *cfmt = &ov772x_cfmts[i]; 986 break; 987 } 988 } 989 990 /* Select a window size. */ 991 *win = ov772x_select_win(mf->width, mf->height); 992 } 993 994 static int ov772x_edgectrl(struct ov772x_priv *priv) 995 { 996 struct regmap *regmap = priv->regmap; 997 int ret; 998 999 if (!priv->info) 1000 return 0; 1001 1002 if (priv->info->edgectrl.strength & OV772X_MANUAL_EDGE_CTRL) { 1003 /* 1004 * Manual Edge Control Mode. 1005 * 1006 * Edge auto strength bit is set by default. 1007 * Remove it when manual mode. 1008 */ 1009 1010 ret = regmap_update_bits(regmap, DSPAUTO, EDGE_ACTRL, 0x00); 1011 if (ret < 0) 1012 return ret; 1013 1014 ret = regmap_update_bits(regmap, EDGE_TRSHLD, 1015 OV772X_EDGE_THRESHOLD_MASK, 1016 priv->info->edgectrl.threshold); 1017 if (ret < 0) 1018 return ret; 1019 1020 ret = regmap_update_bits(regmap, EDGE_STRNGT, 1021 OV772X_EDGE_STRENGTH_MASK, 1022 priv->info->edgectrl.strength); 1023 if (ret < 0) 1024 return ret; 1025 1026 } else if (priv->info->edgectrl.upper > priv->info->edgectrl.lower) { 1027 /* 1028 * Auto Edge Control Mode. 1029 * 1030 * Set upper and lower limit. 1031 */ 1032 ret = regmap_update_bits(regmap, EDGE_UPPER, 1033 OV772X_EDGE_UPPER_MASK, 1034 priv->info->edgectrl.upper); 1035 if (ret < 0) 1036 return ret; 1037 1038 ret = regmap_update_bits(regmap, EDGE_LOWER, 1039 OV772X_EDGE_LOWER_MASK, 1040 priv->info->edgectrl.lower); 1041 if (ret < 0) 1042 return ret; 1043 } 1044 1045 return 0; 1046 } 1047 1048 static int ov772x_set_params(struct ov772x_priv *priv, 1049 const struct ov772x_color_format *cfmt, 1050 const struct ov772x_win_size *win) 1051 { 1052 int ret; 1053 u8 val; 1054 1055 /* Reset hardware. */ 1056 ov772x_reset(priv); 1057 1058 /* Edge Ctrl. */ 1059 ret = ov772x_edgectrl(priv); 1060 if (ret < 0) 1061 return ret; 1062 1063 /* Format and window size. */ 1064 ret = regmap_write(priv->regmap, HSTART, win->rect.left >> 2); 1065 if (ret < 0) 1066 goto ov772x_set_fmt_error; 1067 ret = regmap_write(priv->regmap, HSIZE, win->rect.width >> 2); 1068 if (ret < 0) 1069 goto ov772x_set_fmt_error; 1070 ret = regmap_write(priv->regmap, VSTART, win->rect.top >> 1); 1071 if (ret < 0) 1072 goto ov772x_set_fmt_error; 1073 ret = regmap_write(priv->regmap, VSIZE, win->rect.height >> 1); 1074 if (ret < 0) 1075 goto ov772x_set_fmt_error; 1076 ret = regmap_write(priv->regmap, HOUTSIZE, win->rect.width >> 2); 1077 if (ret < 0) 1078 goto ov772x_set_fmt_error; 1079 ret = regmap_write(priv->regmap, VOUTSIZE, win->rect.height >> 1); 1080 if (ret < 0) 1081 goto ov772x_set_fmt_error; 1082 ret = regmap_write(priv->regmap, HREF, 1083 ((win->rect.top & 1) << HREF_VSTART_SHIFT) | 1084 ((win->rect.left & 3) << HREF_HSTART_SHIFT) | 1085 ((win->rect.height & 1) << HREF_VSIZE_SHIFT) | 1086 ((win->rect.width & 3) << HREF_HSIZE_SHIFT)); 1087 if (ret < 0) 1088 goto ov772x_set_fmt_error; 1089 ret = regmap_write(priv->regmap, EXHCH, 1090 ((win->rect.height & 1) << EXHCH_VSIZE_SHIFT) | 1091 ((win->rect.width & 3) << EXHCH_HSIZE_SHIFT)); 1092 if (ret < 0) 1093 goto ov772x_set_fmt_error; 1094 1095 /* Set DSP_CTRL3. */ 1096 val = cfmt->dsp3; 1097 if (val) { 1098 ret = regmap_update_bits(priv->regmap, DSP_CTRL3, UV_MASK, val); 1099 if (ret < 0) 1100 goto ov772x_set_fmt_error; 1101 } 1102 1103 /* DSP_CTRL4: AEC reference point and DSP output format. */ 1104 if (cfmt->dsp4) { 1105 ret = regmap_write(priv->regmap, DSP_CTRL4, cfmt->dsp4); 1106 if (ret < 0) 1107 goto ov772x_set_fmt_error; 1108 } 1109 1110 /* Set COM3. */ 1111 val = cfmt->com3; 1112 if (priv->info && (priv->info->flags & OV772X_FLAG_VFLIP)) 1113 val |= VFLIP_IMG; 1114 if (priv->info && (priv->info->flags & OV772X_FLAG_HFLIP)) 1115 val |= HFLIP_IMG; 1116 if (priv->vflip_ctrl->val) 1117 val ^= VFLIP_IMG; 1118 if (priv->hflip_ctrl->val) 1119 val ^= HFLIP_IMG; 1120 if (priv->test_pattern) 1121 val |= SCOLOR_TEST; 1122 1123 ret = regmap_update_bits(priv->regmap, COM3, SWAP_MASK | IMG_MASK, val); 1124 if (ret < 0) 1125 goto ov772x_set_fmt_error; 1126 1127 /* COM7: Sensor resolution and output format control. */ 1128 ret = regmap_write(priv->regmap, COM7, win->com7_bit | cfmt->com7); 1129 if (ret < 0) 1130 goto ov772x_set_fmt_error; 1131 1132 /* COM4, CLKRC: Set pixel clock and framerate. */ 1133 ret = ov772x_set_frame_rate(priv, priv->fps, cfmt, win); 1134 if (ret < 0) 1135 goto ov772x_set_fmt_error; 1136 1137 /* Set COM8. */ 1138 if (priv->band_filter_ctrl->val) { 1139 unsigned short band_filter = priv->band_filter_ctrl->val; 1140 1141 ret = regmap_update_bits(priv->regmap, COM8, 1142 BNDF_ON_OFF, BNDF_ON_OFF); 1143 if (!ret) 1144 ret = regmap_update_bits(priv->regmap, BDBASE, 1145 0xff, 256 - band_filter); 1146 if (ret < 0) 1147 goto ov772x_set_fmt_error; 1148 } 1149 1150 return ret; 1151 1152 ov772x_set_fmt_error: 1153 1154 ov772x_reset(priv); 1155 1156 return ret; 1157 } 1158 1159 static int ov772x_get_selection(struct v4l2_subdev *sd, 1160 struct v4l2_subdev_state *sd_state, 1161 struct v4l2_subdev_selection *sel) 1162 { 1163 struct ov772x_priv *priv = to_ov772x(sd); 1164 1165 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE) 1166 return -EINVAL; 1167 1168 sel->r.left = 0; 1169 sel->r.top = 0; 1170 switch (sel->target) { 1171 case V4L2_SEL_TGT_CROP_BOUNDS: 1172 case V4L2_SEL_TGT_CROP: 1173 sel->r.width = priv->win->rect.width; 1174 sel->r.height = priv->win->rect.height; 1175 return 0; 1176 default: 1177 return -EINVAL; 1178 } 1179 } 1180 1181 static int ov772x_get_fmt(struct v4l2_subdev *sd, 1182 struct v4l2_subdev_state *sd_state, 1183 struct v4l2_subdev_format *format) 1184 { 1185 struct v4l2_mbus_framefmt *mf = &format->format; 1186 struct ov772x_priv *priv = to_ov772x(sd); 1187 1188 if (format->pad) 1189 return -EINVAL; 1190 1191 mf->width = priv->win->rect.width; 1192 mf->height = priv->win->rect.height; 1193 mf->code = priv->cfmt->code; 1194 mf->colorspace = priv->cfmt->colorspace; 1195 mf->field = V4L2_FIELD_NONE; 1196 1197 return 0; 1198 } 1199 1200 static int ov772x_set_fmt(struct v4l2_subdev *sd, 1201 struct v4l2_subdev_state *sd_state, 1202 struct v4l2_subdev_format *format) 1203 { 1204 struct ov772x_priv *priv = to_ov772x(sd); 1205 struct v4l2_mbus_framefmt *mf = &format->format; 1206 const struct ov772x_color_format *cfmt; 1207 const struct ov772x_win_size *win; 1208 int ret = 0; 1209 1210 if (format->pad) 1211 return -EINVAL; 1212 1213 ov772x_select_params(mf, &cfmt, &win); 1214 1215 mf->code = cfmt->code; 1216 mf->width = win->rect.width; 1217 mf->height = win->rect.height; 1218 mf->field = V4L2_FIELD_NONE; 1219 mf->colorspace = cfmt->colorspace; 1220 mf->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 1221 mf->quantization = V4L2_QUANTIZATION_DEFAULT; 1222 mf->xfer_func = V4L2_XFER_FUNC_DEFAULT; 1223 1224 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 1225 sd_state->pads->try_fmt = *mf; 1226 return 0; 1227 } 1228 1229 mutex_lock(&priv->lock); 1230 1231 if (priv->streaming) { 1232 ret = -EBUSY; 1233 goto error; 1234 } 1235 1236 /* 1237 * If the device is not powered up by the host driver do 1238 * not apply any changes to H/W at this time. Instead 1239 * the format will be restored right after power-up. 1240 */ 1241 if (priv->power_count > 0) { 1242 ret = ov772x_set_params(priv, cfmt, win); 1243 if (ret < 0) 1244 goto error; 1245 } 1246 priv->win = win; 1247 priv->cfmt = cfmt; 1248 1249 error: 1250 mutex_unlock(&priv->lock); 1251 1252 return ret; 1253 } 1254 1255 static int ov772x_video_probe(struct ov772x_priv *priv) 1256 { 1257 struct i2c_client *client = v4l2_get_subdevdata(&priv->subdev); 1258 int pid, ver, midh, midl; 1259 const char *devname; 1260 int ret; 1261 1262 ret = ov772x_power_on(priv); 1263 if (ret < 0) 1264 return ret; 1265 1266 /* Check and show product ID and manufacturer ID. */ 1267 ret = regmap_read(priv->regmap, PID, &pid); 1268 if (ret < 0) 1269 return ret; 1270 ret = regmap_read(priv->regmap, VER, &ver); 1271 if (ret < 0) 1272 return ret; 1273 1274 switch (VERSION(pid, ver)) { 1275 case OV7720: 1276 devname = "ov7720"; 1277 break; 1278 case OV7725: 1279 devname = "ov7725"; 1280 break; 1281 default: 1282 dev_err(&client->dev, 1283 "Product ID error %x:%x\n", pid, ver); 1284 ret = -ENODEV; 1285 goto done; 1286 } 1287 1288 ret = regmap_read(priv->regmap, MIDH, &midh); 1289 if (ret < 0) 1290 return ret; 1291 ret = regmap_read(priv->regmap, MIDL, &midl); 1292 if (ret < 0) 1293 return ret; 1294 1295 dev_info(&client->dev, 1296 "%s Product ID %0x:%0x Manufacturer ID %x:%x\n", 1297 devname, pid, ver, midh, midl); 1298 1299 ret = v4l2_ctrl_handler_setup(&priv->hdl); 1300 1301 done: 1302 ov772x_power_off(priv); 1303 1304 return ret; 1305 } 1306 1307 static const struct v4l2_ctrl_ops ov772x_ctrl_ops = { 1308 .s_ctrl = ov772x_s_ctrl, 1309 }; 1310 1311 static const struct v4l2_subdev_core_ops ov772x_subdev_core_ops = { 1312 .log_status = v4l2_ctrl_subdev_log_status, 1313 .subscribe_event = v4l2_ctrl_subdev_subscribe_event, 1314 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 1315 #ifdef CONFIG_VIDEO_ADV_DEBUG 1316 .g_register = ov772x_g_register, 1317 .s_register = ov772x_s_register, 1318 #endif 1319 .s_power = ov772x_s_power, 1320 }; 1321 1322 static int ov772x_enum_frame_interval(struct v4l2_subdev *sd, 1323 struct v4l2_subdev_state *sd_state, 1324 struct v4l2_subdev_frame_interval_enum *fie) 1325 { 1326 if (fie->pad || fie->index >= ARRAY_SIZE(ov772x_frame_intervals)) 1327 return -EINVAL; 1328 1329 if (fie->width != VGA_WIDTH && fie->width != QVGA_WIDTH) 1330 return -EINVAL; 1331 if (fie->height != VGA_HEIGHT && fie->height != QVGA_HEIGHT) 1332 return -EINVAL; 1333 1334 fie->interval.numerator = 1; 1335 fie->interval.denominator = ov772x_frame_intervals[fie->index]; 1336 1337 return 0; 1338 } 1339 1340 static int ov772x_enum_mbus_code(struct v4l2_subdev *sd, 1341 struct v4l2_subdev_state *sd_state, 1342 struct v4l2_subdev_mbus_code_enum *code) 1343 { 1344 if (code->pad || code->index >= ARRAY_SIZE(ov772x_cfmts)) 1345 return -EINVAL; 1346 1347 code->code = ov772x_cfmts[code->index].code; 1348 1349 return 0; 1350 } 1351 1352 static const struct v4l2_subdev_video_ops ov772x_subdev_video_ops = { 1353 .s_stream = ov772x_s_stream, 1354 .s_frame_interval = ov772x_s_frame_interval, 1355 .g_frame_interval = ov772x_g_frame_interval, 1356 }; 1357 1358 static const struct v4l2_subdev_pad_ops ov772x_subdev_pad_ops = { 1359 .enum_frame_interval = ov772x_enum_frame_interval, 1360 .enum_mbus_code = ov772x_enum_mbus_code, 1361 .get_selection = ov772x_get_selection, 1362 .get_fmt = ov772x_get_fmt, 1363 .set_fmt = ov772x_set_fmt, 1364 }; 1365 1366 static const struct v4l2_subdev_ops ov772x_subdev_ops = { 1367 .core = &ov772x_subdev_core_ops, 1368 .video = &ov772x_subdev_video_ops, 1369 .pad = &ov772x_subdev_pad_ops, 1370 }; 1371 1372 static int ov772x_parse_dt(struct i2c_client *client, 1373 struct ov772x_priv *priv) 1374 { 1375 struct v4l2_fwnode_endpoint bus_cfg = { 1376 .bus_type = V4L2_MBUS_PARALLEL 1377 }; 1378 struct fwnode_handle *ep; 1379 int ret; 1380 1381 ep = fwnode_graph_get_next_endpoint(dev_fwnode(&client->dev), NULL); 1382 if (!ep) { 1383 dev_err(&client->dev, "Endpoint node not found\n"); 1384 return -EINVAL; 1385 } 1386 1387 /* 1388 * For backward compatibility with older DTS where the 1389 * bus-type property was not mandatory, assume 1390 * V4L2_MBUS_PARALLEL as it was the only supported bus at the 1391 * time. v4l2_fwnode_endpoint_alloc_parse() will not fail if 1392 * 'bus-type' is not specified. 1393 */ 1394 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); 1395 if (ret) { 1396 bus_cfg = (struct v4l2_fwnode_endpoint) 1397 { .bus_type = V4L2_MBUS_BT656 }; 1398 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); 1399 if (ret) 1400 goto error_fwnode_put; 1401 } 1402 1403 priv->bus_type = bus_cfg.bus_type; 1404 v4l2_fwnode_endpoint_free(&bus_cfg); 1405 1406 error_fwnode_put: 1407 fwnode_handle_put(ep); 1408 1409 return ret; 1410 } 1411 1412 /* 1413 * i2c_driver function 1414 */ 1415 1416 static int ov772x_probe(struct i2c_client *client) 1417 { 1418 struct ov772x_priv *priv; 1419 int ret; 1420 static const struct regmap_config ov772x_regmap_config = { 1421 .reg_bits = 8, 1422 .val_bits = 8, 1423 .max_register = DSPAUTO, 1424 }; 1425 1426 if (!client->dev.of_node && !client->dev.platform_data) { 1427 dev_err(&client->dev, 1428 "Missing ov772x platform data for non-DT device\n"); 1429 return -EINVAL; 1430 } 1431 1432 priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL); 1433 if (!priv) 1434 return -ENOMEM; 1435 1436 priv->regmap = devm_regmap_init_sccb(client, &ov772x_regmap_config); 1437 if (IS_ERR(priv->regmap)) { 1438 dev_err(&client->dev, "Failed to allocate register map\n"); 1439 return PTR_ERR(priv->regmap); 1440 } 1441 1442 priv->info = client->dev.platform_data; 1443 mutex_init(&priv->lock); 1444 1445 v4l2_i2c_subdev_init(&priv->subdev, client, &ov772x_subdev_ops); 1446 priv->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | 1447 V4L2_SUBDEV_FL_HAS_EVENTS; 1448 v4l2_ctrl_handler_init(&priv->hdl, 3); 1449 /* Use our mutex for the controls */ 1450 priv->hdl.lock = &priv->lock; 1451 priv->vflip_ctrl = v4l2_ctrl_new_std(&priv->hdl, &ov772x_ctrl_ops, 1452 V4L2_CID_VFLIP, 0, 1, 1, 0); 1453 priv->hflip_ctrl = v4l2_ctrl_new_std(&priv->hdl, &ov772x_ctrl_ops, 1454 V4L2_CID_HFLIP, 0, 1, 1, 0); 1455 priv->band_filter_ctrl = v4l2_ctrl_new_std(&priv->hdl, &ov772x_ctrl_ops, 1456 V4L2_CID_BAND_STOP_FILTER, 1457 0, 256, 1, 0); 1458 v4l2_ctrl_new_std_menu_items(&priv->hdl, &ov772x_ctrl_ops, 1459 V4L2_CID_TEST_PATTERN, 1460 ARRAY_SIZE(ov772x_test_pattern_menu) - 1, 1461 0, 0, ov772x_test_pattern_menu); 1462 priv->subdev.ctrl_handler = &priv->hdl; 1463 if (priv->hdl.error) { 1464 ret = priv->hdl.error; 1465 goto error_ctrl_free; 1466 } 1467 1468 priv->clk = clk_get(&client->dev, NULL); 1469 if (IS_ERR(priv->clk)) { 1470 dev_err(&client->dev, "Unable to get xclk clock\n"); 1471 ret = PTR_ERR(priv->clk); 1472 goto error_ctrl_free; 1473 } 1474 1475 priv->pwdn_gpio = gpiod_get_optional(&client->dev, "powerdown", 1476 GPIOD_OUT_LOW); 1477 if (IS_ERR(priv->pwdn_gpio)) { 1478 dev_info(&client->dev, "Unable to get GPIO \"powerdown\""); 1479 ret = PTR_ERR(priv->pwdn_gpio); 1480 goto error_clk_put; 1481 } 1482 1483 ret = ov772x_parse_dt(client, priv); 1484 if (ret) 1485 goto error_clk_put; 1486 1487 ret = ov772x_video_probe(priv); 1488 if (ret < 0) 1489 goto error_gpio_put; 1490 1491 #ifdef CONFIG_MEDIA_CONTROLLER 1492 priv->pad.flags = MEDIA_PAD_FL_SOURCE; 1493 priv->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1494 ret = media_entity_pads_init(&priv->subdev.entity, 1, &priv->pad); 1495 if (ret < 0) 1496 goto error_gpio_put; 1497 #endif 1498 1499 priv->cfmt = &ov772x_cfmts[0]; 1500 priv->win = &ov772x_win_sizes[0]; 1501 priv->fps = 15; 1502 1503 ret = v4l2_async_register_subdev(&priv->subdev); 1504 if (ret) 1505 goto error_entity_cleanup; 1506 1507 return 0; 1508 1509 error_entity_cleanup: 1510 media_entity_cleanup(&priv->subdev.entity); 1511 error_gpio_put: 1512 if (priv->pwdn_gpio) 1513 gpiod_put(priv->pwdn_gpio); 1514 error_clk_put: 1515 clk_put(priv->clk); 1516 error_ctrl_free: 1517 v4l2_ctrl_handler_free(&priv->hdl); 1518 mutex_destroy(&priv->lock); 1519 1520 return ret; 1521 } 1522 1523 static void ov772x_remove(struct i2c_client *client) 1524 { 1525 struct ov772x_priv *priv = to_ov772x(i2c_get_clientdata(client)); 1526 1527 media_entity_cleanup(&priv->subdev.entity); 1528 clk_put(priv->clk); 1529 if (priv->pwdn_gpio) 1530 gpiod_put(priv->pwdn_gpio); 1531 v4l2_async_unregister_subdev(&priv->subdev); 1532 v4l2_ctrl_handler_free(&priv->hdl); 1533 mutex_destroy(&priv->lock); 1534 } 1535 1536 static const struct i2c_device_id ov772x_id[] = { 1537 { "ov772x", 0 }, 1538 { } 1539 }; 1540 MODULE_DEVICE_TABLE(i2c, ov772x_id); 1541 1542 static const struct of_device_id ov772x_of_match[] = { 1543 { .compatible = "ovti,ov7725", }, 1544 { .compatible = "ovti,ov7720", }, 1545 { /* sentinel */ }, 1546 }; 1547 MODULE_DEVICE_TABLE(of, ov772x_of_match); 1548 1549 static struct i2c_driver ov772x_i2c_driver = { 1550 .driver = { 1551 .name = "ov772x", 1552 .of_match_table = ov772x_of_match, 1553 }, 1554 .probe_new = ov772x_probe, 1555 .remove = ov772x_remove, 1556 .id_table = ov772x_id, 1557 }; 1558 1559 module_i2c_driver(ov772x_i2c_driver); 1560 1561 MODULE_DESCRIPTION("V4L2 driver for OV772x image sensor"); 1562 MODULE_AUTHOR("Kuninori Morimoto"); 1563 MODULE_LICENSE("GPL v2"); 1564