1 /* 2 * A V4L2 driver for OmniVision OV7670 cameras. 3 * 4 * Copyright 2006 One Laptop Per Child Association, Inc. Written 5 * by Jonathan Corbet with substantial inspiration from Mark 6 * McClelland's ovcamchip code. 7 * 8 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net> 9 * 10 * This file may be distributed under the terms of the GNU General 11 * Public License, version 2. 12 */ 13 #include <linux/clk.h> 14 #include <linux/init.h> 15 #include <linux/module.h> 16 #include <linux/slab.h> 17 #include <linux/i2c.h> 18 #include <linux/delay.h> 19 #include <linux/videodev2.h> 20 #include <linux/gpio.h> 21 #include <linux/gpio/consumer.h> 22 #include <media/v4l2-device.h> 23 #include <media/v4l2-ctrls.h> 24 #include <media/v4l2-fwnode.h> 25 #include <media/v4l2-mediabus.h> 26 #include <media/v4l2-image-sizes.h> 27 #include <media/i2c/ov7670.h> 28 29 MODULE_AUTHOR("Jonathan Corbet <corbet@lwn.net>"); 30 MODULE_DESCRIPTION("A low-level driver for OmniVision ov7670 sensors"); 31 MODULE_LICENSE("GPL"); 32 33 static bool debug; 34 module_param(debug, bool, 0644); 35 MODULE_PARM_DESC(debug, "Debug level (0-1)"); 36 37 /* 38 * The 7670 sits on i2c with ID 0x42 39 */ 40 #define OV7670_I2C_ADDR 0x42 41 42 #define PLL_FACTOR 4 43 44 /* Registers */ 45 #define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */ 46 #define REG_BLUE 0x01 /* blue gain */ 47 #define REG_RED 0x02 /* red gain */ 48 #define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */ 49 #define REG_COM1 0x04 /* Control 1 */ 50 #define COM1_CCIR656 0x40 /* CCIR656 enable */ 51 #define REG_BAVE 0x05 /* U/B Average level */ 52 #define REG_GbAVE 0x06 /* Y/Gb Average level */ 53 #define REG_AECHH 0x07 /* AEC MS 5 bits */ 54 #define REG_RAVE 0x08 /* V/R Average level */ 55 #define REG_COM2 0x09 /* Control 2 */ 56 #define COM2_SSLEEP 0x10 /* Soft sleep mode */ 57 #define REG_PID 0x0a /* Product ID MSB */ 58 #define REG_VER 0x0b /* Product ID LSB */ 59 #define REG_COM3 0x0c /* Control 3 */ 60 #define COM3_SWAP 0x40 /* Byte swap */ 61 #define COM3_SCALEEN 0x08 /* Enable scaling */ 62 #define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */ 63 #define REG_COM4 0x0d /* Control 4 */ 64 #define REG_COM5 0x0e /* All "reserved" */ 65 #define REG_COM6 0x0f /* Control 6 */ 66 #define REG_AECH 0x10 /* More bits of AEC value */ 67 #define REG_CLKRC 0x11 /* Clocl control */ 68 #define CLK_EXT 0x40 /* Use external clock directly */ 69 #define CLK_SCALE 0x3f /* Mask for internal clock scale */ 70 #define REG_COM7 0x12 /* Control 7 */ 71 #define COM7_RESET 0x80 /* Register reset */ 72 #define COM7_FMT_MASK 0x38 73 #define COM7_FMT_VGA 0x00 74 #define COM7_FMT_CIF 0x20 /* CIF format */ 75 #define COM7_FMT_QVGA 0x10 /* QVGA format */ 76 #define COM7_FMT_QCIF 0x08 /* QCIF format */ 77 #define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */ 78 #define COM7_YUV 0x00 /* YUV */ 79 #define COM7_BAYER 0x01 /* Bayer format */ 80 #define COM7_PBAYER 0x05 /* "Processed bayer" */ 81 #define REG_COM8 0x13 /* Control 8 */ 82 #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */ 83 #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */ 84 #define COM8_BFILT 0x20 /* Band filter enable */ 85 #define COM8_AGC 0x04 /* Auto gain enable */ 86 #define COM8_AWB 0x02 /* White balance enable */ 87 #define COM8_AEC 0x01 /* Auto exposure enable */ 88 #define REG_COM9 0x14 /* Control 9 - gain ceiling */ 89 #define REG_COM10 0x15 /* Control 10 */ 90 #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */ 91 #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */ 92 #define COM10_HREF_REV 0x08 /* Reverse HREF */ 93 #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */ 94 #define COM10_VS_NEG 0x02 /* VSYNC negative */ 95 #define COM10_HS_NEG 0x01 /* HSYNC negative */ 96 #define REG_HSTART 0x17 /* Horiz start high bits */ 97 #define REG_HSTOP 0x18 /* Horiz stop high bits */ 98 #define REG_VSTART 0x19 /* Vert start high bits */ 99 #define REG_VSTOP 0x1a /* Vert stop high bits */ 100 #define REG_PSHFT 0x1b /* Pixel delay after HREF */ 101 #define REG_MIDH 0x1c /* Manuf. ID high */ 102 #define REG_MIDL 0x1d /* Manuf. ID low */ 103 #define REG_MVFP 0x1e /* Mirror / vflip */ 104 #define MVFP_MIRROR 0x20 /* Mirror image */ 105 #define MVFP_FLIP 0x10 /* Vertical flip */ 106 107 #define REG_AEW 0x24 /* AGC upper limit */ 108 #define REG_AEB 0x25 /* AGC lower limit */ 109 #define REG_VPT 0x26 /* AGC/AEC fast mode op region */ 110 #define REG_HSYST 0x30 /* HSYNC rising edge delay */ 111 #define REG_HSYEN 0x31 /* HSYNC falling edge delay */ 112 #define REG_HREF 0x32 /* HREF pieces */ 113 #define REG_TSLB 0x3a /* lots of stuff */ 114 #define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */ 115 #define REG_COM11 0x3b /* Control 11 */ 116 #define COM11_NIGHT 0x80 /* NIght mode enable */ 117 #define COM11_NMFR 0x60 /* Two bit NM frame rate */ 118 #define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */ 119 #define COM11_50HZ 0x08 /* Manual 50Hz select */ 120 #define COM11_EXP 0x02 121 #define REG_COM12 0x3c /* Control 12 */ 122 #define COM12_HREF 0x80 /* HREF always */ 123 #define REG_COM13 0x3d /* Control 13 */ 124 #define COM13_GAMMA 0x80 /* Gamma enable */ 125 #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */ 126 #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */ 127 #define REG_COM14 0x3e /* Control 14 */ 128 #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */ 129 #define REG_EDGE 0x3f /* Edge enhancement factor */ 130 #define REG_COM15 0x40 /* Control 15 */ 131 #define COM15_R10F0 0x00 /* Data range 10 to F0 */ 132 #define COM15_R01FE 0x80 /* 01 to FE */ 133 #define COM15_R00FF 0xc0 /* 00 to FF */ 134 #define COM15_RGB565 0x10 /* RGB565 output */ 135 #define COM15_RGB555 0x30 /* RGB555 output */ 136 #define REG_COM16 0x41 /* Control 16 */ 137 #define COM16_AWBGAIN 0x08 /* AWB gain enable */ 138 #define REG_COM17 0x42 /* Control 17 */ 139 #define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */ 140 #define COM17_CBAR 0x08 /* DSP Color bar */ 141 142 /* 143 * This matrix defines how the colors are generated, must be 144 * tweaked to adjust hue and saturation. 145 * 146 * Order: v-red, v-green, v-blue, u-red, u-green, u-blue 147 * 148 * They are nine-bit signed quantities, with the sign bit 149 * stored in 0x58. Sign for v-red is bit 0, and up from there. 150 */ 151 #define REG_CMATRIX_BASE 0x4f 152 #define CMATRIX_LEN 6 153 #define REG_CMATRIX_SIGN 0x58 154 155 156 #define REG_BRIGHT 0x55 /* Brightness */ 157 #define REG_CONTRAS 0x56 /* Contrast control */ 158 159 #define REG_GFIX 0x69 /* Fix gain control */ 160 161 #define REG_DBLV 0x6b /* PLL control an debugging */ 162 #define DBLV_BYPASS 0x00 /* Bypass PLL */ 163 #define DBLV_X4 0x01 /* clock x4 */ 164 #define DBLV_X6 0x10 /* clock x6 */ 165 #define DBLV_X8 0x11 /* clock x8 */ 166 167 #define REG_SCALING_XSC 0x70 /* Test pattern and horizontal scale factor */ 168 #define TEST_PATTTERN_0 0x80 169 #define REG_SCALING_YSC 0x71 /* Test pattern and vertical scale factor */ 170 #define TEST_PATTTERN_1 0x80 171 172 #define REG_REG76 0x76 /* OV's name */ 173 #define R76_BLKPCOR 0x80 /* Black pixel correction enable */ 174 #define R76_WHTPCOR 0x40 /* White pixel correction enable */ 175 176 #define REG_RGB444 0x8c /* RGB 444 control */ 177 #define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */ 178 #define R444_RGBX 0x01 /* Empty nibble at end */ 179 180 #define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */ 181 #define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */ 182 183 #define REG_BD50MAX 0xa5 /* 50hz banding step limit */ 184 #define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */ 185 #define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */ 186 #define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */ 187 #define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */ 188 #define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */ 189 #define REG_BD60MAX 0xab /* 60hz banding step limit */ 190 191 enum ov7670_model { 192 MODEL_OV7670 = 0, 193 MODEL_OV7675, 194 }; 195 196 struct ov7670_win_size { 197 int width; 198 int height; 199 unsigned char com7_bit; 200 int hstart; /* Start/stop values for the camera. Note */ 201 int hstop; /* that they do not always make complete */ 202 int vstart; /* sense to humans, but evidently the sensor */ 203 int vstop; /* will do the right thing... */ 204 struct regval_list *regs; /* Regs to tweak */ 205 }; 206 207 struct ov7670_devtype { 208 /* formats supported for each model */ 209 struct ov7670_win_size *win_sizes; 210 unsigned int n_win_sizes; 211 /* callbacks for frame rate control */ 212 int (*set_framerate)(struct v4l2_subdev *, struct v4l2_fract *); 213 void (*get_framerate)(struct v4l2_subdev *, struct v4l2_fract *); 214 }; 215 216 /* 217 * Information we maintain about a known sensor. 218 */ 219 struct ov7670_format_struct; /* coming later */ 220 struct ov7670_info { 221 struct v4l2_subdev sd; 222 #if defined(CONFIG_MEDIA_CONTROLLER) 223 struct media_pad pad; 224 #endif 225 struct v4l2_ctrl_handler hdl; 226 struct { 227 /* gain cluster */ 228 struct v4l2_ctrl *auto_gain; 229 struct v4l2_ctrl *gain; 230 }; 231 struct { 232 /* exposure cluster */ 233 struct v4l2_ctrl *auto_exposure; 234 struct v4l2_ctrl *exposure; 235 }; 236 struct { 237 /* saturation/hue cluster */ 238 struct v4l2_ctrl *saturation; 239 struct v4l2_ctrl *hue; 240 }; 241 struct v4l2_mbus_framefmt format; 242 struct ov7670_format_struct *fmt; /* Current format */ 243 struct clk *clk; 244 struct gpio_desc *resetb_gpio; 245 struct gpio_desc *pwdn_gpio; 246 unsigned int mbus_config; /* Media bus configuration flags */ 247 int min_width; /* Filter out smaller sizes */ 248 int min_height; /* Filter out smaller sizes */ 249 int clock_speed; /* External clock speed (MHz) */ 250 u8 clkrc; /* Clock divider value */ 251 bool use_smbus; /* Use smbus I/O instead of I2C */ 252 bool pll_bypass; 253 bool pclk_hb_disable; 254 const struct ov7670_devtype *devtype; /* Device specifics */ 255 }; 256 257 static inline struct ov7670_info *to_state(struct v4l2_subdev *sd) 258 { 259 return container_of(sd, struct ov7670_info, sd); 260 } 261 262 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) 263 { 264 return &container_of(ctrl->handler, struct ov7670_info, hdl)->sd; 265 } 266 267 268 269 /* 270 * The default register settings, as obtained from OmniVision. There 271 * is really no making sense of most of these - lots of "reserved" values 272 * and such. 273 * 274 * These settings give VGA YUYV. 275 */ 276 277 struct regval_list { 278 unsigned char reg_num; 279 unsigned char value; 280 }; 281 282 static struct regval_list ov7670_default_regs[] = { 283 { REG_COM7, COM7_RESET }, 284 /* 285 * Clock scale: 3 = 15fps 286 * 2 = 20fps 287 * 1 = 30fps 288 */ 289 { REG_CLKRC, 0x1 }, /* OV: clock scale (30 fps) */ 290 { REG_TSLB, 0x04 }, /* OV */ 291 { REG_COM7, 0 }, /* VGA */ 292 /* 293 * Set the hardware window. These values from OV don't entirely 294 * make sense - hstop is less than hstart. But they work... 295 */ 296 { REG_HSTART, 0x13 }, { REG_HSTOP, 0x01 }, 297 { REG_HREF, 0xb6 }, { REG_VSTART, 0x02 }, 298 { REG_VSTOP, 0x7a }, { REG_VREF, 0x0a }, 299 300 { REG_COM3, 0 }, { REG_COM14, 0 }, 301 /* Mystery scaling numbers */ 302 { REG_SCALING_XSC, 0x3a }, 303 { REG_SCALING_YSC, 0x35 }, 304 { 0x72, 0x11 }, { 0x73, 0xf0 }, 305 { 0xa2, 0x02 }, { REG_COM10, 0x0 }, 306 307 /* Gamma curve values */ 308 { 0x7a, 0x20 }, { 0x7b, 0x10 }, 309 { 0x7c, 0x1e }, { 0x7d, 0x35 }, 310 { 0x7e, 0x5a }, { 0x7f, 0x69 }, 311 { 0x80, 0x76 }, { 0x81, 0x80 }, 312 { 0x82, 0x88 }, { 0x83, 0x8f }, 313 { 0x84, 0x96 }, { 0x85, 0xa3 }, 314 { 0x86, 0xaf }, { 0x87, 0xc4 }, 315 { 0x88, 0xd7 }, { 0x89, 0xe8 }, 316 317 /* AGC and AEC parameters. Note we start by disabling those features, 318 then turn them only after tweaking the values. */ 319 { REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_BFILT }, 320 { REG_GAIN, 0 }, { REG_AECH, 0 }, 321 { REG_COM4, 0x40 }, /* magic reserved bit */ 322 { REG_COM9, 0x18 }, /* 4x gain + magic rsvd bit */ 323 { REG_BD50MAX, 0x05 }, { REG_BD60MAX, 0x07 }, 324 { REG_AEW, 0x95 }, { REG_AEB, 0x33 }, 325 { REG_VPT, 0xe3 }, { REG_HAECC1, 0x78 }, 326 { REG_HAECC2, 0x68 }, { 0xa1, 0x03 }, /* magic */ 327 { REG_HAECC3, 0xd8 }, { REG_HAECC4, 0xd8 }, 328 { REG_HAECC5, 0xf0 }, { REG_HAECC6, 0x90 }, 329 { REG_HAECC7, 0x94 }, 330 { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC }, 331 332 /* Almost all of these are magic "reserved" values. */ 333 { REG_COM5, 0x61 }, { REG_COM6, 0x4b }, 334 { 0x16, 0x02 }, { REG_MVFP, 0x07 }, 335 { 0x21, 0x02 }, { 0x22, 0x91 }, 336 { 0x29, 0x07 }, { 0x33, 0x0b }, 337 { 0x35, 0x0b }, { 0x37, 0x1d }, 338 { 0x38, 0x71 }, { 0x39, 0x2a }, 339 { REG_COM12, 0x78 }, { 0x4d, 0x40 }, 340 { 0x4e, 0x20 }, { REG_GFIX, 0 }, 341 { 0x6b, 0x4a }, { 0x74, 0x10 }, 342 { 0x8d, 0x4f }, { 0x8e, 0 }, 343 { 0x8f, 0 }, { 0x90, 0 }, 344 { 0x91, 0 }, { 0x96, 0 }, 345 { 0x9a, 0 }, { 0xb0, 0x84 }, 346 { 0xb1, 0x0c }, { 0xb2, 0x0e }, 347 { 0xb3, 0x82 }, { 0xb8, 0x0a }, 348 349 /* More reserved magic, some of which tweaks white balance */ 350 { 0x43, 0x0a }, { 0x44, 0xf0 }, 351 { 0x45, 0x34 }, { 0x46, 0x58 }, 352 { 0x47, 0x28 }, { 0x48, 0x3a }, 353 { 0x59, 0x88 }, { 0x5a, 0x88 }, 354 { 0x5b, 0x44 }, { 0x5c, 0x67 }, 355 { 0x5d, 0x49 }, { 0x5e, 0x0e }, 356 { 0x6c, 0x0a }, { 0x6d, 0x55 }, 357 { 0x6e, 0x11 }, { 0x6f, 0x9f }, /* "9e for advance AWB" */ 358 { 0x6a, 0x40 }, { REG_BLUE, 0x40 }, 359 { REG_RED, 0x60 }, 360 { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC|COM8_AWB }, 361 362 /* Matrix coefficients */ 363 { 0x4f, 0x80 }, { 0x50, 0x80 }, 364 { 0x51, 0 }, { 0x52, 0x22 }, 365 { 0x53, 0x5e }, { 0x54, 0x80 }, 366 { 0x58, 0x9e }, 367 368 { REG_COM16, COM16_AWBGAIN }, { REG_EDGE, 0 }, 369 { 0x75, 0x05 }, { 0x76, 0xe1 }, 370 { 0x4c, 0 }, { 0x77, 0x01 }, 371 { REG_COM13, 0xc3 }, { 0x4b, 0x09 }, 372 { 0xc9, 0x60 }, { REG_COM16, 0x38 }, 373 { 0x56, 0x40 }, 374 375 { 0x34, 0x11 }, { REG_COM11, COM11_EXP|COM11_HZAUTO }, 376 { 0xa4, 0x88 }, { 0x96, 0 }, 377 { 0x97, 0x30 }, { 0x98, 0x20 }, 378 { 0x99, 0x30 }, { 0x9a, 0x84 }, 379 { 0x9b, 0x29 }, { 0x9c, 0x03 }, 380 { 0x9d, 0x4c }, { 0x9e, 0x3f }, 381 { 0x78, 0x04 }, 382 383 /* Extra-weird stuff. Some sort of multiplexor register */ 384 { 0x79, 0x01 }, { 0xc8, 0xf0 }, 385 { 0x79, 0x0f }, { 0xc8, 0x00 }, 386 { 0x79, 0x10 }, { 0xc8, 0x7e }, 387 { 0x79, 0x0a }, { 0xc8, 0x80 }, 388 { 0x79, 0x0b }, { 0xc8, 0x01 }, 389 { 0x79, 0x0c }, { 0xc8, 0x0f }, 390 { 0x79, 0x0d }, { 0xc8, 0x20 }, 391 { 0x79, 0x09 }, { 0xc8, 0x80 }, 392 { 0x79, 0x02 }, { 0xc8, 0xc0 }, 393 { 0x79, 0x03 }, { 0xc8, 0x40 }, 394 { 0x79, 0x05 }, { 0xc8, 0x30 }, 395 { 0x79, 0x26 }, 396 397 { 0xff, 0xff }, /* END MARKER */ 398 }; 399 400 401 /* 402 * Here we'll try to encapsulate the changes for just the output 403 * video format. 404 * 405 * RGB656 and YUV422 come from OV; RGB444 is homebrewed. 406 * 407 * IMPORTANT RULE: the first entry must be for COM7, see ov7670_s_fmt for why. 408 */ 409 410 411 static struct regval_list ov7670_fmt_yuv422[] = { 412 { REG_COM7, 0x0 }, /* Selects YUV mode */ 413 { REG_RGB444, 0 }, /* No RGB444 please */ 414 { REG_COM1, 0 }, /* CCIR601 */ 415 { REG_COM15, COM15_R00FF }, 416 { REG_COM9, 0x48 }, /* 32x gain ceiling; 0x8 is reserved bit */ 417 { 0x4f, 0x80 }, /* "matrix coefficient 1" */ 418 { 0x50, 0x80 }, /* "matrix coefficient 2" */ 419 { 0x51, 0 }, /* vb */ 420 { 0x52, 0x22 }, /* "matrix coefficient 4" */ 421 { 0x53, 0x5e }, /* "matrix coefficient 5" */ 422 { 0x54, 0x80 }, /* "matrix coefficient 6" */ 423 { REG_COM13, COM13_GAMMA|COM13_UVSAT }, 424 { 0xff, 0xff }, 425 }; 426 427 static struct regval_list ov7670_fmt_rgb565[] = { 428 { REG_COM7, COM7_RGB }, /* Selects RGB mode */ 429 { REG_RGB444, 0 }, /* No RGB444 please */ 430 { REG_COM1, 0x0 }, /* CCIR601 */ 431 { REG_COM15, COM15_RGB565 }, 432 { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */ 433 { 0x4f, 0xb3 }, /* "matrix coefficient 1" */ 434 { 0x50, 0xb3 }, /* "matrix coefficient 2" */ 435 { 0x51, 0 }, /* vb */ 436 { 0x52, 0x3d }, /* "matrix coefficient 4" */ 437 { 0x53, 0xa7 }, /* "matrix coefficient 5" */ 438 { 0x54, 0xe4 }, /* "matrix coefficient 6" */ 439 { REG_COM13, COM13_GAMMA|COM13_UVSAT }, 440 { 0xff, 0xff }, 441 }; 442 443 static struct regval_list ov7670_fmt_rgb444[] = { 444 { REG_COM7, COM7_RGB }, /* Selects RGB mode */ 445 { REG_RGB444, R444_ENABLE }, /* Enable xxxxrrrr ggggbbbb */ 446 { REG_COM1, 0x0 }, /* CCIR601 */ 447 { REG_COM15, COM15_R01FE|COM15_RGB565 }, /* Data range needed? */ 448 { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */ 449 { 0x4f, 0xb3 }, /* "matrix coefficient 1" */ 450 { 0x50, 0xb3 }, /* "matrix coefficient 2" */ 451 { 0x51, 0 }, /* vb */ 452 { 0x52, 0x3d }, /* "matrix coefficient 4" */ 453 { 0x53, 0xa7 }, /* "matrix coefficient 5" */ 454 { 0x54, 0xe4 }, /* "matrix coefficient 6" */ 455 { REG_COM13, COM13_GAMMA|COM13_UVSAT|0x2 }, /* Magic rsvd bit */ 456 { 0xff, 0xff }, 457 }; 458 459 static struct regval_list ov7670_fmt_raw[] = { 460 { REG_COM7, COM7_BAYER }, 461 { REG_COM13, 0x08 }, /* No gamma, magic rsvd bit */ 462 { REG_COM16, 0x3d }, /* Edge enhancement, denoise */ 463 { REG_REG76, 0xe1 }, /* Pix correction, magic rsvd */ 464 { 0xff, 0xff }, 465 }; 466 467 468 469 /* 470 * Low-level register I/O. 471 * 472 * Note that there are two versions of these. On the XO 1, the 473 * i2c controller only does SMBUS, so that's what we use. The 474 * ov7670 is not really an SMBUS device, though, so the communication 475 * is not always entirely reliable. 476 */ 477 static int ov7670_read_smbus(struct v4l2_subdev *sd, unsigned char reg, 478 unsigned char *value) 479 { 480 struct i2c_client *client = v4l2_get_subdevdata(sd); 481 int ret; 482 483 ret = i2c_smbus_read_byte_data(client, reg); 484 if (ret >= 0) { 485 *value = (unsigned char)ret; 486 ret = 0; 487 } 488 return ret; 489 } 490 491 492 static int ov7670_write_smbus(struct v4l2_subdev *sd, unsigned char reg, 493 unsigned char value) 494 { 495 struct i2c_client *client = v4l2_get_subdevdata(sd); 496 int ret = i2c_smbus_write_byte_data(client, reg, value); 497 498 if (reg == REG_COM7 && (value & COM7_RESET)) 499 msleep(5); /* Wait for reset to run */ 500 return ret; 501 } 502 503 /* 504 * On most platforms, we'd rather do straight i2c I/O. 505 */ 506 static int ov7670_read_i2c(struct v4l2_subdev *sd, unsigned char reg, 507 unsigned char *value) 508 { 509 struct i2c_client *client = v4l2_get_subdevdata(sd); 510 u8 data = reg; 511 struct i2c_msg msg; 512 int ret; 513 514 /* 515 * Send out the register address... 516 */ 517 msg.addr = client->addr; 518 msg.flags = 0; 519 msg.len = 1; 520 msg.buf = &data; 521 ret = i2c_transfer(client->adapter, &msg, 1); 522 if (ret < 0) { 523 printk(KERN_ERR "Error %d on register write\n", ret); 524 return ret; 525 } 526 /* 527 * ...then read back the result. 528 */ 529 msg.flags = I2C_M_RD; 530 ret = i2c_transfer(client->adapter, &msg, 1); 531 if (ret >= 0) { 532 *value = data; 533 ret = 0; 534 } 535 return ret; 536 } 537 538 539 static int ov7670_write_i2c(struct v4l2_subdev *sd, unsigned char reg, 540 unsigned char value) 541 { 542 struct i2c_client *client = v4l2_get_subdevdata(sd); 543 struct i2c_msg msg; 544 unsigned char data[2] = { reg, value }; 545 int ret; 546 547 msg.addr = client->addr; 548 msg.flags = 0; 549 msg.len = 2; 550 msg.buf = data; 551 ret = i2c_transfer(client->adapter, &msg, 1); 552 if (ret > 0) 553 ret = 0; 554 if (reg == REG_COM7 && (value & COM7_RESET)) 555 msleep(5); /* Wait for reset to run */ 556 return ret; 557 } 558 559 static int ov7670_read(struct v4l2_subdev *sd, unsigned char reg, 560 unsigned char *value) 561 { 562 struct ov7670_info *info = to_state(sd); 563 if (info->use_smbus) 564 return ov7670_read_smbus(sd, reg, value); 565 else 566 return ov7670_read_i2c(sd, reg, value); 567 } 568 569 static int ov7670_write(struct v4l2_subdev *sd, unsigned char reg, 570 unsigned char value) 571 { 572 struct ov7670_info *info = to_state(sd); 573 if (info->use_smbus) 574 return ov7670_write_smbus(sd, reg, value); 575 else 576 return ov7670_write_i2c(sd, reg, value); 577 } 578 579 static int ov7670_update_bits(struct v4l2_subdev *sd, unsigned char reg, 580 unsigned char mask, unsigned char value) 581 { 582 unsigned char orig; 583 int ret; 584 585 ret = ov7670_read(sd, reg, &orig); 586 if (ret) 587 return ret; 588 589 return ov7670_write(sd, reg, (orig & ~mask) | (value & mask)); 590 } 591 592 /* 593 * Write a list of register settings; ff/ff stops the process. 594 */ 595 static int ov7670_write_array(struct v4l2_subdev *sd, struct regval_list *vals) 596 { 597 while (vals->reg_num != 0xff || vals->value != 0xff) { 598 int ret = ov7670_write(sd, vals->reg_num, vals->value); 599 if (ret < 0) 600 return ret; 601 vals++; 602 } 603 return 0; 604 } 605 606 607 /* 608 * Stuff that knows about the sensor. 609 */ 610 static int ov7670_reset(struct v4l2_subdev *sd, u32 val) 611 { 612 ov7670_write(sd, REG_COM7, COM7_RESET); 613 msleep(1); 614 return 0; 615 } 616 617 618 static int ov7670_init(struct v4l2_subdev *sd, u32 val) 619 { 620 return ov7670_write_array(sd, ov7670_default_regs); 621 } 622 623 static int ov7670_detect(struct v4l2_subdev *sd) 624 { 625 unsigned char v; 626 int ret; 627 628 ret = ov7670_init(sd, 0); 629 if (ret < 0) 630 return ret; 631 ret = ov7670_read(sd, REG_MIDH, &v); 632 if (ret < 0) 633 return ret; 634 if (v != 0x7f) /* OV manuf. id. */ 635 return -ENODEV; 636 ret = ov7670_read(sd, REG_MIDL, &v); 637 if (ret < 0) 638 return ret; 639 if (v != 0xa2) 640 return -ENODEV; 641 /* 642 * OK, we know we have an OmniVision chip...but which one? 643 */ 644 ret = ov7670_read(sd, REG_PID, &v); 645 if (ret < 0) 646 return ret; 647 if (v != 0x76) /* PID + VER = 0x76 / 0x73 */ 648 return -ENODEV; 649 ret = ov7670_read(sd, REG_VER, &v); 650 if (ret < 0) 651 return ret; 652 if (v != 0x73) /* PID + VER = 0x76 / 0x73 */ 653 return -ENODEV; 654 return 0; 655 } 656 657 658 /* 659 * Store information about the video data format. The color matrix 660 * is deeply tied into the format, so keep the relevant values here. 661 * The magic matrix numbers come from OmniVision. 662 */ 663 static struct ov7670_format_struct { 664 u32 mbus_code; 665 enum v4l2_colorspace colorspace; 666 struct regval_list *regs; 667 int cmatrix[CMATRIX_LEN]; 668 } ov7670_formats[] = { 669 { 670 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, 671 .colorspace = V4L2_COLORSPACE_SRGB, 672 .regs = ov7670_fmt_yuv422, 673 .cmatrix = { 128, -128, 0, -34, -94, 128 }, 674 }, 675 { 676 .mbus_code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE, 677 .colorspace = V4L2_COLORSPACE_SRGB, 678 .regs = ov7670_fmt_rgb444, 679 .cmatrix = { 179, -179, 0, -61, -176, 228 }, 680 }, 681 { 682 .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE, 683 .colorspace = V4L2_COLORSPACE_SRGB, 684 .regs = ov7670_fmt_rgb565, 685 .cmatrix = { 179, -179, 0, -61, -176, 228 }, 686 }, 687 { 688 .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8, 689 .colorspace = V4L2_COLORSPACE_SRGB, 690 .regs = ov7670_fmt_raw, 691 .cmatrix = { 0, 0, 0, 0, 0, 0 }, 692 }, 693 }; 694 #define N_OV7670_FMTS ARRAY_SIZE(ov7670_formats) 695 696 697 /* 698 * Then there is the issue of window sizes. Try to capture the info here. 699 */ 700 701 /* 702 * QCIF mode is done (by OV) in a very strange way - it actually looks like 703 * VGA with weird scaling options - they do *not* use the canned QCIF mode 704 * which is allegedly provided by the sensor. So here's the weird register 705 * settings. 706 */ 707 static struct regval_list ov7670_qcif_regs[] = { 708 { REG_COM3, COM3_SCALEEN|COM3_DCWEN }, 709 { REG_COM3, COM3_DCWEN }, 710 { REG_COM14, COM14_DCWEN | 0x01}, 711 { 0x73, 0xf1 }, 712 { 0xa2, 0x52 }, 713 { 0x7b, 0x1c }, 714 { 0x7c, 0x28 }, 715 { 0x7d, 0x3c }, 716 { 0x7f, 0x69 }, 717 { REG_COM9, 0x38 }, 718 { 0xa1, 0x0b }, 719 { 0x74, 0x19 }, 720 { 0x9a, 0x80 }, 721 { 0x43, 0x14 }, 722 { REG_COM13, 0xc0 }, 723 { 0xff, 0xff }, 724 }; 725 726 static struct ov7670_win_size ov7670_win_sizes[] = { 727 /* VGA */ 728 { 729 .width = VGA_WIDTH, 730 .height = VGA_HEIGHT, 731 .com7_bit = COM7_FMT_VGA, 732 .hstart = 158, /* These values from */ 733 .hstop = 14, /* Omnivision */ 734 .vstart = 10, 735 .vstop = 490, 736 .regs = NULL, 737 }, 738 /* CIF */ 739 { 740 .width = CIF_WIDTH, 741 .height = CIF_HEIGHT, 742 .com7_bit = COM7_FMT_CIF, 743 .hstart = 170, /* Empirically determined */ 744 .hstop = 90, 745 .vstart = 14, 746 .vstop = 494, 747 .regs = NULL, 748 }, 749 /* QVGA */ 750 { 751 .width = QVGA_WIDTH, 752 .height = QVGA_HEIGHT, 753 .com7_bit = COM7_FMT_QVGA, 754 .hstart = 168, /* Empirically determined */ 755 .hstop = 24, 756 .vstart = 12, 757 .vstop = 492, 758 .regs = NULL, 759 }, 760 /* QCIF */ 761 { 762 .width = QCIF_WIDTH, 763 .height = QCIF_HEIGHT, 764 .com7_bit = COM7_FMT_VGA, /* see comment above */ 765 .hstart = 456, /* Empirically determined */ 766 .hstop = 24, 767 .vstart = 14, 768 .vstop = 494, 769 .regs = ov7670_qcif_regs, 770 } 771 }; 772 773 static struct ov7670_win_size ov7675_win_sizes[] = { 774 /* 775 * Currently, only VGA is supported. Theoretically it could be possible 776 * to support CIF, QVGA and QCIF too. Taking values for ov7670 as a 777 * base and tweak them empirically could be required. 778 */ 779 { 780 .width = VGA_WIDTH, 781 .height = VGA_HEIGHT, 782 .com7_bit = COM7_FMT_VGA, 783 .hstart = 158, /* These values from */ 784 .hstop = 14, /* Omnivision */ 785 .vstart = 14, /* Empirically determined */ 786 .vstop = 494, 787 .regs = NULL, 788 } 789 }; 790 791 static void ov7675_get_framerate(struct v4l2_subdev *sd, 792 struct v4l2_fract *tpf) 793 { 794 struct ov7670_info *info = to_state(sd); 795 u32 clkrc = info->clkrc; 796 int pll_factor; 797 798 if (info->pll_bypass) 799 pll_factor = 1; 800 else 801 pll_factor = PLL_FACTOR; 802 803 clkrc++; 804 if (info->fmt->mbus_code == MEDIA_BUS_FMT_SBGGR8_1X8) 805 clkrc = (clkrc >> 1); 806 807 tpf->numerator = 1; 808 tpf->denominator = (5 * pll_factor * info->clock_speed) / 809 (4 * clkrc); 810 } 811 812 static int ov7675_set_framerate(struct v4l2_subdev *sd, 813 struct v4l2_fract *tpf) 814 { 815 struct ov7670_info *info = to_state(sd); 816 u32 clkrc; 817 int pll_factor; 818 int ret; 819 820 /* 821 * The formula is fps = 5/4*pixclk for YUV/RGB and 822 * fps = 5/2*pixclk for RAW. 823 * 824 * pixclk = clock_speed / (clkrc + 1) * PLLfactor 825 * 826 */ 827 if (info->pll_bypass) { 828 pll_factor = 1; 829 ret = ov7670_write(sd, REG_DBLV, DBLV_BYPASS); 830 } else { 831 pll_factor = PLL_FACTOR; 832 ret = ov7670_write(sd, REG_DBLV, DBLV_X4); 833 } 834 if (ret < 0) 835 return ret; 836 837 if (tpf->numerator == 0 || tpf->denominator == 0) { 838 clkrc = 0; 839 } else { 840 clkrc = (5 * pll_factor * info->clock_speed * tpf->numerator) / 841 (4 * tpf->denominator); 842 if (info->fmt->mbus_code == MEDIA_BUS_FMT_SBGGR8_1X8) 843 clkrc = (clkrc << 1); 844 clkrc--; 845 } 846 847 /* 848 * The datasheet claims that clkrc = 0 will divide the input clock by 1 849 * but we've checked with an oscilloscope that it divides by 2 instead. 850 * So, if clkrc = 0 just bypass the divider. 851 */ 852 if (clkrc <= 0) 853 clkrc = CLK_EXT; 854 else if (clkrc > CLK_SCALE) 855 clkrc = CLK_SCALE; 856 info->clkrc = clkrc; 857 858 /* Recalculate frame rate */ 859 ov7675_get_framerate(sd, tpf); 860 861 ret = ov7670_write(sd, REG_CLKRC, info->clkrc); 862 if (ret < 0) 863 return ret; 864 865 return ov7670_write(sd, REG_DBLV, DBLV_X4); 866 } 867 868 static void ov7670_get_framerate_legacy(struct v4l2_subdev *sd, 869 struct v4l2_fract *tpf) 870 { 871 struct ov7670_info *info = to_state(sd); 872 873 tpf->numerator = 1; 874 tpf->denominator = info->clock_speed; 875 if ((info->clkrc & CLK_EXT) == 0 && (info->clkrc & CLK_SCALE) > 1) 876 tpf->denominator /= (info->clkrc & CLK_SCALE); 877 } 878 879 static int ov7670_set_framerate_legacy(struct v4l2_subdev *sd, 880 struct v4l2_fract *tpf) 881 { 882 struct ov7670_info *info = to_state(sd); 883 int div; 884 885 if (tpf->numerator == 0 || tpf->denominator == 0) 886 div = 1; /* Reset to full rate */ 887 else 888 div = (tpf->numerator * info->clock_speed) / tpf->denominator; 889 if (div == 0) 890 div = 1; 891 else if (div > CLK_SCALE) 892 div = CLK_SCALE; 893 info->clkrc = (info->clkrc & 0x80) | div; 894 tpf->numerator = 1; 895 tpf->denominator = info->clock_speed / div; 896 return ov7670_write(sd, REG_CLKRC, info->clkrc); 897 } 898 899 /* 900 * Store a set of start/stop values into the camera. 901 */ 902 static int ov7670_set_hw(struct v4l2_subdev *sd, int hstart, int hstop, 903 int vstart, int vstop) 904 { 905 int ret; 906 unsigned char v; 907 /* 908 * Horizontal: 11 bits, top 8 live in hstart and hstop. Bottom 3 of 909 * hstart are in href[2:0], bottom 3 of hstop in href[5:3]. There is 910 * a mystery "edge offset" value in the top two bits of href. 911 */ 912 ret = ov7670_write(sd, REG_HSTART, (hstart >> 3) & 0xff); 913 ret += ov7670_write(sd, REG_HSTOP, (hstop >> 3) & 0xff); 914 ret += ov7670_read(sd, REG_HREF, &v); 915 v = (v & 0xc0) | ((hstop & 0x7) << 3) | (hstart & 0x7); 916 msleep(10); 917 ret += ov7670_write(sd, REG_HREF, v); 918 /* 919 * Vertical: similar arrangement, but only 10 bits. 920 */ 921 ret += ov7670_write(sd, REG_VSTART, (vstart >> 2) & 0xff); 922 ret += ov7670_write(sd, REG_VSTOP, (vstop >> 2) & 0xff); 923 ret += ov7670_read(sd, REG_VREF, &v); 924 v = (v & 0xf0) | ((vstop & 0x3) << 2) | (vstart & 0x3); 925 msleep(10); 926 ret += ov7670_write(sd, REG_VREF, v); 927 return ret; 928 } 929 930 931 static int ov7670_enum_mbus_code(struct v4l2_subdev *sd, 932 struct v4l2_subdev_pad_config *cfg, 933 struct v4l2_subdev_mbus_code_enum *code) 934 { 935 if (code->pad || code->index >= N_OV7670_FMTS) 936 return -EINVAL; 937 938 code->code = ov7670_formats[code->index].mbus_code; 939 return 0; 940 } 941 942 static int ov7670_try_fmt_internal(struct v4l2_subdev *sd, 943 struct v4l2_mbus_framefmt *fmt, 944 struct ov7670_format_struct **ret_fmt, 945 struct ov7670_win_size **ret_wsize) 946 { 947 int index, i; 948 struct ov7670_win_size *wsize; 949 struct ov7670_info *info = to_state(sd); 950 unsigned int n_win_sizes = info->devtype->n_win_sizes; 951 unsigned int win_sizes_limit = n_win_sizes; 952 953 for (index = 0; index < N_OV7670_FMTS; index++) 954 if (ov7670_formats[index].mbus_code == fmt->code) 955 break; 956 if (index >= N_OV7670_FMTS) { 957 /* default to first format */ 958 index = 0; 959 fmt->code = ov7670_formats[0].mbus_code; 960 } 961 if (ret_fmt != NULL) 962 *ret_fmt = ov7670_formats + index; 963 /* 964 * Fields: the OV devices claim to be progressive. 965 */ 966 fmt->field = V4L2_FIELD_NONE; 967 968 /* 969 * Don't consider values that don't match min_height and min_width 970 * constraints. 971 */ 972 if (info->min_width || info->min_height) 973 for (i = 0; i < n_win_sizes; i++) { 974 wsize = info->devtype->win_sizes + i; 975 976 if (wsize->width < info->min_width || 977 wsize->height < info->min_height) { 978 win_sizes_limit = i; 979 break; 980 } 981 } 982 /* 983 * Round requested image size down to the nearest 984 * we support, but not below the smallest. 985 */ 986 for (wsize = info->devtype->win_sizes; 987 wsize < info->devtype->win_sizes + win_sizes_limit; wsize++) 988 if (fmt->width >= wsize->width && fmt->height >= wsize->height) 989 break; 990 if (wsize >= info->devtype->win_sizes + win_sizes_limit) 991 wsize--; /* Take the smallest one */ 992 if (ret_wsize != NULL) 993 *ret_wsize = wsize; 994 /* 995 * Note the size we'll actually handle. 996 */ 997 fmt->width = wsize->width; 998 fmt->height = wsize->height; 999 fmt->colorspace = ov7670_formats[index].colorspace; 1000 1001 info->format = *fmt; 1002 1003 return 0; 1004 } 1005 1006 /* 1007 * Set a format. 1008 */ 1009 static int ov7670_set_fmt(struct v4l2_subdev *sd, 1010 struct v4l2_subdev_pad_config *cfg, 1011 struct v4l2_subdev_format *format) 1012 { 1013 struct ov7670_format_struct *ovfmt; 1014 struct ov7670_win_size *wsize; 1015 struct ov7670_info *info = to_state(sd); 1016 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1017 struct v4l2_mbus_framefmt *mbus_fmt; 1018 #endif 1019 unsigned char com7, com10 = 0; 1020 int ret; 1021 1022 if (format->pad) 1023 return -EINVAL; 1024 1025 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 1026 ret = ov7670_try_fmt_internal(sd, &format->format, NULL, NULL); 1027 if (ret) 1028 return ret; 1029 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1030 mbus_fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad); 1031 *mbus_fmt = format->format; 1032 return 0; 1033 #else 1034 return -ENOTTY; 1035 #endif 1036 } 1037 1038 ret = ov7670_try_fmt_internal(sd, &format->format, &ovfmt, &wsize); 1039 if (ret) 1040 return ret; 1041 /* 1042 * COM7 is a pain in the ass, it doesn't like to be read then 1043 * quickly written afterward. But we have everything we need 1044 * to set it absolutely here, as long as the format-specific 1045 * register sets list it first. 1046 */ 1047 com7 = ovfmt->regs[0].value; 1048 com7 |= wsize->com7_bit; 1049 ret = ov7670_write(sd, REG_COM7, com7); 1050 if (ret) 1051 return ret; 1052 1053 /* 1054 * Configure the media bus through COM10 register 1055 */ 1056 if (info->mbus_config & V4L2_MBUS_VSYNC_ACTIVE_LOW) 1057 com10 |= COM10_VS_NEG; 1058 if (info->mbus_config & V4L2_MBUS_HSYNC_ACTIVE_LOW) 1059 com10 |= COM10_HREF_REV; 1060 if (info->pclk_hb_disable) 1061 com10 |= COM10_PCLK_HB; 1062 ret = ov7670_write(sd, REG_COM10, com10); 1063 if (ret) 1064 return ret; 1065 1066 /* 1067 * Now write the rest of the array. Also store start/stops 1068 */ 1069 ret = ov7670_write_array(sd, ovfmt->regs + 1); 1070 if (ret) 1071 return ret; 1072 1073 ret = ov7670_set_hw(sd, wsize->hstart, wsize->hstop, wsize->vstart, 1074 wsize->vstop); 1075 if (ret) 1076 return ret; 1077 1078 if (wsize->regs) { 1079 ret = ov7670_write_array(sd, wsize->regs); 1080 if (ret) 1081 return ret; 1082 } 1083 1084 info->fmt = ovfmt; 1085 1086 /* 1087 * If we're running RGB565, we must rewrite clkrc after setting 1088 * the other parameters or the image looks poor. If we're *not* 1089 * doing RGB565, we must not rewrite clkrc or the image looks 1090 * *really* poor. 1091 * 1092 * (Update) Now that we retain clkrc state, we should be able 1093 * to write it unconditionally, and that will make the frame 1094 * rate persistent too. 1095 */ 1096 ret = ov7670_write(sd, REG_CLKRC, info->clkrc); 1097 if (ret) 1098 return ret; 1099 1100 return 0; 1101 } 1102 1103 static int ov7670_get_fmt(struct v4l2_subdev *sd, 1104 struct v4l2_subdev_pad_config *cfg, 1105 struct v4l2_subdev_format *format) 1106 { 1107 struct ov7670_info *info = to_state(sd); 1108 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1109 struct v4l2_mbus_framefmt *mbus_fmt; 1110 #endif 1111 1112 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 1113 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1114 mbus_fmt = v4l2_subdev_get_try_format(sd, cfg, 0); 1115 format->format = *mbus_fmt; 1116 return 0; 1117 #else 1118 return -ENOTTY; 1119 #endif 1120 } else { 1121 format->format = info->format; 1122 } 1123 1124 return 0; 1125 } 1126 1127 /* 1128 * Implement G/S_PARM. There is a "high quality" mode we could try 1129 * to do someday; for now, we just do the frame rate tweak. 1130 */ 1131 static int ov7670_g_frame_interval(struct v4l2_subdev *sd, 1132 struct v4l2_subdev_frame_interval *ival) 1133 { 1134 struct ov7670_info *info = to_state(sd); 1135 1136 1137 info->devtype->get_framerate(sd, &ival->interval); 1138 1139 return 0; 1140 } 1141 1142 static int ov7670_s_frame_interval(struct v4l2_subdev *sd, 1143 struct v4l2_subdev_frame_interval *ival) 1144 { 1145 struct v4l2_fract *tpf = &ival->interval; 1146 struct ov7670_info *info = to_state(sd); 1147 1148 1149 return info->devtype->set_framerate(sd, tpf); 1150 } 1151 1152 1153 /* 1154 * Frame intervals. Since frame rates are controlled with the clock 1155 * divider, we can only do 30/n for integer n values. So no continuous 1156 * or stepwise options. Here we just pick a handful of logical values. 1157 */ 1158 1159 static int ov7670_frame_rates[] = { 30, 15, 10, 5, 1 }; 1160 1161 static int ov7670_enum_frame_interval(struct v4l2_subdev *sd, 1162 struct v4l2_subdev_pad_config *cfg, 1163 struct v4l2_subdev_frame_interval_enum *fie) 1164 { 1165 struct ov7670_info *info = to_state(sd); 1166 unsigned int n_win_sizes = info->devtype->n_win_sizes; 1167 int i; 1168 1169 if (fie->pad) 1170 return -EINVAL; 1171 if (fie->index >= ARRAY_SIZE(ov7670_frame_rates)) 1172 return -EINVAL; 1173 1174 /* 1175 * Check if the width/height is valid. 1176 * 1177 * If a minimum width/height was requested, filter out the capture 1178 * windows that fall outside that. 1179 */ 1180 for (i = 0; i < n_win_sizes; i++) { 1181 struct ov7670_win_size *win = &info->devtype->win_sizes[i]; 1182 1183 if (info->min_width && win->width < info->min_width) 1184 continue; 1185 if (info->min_height && win->height < info->min_height) 1186 continue; 1187 if (fie->width == win->width && fie->height == win->height) 1188 break; 1189 } 1190 if (i == n_win_sizes) 1191 return -EINVAL; 1192 fie->interval.numerator = 1; 1193 fie->interval.denominator = ov7670_frame_rates[fie->index]; 1194 return 0; 1195 } 1196 1197 /* 1198 * Frame size enumeration 1199 */ 1200 static int ov7670_enum_frame_size(struct v4l2_subdev *sd, 1201 struct v4l2_subdev_pad_config *cfg, 1202 struct v4l2_subdev_frame_size_enum *fse) 1203 { 1204 struct ov7670_info *info = to_state(sd); 1205 int i; 1206 int num_valid = -1; 1207 __u32 index = fse->index; 1208 unsigned int n_win_sizes = info->devtype->n_win_sizes; 1209 1210 if (fse->pad) 1211 return -EINVAL; 1212 1213 /* 1214 * If a minimum width/height was requested, filter out the capture 1215 * windows that fall outside that. 1216 */ 1217 for (i = 0; i < n_win_sizes; i++) { 1218 struct ov7670_win_size *win = &info->devtype->win_sizes[i]; 1219 if (info->min_width && win->width < info->min_width) 1220 continue; 1221 if (info->min_height && win->height < info->min_height) 1222 continue; 1223 if (index == ++num_valid) { 1224 fse->min_width = fse->max_width = win->width; 1225 fse->min_height = fse->max_height = win->height; 1226 return 0; 1227 } 1228 } 1229 1230 return -EINVAL; 1231 } 1232 1233 /* 1234 * Code for dealing with controls. 1235 */ 1236 1237 static int ov7670_store_cmatrix(struct v4l2_subdev *sd, 1238 int matrix[CMATRIX_LEN]) 1239 { 1240 int i, ret; 1241 unsigned char signbits = 0; 1242 1243 /* 1244 * Weird crap seems to exist in the upper part of 1245 * the sign bits register, so let's preserve it. 1246 */ 1247 ret = ov7670_read(sd, REG_CMATRIX_SIGN, &signbits); 1248 signbits &= 0xc0; 1249 1250 for (i = 0; i < CMATRIX_LEN; i++) { 1251 unsigned char raw; 1252 1253 if (matrix[i] < 0) { 1254 signbits |= (1 << i); 1255 if (matrix[i] < -255) 1256 raw = 0xff; 1257 else 1258 raw = (-1 * matrix[i]) & 0xff; 1259 } 1260 else { 1261 if (matrix[i] > 255) 1262 raw = 0xff; 1263 else 1264 raw = matrix[i] & 0xff; 1265 } 1266 ret += ov7670_write(sd, REG_CMATRIX_BASE + i, raw); 1267 } 1268 ret += ov7670_write(sd, REG_CMATRIX_SIGN, signbits); 1269 return ret; 1270 } 1271 1272 1273 /* 1274 * Hue also requires messing with the color matrix. It also requires 1275 * trig functions, which tend not to be well supported in the kernel. 1276 * So here is a simple table of sine values, 0-90 degrees, in steps 1277 * of five degrees. Values are multiplied by 1000. 1278 * 1279 * The following naive approximate trig functions require an argument 1280 * carefully limited to -180 <= theta <= 180. 1281 */ 1282 #define SIN_STEP 5 1283 static const int ov7670_sin_table[] = { 1284 0, 87, 173, 258, 342, 422, 1285 499, 573, 642, 707, 766, 819, 1286 866, 906, 939, 965, 984, 996, 1287 1000 1288 }; 1289 1290 static int ov7670_sine(int theta) 1291 { 1292 int chs = 1; 1293 int sine; 1294 1295 if (theta < 0) { 1296 theta = -theta; 1297 chs = -1; 1298 } 1299 if (theta <= 90) 1300 sine = ov7670_sin_table[theta/SIN_STEP]; 1301 else { 1302 theta -= 90; 1303 sine = 1000 - ov7670_sin_table[theta/SIN_STEP]; 1304 } 1305 return sine*chs; 1306 } 1307 1308 static int ov7670_cosine(int theta) 1309 { 1310 theta = 90 - theta; 1311 if (theta > 180) 1312 theta -= 360; 1313 else if (theta < -180) 1314 theta += 360; 1315 return ov7670_sine(theta); 1316 } 1317 1318 1319 1320 1321 static void ov7670_calc_cmatrix(struct ov7670_info *info, 1322 int matrix[CMATRIX_LEN], int sat, int hue) 1323 { 1324 int i; 1325 /* 1326 * Apply the current saturation setting first. 1327 */ 1328 for (i = 0; i < CMATRIX_LEN; i++) 1329 matrix[i] = (info->fmt->cmatrix[i] * sat) >> 7; 1330 /* 1331 * Then, if need be, rotate the hue value. 1332 */ 1333 if (hue != 0) { 1334 int sinth, costh, tmpmatrix[CMATRIX_LEN]; 1335 1336 memcpy(tmpmatrix, matrix, CMATRIX_LEN*sizeof(int)); 1337 sinth = ov7670_sine(hue); 1338 costh = ov7670_cosine(hue); 1339 1340 matrix[0] = (matrix[3]*sinth + matrix[0]*costh)/1000; 1341 matrix[1] = (matrix[4]*sinth + matrix[1]*costh)/1000; 1342 matrix[2] = (matrix[5]*sinth + matrix[2]*costh)/1000; 1343 matrix[3] = (matrix[3]*costh - matrix[0]*sinth)/1000; 1344 matrix[4] = (matrix[4]*costh - matrix[1]*sinth)/1000; 1345 matrix[5] = (matrix[5]*costh - matrix[2]*sinth)/1000; 1346 } 1347 } 1348 1349 1350 1351 static int ov7670_s_sat_hue(struct v4l2_subdev *sd, int sat, int hue) 1352 { 1353 struct ov7670_info *info = to_state(sd); 1354 int matrix[CMATRIX_LEN]; 1355 int ret; 1356 1357 ov7670_calc_cmatrix(info, matrix, sat, hue); 1358 ret = ov7670_store_cmatrix(sd, matrix); 1359 return ret; 1360 } 1361 1362 1363 /* 1364 * Some weird registers seem to store values in a sign/magnitude format! 1365 */ 1366 1367 static unsigned char ov7670_abs_to_sm(unsigned char v) 1368 { 1369 if (v > 127) 1370 return v & 0x7f; 1371 return (128 - v) | 0x80; 1372 } 1373 1374 static int ov7670_s_brightness(struct v4l2_subdev *sd, int value) 1375 { 1376 unsigned char com8 = 0, v; 1377 int ret; 1378 1379 ov7670_read(sd, REG_COM8, &com8); 1380 com8 &= ~COM8_AEC; 1381 ov7670_write(sd, REG_COM8, com8); 1382 v = ov7670_abs_to_sm(value); 1383 ret = ov7670_write(sd, REG_BRIGHT, v); 1384 return ret; 1385 } 1386 1387 static int ov7670_s_contrast(struct v4l2_subdev *sd, int value) 1388 { 1389 return ov7670_write(sd, REG_CONTRAS, (unsigned char) value); 1390 } 1391 1392 static int ov7670_s_hflip(struct v4l2_subdev *sd, int value) 1393 { 1394 unsigned char v = 0; 1395 int ret; 1396 1397 ret = ov7670_read(sd, REG_MVFP, &v); 1398 if (value) 1399 v |= MVFP_MIRROR; 1400 else 1401 v &= ~MVFP_MIRROR; 1402 msleep(10); /* FIXME */ 1403 ret += ov7670_write(sd, REG_MVFP, v); 1404 return ret; 1405 } 1406 1407 static int ov7670_s_vflip(struct v4l2_subdev *sd, int value) 1408 { 1409 unsigned char v = 0; 1410 int ret; 1411 1412 ret = ov7670_read(sd, REG_MVFP, &v); 1413 if (value) 1414 v |= MVFP_FLIP; 1415 else 1416 v &= ~MVFP_FLIP; 1417 msleep(10); /* FIXME */ 1418 ret += ov7670_write(sd, REG_MVFP, v); 1419 return ret; 1420 } 1421 1422 /* 1423 * GAIN is split between REG_GAIN and REG_VREF[7:6]. If one believes 1424 * the data sheet, the VREF parts should be the most significant, but 1425 * experience shows otherwise. There seems to be little value in 1426 * messing with the VREF bits, so we leave them alone. 1427 */ 1428 static int ov7670_g_gain(struct v4l2_subdev *sd, __s32 *value) 1429 { 1430 int ret; 1431 unsigned char gain; 1432 1433 ret = ov7670_read(sd, REG_GAIN, &gain); 1434 *value = gain; 1435 return ret; 1436 } 1437 1438 static int ov7670_s_gain(struct v4l2_subdev *sd, int value) 1439 { 1440 int ret; 1441 unsigned char com8; 1442 1443 ret = ov7670_write(sd, REG_GAIN, value & 0xff); 1444 /* Have to turn off AGC as well */ 1445 if (ret == 0) { 1446 ret = ov7670_read(sd, REG_COM8, &com8); 1447 ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AGC); 1448 } 1449 return ret; 1450 } 1451 1452 /* 1453 * Tweak autogain. 1454 */ 1455 static int ov7670_s_autogain(struct v4l2_subdev *sd, int value) 1456 { 1457 int ret; 1458 unsigned char com8; 1459 1460 ret = ov7670_read(sd, REG_COM8, &com8); 1461 if (ret == 0) { 1462 if (value) 1463 com8 |= COM8_AGC; 1464 else 1465 com8 &= ~COM8_AGC; 1466 ret = ov7670_write(sd, REG_COM8, com8); 1467 } 1468 return ret; 1469 } 1470 1471 static int ov7670_s_exp(struct v4l2_subdev *sd, int value) 1472 { 1473 int ret; 1474 unsigned char com1, com8, aech, aechh; 1475 1476 ret = ov7670_read(sd, REG_COM1, &com1) + 1477 ov7670_read(sd, REG_COM8, &com8) + 1478 ov7670_read(sd, REG_AECHH, &aechh); 1479 if (ret) 1480 return ret; 1481 1482 com1 = (com1 & 0xfc) | (value & 0x03); 1483 aech = (value >> 2) & 0xff; 1484 aechh = (aechh & 0xc0) | ((value >> 10) & 0x3f); 1485 ret = ov7670_write(sd, REG_COM1, com1) + 1486 ov7670_write(sd, REG_AECH, aech) + 1487 ov7670_write(sd, REG_AECHH, aechh); 1488 /* Have to turn off AEC as well */ 1489 if (ret == 0) 1490 ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AEC); 1491 return ret; 1492 } 1493 1494 /* 1495 * Tweak autoexposure. 1496 */ 1497 static int ov7670_s_autoexp(struct v4l2_subdev *sd, 1498 enum v4l2_exposure_auto_type value) 1499 { 1500 int ret; 1501 unsigned char com8; 1502 1503 ret = ov7670_read(sd, REG_COM8, &com8); 1504 if (ret == 0) { 1505 if (value == V4L2_EXPOSURE_AUTO) 1506 com8 |= COM8_AEC; 1507 else 1508 com8 &= ~COM8_AEC; 1509 ret = ov7670_write(sd, REG_COM8, com8); 1510 } 1511 return ret; 1512 } 1513 1514 static const char * const ov7670_test_pattern_menu[] = { 1515 "No test output", 1516 "Shifting \"1\"", 1517 "8-bar color bar", 1518 "Fade to gray color bar", 1519 }; 1520 1521 static int ov7670_s_test_pattern(struct v4l2_subdev *sd, int value) 1522 { 1523 int ret; 1524 1525 ret = ov7670_update_bits(sd, REG_SCALING_XSC, TEST_PATTTERN_0, 1526 value & BIT(0) ? TEST_PATTTERN_0 : 0); 1527 if (ret) 1528 return ret; 1529 1530 return ov7670_update_bits(sd, REG_SCALING_YSC, TEST_PATTTERN_1, 1531 value & BIT(1) ? TEST_PATTTERN_1 : 0); 1532 } 1533 1534 static int ov7670_g_volatile_ctrl(struct v4l2_ctrl *ctrl) 1535 { 1536 struct v4l2_subdev *sd = to_sd(ctrl); 1537 struct ov7670_info *info = to_state(sd); 1538 1539 switch (ctrl->id) { 1540 case V4L2_CID_AUTOGAIN: 1541 return ov7670_g_gain(sd, &info->gain->val); 1542 } 1543 return -EINVAL; 1544 } 1545 1546 static int ov7670_s_ctrl(struct v4l2_ctrl *ctrl) 1547 { 1548 struct v4l2_subdev *sd = to_sd(ctrl); 1549 struct ov7670_info *info = to_state(sd); 1550 1551 switch (ctrl->id) { 1552 case V4L2_CID_BRIGHTNESS: 1553 return ov7670_s_brightness(sd, ctrl->val); 1554 case V4L2_CID_CONTRAST: 1555 return ov7670_s_contrast(sd, ctrl->val); 1556 case V4L2_CID_SATURATION: 1557 return ov7670_s_sat_hue(sd, 1558 info->saturation->val, info->hue->val); 1559 case V4L2_CID_VFLIP: 1560 return ov7670_s_vflip(sd, ctrl->val); 1561 case V4L2_CID_HFLIP: 1562 return ov7670_s_hflip(sd, ctrl->val); 1563 case V4L2_CID_AUTOGAIN: 1564 /* Only set manual gain if auto gain is not explicitly 1565 turned on. */ 1566 if (!ctrl->val) { 1567 /* ov7670_s_gain turns off auto gain */ 1568 return ov7670_s_gain(sd, info->gain->val); 1569 } 1570 return ov7670_s_autogain(sd, ctrl->val); 1571 case V4L2_CID_EXPOSURE_AUTO: 1572 /* Only set manual exposure if auto exposure is not explicitly 1573 turned on. */ 1574 if (ctrl->val == V4L2_EXPOSURE_MANUAL) { 1575 /* ov7670_s_exp turns off auto exposure */ 1576 return ov7670_s_exp(sd, info->exposure->val); 1577 } 1578 return ov7670_s_autoexp(sd, ctrl->val); 1579 case V4L2_CID_TEST_PATTERN: 1580 return ov7670_s_test_pattern(sd, ctrl->val); 1581 } 1582 return -EINVAL; 1583 } 1584 1585 static const struct v4l2_ctrl_ops ov7670_ctrl_ops = { 1586 .s_ctrl = ov7670_s_ctrl, 1587 .g_volatile_ctrl = ov7670_g_volatile_ctrl, 1588 }; 1589 1590 #ifdef CONFIG_VIDEO_ADV_DEBUG 1591 static int ov7670_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) 1592 { 1593 unsigned char val = 0; 1594 int ret; 1595 1596 ret = ov7670_read(sd, reg->reg & 0xff, &val); 1597 reg->val = val; 1598 reg->size = 1; 1599 return ret; 1600 } 1601 1602 static int ov7670_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg) 1603 { 1604 ov7670_write(sd, reg->reg & 0xff, reg->val & 0xff); 1605 return 0; 1606 } 1607 #endif 1608 1609 static int ov7670_s_power(struct v4l2_subdev *sd, int on) 1610 { 1611 struct ov7670_info *info = to_state(sd); 1612 1613 if (info->pwdn_gpio) 1614 gpiod_set_value(info->pwdn_gpio, !on); 1615 if (on && info->resetb_gpio) { 1616 gpiod_set_value(info->resetb_gpio, 1); 1617 usleep_range(500, 1000); 1618 gpiod_set_value(info->resetb_gpio, 0); 1619 usleep_range(3000, 5000); 1620 } 1621 1622 return 0; 1623 } 1624 1625 static void ov7670_get_default_format(struct v4l2_subdev *sd, 1626 struct v4l2_mbus_framefmt *format) 1627 { 1628 struct ov7670_info *info = to_state(sd); 1629 1630 format->width = info->devtype->win_sizes[0].width; 1631 format->height = info->devtype->win_sizes[0].height; 1632 format->colorspace = info->fmt->colorspace; 1633 format->code = info->fmt->mbus_code; 1634 format->field = V4L2_FIELD_NONE; 1635 } 1636 1637 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1638 static int ov7670_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) 1639 { 1640 struct v4l2_mbus_framefmt *format = 1641 v4l2_subdev_get_try_format(sd, fh->pad, 0); 1642 1643 ov7670_get_default_format(sd, format); 1644 1645 return 0; 1646 } 1647 #endif 1648 1649 /* ----------------------------------------------------------------------- */ 1650 1651 static const struct v4l2_subdev_core_ops ov7670_core_ops = { 1652 .reset = ov7670_reset, 1653 .init = ov7670_init, 1654 #ifdef CONFIG_VIDEO_ADV_DEBUG 1655 .g_register = ov7670_g_register, 1656 .s_register = ov7670_s_register, 1657 #endif 1658 }; 1659 1660 static const struct v4l2_subdev_video_ops ov7670_video_ops = { 1661 .s_frame_interval = ov7670_s_frame_interval, 1662 .g_frame_interval = ov7670_g_frame_interval, 1663 }; 1664 1665 static const struct v4l2_subdev_pad_ops ov7670_pad_ops = { 1666 .enum_frame_interval = ov7670_enum_frame_interval, 1667 .enum_frame_size = ov7670_enum_frame_size, 1668 .enum_mbus_code = ov7670_enum_mbus_code, 1669 .get_fmt = ov7670_get_fmt, 1670 .set_fmt = ov7670_set_fmt, 1671 }; 1672 1673 static const struct v4l2_subdev_ops ov7670_ops = { 1674 .core = &ov7670_core_ops, 1675 .video = &ov7670_video_ops, 1676 .pad = &ov7670_pad_ops, 1677 }; 1678 1679 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1680 static const struct v4l2_subdev_internal_ops ov7670_subdev_internal_ops = { 1681 .open = ov7670_open, 1682 }; 1683 #endif 1684 1685 /* ----------------------------------------------------------------------- */ 1686 1687 static const struct ov7670_devtype ov7670_devdata[] = { 1688 [MODEL_OV7670] = { 1689 .win_sizes = ov7670_win_sizes, 1690 .n_win_sizes = ARRAY_SIZE(ov7670_win_sizes), 1691 .set_framerate = ov7670_set_framerate_legacy, 1692 .get_framerate = ov7670_get_framerate_legacy, 1693 }, 1694 [MODEL_OV7675] = { 1695 .win_sizes = ov7675_win_sizes, 1696 .n_win_sizes = ARRAY_SIZE(ov7675_win_sizes), 1697 .set_framerate = ov7675_set_framerate, 1698 .get_framerate = ov7675_get_framerate, 1699 }, 1700 }; 1701 1702 static int ov7670_init_gpio(struct i2c_client *client, struct ov7670_info *info) 1703 { 1704 info->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown", 1705 GPIOD_OUT_LOW); 1706 if (IS_ERR(info->pwdn_gpio)) { 1707 dev_info(&client->dev, "can't get %s GPIO\n", "powerdown"); 1708 return PTR_ERR(info->pwdn_gpio); 1709 } 1710 1711 info->resetb_gpio = devm_gpiod_get_optional(&client->dev, "reset", 1712 GPIOD_OUT_LOW); 1713 if (IS_ERR(info->resetb_gpio)) { 1714 dev_info(&client->dev, "can't get %s GPIO\n", "reset"); 1715 return PTR_ERR(info->resetb_gpio); 1716 } 1717 1718 usleep_range(3000, 5000); 1719 1720 return 0; 1721 } 1722 1723 /* 1724 * ov7670_parse_dt() - Parse device tree to collect mbus configuration 1725 * properties 1726 */ 1727 static int ov7670_parse_dt(struct device *dev, 1728 struct ov7670_info *info) 1729 { 1730 struct fwnode_handle *fwnode = dev_fwnode(dev); 1731 struct v4l2_fwnode_endpoint bus_cfg; 1732 struct fwnode_handle *ep; 1733 int ret; 1734 1735 if (!fwnode) 1736 return -EINVAL; 1737 1738 info->pclk_hb_disable = false; 1739 if (fwnode_property_present(fwnode, "ov7670,pclk-hb-disable")) 1740 info->pclk_hb_disable = true; 1741 1742 ep = fwnode_graph_get_next_endpoint(fwnode, NULL); 1743 if (!ep) 1744 return -EINVAL; 1745 1746 ret = v4l2_fwnode_endpoint_parse(ep, &bus_cfg); 1747 if (ret) { 1748 fwnode_handle_put(ep); 1749 return ret; 1750 } 1751 1752 if (bus_cfg.bus_type != V4L2_MBUS_PARALLEL) { 1753 dev_err(dev, "Unsupported media bus type\n"); 1754 fwnode_handle_put(ep); 1755 return ret; 1756 } 1757 info->mbus_config = bus_cfg.bus.parallel.flags; 1758 1759 return 0; 1760 } 1761 1762 static int ov7670_probe(struct i2c_client *client, 1763 const struct i2c_device_id *id) 1764 { 1765 struct v4l2_fract tpf; 1766 struct v4l2_subdev *sd; 1767 struct ov7670_info *info; 1768 int ret; 1769 1770 info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL); 1771 if (info == NULL) 1772 return -ENOMEM; 1773 sd = &info->sd; 1774 v4l2_i2c_subdev_init(sd, client, &ov7670_ops); 1775 1776 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1777 sd->internal_ops = &ov7670_subdev_internal_ops; 1778 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1779 #endif 1780 1781 info->clock_speed = 30; /* default: a guess */ 1782 1783 if (dev_fwnode(&client->dev)) { 1784 ret = ov7670_parse_dt(&client->dev, info); 1785 if (ret) 1786 return ret; 1787 1788 } else if (client->dev.platform_data) { 1789 struct ov7670_config *config = client->dev.platform_data; 1790 1791 /* 1792 * Must apply configuration before initializing device, because it 1793 * selects I/O method. 1794 */ 1795 info->min_width = config->min_width; 1796 info->min_height = config->min_height; 1797 info->use_smbus = config->use_smbus; 1798 1799 if (config->clock_speed) 1800 info->clock_speed = config->clock_speed; 1801 1802 /* 1803 * It should be allowed for ov7670 too when it is migrated to 1804 * the new frame rate formula. 1805 */ 1806 if (config->pll_bypass && id->driver_data != MODEL_OV7670) 1807 info->pll_bypass = true; 1808 1809 if (config->pclk_hb_disable) 1810 info->pclk_hb_disable = true; 1811 } 1812 1813 info->clk = devm_clk_get(&client->dev, "xclk"); 1814 if (IS_ERR(info->clk)) 1815 return PTR_ERR(info->clk); 1816 ret = clk_prepare_enable(info->clk); 1817 if (ret) 1818 return ret; 1819 1820 info->clock_speed = clk_get_rate(info->clk) / 1000000; 1821 if (info->clock_speed < 10 || info->clock_speed > 48) { 1822 ret = -EINVAL; 1823 goto clk_disable; 1824 } 1825 1826 ret = ov7670_init_gpio(client, info); 1827 if (ret) 1828 goto clk_disable; 1829 1830 ov7670_s_power(sd, 1); 1831 1832 /* Make sure it's an ov7670 */ 1833 ret = ov7670_detect(sd); 1834 if (ret) { 1835 v4l_dbg(1, debug, client, 1836 "chip found @ 0x%x (%s) is not an ov7670 chip.\n", 1837 client->addr << 1, client->adapter->name); 1838 goto power_off; 1839 } 1840 v4l_info(client, "chip found @ 0x%02x (%s)\n", 1841 client->addr << 1, client->adapter->name); 1842 1843 info->devtype = &ov7670_devdata[id->driver_data]; 1844 info->fmt = &ov7670_formats[0]; 1845 1846 ov7670_get_default_format(sd, &info->format); 1847 1848 info->clkrc = 0; 1849 1850 /* Set default frame rate to 30 fps */ 1851 tpf.numerator = 1; 1852 tpf.denominator = 30; 1853 info->devtype->set_framerate(sd, &tpf); 1854 1855 v4l2_ctrl_handler_init(&info->hdl, 10); 1856 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1857 V4L2_CID_BRIGHTNESS, 0, 255, 1, 128); 1858 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1859 V4L2_CID_CONTRAST, 0, 127, 1, 64); 1860 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1861 V4L2_CID_VFLIP, 0, 1, 1, 0); 1862 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1863 V4L2_CID_HFLIP, 0, 1, 1, 0); 1864 info->saturation = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1865 V4L2_CID_SATURATION, 0, 256, 1, 128); 1866 info->hue = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1867 V4L2_CID_HUE, -180, 180, 5, 0); 1868 info->gain = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1869 V4L2_CID_GAIN, 0, 255, 1, 128); 1870 info->auto_gain = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1871 V4L2_CID_AUTOGAIN, 0, 1, 1, 1); 1872 info->exposure = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1873 V4L2_CID_EXPOSURE, 0, 65535, 1, 500); 1874 info->auto_exposure = v4l2_ctrl_new_std_menu(&info->hdl, &ov7670_ctrl_ops, 1875 V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL, 0, 1876 V4L2_EXPOSURE_AUTO); 1877 v4l2_ctrl_new_std_menu_items(&info->hdl, &ov7670_ctrl_ops, 1878 V4L2_CID_TEST_PATTERN, 1879 ARRAY_SIZE(ov7670_test_pattern_menu) - 1, 0, 0, 1880 ov7670_test_pattern_menu); 1881 sd->ctrl_handler = &info->hdl; 1882 if (info->hdl.error) { 1883 ret = info->hdl.error; 1884 1885 goto hdl_free; 1886 } 1887 /* 1888 * We have checked empirically that hw allows to read back the gain 1889 * value chosen by auto gain but that's not the case for auto exposure. 1890 */ 1891 v4l2_ctrl_auto_cluster(2, &info->auto_gain, 0, true); 1892 v4l2_ctrl_auto_cluster(2, &info->auto_exposure, 1893 V4L2_EXPOSURE_MANUAL, false); 1894 v4l2_ctrl_cluster(2, &info->saturation); 1895 1896 #if defined(CONFIG_MEDIA_CONTROLLER) 1897 info->pad.flags = MEDIA_PAD_FL_SOURCE; 1898 info->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1899 ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad); 1900 if (ret < 0) 1901 goto hdl_free; 1902 #endif 1903 1904 v4l2_ctrl_handler_setup(&info->hdl); 1905 1906 ret = v4l2_async_register_subdev(&info->sd); 1907 if (ret < 0) 1908 goto entity_cleanup; 1909 1910 return 0; 1911 1912 entity_cleanup: 1913 media_entity_cleanup(&info->sd.entity); 1914 hdl_free: 1915 v4l2_ctrl_handler_free(&info->hdl); 1916 power_off: 1917 ov7670_s_power(sd, 0); 1918 clk_disable: 1919 clk_disable_unprepare(info->clk); 1920 return ret; 1921 } 1922 1923 1924 static int ov7670_remove(struct i2c_client *client) 1925 { 1926 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1927 struct ov7670_info *info = to_state(sd); 1928 1929 v4l2_async_unregister_subdev(sd); 1930 v4l2_ctrl_handler_free(&info->hdl); 1931 clk_disable_unprepare(info->clk); 1932 media_entity_cleanup(&info->sd.entity); 1933 ov7670_s_power(sd, 0); 1934 return 0; 1935 } 1936 1937 static const struct i2c_device_id ov7670_id[] = { 1938 { "ov7670", MODEL_OV7670 }, 1939 { "ov7675", MODEL_OV7675 }, 1940 { } 1941 }; 1942 MODULE_DEVICE_TABLE(i2c, ov7670_id); 1943 1944 #if IS_ENABLED(CONFIG_OF) 1945 static const struct of_device_id ov7670_of_match[] = { 1946 { .compatible = "ovti,ov7670", }, 1947 { /* sentinel */ }, 1948 }; 1949 MODULE_DEVICE_TABLE(of, ov7670_of_match); 1950 #endif 1951 1952 static struct i2c_driver ov7670_driver = { 1953 .driver = { 1954 .name = "ov7670", 1955 .of_match_table = of_match_ptr(ov7670_of_match), 1956 }, 1957 .probe = ov7670_probe, 1958 .remove = ov7670_remove, 1959 .id_table = ov7670_id, 1960 }; 1961 1962 module_i2c_driver(ov7670_driver); 1963