1 /* 2 * A V4L2 driver for OmniVision OV7670 cameras. 3 * 4 * Copyright 2006 One Laptop Per Child Association, Inc. Written 5 * by Jonathan Corbet with substantial inspiration from Mark 6 * McClelland's ovcamchip code. 7 * 8 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net> 9 * 10 * This file may be distributed under the terms of the GNU General 11 * Public License, version 2. 12 */ 13 #include <linux/init.h> 14 #include <linux/module.h> 15 #include <linux/slab.h> 16 #include <linux/i2c.h> 17 #include <linux/delay.h> 18 #include <linux/videodev2.h> 19 #include <media/v4l2-device.h> 20 #include <media/v4l2-ctrls.h> 21 #include <media/v4l2-mediabus.h> 22 #include <media/ov7670.h> 23 24 MODULE_AUTHOR("Jonathan Corbet <corbet@lwn.net>"); 25 MODULE_DESCRIPTION("A low-level driver for OmniVision ov7670 sensors"); 26 MODULE_LICENSE("GPL"); 27 28 static bool debug; 29 module_param(debug, bool, 0644); 30 MODULE_PARM_DESC(debug, "Debug level (0-1)"); 31 32 /* 33 * Basic window sizes. These probably belong somewhere more globally 34 * useful. 35 */ 36 #define VGA_WIDTH 640 37 #define VGA_HEIGHT 480 38 #define QVGA_WIDTH 320 39 #define QVGA_HEIGHT 240 40 #define CIF_WIDTH 352 41 #define CIF_HEIGHT 288 42 #define QCIF_WIDTH 176 43 #define QCIF_HEIGHT 144 44 45 /* 46 * The 7670 sits on i2c with ID 0x42 47 */ 48 #define OV7670_I2C_ADDR 0x42 49 50 #define PLL_FACTOR 4 51 52 /* Registers */ 53 #define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */ 54 #define REG_BLUE 0x01 /* blue gain */ 55 #define REG_RED 0x02 /* red gain */ 56 #define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */ 57 #define REG_COM1 0x04 /* Control 1 */ 58 #define COM1_CCIR656 0x40 /* CCIR656 enable */ 59 #define REG_BAVE 0x05 /* U/B Average level */ 60 #define REG_GbAVE 0x06 /* Y/Gb Average level */ 61 #define REG_AECHH 0x07 /* AEC MS 5 bits */ 62 #define REG_RAVE 0x08 /* V/R Average level */ 63 #define REG_COM2 0x09 /* Control 2 */ 64 #define COM2_SSLEEP 0x10 /* Soft sleep mode */ 65 #define REG_PID 0x0a /* Product ID MSB */ 66 #define REG_VER 0x0b /* Product ID LSB */ 67 #define REG_COM3 0x0c /* Control 3 */ 68 #define COM3_SWAP 0x40 /* Byte swap */ 69 #define COM3_SCALEEN 0x08 /* Enable scaling */ 70 #define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */ 71 #define REG_COM4 0x0d /* Control 4 */ 72 #define REG_COM5 0x0e /* All "reserved" */ 73 #define REG_COM6 0x0f /* Control 6 */ 74 #define REG_AECH 0x10 /* More bits of AEC value */ 75 #define REG_CLKRC 0x11 /* Clocl control */ 76 #define CLK_EXT 0x40 /* Use external clock directly */ 77 #define CLK_SCALE 0x3f /* Mask for internal clock scale */ 78 #define REG_COM7 0x12 /* Control 7 */ 79 #define COM7_RESET 0x80 /* Register reset */ 80 #define COM7_FMT_MASK 0x38 81 #define COM7_FMT_VGA 0x00 82 #define COM7_FMT_CIF 0x20 /* CIF format */ 83 #define COM7_FMT_QVGA 0x10 /* QVGA format */ 84 #define COM7_FMT_QCIF 0x08 /* QCIF format */ 85 #define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */ 86 #define COM7_YUV 0x00 /* YUV */ 87 #define COM7_BAYER 0x01 /* Bayer format */ 88 #define COM7_PBAYER 0x05 /* "Processed bayer" */ 89 #define REG_COM8 0x13 /* Control 8 */ 90 #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */ 91 #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */ 92 #define COM8_BFILT 0x20 /* Band filter enable */ 93 #define COM8_AGC 0x04 /* Auto gain enable */ 94 #define COM8_AWB 0x02 /* White balance enable */ 95 #define COM8_AEC 0x01 /* Auto exposure enable */ 96 #define REG_COM9 0x14 /* Control 9 - gain ceiling */ 97 #define REG_COM10 0x15 /* Control 10 */ 98 #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */ 99 #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */ 100 #define COM10_HREF_REV 0x08 /* Reverse HREF */ 101 #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */ 102 #define COM10_VS_NEG 0x02 /* VSYNC negative */ 103 #define COM10_HS_NEG 0x01 /* HSYNC negative */ 104 #define REG_HSTART 0x17 /* Horiz start high bits */ 105 #define REG_HSTOP 0x18 /* Horiz stop high bits */ 106 #define REG_VSTART 0x19 /* Vert start high bits */ 107 #define REG_VSTOP 0x1a /* Vert stop high bits */ 108 #define REG_PSHFT 0x1b /* Pixel delay after HREF */ 109 #define REG_MIDH 0x1c /* Manuf. ID high */ 110 #define REG_MIDL 0x1d /* Manuf. ID low */ 111 #define REG_MVFP 0x1e /* Mirror / vflip */ 112 #define MVFP_MIRROR 0x20 /* Mirror image */ 113 #define MVFP_FLIP 0x10 /* Vertical flip */ 114 115 #define REG_AEW 0x24 /* AGC upper limit */ 116 #define REG_AEB 0x25 /* AGC lower limit */ 117 #define REG_VPT 0x26 /* AGC/AEC fast mode op region */ 118 #define REG_HSYST 0x30 /* HSYNC rising edge delay */ 119 #define REG_HSYEN 0x31 /* HSYNC falling edge delay */ 120 #define REG_HREF 0x32 /* HREF pieces */ 121 #define REG_TSLB 0x3a /* lots of stuff */ 122 #define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */ 123 #define REG_COM11 0x3b /* Control 11 */ 124 #define COM11_NIGHT 0x80 /* NIght mode enable */ 125 #define COM11_NMFR 0x60 /* Two bit NM frame rate */ 126 #define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */ 127 #define COM11_50HZ 0x08 /* Manual 50Hz select */ 128 #define COM11_EXP 0x02 129 #define REG_COM12 0x3c /* Control 12 */ 130 #define COM12_HREF 0x80 /* HREF always */ 131 #define REG_COM13 0x3d /* Control 13 */ 132 #define COM13_GAMMA 0x80 /* Gamma enable */ 133 #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */ 134 #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */ 135 #define REG_COM14 0x3e /* Control 14 */ 136 #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */ 137 #define REG_EDGE 0x3f /* Edge enhancement factor */ 138 #define REG_COM15 0x40 /* Control 15 */ 139 #define COM15_R10F0 0x00 /* Data range 10 to F0 */ 140 #define COM15_R01FE 0x80 /* 01 to FE */ 141 #define COM15_R00FF 0xc0 /* 00 to FF */ 142 #define COM15_RGB565 0x10 /* RGB565 output */ 143 #define COM15_RGB555 0x30 /* RGB555 output */ 144 #define REG_COM16 0x41 /* Control 16 */ 145 #define COM16_AWBGAIN 0x08 /* AWB gain enable */ 146 #define REG_COM17 0x42 /* Control 17 */ 147 #define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */ 148 #define COM17_CBAR 0x08 /* DSP Color bar */ 149 150 /* 151 * This matrix defines how the colors are generated, must be 152 * tweaked to adjust hue and saturation. 153 * 154 * Order: v-red, v-green, v-blue, u-red, u-green, u-blue 155 * 156 * They are nine-bit signed quantities, with the sign bit 157 * stored in 0x58. Sign for v-red is bit 0, and up from there. 158 */ 159 #define REG_CMATRIX_BASE 0x4f 160 #define CMATRIX_LEN 6 161 #define REG_CMATRIX_SIGN 0x58 162 163 164 #define REG_BRIGHT 0x55 /* Brightness */ 165 #define REG_CONTRAS 0x56 /* Contrast control */ 166 167 #define REG_GFIX 0x69 /* Fix gain control */ 168 169 #define REG_DBLV 0x6b /* PLL control an debugging */ 170 #define DBLV_BYPASS 0x00 /* Bypass PLL */ 171 #define DBLV_X4 0x01 /* clock x4 */ 172 #define DBLV_X6 0x10 /* clock x6 */ 173 #define DBLV_X8 0x11 /* clock x8 */ 174 175 #define REG_REG76 0x76 /* OV's name */ 176 #define R76_BLKPCOR 0x80 /* Black pixel correction enable */ 177 #define R76_WHTPCOR 0x40 /* White pixel correction enable */ 178 179 #define REG_RGB444 0x8c /* RGB 444 control */ 180 #define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */ 181 #define R444_RGBX 0x01 /* Empty nibble at end */ 182 183 #define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */ 184 #define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */ 185 186 #define REG_BD50MAX 0xa5 /* 50hz banding step limit */ 187 #define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */ 188 #define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */ 189 #define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */ 190 #define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */ 191 #define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */ 192 #define REG_BD60MAX 0xab /* 60hz banding step limit */ 193 194 enum ov7670_model { 195 MODEL_OV7670 = 0, 196 MODEL_OV7675, 197 }; 198 199 struct ov7670_win_size { 200 int width; 201 int height; 202 unsigned char com7_bit; 203 int hstart; /* Start/stop values for the camera. Note */ 204 int hstop; /* that they do not always make complete */ 205 int vstart; /* sense to humans, but evidently the sensor */ 206 int vstop; /* will do the right thing... */ 207 struct regval_list *regs; /* Regs to tweak */ 208 }; 209 210 struct ov7670_devtype { 211 /* formats supported for each model */ 212 struct ov7670_win_size *win_sizes; 213 unsigned int n_win_sizes; 214 /* callbacks for frame rate control */ 215 int (*set_framerate)(struct v4l2_subdev *, struct v4l2_fract *); 216 void (*get_framerate)(struct v4l2_subdev *, struct v4l2_fract *); 217 }; 218 219 /* 220 * Information we maintain about a known sensor. 221 */ 222 struct ov7670_format_struct; /* coming later */ 223 struct ov7670_info { 224 struct v4l2_subdev sd; 225 struct v4l2_ctrl_handler hdl; 226 struct { 227 /* gain cluster */ 228 struct v4l2_ctrl *auto_gain; 229 struct v4l2_ctrl *gain; 230 }; 231 struct { 232 /* exposure cluster */ 233 struct v4l2_ctrl *auto_exposure; 234 struct v4l2_ctrl *exposure; 235 }; 236 struct { 237 /* saturation/hue cluster */ 238 struct v4l2_ctrl *saturation; 239 struct v4l2_ctrl *hue; 240 }; 241 struct ov7670_format_struct *fmt; /* Current format */ 242 int min_width; /* Filter out smaller sizes */ 243 int min_height; /* Filter out smaller sizes */ 244 int clock_speed; /* External clock speed (MHz) */ 245 u8 clkrc; /* Clock divider value */ 246 bool use_smbus; /* Use smbus I/O instead of I2C */ 247 bool pll_bypass; 248 bool pclk_hb_disable; 249 const struct ov7670_devtype *devtype; /* Device specifics */ 250 }; 251 252 static inline struct ov7670_info *to_state(struct v4l2_subdev *sd) 253 { 254 return container_of(sd, struct ov7670_info, sd); 255 } 256 257 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) 258 { 259 return &container_of(ctrl->handler, struct ov7670_info, hdl)->sd; 260 } 261 262 263 264 /* 265 * The default register settings, as obtained from OmniVision. There 266 * is really no making sense of most of these - lots of "reserved" values 267 * and such. 268 * 269 * These settings give VGA YUYV. 270 */ 271 272 struct regval_list { 273 unsigned char reg_num; 274 unsigned char value; 275 }; 276 277 static struct regval_list ov7670_default_regs[] = { 278 { REG_COM7, COM7_RESET }, 279 /* 280 * Clock scale: 3 = 15fps 281 * 2 = 20fps 282 * 1 = 30fps 283 */ 284 { REG_CLKRC, 0x1 }, /* OV: clock scale (30 fps) */ 285 { REG_TSLB, 0x04 }, /* OV */ 286 { REG_COM7, 0 }, /* VGA */ 287 /* 288 * Set the hardware window. These values from OV don't entirely 289 * make sense - hstop is less than hstart. But they work... 290 */ 291 { REG_HSTART, 0x13 }, { REG_HSTOP, 0x01 }, 292 { REG_HREF, 0xb6 }, { REG_VSTART, 0x02 }, 293 { REG_VSTOP, 0x7a }, { REG_VREF, 0x0a }, 294 295 { REG_COM3, 0 }, { REG_COM14, 0 }, 296 /* Mystery scaling numbers */ 297 { 0x70, 0x3a }, { 0x71, 0x35 }, 298 { 0x72, 0x11 }, { 0x73, 0xf0 }, 299 { 0xa2, 0x02 }, { REG_COM10, 0x0 }, 300 301 /* Gamma curve values */ 302 { 0x7a, 0x20 }, { 0x7b, 0x10 }, 303 { 0x7c, 0x1e }, { 0x7d, 0x35 }, 304 { 0x7e, 0x5a }, { 0x7f, 0x69 }, 305 { 0x80, 0x76 }, { 0x81, 0x80 }, 306 { 0x82, 0x88 }, { 0x83, 0x8f }, 307 { 0x84, 0x96 }, { 0x85, 0xa3 }, 308 { 0x86, 0xaf }, { 0x87, 0xc4 }, 309 { 0x88, 0xd7 }, { 0x89, 0xe8 }, 310 311 /* AGC and AEC parameters. Note we start by disabling those features, 312 then turn them only after tweaking the values. */ 313 { REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_BFILT }, 314 { REG_GAIN, 0 }, { REG_AECH, 0 }, 315 { REG_COM4, 0x40 }, /* magic reserved bit */ 316 { REG_COM9, 0x18 }, /* 4x gain + magic rsvd bit */ 317 { REG_BD50MAX, 0x05 }, { REG_BD60MAX, 0x07 }, 318 { REG_AEW, 0x95 }, { REG_AEB, 0x33 }, 319 { REG_VPT, 0xe3 }, { REG_HAECC1, 0x78 }, 320 { REG_HAECC2, 0x68 }, { 0xa1, 0x03 }, /* magic */ 321 { REG_HAECC3, 0xd8 }, { REG_HAECC4, 0xd8 }, 322 { REG_HAECC5, 0xf0 }, { REG_HAECC6, 0x90 }, 323 { REG_HAECC7, 0x94 }, 324 { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC }, 325 326 /* Almost all of these are magic "reserved" values. */ 327 { REG_COM5, 0x61 }, { REG_COM6, 0x4b }, 328 { 0x16, 0x02 }, { REG_MVFP, 0x07 }, 329 { 0x21, 0x02 }, { 0x22, 0x91 }, 330 { 0x29, 0x07 }, { 0x33, 0x0b }, 331 { 0x35, 0x0b }, { 0x37, 0x1d }, 332 { 0x38, 0x71 }, { 0x39, 0x2a }, 333 { REG_COM12, 0x78 }, { 0x4d, 0x40 }, 334 { 0x4e, 0x20 }, { REG_GFIX, 0 }, 335 { 0x6b, 0x4a }, { 0x74, 0x10 }, 336 { 0x8d, 0x4f }, { 0x8e, 0 }, 337 { 0x8f, 0 }, { 0x90, 0 }, 338 { 0x91, 0 }, { 0x96, 0 }, 339 { 0x9a, 0 }, { 0xb0, 0x84 }, 340 { 0xb1, 0x0c }, { 0xb2, 0x0e }, 341 { 0xb3, 0x82 }, { 0xb8, 0x0a }, 342 343 /* More reserved magic, some of which tweaks white balance */ 344 { 0x43, 0x0a }, { 0x44, 0xf0 }, 345 { 0x45, 0x34 }, { 0x46, 0x58 }, 346 { 0x47, 0x28 }, { 0x48, 0x3a }, 347 { 0x59, 0x88 }, { 0x5a, 0x88 }, 348 { 0x5b, 0x44 }, { 0x5c, 0x67 }, 349 { 0x5d, 0x49 }, { 0x5e, 0x0e }, 350 { 0x6c, 0x0a }, { 0x6d, 0x55 }, 351 { 0x6e, 0x11 }, { 0x6f, 0x9f }, /* "9e for advance AWB" */ 352 { 0x6a, 0x40 }, { REG_BLUE, 0x40 }, 353 { REG_RED, 0x60 }, 354 { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC|COM8_AWB }, 355 356 /* Matrix coefficients */ 357 { 0x4f, 0x80 }, { 0x50, 0x80 }, 358 { 0x51, 0 }, { 0x52, 0x22 }, 359 { 0x53, 0x5e }, { 0x54, 0x80 }, 360 { 0x58, 0x9e }, 361 362 { REG_COM16, COM16_AWBGAIN }, { REG_EDGE, 0 }, 363 { 0x75, 0x05 }, { 0x76, 0xe1 }, 364 { 0x4c, 0 }, { 0x77, 0x01 }, 365 { REG_COM13, 0xc3 }, { 0x4b, 0x09 }, 366 { 0xc9, 0x60 }, { REG_COM16, 0x38 }, 367 { 0x56, 0x40 }, 368 369 { 0x34, 0x11 }, { REG_COM11, COM11_EXP|COM11_HZAUTO }, 370 { 0xa4, 0x88 }, { 0x96, 0 }, 371 { 0x97, 0x30 }, { 0x98, 0x20 }, 372 { 0x99, 0x30 }, { 0x9a, 0x84 }, 373 { 0x9b, 0x29 }, { 0x9c, 0x03 }, 374 { 0x9d, 0x4c }, { 0x9e, 0x3f }, 375 { 0x78, 0x04 }, 376 377 /* Extra-weird stuff. Some sort of multiplexor register */ 378 { 0x79, 0x01 }, { 0xc8, 0xf0 }, 379 { 0x79, 0x0f }, { 0xc8, 0x00 }, 380 { 0x79, 0x10 }, { 0xc8, 0x7e }, 381 { 0x79, 0x0a }, { 0xc8, 0x80 }, 382 { 0x79, 0x0b }, { 0xc8, 0x01 }, 383 { 0x79, 0x0c }, { 0xc8, 0x0f }, 384 { 0x79, 0x0d }, { 0xc8, 0x20 }, 385 { 0x79, 0x09 }, { 0xc8, 0x80 }, 386 { 0x79, 0x02 }, { 0xc8, 0xc0 }, 387 { 0x79, 0x03 }, { 0xc8, 0x40 }, 388 { 0x79, 0x05 }, { 0xc8, 0x30 }, 389 { 0x79, 0x26 }, 390 391 { 0xff, 0xff }, /* END MARKER */ 392 }; 393 394 395 /* 396 * Here we'll try to encapsulate the changes for just the output 397 * video format. 398 * 399 * RGB656 and YUV422 come from OV; RGB444 is homebrewed. 400 * 401 * IMPORTANT RULE: the first entry must be for COM7, see ov7670_s_fmt for why. 402 */ 403 404 405 static struct regval_list ov7670_fmt_yuv422[] = { 406 { REG_COM7, 0x0 }, /* Selects YUV mode */ 407 { REG_RGB444, 0 }, /* No RGB444 please */ 408 { REG_COM1, 0 }, /* CCIR601 */ 409 { REG_COM15, COM15_R00FF }, 410 { REG_COM9, 0x48 }, /* 32x gain ceiling; 0x8 is reserved bit */ 411 { 0x4f, 0x80 }, /* "matrix coefficient 1" */ 412 { 0x50, 0x80 }, /* "matrix coefficient 2" */ 413 { 0x51, 0 }, /* vb */ 414 { 0x52, 0x22 }, /* "matrix coefficient 4" */ 415 { 0x53, 0x5e }, /* "matrix coefficient 5" */ 416 { 0x54, 0x80 }, /* "matrix coefficient 6" */ 417 { REG_COM13, COM13_GAMMA|COM13_UVSAT }, 418 { 0xff, 0xff }, 419 }; 420 421 static struct regval_list ov7670_fmt_rgb565[] = { 422 { REG_COM7, COM7_RGB }, /* Selects RGB mode */ 423 { REG_RGB444, 0 }, /* No RGB444 please */ 424 { REG_COM1, 0x0 }, /* CCIR601 */ 425 { REG_COM15, COM15_RGB565 }, 426 { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */ 427 { 0x4f, 0xb3 }, /* "matrix coefficient 1" */ 428 { 0x50, 0xb3 }, /* "matrix coefficient 2" */ 429 { 0x51, 0 }, /* vb */ 430 { 0x52, 0x3d }, /* "matrix coefficient 4" */ 431 { 0x53, 0xa7 }, /* "matrix coefficient 5" */ 432 { 0x54, 0xe4 }, /* "matrix coefficient 6" */ 433 { REG_COM13, COM13_GAMMA|COM13_UVSAT }, 434 { 0xff, 0xff }, 435 }; 436 437 static struct regval_list ov7670_fmt_rgb444[] = { 438 { REG_COM7, COM7_RGB }, /* Selects RGB mode */ 439 { REG_RGB444, R444_ENABLE }, /* Enable xxxxrrrr ggggbbbb */ 440 { REG_COM1, 0x0 }, /* CCIR601 */ 441 { REG_COM15, COM15_R01FE|COM15_RGB565 }, /* Data range needed? */ 442 { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */ 443 { 0x4f, 0xb3 }, /* "matrix coefficient 1" */ 444 { 0x50, 0xb3 }, /* "matrix coefficient 2" */ 445 { 0x51, 0 }, /* vb */ 446 { 0x52, 0x3d }, /* "matrix coefficient 4" */ 447 { 0x53, 0xa7 }, /* "matrix coefficient 5" */ 448 { 0x54, 0xe4 }, /* "matrix coefficient 6" */ 449 { REG_COM13, COM13_GAMMA|COM13_UVSAT|0x2 }, /* Magic rsvd bit */ 450 { 0xff, 0xff }, 451 }; 452 453 static struct regval_list ov7670_fmt_raw[] = { 454 { REG_COM7, COM7_BAYER }, 455 { REG_COM13, 0x08 }, /* No gamma, magic rsvd bit */ 456 { REG_COM16, 0x3d }, /* Edge enhancement, denoise */ 457 { REG_REG76, 0xe1 }, /* Pix correction, magic rsvd */ 458 { 0xff, 0xff }, 459 }; 460 461 462 463 /* 464 * Low-level register I/O. 465 * 466 * Note that there are two versions of these. On the XO 1, the 467 * i2c controller only does SMBUS, so that's what we use. The 468 * ov7670 is not really an SMBUS device, though, so the communication 469 * is not always entirely reliable. 470 */ 471 static int ov7670_read_smbus(struct v4l2_subdev *sd, unsigned char reg, 472 unsigned char *value) 473 { 474 struct i2c_client *client = v4l2_get_subdevdata(sd); 475 int ret; 476 477 ret = i2c_smbus_read_byte_data(client, reg); 478 if (ret >= 0) { 479 *value = (unsigned char)ret; 480 ret = 0; 481 } 482 return ret; 483 } 484 485 486 static int ov7670_write_smbus(struct v4l2_subdev *sd, unsigned char reg, 487 unsigned char value) 488 { 489 struct i2c_client *client = v4l2_get_subdevdata(sd); 490 int ret = i2c_smbus_write_byte_data(client, reg, value); 491 492 if (reg == REG_COM7 && (value & COM7_RESET)) 493 msleep(5); /* Wait for reset to run */ 494 return ret; 495 } 496 497 /* 498 * On most platforms, we'd rather do straight i2c I/O. 499 */ 500 static int ov7670_read_i2c(struct v4l2_subdev *sd, unsigned char reg, 501 unsigned char *value) 502 { 503 struct i2c_client *client = v4l2_get_subdevdata(sd); 504 u8 data = reg; 505 struct i2c_msg msg; 506 int ret; 507 508 /* 509 * Send out the register address... 510 */ 511 msg.addr = client->addr; 512 msg.flags = 0; 513 msg.len = 1; 514 msg.buf = &data; 515 ret = i2c_transfer(client->adapter, &msg, 1); 516 if (ret < 0) { 517 printk(KERN_ERR "Error %d on register write\n", ret); 518 return ret; 519 } 520 /* 521 * ...then read back the result. 522 */ 523 msg.flags = I2C_M_RD; 524 ret = i2c_transfer(client->adapter, &msg, 1); 525 if (ret >= 0) { 526 *value = data; 527 ret = 0; 528 } 529 return ret; 530 } 531 532 533 static int ov7670_write_i2c(struct v4l2_subdev *sd, unsigned char reg, 534 unsigned char value) 535 { 536 struct i2c_client *client = v4l2_get_subdevdata(sd); 537 struct i2c_msg msg; 538 unsigned char data[2] = { reg, value }; 539 int ret; 540 541 msg.addr = client->addr; 542 msg.flags = 0; 543 msg.len = 2; 544 msg.buf = data; 545 ret = i2c_transfer(client->adapter, &msg, 1); 546 if (ret > 0) 547 ret = 0; 548 if (reg == REG_COM7 && (value & COM7_RESET)) 549 msleep(5); /* Wait for reset to run */ 550 return ret; 551 } 552 553 static int ov7670_read(struct v4l2_subdev *sd, unsigned char reg, 554 unsigned char *value) 555 { 556 struct ov7670_info *info = to_state(sd); 557 if (info->use_smbus) 558 return ov7670_read_smbus(sd, reg, value); 559 else 560 return ov7670_read_i2c(sd, reg, value); 561 } 562 563 static int ov7670_write(struct v4l2_subdev *sd, unsigned char reg, 564 unsigned char value) 565 { 566 struct ov7670_info *info = to_state(sd); 567 if (info->use_smbus) 568 return ov7670_write_smbus(sd, reg, value); 569 else 570 return ov7670_write_i2c(sd, reg, value); 571 } 572 573 /* 574 * Write a list of register settings; ff/ff stops the process. 575 */ 576 static int ov7670_write_array(struct v4l2_subdev *sd, struct regval_list *vals) 577 { 578 while (vals->reg_num != 0xff || vals->value != 0xff) { 579 int ret = ov7670_write(sd, vals->reg_num, vals->value); 580 if (ret < 0) 581 return ret; 582 vals++; 583 } 584 return 0; 585 } 586 587 588 /* 589 * Stuff that knows about the sensor. 590 */ 591 static int ov7670_reset(struct v4l2_subdev *sd, u32 val) 592 { 593 ov7670_write(sd, REG_COM7, COM7_RESET); 594 msleep(1); 595 return 0; 596 } 597 598 599 static int ov7670_init(struct v4l2_subdev *sd, u32 val) 600 { 601 return ov7670_write_array(sd, ov7670_default_regs); 602 } 603 604 605 606 static int ov7670_detect(struct v4l2_subdev *sd) 607 { 608 unsigned char v; 609 int ret; 610 611 ret = ov7670_init(sd, 0); 612 if (ret < 0) 613 return ret; 614 ret = ov7670_read(sd, REG_MIDH, &v); 615 if (ret < 0) 616 return ret; 617 if (v != 0x7f) /* OV manuf. id. */ 618 return -ENODEV; 619 ret = ov7670_read(sd, REG_MIDL, &v); 620 if (ret < 0) 621 return ret; 622 if (v != 0xa2) 623 return -ENODEV; 624 /* 625 * OK, we know we have an OmniVision chip...but which one? 626 */ 627 ret = ov7670_read(sd, REG_PID, &v); 628 if (ret < 0) 629 return ret; 630 if (v != 0x76) /* PID + VER = 0x76 / 0x73 */ 631 return -ENODEV; 632 ret = ov7670_read(sd, REG_VER, &v); 633 if (ret < 0) 634 return ret; 635 if (v != 0x73) /* PID + VER = 0x76 / 0x73 */ 636 return -ENODEV; 637 return 0; 638 } 639 640 641 /* 642 * Store information about the video data format. The color matrix 643 * is deeply tied into the format, so keep the relevant values here. 644 * The magic matrix numbers come from OmniVision. 645 */ 646 static struct ov7670_format_struct { 647 enum v4l2_mbus_pixelcode mbus_code; 648 enum v4l2_colorspace colorspace; 649 struct regval_list *regs; 650 int cmatrix[CMATRIX_LEN]; 651 } ov7670_formats[] = { 652 { 653 .mbus_code = V4L2_MBUS_FMT_YUYV8_2X8, 654 .colorspace = V4L2_COLORSPACE_JPEG, 655 .regs = ov7670_fmt_yuv422, 656 .cmatrix = { 128, -128, 0, -34, -94, 128 }, 657 }, 658 { 659 .mbus_code = V4L2_MBUS_FMT_RGB444_2X8_PADHI_LE, 660 .colorspace = V4L2_COLORSPACE_SRGB, 661 .regs = ov7670_fmt_rgb444, 662 .cmatrix = { 179, -179, 0, -61, -176, 228 }, 663 }, 664 { 665 .mbus_code = V4L2_MBUS_FMT_RGB565_2X8_LE, 666 .colorspace = V4L2_COLORSPACE_SRGB, 667 .regs = ov7670_fmt_rgb565, 668 .cmatrix = { 179, -179, 0, -61, -176, 228 }, 669 }, 670 { 671 .mbus_code = V4L2_MBUS_FMT_SBGGR8_1X8, 672 .colorspace = V4L2_COLORSPACE_SRGB, 673 .regs = ov7670_fmt_raw, 674 .cmatrix = { 0, 0, 0, 0, 0, 0 }, 675 }, 676 }; 677 #define N_OV7670_FMTS ARRAY_SIZE(ov7670_formats) 678 679 680 /* 681 * Then there is the issue of window sizes. Try to capture the info here. 682 */ 683 684 /* 685 * QCIF mode is done (by OV) in a very strange way - it actually looks like 686 * VGA with weird scaling options - they do *not* use the canned QCIF mode 687 * which is allegedly provided by the sensor. So here's the weird register 688 * settings. 689 */ 690 static struct regval_list ov7670_qcif_regs[] = { 691 { REG_COM3, COM3_SCALEEN|COM3_DCWEN }, 692 { REG_COM3, COM3_DCWEN }, 693 { REG_COM14, COM14_DCWEN | 0x01}, 694 { 0x73, 0xf1 }, 695 { 0xa2, 0x52 }, 696 { 0x7b, 0x1c }, 697 { 0x7c, 0x28 }, 698 { 0x7d, 0x3c }, 699 { 0x7f, 0x69 }, 700 { REG_COM9, 0x38 }, 701 { 0xa1, 0x0b }, 702 { 0x74, 0x19 }, 703 { 0x9a, 0x80 }, 704 { 0x43, 0x14 }, 705 { REG_COM13, 0xc0 }, 706 { 0xff, 0xff }, 707 }; 708 709 static struct ov7670_win_size ov7670_win_sizes[] = { 710 /* VGA */ 711 { 712 .width = VGA_WIDTH, 713 .height = VGA_HEIGHT, 714 .com7_bit = COM7_FMT_VGA, 715 .hstart = 158, /* These values from */ 716 .hstop = 14, /* Omnivision */ 717 .vstart = 10, 718 .vstop = 490, 719 .regs = NULL, 720 }, 721 /* CIF */ 722 { 723 .width = CIF_WIDTH, 724 .height = CIF_HEIGHT, 725 .com7_bit = COM7_FMT_CIF, 726 .hstart = 170, /* Empirically determined */ 727 .hstop = 90, 728 .vstart = 14, 729 .vstop = 494, 730 .regs = NULL, 731 }, 732 /* QVGA */ 733 { 734 .width = QVGA_WIDTH, 735 .height = QVGA_HEIGHT, 736 .com7_bit = COM7_FMT_QVGA, 737 .hstart = 168, /* Empirically determined */ 738 .hstop = 24, 739 .vstart = 12, 740 .vstop = 492, 741 .regs = NULL, 742 }, 743 /* QCIF */ 744 { 745 .width = QCIF_WIDTH, 746 .height = QCIF_HEIGHT, 747 .com7_bit = COM7_FMT_VGA, /* see comment above */ 748 .hstart = 456, /* Empirically determined */ 749 .hstop = 24, 750 .vstart = 14, 751 .vstop = 494, 752 .regs = ov7670_qcif_regs, 753 } 754 }; 755 756 static struct ov7670_win_size ov7675_win_sizes[] = { 757 /* 758 * Currently, only VGA is supported. Theoretically it could be possible 759 * to support CIF, QVGA and QCIF too. Taking values for ov7670 as a 760 * base and tweak them empirically could be required. 761 */ 762 { 763 .width = VGA_WIDTH, 764 .height = VGA_HEIGHT, 765 .com7_bit = COM7_FMT_VGA, 766 .hstart = 158, /* These values from */ 767 .hstop = 14, /* Omnivision */ 768 .vstart = 14, /* Empirically determined */ 769 .vstop = 494, 770 .regs = NULL, 771 } 772 }; 773 774 static void ov7675_get_framerate(struct v4l2_subdev *sd, 775 struct v4l2_fract *tpf) 776 { 777 struct ov7670_info *info = to_state(sd); 778 u32 clkrc = info->clkrc; 779 int pll_factor; 780 781 if (info->pll_bypass) 782 pll_factor = 1; 783 else 784 pll_factor = PLL_FACTOR; 785 786 clkrc++; 787 if (info->fmt->mbus_code == V4L2_MBUS_FMT_SBGGR8_1X8) 788 clkrc = (clkrc >> 1); 789 790 tpf->numerator = 1; 791 tpf->denominator = (5 * pll_factor * info->clock_speed) / 792 (4 * clkrc); 793 } 794 795 static int ov7675_set_framerate(struct v4l2_subdev *sd, 796 struct v4l2_fract *tpf) 797 { 798 struct ov7670_info *info = to_state(sd); 799 u32 clkrc; 800 int pll_factor; 801 int ret; 802 803 /* 804 * The formula is fps = 5/4*pixclk for YUV/RGB and 805 * fps = 5/2*pixclk for RAW. 806 * 807 * pixclk = clock_speed / (clkrc + 1) * PLLfactor 808 * 809 */ 810 if (info->pll_bypass) { 811 pll_factor = 1; 812 ret = ov7670_write(sd, REG_DBLV, DBLV_BYPASS); 813 } else { 814 pll_factor = PLL_FACTOR; 815 ret = ov7670_write(sd, REG_DBLV, DBLV_X4); 816 } 817 if (ret < 0) 818 return ret; 819 820 if (tpf->numerator == 0 || tpf->denominator == 0) { 821 clkrc = 0; 822 } else { 823 clkrc = (5 * pll_factor * info->clock_speed * tpf->numerator) / 824 (4 * tpf->denominator); 825 if (info->fmt->mbus_code == V4L2_MBUS_FMT_SBGGR8_1X8) 826 clkrc = (clkrc << 1); 827 clkrc--; 828 } 829 830 /* 831 * The datasheet claims that clkrc = 0 will divide the input clock by 1 832 * but we've checked with an oscilloscope that it divides by 2 instead. 833 * So, if clkrc = 0 just bypass the divider. 834 */ 835 if (clkrc <= 0) 836 clkrc = CLK_EXT; 837 else if (clkrc > CLK_SCALE) 838 clkrc = CLK_SCALE; 839 info->clkrc = clkrc; 840 841 /* Recalculate frame rate */ 842 ov7675_get_framerate(sd, tpf); 843 844 ret = ov7670_write(sd, REG_CLKRC, info->clkrc); 845 if (ret < 0) 846 return ret; 847 848 return ov7670_write(sd, REG_DBLV, DBLV_X4); 849 } 850 851 static void ov7670_get_framerate_legacy(struct v4l2_subdev *sd, 852 struct v4l2_fract *tpf) 853 { 854 struct ov7670_info *info = to_state(sd); 855 856 tpf->numerator = 1; 857 tpf->denominator = info->clock_speed; 858 if ((info->clkrc & CLK_EXT) == 0 && (info->clkrc & CLK_SCALE) > 1) 859 tpf->denominator /= (info->clkrc & CLK_SCALE); 860 } 861 862 static int ov7670_set_framerate_legacy(struct v4l2_subdev *sd, 863 struct v4l2_fract *tpf) 864 { 865 struct ov7670_info *info = to_state(sd); 866 int div; 867 868 if (tpf->numerator == 0 || tpf->denominator == 0) 869 div = 1; /* Reset to full rate */ 870 else 871 div = (tpf->numerator * info->clock_speed) / tpf->denominator; 872 if (div == 0) 873 div = 1; 874 else if (div > CLK_SCALE) 875 div = CLK_SCALE; 876 info->clkrc = (info->clkrc & 0x80) | div; 877 tpf->numerator = 1; 878 tpf->denominator = info->clock_speed / div; 879 return ov7670_write(sd, REG_CLKRC, info->clkrc); 880 } 881 882 /* 883 * Store a set of start/stop values into the camera. 884 */ 885 static int ov7670_set_hw(struct v4l2_subdev *sd, int hstart, int hstop, 886 int vstart, int vstop) 887 { 888 int ret; 889 unsigned char v; 890 /* 891 * Horizontal: 11 bits, top 8 live in hstart and hstop. Bottom 3 of 892 * hstart are in href[2:0], bottom 3 of hstop in href[5:3]. There is 893 * a mystery "edge offset" value in the top two bits of href. 894 */ 895 ret = ov7670_write(sd, REG_HSTART, (hstart >> 3) & 0xff); 896 ret += ov7670_write(sd, REG_HSTOP, (hstop >> 3) & 0xff); 897 ret += ov7670_read(sd, REG_HREF, &v); 898 v = (v & 0xc0) | ((hstop & 0x7) << 3) | (hstart & 0x7); 899 msleep(10); 900 ret += ov7670_write(sd, REG_HREF, v); 901 /* 902 * Vertical: similar arrangement, but only 10 bits. 903 */ 904 ret += ov7670_write(sd, REG_VSTART, (vstart >> 2) & 0xff); 905 ret += ov7670_write(sd, REG_VSTOP, (vstop >> 2) & 0xff); 906 ret += ov7670_read(sd, REG_VREF, &v); 907 v = (v & 0xf0) | ((vstop & 0x3) << 2) | (vstart & 0x3); 908 msleep(10); 909 ret += ov7670_write(sd, REG_VREF, v); 910 return ret; 911 } 912 913 914 static int ov7670_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned index, 915 enum v4l2_mbus_pixelcode *code) 916 { 917 if (index >= N_OV7670_FMTS) 918 return -EINVAL; 919 920 *code = ov7670_formats[index].mbus_code; 921 return 0; 922 } 923 924 static int ov7670_try_fmt_internal(struct v4l2_subdev *sd, 925 struct v4l2_mbus_framefmt *fmt, 926 struct ov7670_format_struct **ret_fmt, 927 struct ov7670_win_size **ret_wsize) 928 { 929 int index, i; 930 struct ov7670_win_size *wsize; 931 struct ov7670_info *info = to_state(sd); 932 unsigned int n_win_sizes = info->devtype->n_win_sizes; 933 unsigned int win_sizes_limit = n_win_sizes; 934 935 for (index = 0; index < N_OV7670_FMTS; index++) 936 if (ov7670_formats[index].mbus_code == fmt->code) 937 break; 938 if (index >= N_OV7670_FMTS) { 939 /* default to first format */ 940 index = 0; 941 fmt->code = ov7670_formats[0].mbus_code; 942 } 943 if (ret_fmt != NULL) 944 *ret_fmt = ov7670_formats + index; 945 /* 946 * Fields: the OV devices claim to be progressive. 947 */ 948 fmt->field = V4L2_FIELD_NONE; 949 950 /* 951 * Don't consider values that don't match min_height and min_width 952 * constraints. 953 */ 954 if (info->min_width || info->min_height) 955 for (i = 0; i < n_win_sizes; i++) { 956 wsize = info->devtype->win_sizes + i; 957 958 if (wsize->width < info->min_width || 959 wsize->height < info->min_height) { 960 win_sizes_limit = i; 961 break; 962 } 963 } 964 /* 965 * Round requested image size down to the nearest 966 * we support, but not below the smallest. 967 */ 968 for (wsize = info->devtype->win_sizes; 969 wsize < info->devtype->win_sizes + win_sizes_limit; wsize++) 970 if (fmt->width >= wsize->width && fmt->height >= wsize->height) 971 break; 972 if (wsize >= info->devtype->win_sizes + win_sizes_limit) 973 wsize--; /* Take the smallest one */ 974 if (ret_wsize != NULL) 975 *ret_wsize = wsize; 976 /* 977 * Note the size we'll actually handle. 978 */ 979 fmt->width = wsize->width; 980 fmt->height = wsize->height; 981 fmt->colorspace = ov7670_formats[index].colorspace; 982 return 0; 983 } 984 985 static int ov7670_try_mbus_fmt(struct v4l2_subdev *sd, 986 struct v4l2_mbus_framefmt *fmt) 987 { 988 return ov7670_try_fmt_internal(sd, fmt, NULL, NULL); 989 } 990 991 /* 992 * Set a format. 993 */ 994 static int ov7670_s_mbus_fmt(struct v4l2_subdev *sd, 995 struct v4l2_mbus_framefmt *fmt) 996 { 997 struct ov7670_format_struct *ovfmt; 998 struct ov7670_win_size *wsize; 999 struct ov7670_info *info = to_state(sd); 1000 unsigned char com7; 1001 int ret; 1002 1003 ret = ov7670_try_fmt_internal(sd, fmt, &ovfmt, &wsize); 1004 1005 if (ret) 1006 return ret; 1007 /* 1008 * COM7 is a pain in the ass, it doesn't like to be read then 1009 * quickly written afterward. But we have everything we need 1010 * to set it absolutely here, as long as the format-specific 1011 * register sets list it first. 1012 */ 1013 com7 = ovfmt->regs[0].value; 1014 com7 |= wsize->com7_bit; 1015 ov7670_write(sd, REG_COM7, com7); 1016 /* 1017 * Now write the rest of the array. Also store start/stops 1018 */ 1019 ov7670_write_array(sd, ovfmt->regs + 1); 1020 ov7670_set_hw(sd, wsize->hstart, wsize->hstop, wsize->vstart, 1021 wsize->vstop); 1022 ret = 0; 1023 if (wsize->regs) 1024 ret = ov7670_write_array(sd, wsize->regs); 1025 info->fmt = ovfmt; 1026 1027 /* 1028 * If we're running RGB565, we must rewrite clkrc after setting 1029 * the other parameters or the image looks poor. If we're *not* 1030 * doing RGB565, we must not rewrite clkrc or the image looks 1031 * *really* poor. 1032 * 1033 * (Update) Now that we retain clkrc state, we should be able 1034 * to write it unconditionally, and that will make the frame 1035 * rate persistent too. 1036 */ 1037 if (ret == 0) 1038 ret = ov7670_write(sd, REG_CLKRC, info->clkrc); 1039 return 0; 1040 } 1041 1042 /* 1043 * Implement G/S_PARM. There is a "high quality" mode we could try 1044 * to do someday; for now, we just do the frame rate tweak. 1045 */ 1046 static int ov7670_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms) 1047 { 1048 struct v4l2_captureparm *cp = &parms->parm.capture; 1049 struct ov7670_info *info = to_state(sd); 1050 1051 if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) 1052 return -EINVAL; 1053 1054 memset(cp, 0, sizeof(struct v4l2_captureparm)); 1055 cp->capability = V4L2_CAP_TIMEPERFRAME; 1056 info->devtype->get_framerate(sd, &cp->timeperframe); 1057 1058 return 0; 1059 } 1060 1061 static int ov7670_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms) 1062 { 1063 struct v4l2_captureparm *cp = &parms->parm.capture; 1064 struct v4l2_fract *tpf = &cp->timeperframe; 1065 struct ov7670_info *info = to_state(sd); 1066 1067 if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) 1068 return -EINVAL; 1069 if (cp->extendedmode != 0) 1070 return -EINVAL; 1071 1072 return info->devtype->set_framerate(sd, tpf); 1073 } 1074 1075 1076 /* 1077 * Frame intervals. Since frame rates are controlled with the clock 1078 * divider, we can only do 30/n for integer n values. So no continuous 1079 * or stepwise options. Here we just pick a handful of logical values. 1080 */ 1081 1082 static int ov7670_frame_rates[] = { 30, 15, 10, 5, 1 }; 1083 1084 static int ov7670_enum_frameintervals(struct v4l2_subdev *sd, 1085 struct v4l2_frmivalenum *interval) 1086 { 1087 if (interval->index >= ARRAY_SIZE(ov7670_frame_rates)) 1088 return -EINVAL; 1089 interval->type = V4L2_FRMIVAL_TYPE_DISCRETE; 1090 interval->discrete.numerator = 1; 1091 interval->discrete.denominator = ov7670_frame_rates[interval->index]; 1092 return 0; 1093 } 1094 1095 /* 1096 * Frame size enumeration 1097 */ 1098 static int ov7670_enum_framesizes(struct v4l2_subdev *sd, 1099 struct v4l2_frmsizeenum *fsize) 1100 { 1101 struct ov7670_info *info = to_state(sd); 1102 int i; 1103 int num_valid = -1; 1104 __u32 index = fsize->index; 1105 unsigned int n_win_sizes = info->devtype->n_win_sizes; 1106 1107 /* 1108 * If a minimum width/height was requested, filter out the capture 1109 * windows that fall outside that. 1110 */ 1111 for (i = 0; i < n_win_sizes; i++) { 1112 struct ov7670_win_size *win = &info->devtype->win_sizes[i]; 1113 if (info->min_width && win->width < info->min_width) 1114 continue; 1115 if (info->min_height && win->height < info->min_height) 1116 continue; 1117 if (index == ++num_valid) { 1118 fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE; 1119 fsize->discrete.width = win->width; 1120 fsize->discrete.height = win->height; 1121 return 0; 1122 } 1123 } 1124 1125 return -EINVAL; 1126 } 1127 1128 /* 1129 * Code for dealing with controls. 1130 */ 1131 1132 static int ov7670_store_cmatrix(struct v4l2_subdev *sd, 1133 int matrix[CMATRIX_LEN]) 1134 { 1135 int i, ret; 1136 unsigned char signbits = 0; 1137 1138 /* 1139 * Weird crap seems to exist in the upper part of 1140 * the sign bits register, so let's preserve it. 1141 */ 1142 ret = ov7670_read(sd, REG_CMATRIX_SIGN, &signbits); 1143 signbits &= 0xc0; 1144 1145 for (i = 0; i < CMATRIX_LEN; i++) { 1146 unsigned char raw; 1147 1148 if (matrix[i] < 0) { 1149 signbits |= (1 << i); 1150 if (matrix[i] < -255) 1151 raw = 0xff; 1152 else 1153 raw = (-1 * matrix[i]) & 0xff; 1154 } 1155 else { 1156 if (matrix[i] > 255) 1157 raw = 0xff; 1158 else 1159 raw = matrix[i] & 0xff; 1160 } 1161 ret += ov7670_write(sd, REG_CMATRIX_BASE + i, raw); 1162 } 1163 ret += ov7670_write(sd, REG_CMATRIX_SIGN, signbits); 1164 return ret; 1165 } 1166 1167 1168 /* 1169 * Hue also requires messing with the color matrix. It also requires 1170 * trig functions, which tend not to be well supported in the kernel. 1171 * So here is a simple table of sine values, 0-90 degrees, in steps 1172 * of five degrees. Values are multiplied by 1000. 1173 * 1174 * The following naive approximate trig functions require an argument 1175 * carefully limited to -180 <= theta <= 180. 1176 */ 1177 #define SIN_STEP 5 1178 static const int ov7670_sin_table[] = { 1179 0, 87, 173, 258, 342, 422, 1180 499, 573, 642, 707, 766, 819, 1181 866, 906, 939, 965, 984, 996, 1182 1000 1183 }; 1184 1185 static int ov7670_sine(int theta) 1186 { 1187 int chs = 1; 1188 int sine; 1189 1190 if (theta < 0) { 1191 theta = -theta; 1192 chs = -1; 1193 } 1194 if (theta <= 90) 1195 sine = ov7670_sin_table[theta/SIN_STEP]; 1196 else { 1197 theta -= 90; 1198 sine = 1000 - ov7670_sin_table[theta/SIN_STEP]; 1199 } 1200 return sine*chs; 1201 } 1202 1203 static int ov7670_cosine(int theta) 1204 { 1205 theta = 90 - theta; 1206 if (theta > 180) 1207 theta -= 360; 1208 else if (theta < -180) 1209 theta += 360; 1210 return ov7670_sine(theta); 1211 } 1212 1213 1214 1215 1216 static void ov7670_calc_cmatrix(struct ov7670_info *info, 1217 int matrix[CMATRIX_LEN], int sat, int hue) 1218 { 1219 int i; 1220 /* 1221 * Apply the current saturation setting first. 1222 */ 1223 for (i = 0; i < CMATRIX_LEN; i++) 1224 matrix[i] = (info->fmt->cmatrix[i] * sat) >> 7; 1225 /* 1226 * Then, if need be, rotate the hue value. 1227 */ 1228 if (hue != 0) { 1229 int sinth, costh, tmpmatrix[CMATRIX_LEN]; 1230 1231 memcpy(tmpmatrix, matrix, CMATRIX_LEN*sizeof(int)); 1232 sinth = ov7670_sine(hue); 1233 costh = ov7670_cosine(hue); 1234 1235 matrix[0] = (matrix[3]*sinth + matrix[0]*costh)/1000; 1236 matrix[1] = (matrix[4]*sinth + matrix[1]*costh)/1000; 1237 matrix[2] = (matrix[5]*sinth + matrix[2]*costh)/1000; 1238 matrix[3] = (matrix[3]*costh - matrix[0]*sinth)/1000; 1239 matrix[4] = (matrix[4]*costh - matrix[1]*sinth)/1000; 1240 matrix[5] = (matrix[5]*costh - matrix[2]*sinth)/1000; 1241 } 1242 } 1243 1244 1245 1246 static int ov7670_s_sat_hue(struct v4l2_subdev *sd, int sat, int hue) 1247 { 1248 struct ov7670_info *info = to_state(sd); 1249 int matrix[CMATRIX_LEN]; 1250 int ret; 1251 1252 ov7670_calc_cmatrix(info, matrix, sat, hue); 1253 ret = ov7670_store_cmatrix(sd, matrix); 1254 return ret; 1255 } 1256 1257 1258 /* 1259 * Some weird registers seem to store values in a sign/magnitude format! 1260 */ 1261 1262 static unsigned char ov7670_abs_to_sm(unsigned char v) 1263 { 1264 if (v > 127) 1265 return v & 0x7f; 1266 return (128 - v) | 0x80; 1267 } 1268 1269 static int ov7670_s_brightness(struct v4l2_subdev *sd, int value) 1270 { 1271 unsigned char com8 = 0, v; 1272 int ret; 1273 1274 ov7670_read(sd, REG_COM8, &com8); 1275 com8 &= ~COM8_AEC; 1276 ov7670_write(sd, REG_COM8, com8); 1277 v = ov7670_abs_to_sm(value); 1278 ret = ov7670_write(sd, REG_BRIGHT, v); 1279 return ret; 1280 } 1281 1282 static int ov7670_s_contrast(struct v4l2_subdev *sd, int value) 1283 { 1284 return ov7670_write(sd, REG_CONTRAS, (unsigned char) value); 1285 } 1286 1287 static int ov7670_s_hflip(struct v4l2_subdev *sd, int value) 1288 { 1289 unsigned char v = 0; 1290 int ret; 1291 1292 ret = ov7670_read(sd, REG_MVFP, &v); 1293 if (value) 1294 v |= MVFP_MIRROR; 1295 else 1296 v &= ~MVFP_MIRROR; 1297 msleep(10); /* FIXME */ 1298 ret += ov7670_write(sd, REG_MVFP, v); 1299 return ret; 1300 } 1301 1302 static int ov7670_s_vflip(struct v4l2_subdev *sd, int value) 1303 { 1304 unsigned char v = 0; 1305 int ret; 1306 1307 ret = ov7670_read(sd, REG_MVFP, &v); 1308 if (value) 1309 v |= MVFP_FLIP; 1310 else 1311 v &= ~MVFP_FLIP; 1312 msleep(10); /* FIXME */ 1313 ret += ov7670_write(sd, REG_MVFP, v); 1314 return ret; 1315 } 1316 1317 /* 1318 * GAIN is split between REG_GAIN and REG_VREF[7:6]. If one believes 1319 * the data sheet, the VREF parts should be the most significant, but 1320 * experience shows otherwise. There seems to be little value in 1321 * messing with the VREF bits, so we leave them alone. 1322 */ 1323 static int ov7670_g_gain(struct v4l2_subdev *sd, __s32 *value) 1324 { 1325 int ret; 1326 unsigned char gain; 1327 1328 ret = ov7670_read(sd, REG_GAIN, &gain); 1329 *value = gain; 1330 return ret; 1331 } 1332 1333 static int ov7670_s_gain(struct v4l2_subdev *sd, int value) 1334 { 1335 int ret; 1336 unsigned char com8; 1337 1338 ret = ov7670_write(sd, REG_GAIN, value & 0xff); 1339 /* Have to turn off AGC as well */ 1340 if (ret == 0) { 1341 ret = ov7670_read(sd, REG_COM8, &com8); 1342 ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AGC); 1343 } 1344 return ret; 1345 } 1346 1347 /* 1348 * Tweak autogain. 1349 */ 1350 static int ov7670_s_autogain(struct v4l2_subdev *sd, int value) 1351 { 1352 int ret; 1353 unsigned char com8; 1354 1355 ret = ov7670_read(sd, REG_COM8, &com8); 1356 if (ret == 0) { 1357 if (value) 1358 com8 |= COM8_AGC; 1359 else 1360 com8 &= ~COM8_AGC; 1361 ret = ov7670_write(sd, REG_COM8, com8); 1362 } 1363 return ret; 1364 } 1365 1366 static int ov7670_s_exp(struct v4l2_subdev *sd, int value) 1367 { 1368 int ret; 1369 unsigned char com1, com8, aech, aechh; 1370 1371 ret = ov7670_read(sd, REG_COM1, &com1) + 1372 ov7670_read(sd, REG_COM8, &com8); 1373 ov7670_read(sd, REG_AECHH, &aechh); 1374 if (ret) 1375 return ret; 1376 1377 com1 = (com1 & 0xfc) | (value & 0x03); 1378 aech = (value >> 2) & 0xff; 1379 aechh = (aechh & 0xc0) | ((value >> 10) & 0x3f); 1380 ret = ov7670_write(sd, REG_COM1, com1) + 1381 ov7670_write(sd, REG_AECH, aech) + 1382 ov7670_write(sd, REG_AECHH, aechh); 1383 /* Have to turn off AEC as well */ 1384 if (ret == 0) 1385 ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AEC); 1386 return ret; 1387 } 1388 1389 /* 1390 * Tweak autoexposure. 1391 */ 1392 static int ov7670_s_autoexp(struct v4l2_subdev *sd, 1393 enum v4l2_exposure_auto_type value) 1394 { 1395 int ret; 1396 unsigned char com8; 1397 1398 ret = ov7670_read(sd, REG_COM8, &com8); 1399 if (ret == 0) { 1400 if (value == V4L2_EXPOSURE_AUTO) 1401 com8 |= COM8_AEC; 1402 else 1403 com8 &= ~COM8_AEC; 1404 ret = ov7670_write(sd, REG_COM8, com8); 1405 } 1406 return ret; 1407 } 1408 1409 1410 static int ov7670_g_volatile_ctrl(struct v4l2_ctrl *ctrl) 1411 { 1412 struct v4l2_subdev *sd = to_sd(ctrl); 1413 struct ov7670_info *info = to_state(sd); 1414 1415 switch (ctrl->id) { 1416 case V4L2_CID_AUTOGAIN: 1417 return ov7670_g_gain(sd, &info->gain->val); 1418 } 1419 return -EINVAL; 1420 } 1421 1422 static int ov7670_s_ctrl(struct v4l2_ctrl *ctrl) 1423 { 1424 struct v4l2_subdev *sd = to_sd(ctrl); 1425 struct ov7670_info *info = to_state(sd); 1426 1427 switch (ctrl->id) { 1428 case V4L2_CID_BRIGHTNESS: 1429 return ov7670_s_brightness(sd, ctrl->val); 1430 case V4L2_CID_CONTRAST: 1431 return ov7670_s_contrast(sd, ctrl->val); 1432 case V4L2_CID_SATURATION: 1433 return ov7670_s_sat_hue(sd, 1434 info->saturation->val, info->hue->val); 1435 case V4L2_CID_VFLIP: 1436 return ov7670_s_vflip(sd, ctrl->val); 1437 case V4L2_CID_HFLIP: 1438 return ov7670_s_hflip(sd, ctrl->val); 1439 case V4L2_CID_AUTOGAIN: 1440 /* Only set manual gain if auto gain is not explicitly 1441 turned on. */ 1442 if (!ctrl->val) { 1443 /* ov7670_s_gain turns off auto gain */ 1444 return ov7670_s_gain(sd, info->gain->val); 1445 } 1446 return ov7670_s_autogain(sd, ctrl->val); 1447 case V4L2_CID_EXPOSURE_AUTO: 1448 /* Only set manual exposure if auto exposure is not explicitly 1449 turned on. */ 1450 if (ctrl->val == V4L2_EXPOSURE_MANUAL) { 1451 /* ov7670_s_exp turns off auto exposure */ 1452 return ov7670_s_exp(sd, info->exposure->val); 1453 } 1454 return ov7670_s_autoexp(sd, ctrl->val); 1455 } 1456 return -EINVAL; 1457 } 1458 1459 static const struct v4l2_ctrl_ops ov7670_ctrl_ops = { 1460 .s_ctrl = ov7670_s_ctrl, 1461 .g_volatile_ctrl = ov7670_g_volatile_ctrl, 1462 }; 1463 1464 #ifdef CONFIG_VIDEO_ADV_DEBUG 1465 static int ov7670_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) 1466 { 1467 unsigned char val = 0; 1468 int ret; 1469 1470 ret = ov7670_read(sd, reg->reg & 0xff, &val); 1471 reg->val = val; 1472 reg->size = 1; 1473 return ret; 1474 } 1475 1476 static int ov7670_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg) 1477 { 1478 ov7670_write(sd, reg->reg & 0xff, reg->val & 0xff); 1479 return 0; 1480 } 1481 #endif 1482 1483 /* ----------------------------------------------------------------------- */ 1484 1485 static const struct v4l2_subdev_core_ops ov7670_core_ops = { 1486 .reset = ov7670_reset, 1487 .init = ov7670_init, 1488 #ifdef CONFIG_VIDEO_ADV_DEBUG 1489 .g_register = ov7670_g_register, 1490 .s_register = ov7670_s_register, 1491 #endif 1492 }; 1493 1494 static const struct v4l2_subdev_video_ops ov7670_video_ops = { 1495 .enum_mbus_fmt = ov7670_enum_mbus_fmt, 1496 .try_mbus_fmt = ov7670_try_mbus_fmt, 1497 .s_mbus_fmt = ov7670_s_mbus_fmt, 1498 .s_parm = ov7670_s_parm, 1499 .g_parm = ov7670_g_parm, 1500 .enum_frameintervals = ov7670_enum_frameintervals, 1501 .enum_framesizes = ov7670_enum_framesizes, 1502 }; 1503 1504 static const struct v4l2_subdev_ops ov7670_ops = { 1505 .core = &ov7670_core_ops, 1506 .video = &ov7670_video_ops, 1507 }; 1508 1509 /* ----------------------------------------------------------------------- */ 1510 1511 static const struct ov7670_devtype ov7670_devdata[] = { 1512 [MODEL_OV7670] = { 1513 .win_sizes = ov7670_win_sizes, 1514 .n_win_sizes = ARRAY_SIZE(ov7670_win_sizes), 1515 .set_framerate = ov7670_set_framerate_legacy, 1516 .get_framerate = ov7670_get_framerate_legacy, 1517 }, 1518 [MODEL_OV7675] = { 1519 .win_sizes = ov7675_win_sizes, 1520 .n_win_sizes = ARRAY_SIZE(ov7675_win_sizes), 1521 .set_framerate = ov7675_set_framerate, 1522 .get_framerate = ov7675_get_framerate, 1523 }, 1524 }; 1525 1526 static int ov7670_probe(struct i2c_client *client, 1527 const struct i2c_device_id *id) 1528 { 1529 struct v4l2_fract tpf; 1530 struct v4l2_subdev *sd; 1531 struct ov7670_info *info; 1532 int ret; 1533 1534 info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL); 1535 if (info == NULL) 1536 return -ENOMEM; 1537 sd = &info->sd; 1538 v4l2_i2c_subdev_init(sd, client, &ov7670_ops); 1539 1540 info->clock_speed = 30; /* default: a guess */ 1541 if (client->dev.platform_data) { 1542 struct ov7670_config *config = client->dev.platform_data; 1543 1544 /* 1545 * Must apply configuration before initializing device, because it 1546 * selects I/O method. 1547 */ 1548 info->min_width = config->min_width; 1549 info->min_height = config->min_height; 1550 info->use_smbus = config->use_smbus; 1551 1552 if (config->clock_speed) 1553 info->clock_speed = config->clock_speed; 1554 1555 /* 1556 * It should be allowed for ov7670 too when it is migrated to 1557 * the new frame rate formula. 1558 */ 1559 if (config->pll_bypass && id->driver_data != MODEL_OV7670) 1560 info->pll_bypass = true; 1561 1562 if (config->pclk_hb_disable) 1563 info->pclk_hb_disable = true; 1564 } 1565 1566 /* Make sure it's an ov7670 */ 1567 ret = ov7670_detect(sd); 1568 if (ret) { 1569 v4l_dbg(1, debug, client, 1570 "chip found @ 0x%x (%s) is not an ov7670 chip.\n", 1571 client->addr << 1, client->adapter->name); 1572 return ret; 1573 } 1574 v4l_info(client, "chip found @ 0x%02x (%s)\n", 1575 client->addr << 1, client->adapter->name); 1576 1577 info->devtype = &ov7670_devdata[id->driver_data]; 1578 info->fmt = &ov7670_formats[0]; 1579 info->clkrc = 0; 1580 1581 /* Set default frame rate to 30 fps */ 1582 tpf.numerator = 1; 1583 tpf.denominator = 30; 1584 info->devtype->set_framerate(sd, &tpf); 1585 1586 if (info->pclk_hb_disable) 1587 ov7670_write(sd, REG_COM10, COM10_PCLK_HB); 1588 1589 v4l2_ctrl_handler_init(&info->hdl, 10); 1590 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1591 V4L2_CID_BRIGHTNESS, 0, 255, 1, 128); 1592 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1593 V4L2_CID_CONTRAST, 0, 127, 1, 64); 1594 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1595 V4L2_CID_VFLIP, 0, 1, 1, 0); 1596 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1597 V4L2_CID_HFLIP, 0, 1, 1, 0); 1598 info->saturation = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1599 V4L2_CID_SATURATION, 0, 256, 1, 128); 1600 info->hue = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1601 V4L2_CID_HUE, -180, 180, 5, 0); 1602 info->gain = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1603 V4L2_CID_GAIN, 0, 255, 1, 128); 1604 info->auto_gain = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1605 V4L2_CID_AUTOGAIN, 0, 1, 1, 1); 1606 info->exposure = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1607 V4L2_CID_EXPOSURE, 0, 65535, 1, 500); 1608 info->auto_exposure = v4l2_ctrl_new_std_menu(&info->hdl, &ov7670_ctrl_ops, 1609 V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL, 0, 1610 V4L2_EXPOSURE_AUTO); 1611 sd->ctrl_handler = &info->hdl; 1612 if (info->hdl.error) { 1613 int err = info->hdl.error; 1614 1615 v4l2_ctrl_handler_free(&info->hdl); 1616 return err; 1617 } 1618 /* 1619 * We have checked empirically that hw allows to read back the gain 1620 * value chosen by auto gain but that's not the case for auto exposure. 1621 */ 1622 v4l2_ctrl_auto_cluster(2, &info->auto_gain, 0, true); 1623 v4l2_ctrl_auto_cluster(2, &info->auto_exposure, 1624 V4L2_EXPOSURE_MANUAL, false); 1625 v4l2_ctrl_cluster(2, &info->saturation); 1626 v4l2_ctrl_handler_setup(&info->hdl); 1627 1628 return 0; 1629 } 1630 1631 1632 static int ov7670_remove(struct i2c_client *client) 1633 { 1634 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1635 struct ov7670_info *info = to_state(sd); 1636 1637 v4l2_device_unregister_subdev(sd); 1638 v4l2_ctrl_handler_free(&info->hdl); 1639 return 0; 1640 } 1641 1642 static const struct i2c_device_id ov7670_id[] = { 1643 { "ov7670", MODEL_OV7670 }, 1644 { "ov7675", MODEL_OV7675 }, 1645 { } 1646 }; 1647 MODULE_DEVICE_TABLE(i2c, ov7670_id); 1648 1649 static struct i2c_driver ov7670_driver = { 1650 .driver = { 1651 .owner = THIS_MODULE, 1652 .name = "ov7670", 1653 }, 1654 .probe = ov7670_probe, 1655 .remove = ov7670_remove, 1656 .id_table = ov7670_id, 1657 }; 1658 1659 module_i2c_driver(ov7670_driver); 1660