1 /* 2 * A V4L2 driver for OmniVision OV7670 cameras. 3 * 4 * Copyright 2006 One Laptop Per Child Association, Inc. Written 5 * by Jonathan Corbet with substantial inspiration from Mark 6 * McClelland's ovcamchip code. 7 * 8 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net> 9 * 10 * This file may be distributed under the terms of the GNU General 11 * Public License, version 2. 12 */ 13 #include <linux/clk.h> 14 #include <linux/init.h> 15 #include <linux/module.h> 16 #include <linux/slab.h> 17 #include <linux/i2c.h> 18 #include <linux/delay.h> 19 #include <linux/videodev2.h> 20 #include <linux/gpio.h> 21 #include <linux/gpio/consumer.h> 22 #include <media/v4l2-device.h> 23 #include <media/v4l2-ctrls.h> 24 #include <media/v4l2-mediabus.h> 25 #include <media/v4l2-image-sizes.h> 26 #include <media/i2c/ov7670.h> 27 28 MODULE_AUTHOR("Jonathan Corbet <corbet@lwn.net>"); 29 MODULE_DESCRIPTION("A low-level driver for OmniVision ov7670 sensors"); 30 MODULE_LICENSE("GPL"); 31 32 static bool debug; 33 module_param(debug, bool, 0644); 34 MODULE_PARM_DESC(debug, "Debug level (0-1)"); 35 36 /* 37 * The 7670 sits on i2c with ID 0x42 38 */ 39 #define OV7670_I2C_ADDR 0x42 40 41 #define PLL_FACTOR 4 42 43 /* Registers */ 44 #define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */ 45 #define REG_BLUE 0x01 /* blue gain */ 46 #define REG_RED 0x02 /* red gain */ 47 #define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */ 48 #define REG_COM1 0x04 /* Control 1 */ 49 #define COM1_CCIR656 0x40 /* CCIR656 enable */ 50 #define REG_BAVE 0x05 /* U/B Average level */ 51 #define REG_GbAVE 0x06 /* Y/Gb Average level */ 52 #define REG_AECHH 0x07 /* AEC MS 5 bits */ 53 #define REG_RAVE 0x08 /* V/R Average level */ 54 #define REG_COM2 0x09 /* Control 2 */ 55 #define COM2_SSLEEP 0x10 /* Soft sleep mode */ 56 #define REG_PID 0x0a /* Product ID MSB */ 57 #define REG_VER 0x0b /* Product ID LSB */ 58 #define REG_COM3 0x0c /* Control 3 */ 59 #define COM3_SWAP 0x40 /* Byte swap */ 60 #define COM3_SCALEEN 0x08 /* Enable scaling */ 61 #define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */ 62 #define REG_COM4 0x0d /* Control 4 */ 63 #define REG_COM5 0x0e /* All "reserved" */ 64 #define REG_COM6 0x0f /* Control 6 */ 65 #define REG_AECH 0x10 /* More bits of AEC value */ 66 #define REG_CLKRC 0x11 /* Clocl control */ 67 #define CLK_EXT 0x40 /* Use external clock directly */ 68 #define CLK_SCALE 0x3f /* Mask for internal clock scale */ 69 #define REG_COM7 0x12 /* Control 7 */ 70 #define COM7_RESET 0x80 /* Register reset */ 71 #define COM7_FMT_MASK 0x38 72 #define COM7_FMT_VGA 0x00 73 #define COM7_FMT_CIF 0x20 /* CIF format */ 74 #define COM7_FMT_QVGA 0x10 /* QVGA format */ 75 #define COM7_FMT_QCIF 0x08 /* QCIF format */ 76 #define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */ 77 #define COM7_YUV 0x00 /* YUV */ 78 #define COM7_BAYER 0x01 /* Bayer format */ 79 #define COM7_PBAYER 0x05 /* "Processed bayer" */ 80 #define REG_COM8 0x13 /* Control 8 */ 81 #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */ 82 #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */ 83 #define COM8_BFILT 0x20 /* Band filter enable */ 84 #define COM8_AGC 0x04 /* Auto gain enable */ 85 #define COM8_AWB 0x02 /* White balance enable */ 86 #define COM8_AEC 0x01 /* Auto exposure enable */ 87 #define REG_COM9 0x14 /* Control 9 - gain ceiling */ 88 #define REG_COM10 0x15 /* Control 10 */ 89 #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */ 90 #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */ 91 #define COM10_HREF_REV 0x08 /* Reverse HREF */ 92 #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */ 93 #define COM10_VS_NEG 0x02 /* VSYNC negative */ 94 #define COM10_HS_NEG 0x01 /* HSYNC negative */ 95 #define REG_HSTART 0x17 /* Horiz start high bits */ 96 #define REG_HSTOP 0x18 /* Horiz stop high bits */ 97 #define REG_VSTART 0x19 /* Vert start high bits */ 98 #define REG_VSTOP 0x1a /* Vert stop high bits */ 99 #define REG_PSHFT 0x1b /* Pixel delay after HREF */ 100 #define REG_MIDH 0x1c /* Manuf. ID high */ 101 #define REG_MIDL 0x1d /* Manuf. ID low */ 102 #define REG_MVFP 0x1e /* Mirror / vflip */ 103 #define MVFP_MIRROR 0x20 /* Mirror image */ 104 #define MVFP_FLIP 0x10 /* Vertical flip */ 105 106 #define REG_AEW 0x24 /* AGC upper limit */ 107 #define REG_AEB 0x25 /* AGC lower limit */ 108 #define REG_VPT 0x26 /* AGC/AEC fast mode op region */ 109 #define REG_HSYST 0x30 /* HSYNC rising edge delay */ 110 #define REG_HSYEN 0x31 /* HSYNC falling edge delay */ 111 #define REG_HREF 0x32 /* HREF pieces */ 112 #define REG_TSLB 0x3a /* lots of stuff */ 113 #define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */ 114 #define REG_COM11 0x3b /* Control 11 */ 115 #define COM11_NIGHT 0x80 /* NIght mode enable */ 116 #define COM11_NMFR 0x60 /* Two bit NM frame rate */ 117 #define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */ 118 #define COM11_50HZ 0x08 /* Manual 50Hz select */ 119 #define COM11_EXP 0x02 120 #define REG_COM12 0x3c /* Control 12 */ 121 #define COM12_HREF 0x80 /* HREF always */ 122 #define REG_COM13 0x3d /* Control 13 */ 123 #define COM13_GAMMA 0x80 /* Gamma enable */ 124 #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */ 125 #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */ 126 #define REG_COM14 0x3e /* Control 14 */ 127 #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */ 128 #define REG_EDGE 0x3f /* Edge enhancement factor */ 129 #define REG_COM15 0x40 /* Control 15 */ 130 #define COM15_R10F0 0x00 /* Data range 10 to F0 */ 131 #define COM15_R01FE 0x80 /* 01 to FE */ 132 #define COM15_R00FF 0xc0 /* 00 to FF */ 133 #define COM15_RGB565 0x10 /* RGB565 output */ 134 #define COM15_RGB555 0x30 /* RGB555 output */ 135 #define REG_COM16 0x41 /* Control 16 */ 136 #define COM16_AWBGAIN 0x08 /* AWB gain enable */ 137 #define REG_COM17 0x42 /* Control 17 */ 138 #define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */ 139 #define COM17_CBAR 0x08 /* DSP Color bar */ 140 141 /* 142 * This matrix defines how the colors are generated, must be 143 * tweaked to adjust hue and saturation. 144 * 145 * Order: v-red, v-green, v-blue, u-red, u-green, u-blue 146 * 147 * They are nine-bit signed quantities, with the sign bit 148 * stored in 0x58. Sign for v-red is bit 0, and up from there. 149 */ 150 #define REG_CMATRIX_BASE 0x4f 151 #define CMATRIX_LEN 6 152 #define REG_CMATRIX_SIGN 0x58 153 154 155 #define REG_BRIGHT 0x55 /* Brightness */ 156 #define REG_CONTRAS 0x56 /* Contrast control */ 157 158 #define REG_GFIX 0x69 /* Fix gain control */ 159 160 #define REG_DBLV 0x6b /* PLL control an debugging */ 161 #define DBLV_BYPASS 0x00 /* Bypass PLL */ 162 #define DBLV_X4 0x01 /* clock x4 */ 163 #define DBLV_X6 0x10 /* clock x6 */ 164 #define DBLV_X8 0x11 /* clock x8 */ 165 166 #define REG_REG76 0x76 /* OV's name */ 167 #define R76_BLKPCOR 0x80 /* Black pixel correction enable */ 168 #define R76_WHTPCOR 0x40 /* White pixel correction enable */ 169 170 #define REG_RGB444 0x8c /* RGB 444 control */ 171 #define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */ 172 #define R444_RGBX 0x01 /* Empty nibble at end */ 173 174 #define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */ 175 #define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */ 176 177 #define REG_BD50MAX 0xa5 /* 50hz banding step limit */ 178 #define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */ 179 #define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */ 180 #define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */ 181 #define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */ 182 #define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */ 183 #define REG_BD60MAX 0xab /* 60hz banding step limit */ 184 185 enum ov7670_model { 186 MODEL_OV7670 = 0, 187 MODEL_OV7675, 188 }; 189 190 struct ov7670_win_size { 191 int width; 192 int height; 193 unsigned char com7_bit; 194 int hstart; /* Start/stop values for the camera. Note */ 195 int hstop; /* that they do not always make complete */ 196 int vstart; /* sense to humans, but evidently the sensor */ 197 int vstop; /* will do the right thing... */ 198 struct regval_list *regs; /* Regs to tweak */ 199 }; 200 201 struct ov7670_devtype { 202 /* formats supported for each model */ 203 struct ov7670_win_size *win_sizes; 204 unsigned int n_win_sizes; 205 /* callbacks for frame rate control */ 206 int (*set_framerate)(struct v4l2_subdev *, struct v4l2_fract *); 207 void (*get_framerate)(struct v4l2_subdev *, struct v4l2_fract *); 208 }; 209 210 /* 211 * Information we maintain about a known sensor. 212 */ 213 struct ov7670_format_struct; /* coming later */ 214 struct ov7670_info { 215 struct v4l2_subdev sd; 216 #if defined(CONFIG_MEDIA_CONTROLLER) 217 struct media_pad pad; 218 #endif 219 struct v4l2_ctrl_handler hdl; 220 struct { 221 /* gain cluster */ 222 struct v4l2_ctrl *auto_gain; 223 struct v4l2_ctrl *gain; 224 }; 225 struct { 226 /* exposure cluster */ 227 struct v4l2_ctrl *auto_exposure; 228 struct v4l2_ctrl *exposure; 229 }; 230 struct { 231 /* saturation/hue cluster */ 232 struct v4l2_ctrl *saturation; 233 struct v4l2_ctrl *hue; 234 }; 235 struct v4l2_mbus_framefmt format; 236 struct ov7670_format_struct *fmt; /* Current format */ 237 struct clk *clk; 238 struct gpio_desc *resetb_gpio; 239 struct gpio_desc *pwdn_gpio; 240 int min_width; /* Filter out smaller sizes */ 241 int min_height; /* Filter out smaller sizes */ 242 int clock_speed; /* External clock speed (MHz) */ 243 u8 clkrc; /* Clock divider value */ 244 bool use_smbus; /* Use smbus I/O instead of I2C */ 245 bool pll_bypass; 246 bool pclk_hb_disable; 247 const struct ov7670_devtype *devtype; /* Device specifics */ 248 }; 249 250 static inline struct ov7670_info *to_state(struct v4l2_subdev *sd) 251 { 252 return container_of(sd, struct ov7670_info, sd); 253 } 254 255 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) 256 { 257 return &container_of(ctrl->handler, struct ov7670_info, hdl)->sd; 258 } 259 260 261 262 /* 263 * The default register settings, as obtained from OmniVision. There 264 * is really no making sense of most of these - lots of "reserved" values 265 * and such. 266 * 267 * These settings give VGA YUYV. 268 */ 269 270 struct regval_list { 271 unsigned char reg_num; 272 unsigned char value; 273 }; 274 275 static struct regval_list ov7670_default_regs[] = { 276 { REG_COM7, COM7_RESET }, 277 /* 278 * Clock scale: 3 = 15fps 279 * 2 = 20fps 280 * 1 = 30fps 281 */ 282 { REG_CLKRC, 0x1 }, /* OV: clock scale (30 fps) */ 283 { REG_TSLB, 0x04 }, /* OV */ 284 { REG_COM7, 0 }, /* VGA */ 285 /* 286 * Set the hardware window. These values from OV don't entirely 287 * make sense - hstop is less than hstart. But they work... 288 */ 289 { REG_HSTART, 0x13 }, { REG_HSTOP, 0x01 }, 290 { REG_HREF, 0xb6 }, { REG_VSTART, 0x02 }, 291 { REG_VSTOP, 0x7a }, { REG_VREF, 0x0a }, 292 293 { REG_COM3, 0 }, { REG_COM14, 0 }, 294 /* Mystery scaling numbers */ 295 { 0x70, 0x3a }, { 0x71, 0x35 }, 296 { 0x72, 0x11 }, { 0x73, 0xf0 }, 297 { 0xa2, 0x02 }, { REG_COM10, 0x0 }, 298 299 /* Gamma curve values */ 300 { 0x7a, 0x20 }, { 0x7b, 0x10 }, 301 { 0x7c, 0x1e }, { 0x7d, 0x35 }, 302 { 0x7e, 0x5a }, { 0x7f, 0x69 }, 303 { 0x80, 0x76 }, { 0x81, 0x80 }, 304 { 0x82, 0x88 }, { 0x83, 0x8f }, 305 { 0x84, 0x96 }, { 0x85, 0xa3 }, 306 { 0x86, 0xaf }, { 0x87, 0xc4 }, 307 { 0x88, 0xd7 }, { 0x89, 0xe8 }, 308 309 /* AGC and AEC parameters. Note we start by disabling those features, 310 then turn them only after tweaking the values. */ 311 { REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_BFILT }, 312 { REG_GAIN, 0 }, { REG_AECH, 0 }, 313 { REG_COM4, 0x40 }, /* magic reserved bit */ 314 { REG_COM9, 0x18 }, /* 4x gain + magic rsvd bit */ 315 { REG_BD50MAX, 0x05 }, { REG_BD60MAX, 0x07 }, 316 { REG_AEW, 0x95 }, { REG_AEB, 0x33 }, 317 { REG_VPT, 0xe3 }, { REG_HAECC1, 0x78 }, 318 { REG_HAECC2, 0x68 }, { 0xa1, 0x03 }, /* magic */ 319 { REG_HAECC3, 0xd8 }, { REG_HAECC4, 0xd8 }, 320 { REG_HAECC5, 0xf0 }, { REG_HAECC6, 0x90 }, 321 { REG_HAECC7, 0x94 }, 322 { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC }, 323 324 /* Almost all of these are magic "reserved" values. */ 325 { REG_COM5, 0x61 }, { REG_COM6, 0x4b }, 326 { 0x16, 0x02 }, { REG_MVFP, 0x07 }, 327 { 0x21, 0x02 }, { 0x22, 0x91 }, 328 { 0x29, 0x07 }, { 0x33, 0x0b }, 329 { 0x35, 0x0b }, { 0x37, 0x1d }, 330 { 0x38, 0x71 }, { 0x39, 0x2a }, 331 { REG_COM12, 0x78 }, { 0x4d, 0x40 }, 332 { 0x4e, 0x20 }, { REG_GFIX, 0 }, 333 { 0x6b, 0x4a }, { 0x74, 0x10 }, 334 { 0x8d, 0x4f }, { 0x8e, 0 }, 335 { 0x8f, 0 }, { 0x90, 0 }, 336 { 0x91, 0 }, { 0x96, 0 }, 337 { 0x9a, 0 }, { 0xb0, 0x84 }, 338 { 0xb1, 0x0c }, { 0xb2, 0x0e }, 339 { 0xb3, 0x82 }, { 0xb8, 0x0a }, 340 341 /* More reserved magic, some of which tweaks white balance */ 342 { 0x43, 0x0a }, { 0x44, 0xf0 }, 343 { 0x45, 0x34 }, { 0x46, 0x58 }, 344 { 0x47, 0x28 }, { 0x48, 0x3a }, 345 { 0x59, 0x88 }, { 0x5a, 0x88 }, 346 { 0x5b, 0x44 }, { 0x5c, 0x67 }, 347 { 0x5d, 0x49 }, { 0x5e, 0x0e }, 348 { 0x6c, 0x0a }, { 0x6d, 0x55 }, 349 { 0x6e, 0x11 }, { 0x6f, 0x9f }, /* "9e for advance AWB" */ 350 { 0x6a, 0x40 }, { REG_BLUE, 0x40 }, 351 { REG_RED, 0x60 }, 352 { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC|COM8_AWB }, 353 354 /* Matrix coefficients */ 355 { 0x4f, 0x80 }, { 0x50, 0x80 }, 356 { 0x51, 0 }, { 0x52, 0x22 }, 357 { 0x53, 0x5e }, { 0x54, 0x80 }, 358 { 0x58, 0x9e }, 359 360 { REG_COM16, COM16_AWBGAIN }, { REG_EDGE, 0 }, 361 { 0x75, 0x05 }, { 0x76, 0xe1 }, 362 { 0x4c, 0 }, { 0x77, 0x01 }, 363 { REG_COM13, 0xc3 }, { 0x4b, 0x09 }, 364 { 0xc9, 0x60 }, { REG_COM16, 0x38 }, 365 { 0x56, 0x40 }, 366 367 { 0x34, 0x11 }, { REG_COM11, COM11_EXP|COM11_HZAUTO }, 368 { 0xa4, 0x88 }, { 0x96, 0 }, 369 { 0x97, 0x30 }, { 0x98, 0x20 }, 370 { 0x99, 0x30 }, { 0x9a, 0x84 }, 371 { 0x9b, 0x29 }, { 0x9c, 0x03 }, 372 { 0x9d, 0x4c }, { 0x9e, 0x3f }, 373 { 0x78, 0x04 }, 374 375 /* Extra-weird stuff. Some sort of multiplexor register */ 376 { 0x79, 0x01 }, { 0xc8, 0xf0 }, 377 { 0x79, 0x0f }, { 0xc8, 0x00 }, 378 { 0x79, 0x10 }, { 0xc8, 0x7e }, 379 { 0x79, 0x0a }, { 0xc8, 0x80 }, 380 { 0x79, 0x0b }, { 0xc8, 0x01 }, 381 { 0x79, 0x0c }, { 0xc8, 0x0f }, 382 { 0x79, 0x0d }, { 0xc8, 0x20 }, 383 { 0x79, 0x09 }, { 0xc8, 0x80 }, 384 { 0x79, 0x02 }, { 0xc8, 0xc0 }, 385 { 0x79, 0x03 }, { 0xc8, 0x40 }, 386 { 0x79, 0x05 }, { 0xc8, 0x30 }, 387 { 0x79, 0x26 }, 388 389 { 0xff, 0xff }, /* END MARKER */ 390 }; 391 392 393 /* 394 * Here we'll try to encapsulate the changes for just the output 395 * video format. 396 * 397 * RGB656 and YUV422 come from OV; RGB444 is homebrewed. 398 * 399 * IMPORTANT RULE: the first entry must be for COM7, see ov7670_s_fmt for why. 400 */ 401 402 403 static struct regval_list ov7670_fmt_yuv422[] = { 404 { REG_COM7, 0x0 }, /* Selects YUV mode */ 405 { REG_RGB444, 0 }, /* No RGB444 please */ 406 { REG_COM1, 0 }, /* CCIR601 */ 407 { REG_COM15, COM15_R00FF }, 408 { REG_COM9, 0x48 }, /* 32x gain ceiling; 0x8 is reserved bit */ 409 { 0x4f, 0x80 }, /* "matrix coefficient 1" */ 410 { 0x50, 0x80 }, /* "matrix coefficient 2" */ 411 { 0x51, 0 }, /* vb */ 412 { 0x52, 0x22 }, /* "matrix coefficient 4" */ 413 { 0x53, 0x5e }, /* "matrix coefficient 5" */ 414 { 0x54, 0x80 }, /* "matrix coefficient 6" */ 415 { REG_COM13, COM13_GAMMA|COM13_UVSAT }, 416 { 0xff, 0xff }, 417 }; 418 419 static struct regval_list ov7670_fmt_rgb565[] = { 420 { REG_COM7, COM7_RGB }, /* Selects RGB mode */ 421 { REG_RGB444, 0 }, /* No RGB444 please */ 422 { REG_COM1, 0x0 }, /* CCIR601 */ 423 { REG_COM15, COM15_RGB565 }, 424 { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */ 425 { 0x4f, 0xb3 }, /* "matrix coefficient 1" */ 426 { 0x50, 0xb3 }, /* "matrix coefficient 2" */ 427 { 0x51, 0 }, /* vb */ 428 { 0x52, 0x3d }, /* "matrix coefficient 4" */ 429 { 0x53, 0xa7 }, /* "matrix coefficient 5" */ 430 { 0x54, 0xe4 }, /* "matrix coefficient 6" */ 431 { REG_COM13, COM13_GAMMA|COM13_UVSAT }, 432 { 0xff, 0xff }, 433 }; 434 435 static struct regval_list ov7670_fmt_rgb444[] = { 436 { REG_COM7, COM7_RGB }, /* Selects RGB mode */ 437 { REG_RGB444, R444_ENABLE }, /* Enable xxxxrrrr ggggbbbb */ 438 { REG_COM1, 0x0 }, /* CCIR601 */ 439 { REG_COM15, COM15_R01FE|COM15_RGB565 }, /* Data range needed? */ 440 { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */ 441 { 0x4f, 0xb3 }, /* "matrix coefficient 1" */ 442 { 0x50, 0xb3 }, /* "matrix coefficient 2" */ 443 { 0x51, 0 }, /* vb */ 444 { 0x52, 0x3d }, /* "matrix coefficient 4" */ 445 { 0x53, 0xa7 }, /* "matrix coefficient 5" */ 446 { 0x54, 0xe4 }, /* "matrix coefficient 6" */ 447 { REG_COM13, COM13_GAMMA|COM13_UVSAT|0x2 }, /* Magic rsvd bit */ 448 { 0xff, 0xff }, 449 }; 450 451 static struct regval_list ov7670_fmt_raw[] = { 452 { REG_COM7, COM7_BAYER }, 453 { REG_COM13, 0x08 }, /* No gamma, magic rsvd bit */ 454 { REG_COM16, 0x3d }, /* Edge enhancement, denoise */ 455 { REG_REG76, 0xe1 }, /* Pix correction, magic rsvd */ 456 { 0xff, 0xff }, 457 }; 458 459 460 461 /* 462 * Low-level register I/O. 463 * 464 * Note that there are two versions of these. On the XO 1, the 465 * i2c controller only does SMBUS, so that's what we use. The 466 * ov7670 is not really an SMBUS device, though, so the communication 467 * is not always entirely reliable. 468 */ 469 static int ov7670_read_smbus(struct v4l2_subdev *sd, unsigned char reg, 470 unsigned char *value) 471 { 472 struct i2c_client *client = v4l2_get_subdevdata(sd); 473 int ret; 474 475 ret = i2c_smbus_read_byte_data(client, reg); 476 if (ret >= 0) { 477 *value = (unsigned char)ret; 478 ret = 0; 479 } 480 return ret; 481 } 482 483 484 static int ov7670_write_smbus(struct v4l2_subdev *sd, unsigned char reg, 485 unsigned char value) 486 { 487 struct i2c_client *client = v4l2_get_subdevdata(sd); 488 int ret = i2c_smbus_write_byte_data(client, reg, value); 489 490 if (reg == REG_COM7 && (value & COM7_RESET)) 491 msleep(5); /* Wait for reset to run */ 492 return ret; 493 } 494 495 /* 496 * On most platforms, we'd rather do straight i2c I/O. 497 */ 498 static int ov7670_read_i2c(struct v4l2_subdev *sd, unsigned char reg, 499 unsigned char *value) 500 { 501 struct i2c_client *client = v4l2_get_subdevdata(sd); 502 u8 data = reg; 503 struct i2c_msg msg; 504 int ret; 505 506 /* 507 * Send out the register address... 508 */ 509 msg.addr = client->addr; 510 msg.flags = 0; 511 msg.len = 1; 512 msg.buf = &data; 513 ret = i2c_transfer(client->adapter, &msg, 1); 514 if (ret < 0) { 515 printk(KERN_ERR "Error %d on register write\n", ret); 516 return ret; 517 } 518 /* 519 * ...then read back the result. 520 */ 521 msg.flags = I2C_M_RD; 522 ret = i2c_transfer(client->adapter, &msg, 1); 523 if (ret >= 0) { 524 *value = data; 525 ret = 0; 526 } 527 return ret; 528 } 529 530 531 static int ov7670_write_i2c(struct v4l2_subdev *sd, unsigned char reg, 532 unsigned char value) 533 { 534 struct i2c_client *client = v4l2_get_subdevdata(sd); 535 struct i2c_msg msg; 536 unsigned char data[2] = { reg, value }; 537 int ret; 538 539 msg.addr = client->addr; 540 msg.flags = 0; 541 msg.len = 2; 542 msg.buf = data; 543 ret = i2c_transfer(client->adapter, &msg, 1); 544 if (ret > 0) 545 ret = 0; 546 if (reg == REG_COM7 && (value & COM7_RESET)) 547 msleep(5); /* Wait for reset to run */ 548 return ret; 549 } 550 551 static int ov7670_read(struct v4l2_subdev *sd, unsigned char reg, 552 unsigned char *value) 553 { 554 struct ov7670_info *info = to_state(sd); 555 if (info->use_smbus) 556 return ov7670_read_smbus(sd, reg, value); 557 else 558 return ov7670_read_i2c(sd, reg, value); 559 } 560 561 static int ov7670_write(struct v4l2_subdev *sd, unsigned char reg, 562 unsigned char value) 563 { 564 struct ov7670_info *info = to_state(sd); 565 if (info->use_smbus) 566 return ov7670_write_smbus(sd, reg, value); 567 else 568 return ov7670_write_i2c(sd, reg, value); 569 } 570 571 /* 572 * Write a list of register settings; ff/ff stops the process. 573 */ 574 static int ov7670_write_array(struct v4l2_subdev *sd, struct regval_list *vals) 575 { 576 while (vals->reg_num != 0xff || vals->value != 0xff) { 577 int ret = ov7670_write(sd, vals->reg_num, vals->value); 578 if (ret < 0) 579 return ret; 580 vals++; 581 } 582 return 0; 583 } 584 585 586 /* 587 * Stuff that knows about the sensor. 588 */ 589 static int ov7670_reset(struct v4l2_subdev *sd, u32 val) 590 { 591 ov7670_write(sd, REG_COM7, COM7_RESET); 592 msleep(1); 593 return 0; 594 } 595 596 597 static int ov7670_init(struct v4l2_subdev *sd, u32 val) 598 { 599 return ov7670_write_array(sd, ov7670_default_regs); 600 } 601 602 static int ov7670_detect(struct v4l2_subdev *sd) 603 { 604 unsigned char v; 605 int ret; 606 607 ret = ov7670_init(sd, 0); 608 if (ret < 0) 609 return ret; 610 ret = ov7670_read(sd, REG_MIDH, &v); 611 if (ret < 0) 612 return ret; 613 if (v != 0x7f) /* OV manuf. id. */ 614 return -ENODEV; 615 ret = ov7670_read(sd, REG_MIDL, &v); 616 if (ret < 0) 617 return ret; 618 if (v != 0xa2) 619 return -ENODEV; 620 /* 621 * OK, we know we have an OmniVision chip...but which one? 622 */ 623 ret = ov7670_read(sd, REG_PID, &v); 624 if (ret < 0) 625 return ret; 626 if (v != 0x76) /* PID + VER = 0x76 / 0x73 */ 627 return -ENODEV; 628 ret = ov7670_read(sd, REG_VER, &v); 629 if (ret < 0) 630 return ret; 631 if (v != 0x73) /* PID + VER = 0x76 / 0x73 */ 632 return -ENODEV; 633 return 0; 634 } 635 636 637 /* 638 * Store information about the video data format. The color matrix 639 * is deeply tied into the format, so keep the relevant values here. 640 * The magic matrix numbers come from OmniVision. 641 */ 642 static struct ov7670_format_struct { 643 u32 mbus_code; 644 enum v4l2_colorspace colorspace; 645 struct regval_list *regs; 646 int cmatrix[CMATRIX_LEN]; 647 } ov7670_formats[] = { 648 { 649 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, 650 .colorspace = V4L2_COLORSPACE_SRGB, 651 .regs = ov7670_fmt_yuv422, 652 .cmatrix = { 128, -128, 0, -34, -94, 128 }, 653 }, 654 { 655 .mbus_code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE, 656 .colorspace = V4L2_COLORSPACE_SRGB, 657 .regs = ov7670_fmt_rgb444, 658 .cmatrix = { 179, -179, 0, -61, -176, 228 }, 659 }, 660 { 661 .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE, 662 .colorspace = V4L2_COLORSPACE_SRGB, 663 .regs = ov7670_fmt_rgb565, 664 .cmatrix = { 179, -179, 0, -61, -176, 228 }, 665 }, 666 { 667 .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8, 668 .colorspace = V4L2_COLORSPACE_SRGB, 669 .regs = ov7670_fmt_raw, 670 .cmatrix = { 0, 0, 0, 0, 0, 0 }, 671 }, 672 }; 673 #define N_OV7670_FMTS ARRAY_SIZE(ov7670_formats) 674 675 676 /* 677 * Then there is the issue of window sizes. Try to capture the info here. 678 */ 679 680 /* 681 * QCIF mode is done (by OV) in a very strange way - it actually looks like 682 * VGA with weird scaling options - they do *not* use the canned QCIF mode 683 * which is allegedly provided by the sensor. So here's the weird register 684 * settings. 685 */ 686 static struct regval_list ov7670_qcif_regs[] = { 687 { REG_COM3, COM3_SCALEEN|COM3_DCWEN }, 688 { REG_COM3, COM3_DCWEN }, 689 { REG_COM14, COM14_DCWEN | 0x01}, 690 { 0x73, 0xf1 }, 691 { 0xa2, 0x52 }, 692 { 0x7b, 0x1c }, 693 { 0x7c, 0x28 }, 694 { 0x7d, 0x3c }, 695 { 0x7f, 0x69 }, 696 { REG_COM9, 0x38 }, 697 { 0xa1, 0x0b }, 698 { 0x74, 0x19 }, 699 { 0x9a, 0x80 }, 700 { 0x43, 0x14 }, 701 { REG_COM13, 0xc0 }, 702 { 0xff, 0xff }, 703 }; 704 705 static struct ov7670_win_size ov7670_win_sizes[] = { 706 /* VGA */ 707 { 708 .width = VGA_WIDTH, 709 .height = VGA_HEIGHT, 710 .com7_bit = COM7_FMT_VGA, 711 .hstart = 158, /* These values from */ 712 .hstop = 14, /* Omnivision */ 713 .vstart = 10, 714 .vstop = 490, 715 .regs = NULL, 716 }, 717 /* CIF */ 718 { 719 .width = CIF_WIDTH, 720 .height = CIF_HEIGHT, 721 .com7_bit = COM7_FMT_CIF, 722 .hstart = 170, /* Empirically determined */ 723 .hstop = 90, 724 .vstart = 14, 725 .vstop = 494, 726 .regs = NULL, 727 }, 728 /* QVGA */ 729 { 730 .width = QVGA_WIDTH, 731 .height = QVGA_HEIGHT, 732 .com7_bit = COM7_FMT_QVGA, 733 .hstart = 168, /* Empirically determined */ 734 .hstop = 24, 735 .vstart = 12, 736 .vstop = 492, 737 .regs = NULL, 738 }, 739 /* QCIF */ 740 { 741 .width = QCIF_WIDTH, 742 .height = QCIF_HEIGHT, 743 .com7_bit = COM7_FMT_VGA, /* see comment above */ 744 .hstart = 456, /* Empirically determined */ 745 .hstop = 24, 746 .vstart = 14, 747 .vstop = 494, 748 .regs = ov7670_qcif_regs, 749 } 750 }; 751 752 static struct ov7670_win_size ov7675_win_sizes[] = { 753 /* 754 * Currently, only VGA is supported. Theoretically it could be possible 755 * to support CIF, QVGA and QCIF too. Taking values for ov7670 as a 756 * base and tweak them empirically could be required. 757 */ 758 { 759 .width = VGA_WIDTH, 760 .height = VGA_HEIGHT, 761 .com7_bit = COM7_FMT_VGA, 762 .hstart = 158, /* These values from */ 763 .hstop = 14, /* Omnivision */ 764 .vstart = 14, /* Empirically determined */ 765 .vstop = 494, 766 .regs = NULL, 767 } 768 }; 769 770 static void ov7675_get_framerate(struct v4l2_subdev *sd, 771 struct v4l2_fract *tpf) 772 { 773 struct ov7670_info *info = to_state(sd); 774 u32 clkrc = info->clkrc; 775 int pll_factor; 776 777 if (info->pll_bypass) 778 pll_factor = 1; 779 else 780 pll_factor = PLL_FACTOR; 781 782 clkrc++; 783 if (info->fmt->mbus_code == MEDIA_BUS_FMT_SBGGR8_1X8) 784 clkrc = (clkrc >> 1); 785 786 tpf->numerator = 1; 787 tpf->denominator = (5 * pll_factor * info->clock_speed) / 788 (4 * clkrc); 789 } 790 791 static int ov7675_set_framerate(struct v4l2_subdev *sd, 792 struct v4l2_fract *tpf) 793 { 794 struct ov7670_info *info = to_state(sd); 795 u32 clkrc; 796 int pll_factor; 797 int ret; 798 799 /* 800 * The formula is fps = 5/4*pixclk for YUV/RGB and 801 * fps = 5/2*pixclk for RAW. 802 * 803 * pixclk = clock_speed / (clkrc + 1) * PLLfactor 804 * 805 */ 806 if (info->pll_bypass) { 807 pll_factor = 1; 808 ret = ov7670_write(sd, REG_DBLV, DBLV_BYPASS); 809 } else { 810 pll_factor = PLL_FACTOR; 811 ret = ov7670_write(sd, REG_DBLV, DBLV_X4); 812 } 813 if (ret < 0) 814 return ret; 815 816 if (tpf->numerator == 0 || tpf->denominator == 0) { 817 clkrc = 0; 818 } else { 819 clkrc = (5 * pll_factor * info->clock_speed * tpf->numerator) / 820 (4 * tpf->denominator); 821 if (info->fmt->mbus_code == MEDIA_BUS_FMT_SBGGR8_1X8) 822 clkrc = (clkrc << 1); 823 clkrc--; 824 } 825 826 /* 827 * The datasheet claims that clkrc = 0 will divide the input clock by 1 828 * but we've checked with an oscilloscope that it divides by 2 instead. 829 * So, if clkrc = 0 just bypass the divider. 830 */ 831 if (clkrc <= 0) 832 clkrc = CLK_EXT; 833 else if (clkrc > CLK_SCALE) 834 clkrc = CLK_SCALE; 835 info->clkrc = clkrc; 836 837 /* Recalculate frame rate */ 838 ov7675_get_framerate(sd, tpf); 839 840 ret = ov7670_write(sd, REG_CLKRC, info->clkrc); 841 if (ret < 0) 842 return ret; 843 844 return ov7670_write(sd, REG_DBLV, DBLV_X4); 845 } 846 847 static void ov7670_get_framerate_legacy(struct v4l2_subdev *sd, 848 struct v4l2_fract *tpf) 849 { 850 struct ov7670_info *info = to_state(sd); 851 852 tpf->numerator = 1; 853 tpf->denominator = info->clock_speed; 854 if ((info->clkrc & CLK_EXT) == 0 && (info->clkrc & CLK_SCALE) > 1) 855 tpf->denominator /= (info->clkrc & CLK_SCALE); 856 } 857 858 static int ov7670_set_framerate_legacy(struct v4l2_subdev *sd, 859 struct v4l2_fract *tpf) 860 { 861 struct ov7670_info *info = to_state(sd); 862 int div; 863 864 if (tpf->numerator == 0 || tpf->denominator == 0) 865 div = 1; /* Reset to full rate */ 866 else 867 div = (tpf->numerator * info->clock_speed) / tpf->denominator; 868 if (div == 0) 869 div = 1; 870 else if (div > CLK_SCALE) 871 div = CLK_SCALE; 872 info->clkrc = (info->clkrc & 0x80) | div; 873 tpf->numerator = 1; 874 tpf->denominator = info->clock_speed / div; 875 return ov7670_write(sd, REG_CLKRC, info->clkrc); 876 } 877 878 /* 879 * Store a set of start/stop values into the camera. 880 */ 881 static int ov7670_set_hw(struct v4l2_subdev *sd, int hstart, int hstop, 882 int vstart, int vstop) 883 { 884 int ret; 885 unsigned char v; 886 /* 887 * Horizontal: 11 bits, top 8 live in hstart and hstop. Bottom 3 of 888 * hstart are in href[2:0], bottom 3 of hstop in href[5:3]. There is 889 * a mystery "edge offset" value in the top two bits of href. 890 */ 891 ret = ov7670_write(sd, REG_HSTART, (hstart >> 3) & 0xff); 892 ret += ov7670_write(sd, REG_HSTOP, (hstop >> 3) & 0xff); 893 ret += ov7670_read(sd, REG_HREF, &v); 894 v = (v & 0xc0) | ((hstop & 0x7) << 3) | (hstart & 0x7); 895 msleep(10); 896 ret += ov7670_write(sd, REG_HREF, v); 897 /* 898 * Vertical: similar arrangement, but only 10 bits. 899 */ 900 ret += ov7670_write(sd, REG_VSTART, (vstart >> 2) & 0xff); 901 ret += ov7670_write(sd, REG_VSTOP, (vstop >> 2) & 0xff); 902 ret += ov7670_read(sd, REG_VREF, &v); 903 v = (v & 0xf0) | ((vstop & 0x3) << 2) | (vstart & 0x3); 904 msleep(10); 905 ret += ov7670_write(sd, REG_VREF, v); 906 return ret; 907 } 908 909 910 static int ov7670_enum_mbus_code(struct v4l2_subdev *sd, 911 struct v4l2_subdev_pad_config *cfg, 912 struct v4l2_subdev_mbus_code_enum *code) 913 { 914 if (code->pad || code->index >= N_OV7670_FMTS) 915 return -EINVAL; 916 917 code->code = ov7670_formats[code->index].mbus_code; 918 return 0; 919 } 920 921 static int ov7670_try_fmt_internal(struct v4l2_subdev *sd, 922 struct v4l2_mbus_framefmt *fmt, 923 struct ov7670_format_struct **ret_fmt, 924 struct ov7670_win_size **ret_wsize) 925 { 926 int index, i; 927 struct ov7670_win_size *wsize; 928 struct ov7670_info *info = to_state(sd); 929 unsigned int n_win_sizes = info->devtype->n_win_sizes; 930 unsigned int win_sizes_limit = n_win_sizes; 931 932 for (index = 0; index < N_OV7670_FMTS; index++) 933 if (ov7670_formats[index].mbus_code == fmt->code) 934 break; 935 if (index >= N_OV7670_FMTS) { 936 /* default to first format */ 937 index = 0; 938 fmt->code = ov7670_formats[0].mbus_code; 939 } 940 if (ret_fmt != NULL) 941 *ret_fmt = ov7670_formats + index; 942 /* 943 * Fields: the OV devices claim to be progressive. 944 */ 945 fmt->field = V4L2_FIELD_NONE; 946 947 /* 948 * Don't consider values that don't match min_height and min_width 949 * constraints. 950 */ 951 if (info->min_width || info->min_height) 952 for (i = 0; i < n_win_sizes; i++) { 953 wsize = info->devtype->win_sizes + i; 954 955 if (wsize->width < info->min_width || 956 wsize->height < info->min_height) { 957 win_sizes_limit = i; 958 break; 959 } 960 } 961 /* 962 * Round requested image size down to the nearest 963 * we support, but not below the smallest. 964 */ 965 for (wsize = info->devtype->win_sizes; 966 wsize < info->devtype->win_sizes + win_sizes_limit; wsize++) 967 if (fmt->width >= wsize->width && fmt->height >= wsize->height) 968 break; 969 if (wsize >= info->devtype->win_sizes + win_sizes_limit) 970 wsize--; /* Take the smallest one */ 971 if (ret_wsize != NULL) 972 *ret_wsize = wsize; 973 /* 974 * Note the size we'll actually handle. 975 */ 976 fmt->width = wsize->width; 977 fmt->height = wsize->height; 978 fmt->colorspace = ov7670_formats[index].colorspace; 979 980 info->format = *fmt; 981 982 return 0; 983 } 984 985 /* 986 * Set a format. 987 */ 988 static int ov7670_set_fmt(struct v4l2_subdev *sd, 989 struct v4l2_subdev_pad_config *cfg, 990 struct v4l2_subdev_format *format) 991 { 992 struct ov7670_format_struct *ovfmt; 993 struct ov7670_win_size *wsize; 994 struct ov7670_info *info = to_state(sd); 995 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 996 struct v4l2_mbus_framefmt *mbus_fmt; 997 #endif 998 unsigned char com7; 999 int ret; 1000 1001 if (format->pad) 1002 return -EINVAL; 1003 1004 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 1005 ret = ov7670_try_fmt_internal(sd, &format->format, NULL, NULL); 1006 if (ret) 1007 return ret; 1008 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1009 mbus_fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad); 1010 *mbus_fmt = format->format; 1011 return 0; 1012 #else 1013 return -ENOTTY; 1014 #endif 1015 } 1016 1017 ret = ov7670_try_fmt_internal(sd, &format->format, &ovfmt, &wsize); 1018 1019 if (ret) 1020 return ret; 1021 /* 1022 * COM7 is a pain in the ass, it doesn't like to be read then 1023 * quickly written afterward. But we have everything we need 1024 * to set it absolutely here, as long as the format-specific 1025 * register sets list it first. 1026 */ 1027 com7 = ovfmt->regs[0].value; 1028 com7 |= wsize->com7_bit; 1029 ov7670_write(sd, REG_COM7, com7); 1030 /* 1031 * Now write the rest of the array. Also store start/stops 1032 */ 1033 ov7670_write_array(sd, ovfmt->regs + 1); 1034 ov7670_set_hw(sd, wsize->hstart, wsize->hstop, wsize->vstart, 1035 wsize->vstop); 1036 ret = 0; 1037 if (wsize->regs) 1038 ret = ov7670_write_array(sd, wsize->regs); 1039 info->fmt = ovfmt; 1040 1041 /* 1042 * If we're running RGB565, we must rewrite clkrc after setting 1043 * the other parameters or the image looks poor. If we're *not* 1044 * doing RGB565, we must not rewrite clkrc or the image looks 1045 * *really* poor. 1046 * 1047 * (Update) Now that we retain clkrc state, we should be able 1048 * to write it unconditionally, and that will make the frame 1049 * rate persistent too. 1050 */ 1051 if (ret == 0) 1052 ret = ov7670_write(sd, REG_CLKRC, info->clkrc); 1053 return 0; 1054 } 1055 1056 static int ov7670_get_fmt(struct v4l2_subdev *sd, 1057 struct v4l2_subdev_pad_config *cfg, 1058 struct v4l2_subdev_format *format) 1059 { 1060 struct ov7670_info *info = to_state(sd); 1061 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1062 struct v4l2_mbus_framefmt *mbus_fmt; 1063 #endif 1064 1065 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 1066 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1067 mbus_fmt = v4l2_subdev_get_try_format(sd, cfg, 0); 1068 format->format = *mbus_fmt; 1069 return 0; 1070 #else 1071 return -ENOTTY; 1072 #endif 1073 } else { 1074 format->format = info->format; 1075 } 1076 1077 return 0; 1078 } 1079 1080 /* 1081 * Implement G/S_PARM. There is a "high quality" mode we could try 1082 * to do someday; for now, we just do the frame rate tweak. 1083 */ 1084 static int ov7670_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms) 1085 { 1086 struct v4l2_captureparm *cp = &parms->parm.capture; 1087 struct ov7670_info *info = to_state(sd); 1088 1089 if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) 1090 return -EINVAL; 1091 1092 cp->capability = V4L2_CAP_TIMEPERFRAME; 1093 info->devtype->get_framerate(sd, &cp->timeperframe); 1094 1095 return 0; 1096 } 1097 1098 static int ov7670_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms) 1099 { 1100 struct v4l2_captureparm *cp = &parms->parm.capture; 1101 struct v4l2_fract *tpf = &cp->timeperframe; 1102 struct ov7670_info *info = to_state(sd); 1103 1104 if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) 1105 return -EINVAL; 1106 1107 cp->capability = V4L2_CAP_TIMEPERFRAME; 1108 return info->devtype->set_framerate(sd, tpf); 1109 } 1110 1111 1112 /* 1113 * Frame intervals. Since frame rates are controlled with the clock 1114 * divider, we can only do 30/n for integer n values. So no continuous 1115 * or stepwise options. Here we just pick a handful of logical values. 1116 */ 1117 1118 static int ov7670_frame_rates[] = { 30, 15, 10, 5, 1 }; 1119 1120 static int ov7670_enum_frame_interval(struct v4l2_subdev *sd, 1121 struct v4l2_subdev_pad_config *cfg, 1122 struct v4l2_subdev_frame_interval_enum *fie) 1123 { 1124 struct ov7670_info *info = to_state(sd); 1125 unsigned int n_win_sizes = info->devtype->n_win_sizes; 1126 int i; 1127 1128 if (fie->pad) 1129 return -EINVAL; 1130 if (fie->index >= ARRAY_SIZE(ov7670_frame_rates)) 1131 return -EINVAL; 1132 1133 /* 1134 * Check if the width/height is valid. 1135 * 1136 * If a minimum width/height was requested, filter out the capture 1137 * windows that fall outside that. 1138 */ 1139 for (i = 0; i < n_win_sizes; i++) { 1140 struct ov7670_win_size *win = &info->devtype->win_sizes[i]; 1141 1142 if (info->min_width && win->width < info->min_width) 1143 continue; 1144 if (info->min_height && win->height < info->min_height) 1145 continue; 1146 if (fie->width == win->width && fie->height == win->height) 1147 break; 1148 } 1149 if (i == n_win_sizes) 1150 return -EINVAL; 1151 fie->interval.numerator = 1; 1152 fie->interval.denominator = ov7670_frame_rates[fie->index]; 1153 return 0; 1154 } 1155 1156 /* 1157 * Frame size enumeration 1158 */ 1159 static int ov7670_enum_frame_size(struct v4l2_subdev *sd, 1160 struct v4l2_subdev_pad_config *cfg, 1161 struct v4l2_subdev_frame_size_enum *fse) 1162 { 1163 struct ov7670_info *info = to_state(sd); 1164 int i; 1165 int num_valid = -1; 1166 __u32 index = fse->index; 1167 unsigned int n_win_sizes = info->devtype->n_win_sizes; 1168 1169 if (fse->pad) 1170 return -EINVAL; 1171 1172 /* 1173 * If a minimum width/height was requested, filter out the capture 1174 * windows that fall outside that. 1175 */ 1176 for (i = 0; i < n_win_sizes; i++) { 1177 struct ov7670_win_size *win = &info->devtype->win_sizes[i]; 1178 if (info->min_width && win->width < info->min_width) 1179 continue; 1180 if (info->min_height && win->height < info->min_height) 1181 continue; 1182 if (index == ++num_valid) { 1183 fse->min_width = fse->max_width = win->width; 1184 fse->min_height = fse->max_height = win->height; 1185 return 0; 1186 } 1187 } 1188 1189 return -EINVAL; 1190 } 1191 1192 /* 1193 * Code for dealing with controls. 1194 */ 1195 1196 static int ov7670_store_cmatrix(struct v4l2_subdev *sd, 1197 int matrix[CMATRIX_LEN]) 1198 { 1199 int i, ret; 1200 unsigned char signbits = 0; 1201 1202 /* 1203 * Weird crap seems to exist in the upper part of 1204 * the sign bits register, so let's preserve it. 1205 */ 1206 ret = ov7670_read(sd, REG_CMATRIX_SIGN, &signbits); 1207 signbits &= 0xc0; 1208 1209 for (i = 0; i < CMATRIX_LEN; i++) { 1210 unsigned char raw; 1211 1212 if (matrix[i] < 0) { 1213 signbits |= (1 << i); 1214 if (matrix[i] < -255) 1215 raw = 0xff; 1216 else 1217 raw = (-1 * matrix[i]) & 0xff; 1218 } 1219 else { 1220 if (matrix[i] > 255) 1221 raw = 0xff; 1222 else 1223 raw = matrix[i] & 0xff; 1224 } 1225 ret += ov7670_write(sd, REG_CMATRIX_BASE + i, raw); 1226 } 1227 ret += ov7670_write(sd, REG_CMATRIX_SIGN, signbits); 1228 return ret; 1229 } 1230 1231 1232 /* 1233 * Hue also requires messing with the color matrix. It also requires 1234 * trig functions, which tend not to be well supported in the kernel. 1235 * So here is a simple table of sine values, 0-90 degrees, in steps 1236 * of five degrees. Values are multiplied by 1000. 1237 * 1238 * The following naive approximate trig functions require an argument 1239 * carefully limited to -180 <= theta <= 180. 1240 */ 1241 #define SIN_STEP 5 1242 static const int ov7670_sin_table[] = { 1243 0, 87, 173, 258, 342, 422, 1244 499, 573, 642, 707, 766, 819, 1245 866, 906, 939, 965, 984, 996, 1246 1000 1247 }; 1248 1249 static int ov7670_sine(int theta) 1250 { 1251 int chs = 1; 1252 int sine; 1253 1254 if (theta < 0) { 1255 theta = -theta; 1256 chs = -1; 1257 } 1258 if (theta <= 90) 1259 sine = ov7670_sin_table[theta/SIN_STEP]; 1260 else { 1261 theta -= 90; 1262 sine = 1000 - ov7670_sin_table[theta/SIN_STEP]; 1263 } 1264 return sine*chs; 1265 } 1266 1267 static int ov7670_cosine(int theta) 1268 { 1269 theta = 90 - theta; 1270 if (theta > 180) 1271 theta -= 360; 1272 else if (theta < -180) 1273 theta += 360; 1274 return ov7670_sine(theta); 1275 } 1276 1277 1278 1279 1280 static void ov7670_calc_cmatrix(struct ov7670_info *info, 1281 int matrix[CMATRIX_LEN], int sat, int hue) 1282 { 1283 int i; 1284 /* 1285 * Apply the current saturation setting first. 1286 */ 1287 for (i = 0; i < CMATRIX_LEN; i++) 1288 matrix[i] = (info->fmt->cmatrix[i] * sat) >> 7; 1289 /* 1290 * Then, if need be, rotate the hue value. 1291 */ 1292 if (hue != 0) { 1293 int sinth, costh, tmpmatrix[CMATRIX_LEN]; 1294 1295 memcpy(tmpmatrix, matrix, CMATRIX_LEN*sizeof(int)); 1296 sinth = ov7670_sine(hue); 1297 costh = ov7670_cosine(hue); 1298 1299 matrix[0] = (matrix[3]*sinth + matrix[0]*costh)/1000; 1300 matrix[1] = (matrix[4]*sinth + matrix[1]*costh)/1000; 1301 matrix[2] = (matrix[5]*sinth + matrix[2]*costh)/1000; 1302 matrix[3] = (matrix[3]*costh - matrix[0]*sinth)/1000; 1303 matrix[4] = (matrix[4]*costh - matrix[1]*sinth)/1000; 1304 matrix[5] = (matrix[5]*costh - matrix[2]*sinth)/1000; 1305 } 1306 } 1307 1308 1309 1310 static int ov7670_s_sat_hue(struct v4l2_subdev *sd, int sat, int hue) 1311 { 1312 struct ov7670_info *info = to_state(sd); 1313 int matrix[CMATRIX_LEN]; 1314 int ret; 1315 1316 ov7670_calc_cmatrix(info, matrix, sat, hue); 1317 ret = ov7670_store_cmatrix(sd, matrix); 1318 return ret; 1319 } 1320 1321 1322 /* 1323 * Some weird registers seem to store values in a sign/magnitude format! 1324 */ 1325 1326 static unsigned char ov7670_abs_to_sm(unsigned char v) 1327 { 1328 if (v > 127) 1329 return v & 0x7f; 1330 return (128 - v) | 0x80; 1331 } 1332 1333 static int ov7670_s_brightness(struct v4l2_subdev *sd, int value) 1334 { 1335 unsigned char com8 = 0, v; 1336 int ret; 1337 1338 ov7670_read(sd, REG_COM8, &com8); 1339 com8 &= ~COM8_AEC; 1340 ov7670_write(sd, REG_COM8, com8); 1341 v = ov7670_abs_to_sm(value); 1342 ret = ov7670_write(sd, REG_BRIGHT, v); 1343 return ret; 1344 } 1345 1346 static int ov7670_s_contrast(struct v4l2_subdev *sd, int value) 1347 { 1348 return ov7670_write(sd, REG_CONTRAS, (unsigned char) value); 1349 } 1350 1351 static int ov7670_s_hflip(struct v4l2_subdev *sd, int value) 1352 { 1353 unsigned char v = 0; 1354 int ret; 1355 1356 ret = ov7670_read(sd, REG_MVFP, &v); 1357 if (value) 1358 v |= MVFP_MIRROR; 1359 else 1360 v &= ~MVFP_MIRROR; 1361 msleep(10); /* FIXME */ 1362 ret += ov7670_write(sd, REG_MVFP, v); 1363 return ret; 1364 } 1365 1366 static int ov7670_s_vflip(struct v4l2_subdev *sd, int value) 1367 { 1368 unsigned char v = 0; 1369 int ret; 1370 1371 ret = ov7670_read(sd, REG_MVFP, &v); 1372 if (value) 1373 v |= MVFP_FLIP; 1374 else 1375 v &= ~MVFP_FLIP; 1376 msleep(10); /* FIXME */ 1377 ret += ov7670_write(sd, REG_MVFP, v); 1378 return ret; 1379 } 1380 1381 /* 1382 * GAIN is split between REG_GAIN and REG_VREF[7:6]. If one believes 1383 * the data sheet, the VREF parts should be the most significant, but 1384 * experience shows otherwise. There seems to be little value in 1385 * messing with the VREF bits, so we leave them alone. 1386 */ 1387 static int ov7670_g_gain(struct v4l2_subdev *sd, __s32 *value) 1388 { 1389 int ret; 1390 unsigned char gain; 1391 1392 ret = ov7670_read(sd, REG_GAIN, &gain); 1393 *value = gain; 1394 return ret; 1395 } 1396 1397 static int ov7670_s_gain(struct v4l2_subdev *sd, int value) 1398 { 1399 int ret; 1400 unsigned char com8; 1401 1402 ret = ov7670_write(sd, REG_GAIN, value & 0xff); 1403 /* Have to turn off AGC as well */ 1404 if (ret == 0) { 1405 ret = ov7670_read(sd, REG_COM8, &com8); 1406 ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AGC); 1407 } 1408 return ret; 1409 } 1410 1411 /* 1412 * Tweak autogain. 1413 */ 1414 static int ov7670_s_autogain(struct v4l2_subdev *sd, int value) 1415 { 1416 int ret; 1417 unsigned char com8; 1418 1419 ret = ov7670_read(sd, REG_COM8, &com8); 1420 if (ret == 0) { 1421 if (value) 1422 com8 |= COM8_AGC; 1423 else 1424 com8 &= ~COM8_AGC; 1425 ret = ov7670_write(sd, REG_COM8, com8); 1426 } 1427 return ret; 1428 } 1429 1430 static int ov7670_s_exp(struct v4l2_subdev *sd, int value) 1431 { 1432 int ret; 1433 unsigned char com1, com8, aech, aechh; 1434 1435 ret = ov7670_read(sd, REG_COM1, &com1) + 1436 ov7670_read(sd, REG_COM8, &com8) + 1437 ov7670_read(sd, REG_AECHH, &aechh); 1438 if (ret) 1439 return ret; 1440 1441 com1 = (com1 & 0xfc) | (value & 0x03); 1442 aech = (value >> 2) & 0xff; 1443 aechh = (aechh & 0xc0) | ((value >> 10) & 0x3f); 1444 ret = ov7670_write(sd, REG_COM1, com1) + 1445 ov7670_write(sd, REG_AECH, aech) + 1446 ov7670_write(sd, REG_AECHH, aechh); 1447 /* Have to turn off AEC as well */ 1448 if (ret == 0) 1449 ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AEC); 1450 return ret; 1451 } 1452 1453 /* 1454 * Tweak autoexposure. 1455 */ 1456 static int ov7670_s_autoexp(struct v4l2_subdev *sd, 1457 enum v4l2_exposure_auto_type value) 1458 { 1459 int ret; 1460 unsigned char com8; 1461 1462 ret = ov7670_read(sd, REG_COM8, &com8); 1463 if (ret == 0) { 1464 if (value == V4L2_EXPOSURE_AUTO) 1465 com8 |= COM8_AEC; 1466 else 1467 com8 &= ~COM8_AEC; 1468 ret = ov7670_write(sd, REG_COM8, com8); 1469 } 1470 return ret; 1471 } 1472 1473 1474 static int ov7670_g_volatile_ctrl(struct v4l2_ctrl *ctrl) 1475 { 1476 struct v4l2_subdev *sd = to_sd(ctrl); 1477 struct ov7670_info *info = to_state(sd); 1478 1479 switch (ctrl->id) { 1480 case V4L2_CID_AUTOGAIN: 1481 return ov7670_g_gain(sd, &info->gain->val); 1482 } 1483 return -EINVAL; 1484 } 1485 1486 static int ov7670_s_ctrl(struct v4l2_ctrl *ctrl) 1487 { 1488 struct v4l2_subdev *sd = to_sd(ctrl); 1489 struct ov7670_info *info = to_state(sd); 1490 1491 switch (ctrl->id) { 1492 case V4L2_CID_BRIGHTNESS: 1493 return ov7670_s_brightness(sd, ctrl->val); 1494 case V4L2_CID_CONTRAST: 1495 return ov7670_s_contrast(sd, ctrl->val); 1496 case V4L2_CID_SATURATION: 1497 return ov7670_s_sat_hue(sd, 1498 info->saturation->val, info->hue->val); 1499 case V4L2_CID_VFLIP: 1500 return ov7670_s_vflip(sd, ctrl->val); 1501 case V4L2_CID_HFLIP: 1502 return ov7670_s_hflip(sd, ctrl->val); 1503 case V4L2_CID_AUTOGAIN: 1504 /* Only set manual gain if auto gain is not explicitly 1505 turned on. */ 1506 if (!ctrl->val) { 1507 /* ov7670_s_gain turns off auto gain */ 1508 return ov7670_s_gain(sd, info->gain->val); 1509 } 1510 return ov7670_s_autogain(sd, ctrl->val); 1511 case V4L2_CID_EXPOSURE_AUTO: 1512 /* Only set manual exposure if auto exposure is not explicitly 1513 turned on. */ 1514 if (ctrl->val == V4L2_EXPOSURE_MANUAL) { 1515 /* ov7670_s_exp turns off auto exposure */ 1516 return ov7670_s_exp(sd, info->exposure->val); 1517 } 1518 return ov7670_s_autoexp(sd, ctrl->val); 1519 } 1520 return -EINVAL; 1521 } 1522 1523 static const struct v4l2_ctrl_ops ov7670_ctrl_ops = { 1524 .s_ctrl = ov7670_s_ctrl, 1525 .g_volatile_ctrl = ov7670_g_volatile_ctrl, 1526 }; 1527 1528 #ifdef CONFIG_VIDEO_ADV_DEBUG 1529 static int ov7670_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) 1530 { 1531 unsigned char val = 0; 1532 int ret; 1533 1534 ret = ov7670_read(sd, reg->reg & 0xff, &val); 1535 reg->val = val; 1536 reg->size = 1; 1537 return ret; 1538 } 1539 1540 static int ov7670_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg) 1541 { 1542 ov7670_write(sd, reg->reg & 0xff, reg->val & 0xff); 1543 return 0; 1544 } 1545 #endif 1546 1547 static int ov7670_s_power(struct v4l2_subdev *sd, int on) 1548 { 1549 struct ov7670_info *info = to_state(sd); 1550 1551 if (info->pwdn_gpio) 1552 gpiod_set_value(info->pwdn_gpio, !on); 1553 if (on && info->resetb_gpio) { 1554 gpiod_set_value(info->resetb_gpio, 1); 1555 usleep_range(500, 1000); 1556 gpiod_set_value(info->resetb_gpio, 0); 1557 usleep_range(3000, 5000); 1558 } 1559 1560 return 0; 1561 } 1562 1563 static void ov7670_get_default_format(struct v4l2_subdev *sd, 1564 struct v4l2_mbus_framefmt *format) 1565 { 1566 struct ov7670_info *info = to_state(sd); 1567 1568 format->width = info->devtype->win_sizes[0].width; 1569 format->height = info->devtype->win_sizes[0].height; 1570 format->colorspace = info->fmt->colorspace; 1571 format->code = info->fmt->mbus_code; 1572 format->field = V4L2_FIELD_NONE; 1573 } 1574 1575 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1576 static int ov7670_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) 1577 { 1578 struct v4l2_mbus_framefmt *format = 1579 v4l2_subdev_get_try_format(sd, fh->pad, 0); 1580 1581 ov7670_get_default_format(sd, format); 1582 1583 return 0; 1584 } 1585 #endif 1586 1587 /* ----------------------------------------------------------------------- */ 1588 1589 static const struct v4l2_subdev_core_ops ov7670_core_ops = { 1590 .reset = ov7670_reset, 1591 .init = ov7670_init, 1592 #ifdef CONFIG_VIDEO_ADV_DEBUG 1593 .g_register = ov7670_g_register, 1594 .s_register = ov7670_s_register, 1595 #endif 1596 }; 1597 1598 static const struct v4l2_subdev_video_ops ov7670_video_ops = { 1599 .s_parm = ov7670_s_parm, 1600 .g_parm = ov7670_g_parm, 1601 }; 1602 1603 static const struct v4l2_subdev_pad_ops ov7670_pad_ops = { 1604 .enum_frame_interval = ov7670_enum_frame_interval, 1605 .enum_frame_size = ov7670_enum_frame_size, 1606 .enum_mbus_code = ov7670_enum_mbus_code, 1607 .get_fmt = ov7670_get_fmt, 1608 .set_fmt = ov7670_set_fmt, 1609 }; 1610 1611 static const struct v4l2_subdev_ops ov7670_ops = { 1612 .core = &ov7670_core_ops, 1613 .video = &ov7670_video_ops, 1614 .pad = &ov7670_pad_ops, 1615 }; 1616 1617 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1618 static const struct v4l2_subdev_internal_ops ov7670_subdev_internal_ops = { 1619 .open = ov7670_open, 1620 }; 1621 #endif 1622 1623 /* ----------------------------------------------------------------------- */ 1624 1625 static const struct ov7670_devtype ov7670_devdata[] = { 1626 [MODEL_OV7670] = { 1627 .win_sizes = ov7670_win_sizes, 1628 .n_win_sizes = ARRAY_SIZE(ov7670_win_sizes), 1629 .set_framerate = ov7670_set_framerate_legacy, 1630 .get_framerate = ov7670_get_framerate_legacy, 1631 }, 1632 [MODEL_OV7675] = { 1633 .win_sizes = ov7675_win_sizes, 1634 .n_win_sizes = ARRAY_SIZE(ov7675_win_sizes), 1635 .set_framerate = ov7675_set_framerate, 1636 .get_framerate = ov7675_get_framerate, 1637 }, 1638 }; 1639 1640 static int ov7670_init_gpio(struct i2c_client *client, struct ov7670_info *info) 1641 { 1642 info->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown", 1643 GPIOD_OUT_LOW); 1644 if (IS_ERR(info->pwdn_gpio)) { 1645 dev_info(&client->dev, "can't get %s GPIO\n", "powerdown"); 1646 return PTR_ERR(info->pwdn_gpio); 1647 } 1648 1649 info->resetb_gpio = devm_gpiod_get_optional(&client->dev, "reset", 1650 GPIOD_OUT_LOW); 1651 if (IS_ERR(info->resetb_gpio)) { 1652 dev_info(&client->dev, "can't get %s GPIO\n", "reset"); 1653 return PTR_ERR(info->resetb_gpio); 1654 } 1655 1656 usleep_range(3000, 5000); 1657 1658 return 0; 1659 } 1660 1661 static int ov7670_probe(struct i2c_client *client, 1662 const struct i2c_device_id *id) 1663 { 1664 struct v4l2_fract tpf; 1665 struct v4l2_subdev *sd; 1666 struct ov7670_info *info; 1667 int ret; 1668 1669 info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL); 1670 if (info == NULL) 1671 return -ENOMEM; 1672 sd = &info->sd; 1673 v4l2_i2c_subdev_init(sd, client, &ov7670_ops); 1674 1675 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1676 sd->internal_ops = &ov7670_subdev_internal_ops; 1677 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1678 #endif 1679 1680 info->clock_speed = 30; /* default: a guess */ 1681 if (client->dev.platform_data) { 1682 struct ov7670_config *config = client->dev.platform_data; 1683 1684 /* 1685 * Must apply configuration before initializing device, because it 1686 * selects I/O method. 1687 */ 1688 info->min_width = config->min_width; 1689 info->min_height = config->min_height; 1690 info->use_smbus = config->use_smbus; 1691 1692 if (config->clock_speed) 1693 info->clock_speed = config->clock_speed; 1694 1695 /* 1696 * It should be allowed for ov7670 too when it is migrated to 1697 * the new frame rate formula. 1698 */ 1699 if (config->pll_bypass && id->driver_data != MODEL_OV7670) 1700 info->pll_bypass = true; 1701 1702 if (config->pclk_hb_disable) 1703 info->pclk_hb_disable = true; 1704 } 1705 1706 info->clk = devm_clk_get(&client->dev, "xclk"); 1707 if (IS_ERR(info->clk)) 1708 return PTR_ERR(info->clk); 1709 ret = clk_prepare_enable(info->clk); 1710 if (ret) 1711 return ret; 1712 1713 info->clock_speed = clk_get_rate(info->clk) / 1000000; 1714 if (info->clock_speed < 10 || info->clock_speed > 48) { 1715 ret = -EINVAL; 1716 goto clk_disable; 1717 } 1718 1719 ret = ov7670_init_gpio(client, info); 1720 if (ret) 1721 goto clk_disable; 1722 1723 ov7670_s_power(sd, 1); 1724 1725 /* Make sure it's an ov7670 */ 1726 ret = ov7670_detect(sd); 1727 if (ret) { 1728 v4l_dbg(1, debug, client, 1729 "chip found @ 0x%x (%s) is not an ov7670 chip.\n", 1730 client->addr << 1, client->adapter->name); 1731 goto power_off; 1732 } 1733 v4l_info(client, "chip found @ 0x%02x (%s)\n", 1734 client->addr << 1, client->adapter->name); 1735 1736 info->devtype = &ov7670_devdata[id->driver_data]; 1737 info->fmt = &ov7670_formats[0]; 1738 1739 ov7670_get_default_format(sd, &info->format); 1740 1741 info->clkrc = 0; 1742 1743 /* Set default frame rate to 30 fps */ 1744 tpf.numerator = 1; 1745 tpf.denominator = 30; 1746 info->devtype->set_framerate(sd, &tpf); 1747 1748 if (info->pclk_hb_disable) 1749 ov7670_write(sd, REG_COM10, COM10_PCLK_HB); 1750 1751 v4l2_ctrl_handler_init(&info->hdl, 10); 1752 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1753 V4L2_CID_BRIGHTNESS, 0, 255, 1, 128); 1754 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1755 V4L2_CID_CONTRAST, 0, 127, 1, 64); 1756 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1757 V4L2_CID_VFLIP, 0, 1, 1, 0); 1758 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1759 V4L2_CID_HFLIP, 0, 1, 1, 0); 1760 info->saturation = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1761 V4L2_CID_SATURATION, 0, 256, 1, 128); 1762 info->hue = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1763 V4L2_CID_HUE, -180, 180, 5, 0); 1764 info->gain = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1765 V4L2_CID_GAIN, 0, 255, 1, 128); 1766 info->auto_gain = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1767 V4L2_CID_AUTOGAIN, 0, 1, 1, 1); 1768 info->exposure = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1769 V4L2_CID_EXPOSURE, 0, 65535, 1, 500); 1770 info->auto_exposure = v4l2_ctrl_new_std_menu(&info->hdl, &ov7670_ctrl_ops, 1771 V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL, 0, 1772 V4L2_EXPOSURE_AUTO); 1773 sd->ctrl_handler = &info->hdl; 1774 if (info->hdl.error) { 1775 ret = info->hdl.error; 1776 1777 goto hdl_free; 1778 } 1779 /* 1780 * We have checked empirically that hw allows to read back the gain 1781 * value chosen by auto gain but that's not the case for auto exposure. 1782 */ 1783 v4l2_ctrl_auto_cluster(2, &info->auto_gain, 0, true); 1784 v4l2_ctrl_auto_cluster(2, &info->auto_exposure, 1785 V4L2_EXPOSURE_MANUAL, false); 1786 v4l2_ctrl_cluster(2, &info->saturation); 1787 1788 #if defined(CONFIG_MEDIA_CONTROLLER) 1789 info->pad.flags = MEDIA_PAD_FL_SOURCE; 1790 info->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1791 ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad); 1792 if (ret < 0) 1793 goto hdl_free; 1794 #endif 1795 1796 v4l2_ctrl_handler_setup(&info->hdl); 1797 1798 ret = v4l2_async_register_subdev(&info->sd); 1799 if (ret < 0) 1800 goto entity_cleanup; 1801 1802 return 0; 1803 1804 entity_cleanup: 1805 #if defined(CONFIG_MEDIA_CONTROLLER) 1806 media_entity_cleanup(&info->sd.entity); 1807 #endif 1808 hdl_free: 1809 v4l2_ctrl_handler_free(&info->hdl); 1810 power_off: 1811 ov7670_s_power(sd, 0); 1812 clk_disable: 1813 clk_disable_unprepare(info->clk); 1814 return ret; 1815 } 1816 1817 1818 static int ov7670_remove(struct i2c_client *client) 1819 { 1820 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1821 struct ov7670_info *info = to_state(sd); 1822 1823 v4l2_device_unregister_subdev(sd); 1824 v4l2_ctrl_handler_free(&info->hdl); 1825 clk_disable_unprepare(info->clk); 1826 #if defined(CONFIG_MEDIA_CONTROLLER) 1827 media_entity_cleanup(&info->sd.entity); 1828 #endif 1829 ov7670_s_power(sd, 0); 1830 return 0; 1831 } 1832 1833 static const struct i2c_device_id ov7670_id[] = { 1834 { "ov7670", MODEL_OV7670 }, 1835 { "ov7675", MODEL_OV7675 }, 1836 { } 1837 }; 1838 MODULE_DEVICE_TABLE(i2c, ov7670_id); 1839 1840 #if IS_ENABLED(CONFIG_OF) 1841 static const struct of_device_id ov7670_of_match[] = { 1842 { .compatible = "ovti,ov7670", }, 1843 { /* sentinel */ }, 1844 }; 1845 MODULE_DEVICE_TABLE(of, ov7670_of_match); 1846 #endif 1847 1848 static struct i2c_driver ov7670_driver = { 1849 .driver = { 1850 .name = "ov7670", 1851 .of_match_table = of_match_ptr(ov7670_of_match), 1852 }, 1853 .probe = ov7670_probe, 1854 .remove = ov7670_remove, 1855 .id_table = ov7670_id, 1856 }; 1857 1858 module_i2c_driver(ov7670_driver); 1859