1 /* 2 * A V4L2 driver for OmniVision OV7670 cameras. 3 * 4 * Copyright 2006 One Laptop Per Child Association, Inc. Written 5 * by Jonathan Corbet with substantial inspiration from Mark 6 * McClelland's ovcamchip code. 7 * 8 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net> 9 * 10 * This file may be distributed under the terms of the GNU General 11 * Public License, version 2. 12 */ 13 #include <linux/clk.h> 14 #include <linux/init.h> 15 #include <linux/module.h> 16 #include <linux/slab.h> 17 #include <linux/i2c.h> 18 #include <linux/delay.h> 19 #include <linux/videodev2.h> 20 #include <linux/gpio.h> 21 #include <linux/gpio/consumer.h> 22 #include <media/v4l2-device.h> 23 #include <media/v4l2-event.h> 24 #include <media/v4l2-ctrls.h> 25 #include <media/v4l2-fwnode.h> 26 #include <media/v4l2-mediabus.h> 27 #include <media/v4l2-image-sizes.h> 28 #include <media/i2c/ov7670.h> 29 30 MODULE_AUTHOR("Jonathan Corbet <corbet@lwn.net>"); 31 MODULE_DESCRIPTION("A low-level driver for OmniVision ov7670 sensors"); 32 MODULE_LICENSE("GPL"); 33 34 static bool debug; 35 module_param(debug, bool, 0644); 36 MODULE_PARM_DESC(debug, "Debug level (0-1)"); 37 38 /* 39 * The 7670 sits on i2c with ID 0x42 40 */ 41 #define OV7670_I2C_ADDR 0x42 42 43 #define PLL_FACTOR 4 44 45 /* Registers */ 46 #define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */ 47 #define REG_BLUE 0x01 /* blue gain */ 48 #define REG_RED 0x02 /* red gain */ 49 #define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */ 50 #define REG_COM1 0x04 /* Control 1 */ 51 #define COM1_CCIR656 0x40 /* CCIR656 enable */ 52 #define REG_BAVE 0x05 /* U/B Average level */ 53 #define REG_GbAVE 0x06 /* Y/Gb Average level */ 54 #define REG_AECHH 0x07 /* AEC MS 5 bits */ 55 #define REG_RAVE 0x08 /* V/R Average level */ 56 #define REG_COM2 0x09 /* Control 2 */ 57 #define COM2_SSLEEP 0x10 /* Soft sleep mode */ 58 #define REG_PID 0x0a /* Product ID MSB */ 59 #define REG_VER 0x0b /* Product ID LSB */ 60 #define REG_COM3 0x0c /* Control 3 */ 61 #define COM3_SWAP 0x40 /* Byte swap */ 62 #define COM3_SCALEEN 0x08 /* Enable scaling */ 63 #define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */ 64 #define REG_COM4 0x0d /* Control 4 */ 65 #define REG_COM5 0x0e /* All "reserved" */ 66 #define REG_COM6 0x0f /* Control 6 */ 67 #define REG_AECH 0x10 /* More bits of AEC value */ 68 #define REG_CLKRC 0x11 /* Clocl control */ 69 #define CLK_EXT 0x40 /* Use external clock directly */ 70 #define CLK_SCALE 0x3f /* Mask for internal clock scale */ 71 #define REG_COM7 0x12 /* Control 7 */ 72 #define COM7_RESET 0x80 /* Register reset */ 73 #define COM7_FMT_MASK 0x38 74 #define COM7_FMT_VGA 0x00 75 #define COM7_FMT_CIF 0x20 /* CIF format */ 76 #define COM7_FMT_QVGA 0x10 /* QVGA format */ 77 #define COM7_FMT_QCIF 0x08 /* QCIF format */ 78 #define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */ 79 #define COM7_YUV 0x00 /* YUV */ 80 #define COM7_BAYER 0x01 /* Bayer format */ 81 #define COM7_PBAYER 0x05 /* "Processed bayer" */ 82 #define REG_COM8 0x13 /* Control 8 */ 83 #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */ 84 #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */ 85 #define COM8_BFILT 0x20 /* Band filter enable */ 86 #define COM8_AGC 0x04 /* Auto gain enable */ 87 #define COM8_AWB 0x02 /* White balance enable */ 88 #define COM8_AEC 0x01 /* Auto exposure enable */ 89 #define REG_COM9 0x14 /* Control 9 - gain ceiling */ 90 #define REG_COM10 0x15 /* Control 10 */ 91 #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */ 92 #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */ 93 #define COM10_HREF_REV 0x08 /* Reverse HREF */ 94 #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */ 95 #define COM10_VS_NEG 0x02 /* VSYNC negative */ 96 #define COM10_HS_NEG 0x01 /* HSYNC negative */ 97 #define REG_HSTART 0x17 /* Horiz start high bits */ 98 #define REG_HSTOP 0x18 /* Horiz stop high bits */ 99 #define REG_VSTART 0x19 /* Vert start high bits */ 100 #define REG_VSTOP 0x1a /* Vert stop high bits */ 101 #define REG_PSHFT 0x1b /* Pixel delay after HREF */ 102 #define REG_MIDH 0x1c /* Manuf. ID high */ 103 #define REG_MIDL 0x1d /* Manuf. ID low */ 104 #define REG_MVFP 0x1e /* Mirror / vflip */ 105 #define MVFP_MIRROR 0x20 /* Mirror image */ 106 #define MVFP_FLIP 0x10 /* Vertical flip */ 107 108 #define REG_AEW 0x24 /* AGC upper limit */ 109 #define REG_AEB 0x25 /* AGC lower limit */ 110 #define REG_VPT 0x26 /* AGC/AEC fast mode op region */ 111 #define REG_HSYST 0x30 /* HSYNC rising edge delay */ 112 #define REG_HSYEN 0x31 /* HSYNC falling edge delay */ 113 #define REG_HREF 0x32 /* HREF pieces */ 114 #define REG_TSLB 0x3a /* lots of stuff */ 115 #define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */ 116 #define REG_COM11 0x3b /* Control 11 */ 117 #define COM11_NIGHT 0x80 /* NIght mode enable */ 118 #define COM11_NMFR 0x60 /* Two bit NM frame rate */ 119 #define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */ 120 #define COM11_50HZ 0x08 /* Manual 50Hz select */ 121 #define COM11_EXP 0x02 122 #define REG_COM12 0x3c /* Control 12 */ 123 #define COM12_HREF 0x80 /* HREF always */ 124 #define REG_COM13 0x3d /* Control 13 */ 125 #define COM13_GAMMA 0x80 /* Gamma enable */ 126 #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */ 127 #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */ 128 #define REG_COM14 0x3e /* Control 14 */ 129 #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */ 130 #define REG_EDGE 0x3f /* Edge enhancement factor */ 131 #define REG_COM15 0x40 /* Control 15 */ 132 #define COM15_R10F0 0x00 /* Data range 10 to F0 */ 133 #define COM15_R01FE 0x80 /* 01 to FE */ 134 #define COM15_R00FF 0xc0 /* 00 to FF */ 135 #define COM15_RGB565 0x10 /* RGB565 output */ 136 #define COM15_RGB555 0x30 /* RGB555 output */ 137 #define REG_COM16 0x41 /* Control 16 */ 138 #define COM16_AWBGAIN 0x08 /* AWB gain enable */ 139 #define REG_COM17 0x42 /* Control 17 */ 140 #define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */ 141 #define COM17_CBAR 0x08 /* DSP Color bar */ 142 143 /* 144 * This matrix defines how the colors are generated, must be 145 * tweaked to adjust hue and saturation. 146 * 147 * Order: v-red, v-green, v-blue, u-red, u-green, u-blue 148 * 149 * They are nine-bit signed quantities, with the sign bit 150 * stored in 0x58. Sign for v-red is bit 0, and up from there. 151 */ 152 #define REG_CMATRIX_BASE 0x4f 153 #define CMATRIX_LEN 6 154 #define REG_CMATRIX_SIGN 0x58 155 156 157 #define REG_BRIGHT 0x55 /* Brightness */ 158 #define REG_CONTRAS 0x56 /* Contrast control */ 159 160 #define REG_GFIX 0x69 /* Fix gain control */ 161 162 #define REG_DBLV 0x6b /* PLL control an debugging */ 163 #define DBLV_BYPASS 0x0a /* Bypass PLL */ 164 #define DBLV_X4 0x4a /* clock x4 */ 165 #define DBLV_X6 0x8a /* clock x6 */ 166 #define DBLV_X8 0xca /* clock x8 */ 167 168 #define REG_SCALING_XSC 0x70 /* Test pattern and horizontal scale factor */ 169 #define TEST_PATTTERN_0 0x80 170 #define REG_SCALING_YSC 0x71 /* Test pattern and vertical scale factor */ 171 #define TEST_PATTTERN_1 0x80 172 173 #define REG_REG76 0x76 /* OV's name */ 174 #define R76_BLKPCOR 0x80 /* Black pixel correction enable */ 175 #define R76_WHTPCOR 0x40 /* White pixel correction enable */ 176 177 #define REG_RGB444 0x8c /* RGB 444 control */ 178 #define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */ 179 #define R444_RGBX 0x01 /* Empty nibble at end */ 180 181 #define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */ 182 #define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */ 183 184 #define REG_BD50MAX 0xa5 /* 50hz banding step limit */ 185 #define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */ 186 #define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */ 187 #define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */ 188 #define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */ 189 #define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */ 190 #define REG_BD60MAX 0xab /* 60hz banding step limit */ 191 192 enum ov7670_model { 193 MODEL_OV7670 = 0, 194 MODEL_OV7675, 195 }; 196 197 struct ov7670_win_size { 198 int width; 199 int height; 200 unsigned char com7_bit; 201 int hstart; /* Start/stop values for the camera. Note */ 202 int hstop; /* that they do not always make complete */ 203 int vstart; /* sense to humans, but evidently the sensor */ 204 int vstop; /* will do the right thing... */ 205 struct regval_list *regs; /* Regs to tweak */ 206 }; 207 208 struct ov7670_devtype { 209 /* formats supported for each model */ 210 struct ov7670_win_size *win_sizes; 211 unsigned int n_win_sizes; 212 /* callbacks for frame rate control */ 213 int (*set_framerate)(struct v4l2_subdev *, struct v4l2_fract *); 214 void (*get_framerate)(struct v4l2_subdev *, struct v4l2_fract *); 215 }; 216 217 /* 218 * Information we maintain about a known sensor. 219 */ 220 struct ov7670_format_struct; /* coming later */ 221 struct ov7670_info { 222 struct v4l2_subdev sd; 223 #if defined(CONFIG_MEDIA_CONTROLLER) 224 struct media_pad pad; 225 #endif 226 struct v4l2_ctrl_handler hdl; 227 struct { 228 /* gain cluster */ 229 struct v4l2_ctrl *auto_gain; 230 struct v4l2_ctrl *gain; 231 }; 232 struct { 233 /* exposure cluster */ 234 struct v4l2_ctrl *auto_exposure; 235 struct v4l2_ctrl *exposure; 236 }; 237 struct { 238 /* saturation/hue cluster */ 239 struct v4l2_ctrl *saturation; 240 struct v4l2_ctrl *hue; 241 }; 242 struct v4l2_mbus_framefmt format; 243 struct ov7670_format_struct *fmt; /* Current format */ 244 struct clk *clk; 245 struct gpio_desc *resetb_gpio; 246 struct gpio_desc *pwdn_gpio; 247 unsigned int mbus_config; /* Media bus configuration flags */ 248 int min_width; /* Filter out smaller sizes */ 249 int min_height; /* Filter out smaller sizes */ 250 int clock_speed; /* External clock speed (MHz) */ 251 u8 clkrc; /* Clock divider value */ 252 bool use_smbus; /* Use smbus I/O instead of I2C */ 253 bool pll_bypass; 254 bool pclk_hb_disable; 255 const struct ov7670_devtype *devtype; /* Device specifics */ 256 }; 257 258 static inline struct ov7670_info *to_state(struct v4l2_subdev *sd) 259 { 260 return container_of(sd, struct ov7670_info, sd); 261 } 262 263 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) 264 { 265 return &container_of(ctrl->handler, struct ov7670_info, hdl)->sd; 266 } 267 268 269 270 /* 271 * The default register settings, as obtained from OmniVision. There 272 * is really no making sense of most of these - lots of "reserved" values 273 * and such. 274 * 275 * These settings give VGA YUYV. 276 */ 277 278 struct regval_list { 279 unsigned char reg_num; 280 unsigned char value; 281 }; 282 283 static struct regval_list ov7670_default_regs[] = { 284 { REG_COM7, COM7_RESET }, 285 /* 286 * Clock scale: 3 = 15fps 287 * 2 = 20fps 288 * 1 = 30fps 289 */ 290 { REG_CLKRC, 0x1 }, /* OV: clock scale (30 fps) */ 291 { REG_TSLB, 0x04 }, /* OV */ 292 { REG_COM7, 0 }, /* VGA */ 293 /* 294 * Set the hardware window. These values from OV don't entirely 295 * make sense - hstop is less than hstart. But they work... 296 */ 297 { REG_HSTART, 0x13 }, { REG_HSTOP, 0x01 }, 298 { REG_HREF, 0xb6 }, { REG_VSTART, 0x02 }, 299 { REG_VSTOP, 0x7a }, { REG_VREF, 0x0a }, 300 301 { REG_COM3, 0 }, { REG_COM14, 0 }, 302 /* Mystery scaling numbers */ 303 { REG_SCALING_XSC, 0x3a }, 304 { REG_SCALING_YSC, 0x35 }, 305 { 0x72, 0x11 }, { 0x73, 0xf0 }, 306 { 0xa2, 0x02 }, { REG_COM10, 0x0 }, 307 308 /* Gamma curve values */ 309 { 0x7a, 0x20 }, { 0x7b, 0x10 }, 310 { 0x7c, 0x1e }, { 0x7d, 0x35 }, 311 { 0x7e, 0x5a }, { 0x7f, 0x69 }, 312 { 0x80, 0x76 }, { 0x81, 0x80 }, 313 { 0x82, 0x88 }, { 0x83, 0x8f }, 314 { 0x84, 0x96 }, { 0x85, 0xa3 }, 315 { 0x86, 0xaf }, { 0x87, 0xc4 }, 316 { 0x88, 0xd7 }, { 0x89, 0xe8 }, 317 318 /* AGC and AEC parameters. Note we start by disabling those features, 319 then turn them only after tweaking the values. */ 320 { REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_BFILT }, 321 { REG_GAIN, 0 }, { REG_AECH, 0 }, 322 { REG_COM4, 0x40 }, /* magic reserved bit */ 323 { REG_COM9, 0x18 }, /* 4x gain + magic rsvd bit */ 324 { REG_BD50MAX, 0x05 }, { REG_BD60MAX, 0x07 }, 325 { REG_AEW, 0x95 }, { REG_AEB, 0x33 }, 326 { REG_VPT, 0xe3 }, { REG_HAECC1, 0x78 }, 327 { REG_HAECC2, 0x68 }, { 0xa1, 0x03 }, /* magic */ 328 { REG_HAECC3, 0xd8 }, { REG_HAECC4, 0xd8 }, 329 { REG_HAECC5, 0xf0 }, { REG_HAECC6, 0x90 }, 330 { REG_HAECC7, 0x94 }, 331 { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC }, 332 333 /* Almost all of these are magic "reserved" values. */ 334 { REG_COM5, 0x61 }, { REG_COM6, 0x4b }, 335 { 0x16, 0x02 }, { REG_MVFP, 0x07 }, 336 { 0x21, 0x02 }, { 0x22, 0x91 }, 337 { 0x29, 0x07 }, { 0x33, 0x0b }, 338 { 0x35, 0x0b }, { 0x37, 0x1d }, 339 { 0x38, 0x71 }, { 0x39, 0x2a }, 340 { REG_COM12, 0x78 }, { 0x4d, 0x40 }, 341 { 0x4e, 0x20 }, { REG_GFIX, 0 }, 342 { 0x6b, 0x4a }, { 0x74, 0x10 }, 343 { 0x8d, 0x4f }, { 0x8e, 0 }, 344 { 0x8f, 0 }, { 0x90, 0 }, 345 { 0x91, 0 }, { 0x96, 0 }, 346 { 0x9a, 0 }, { 0xb0, 0x84 }, 347 { 0xb1, 0x0c }, { 0xb2, 0x0e }, 348 { 0xb3, 0x82 }, { 0xb8, 0x0a }, 349 350 /* More reserved magic, some of which tweaks white balance */ 351 { 0x43, 0x0a }, { 0x44, 0xf0 }, 352 { 0x45, 0x34 }, { 0x46, 0x58 }, 353 { 0x47, 0x28 }, { 0x48, 0x3a }, 354 { 0x59, 0x88 }, { 0x5a, 0x88 }, 355 { 0x5b, 0x44 }, { 0x5c, 0x67 }, 356 { 0x5d, 0x49 }, { 0x5e, 0x0e }, 357 { 0x6c, 0x0a }, { 0x6d, 0x55 }, 358 { 0x6e, 0x11 }, { 0x6f, 0x9f }, /* "9e for advance AWB" */ 359 { 0x6a, 0x40 }, { REG_BLUE, 0x40 }, 360 { REG_RED, 0x60 }, 361 { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC|COM8_AWB }, 362 363 /* Matrix coefficients */ 364 { 0x4f, 0x80 }, { 0x50, 0x80 }, 365 { 0x51, 0 }, { 0x52, 0x22 }, 366 { 0x53, 0x5e }, { 0x54, 0x80 }, 367 { 0x58, 0x9e }, 368 369 { REG_COM16, COM16_AWBGAIN }, { REG_EDGE, 0 }, 370 { 0x75, 0x05 }, { 0x76, 0xe1 }, 371 { 0x4c, 0 }, { 0x77, 0x01 }, 372 { REG_COM13, 0xc3 }, { 0x4b, 0x09 }, 373 { 0xc9, 0x60 }, { REG_COM16, 0x38 }, 374 { 0x56, 0x40 }, 375 376 { 0x34, 0x11 }, { REG_COM11, COM11_EXP|COM11_HZAUTO }, 377 { 0xa4, 0x88 }, { 0x96, 0 }, 378 { 0x97, 0x30 }, { 0x98, 0x20 }, 379 { 0x99, 0x30 }, { 0x9a, 0x84 }, 380 { 0x9b, 0x29 }, { 0x9c, 0x03 }, 381 { 0x9d, 0x4c }, { 0x9e, 0x3f }, 382 { 0x78, 0x04 }, 383 384 /* Extra-weird stuff. Some sort of multiplexor register */ 385 { 0x79, 0x01 }, { 0xc8, 0xf0 }, 386 { 0x79, 0x0f }, { 0xc8, 0x00 }, 387 { 0x79, 0x10 }, { 0xc8, 0x7e }, 388 { 0x79, 0x0a }, { 0xc8, 0x80 }, 389 { 0x79, 0x0b }, { 0xc8, 0x01 }, 390 { 0x79, 0x0c }, { 0xc8, 0x0f }, 391 { 0x79, 0x0d }, { 0xc8, 0x20 }, 392 { 0x79, 0x09 }, { 0xc8, 0x80 }, 393 { 0x79, 0x02 }, { 0xc8, 0xc0 }, 394 { 0x79, 0x03 }, { 0xc8, 0x40 }, 395 { 0x79, 0x05 }, { 0xc8, 0x30 }, 396 { 0x79, 0x26 }, 397 398 { 0xff, 0xff }, /* END MARKER */ 399 }; 400 401 402 /* 403 * Here we'll try to encapsulate the changes for just the output 404 * video format. 405 * 406 * RGB656 and YUV422 come from OV; RGB444 is homebrewed. 407 * 408 * IMPORTANT RULE: the first entry must be for COM7, see ov7670_s_fmt for why. 409 */ 410 411 412 static struct regval_list ov7670_fmt_yuv422[] = { 413 { REG_COM7, 0x0 }, /* Selects YUV mode */ 414 { REG_RGB444, 0 }, /* No RGB444 please */ 415 { REG_COM1, 0 }, /* CCIR601 */ 416 { REG_COM15, COM15_R00FF }, 417 { REG_COM9, 0x48 }, /* 32x gain ceiling; 0x8 is reserved bit */ 418 { 0x4f, 0x80 }, /* "matrix coefficient 1" */ 419 { 0x50, 0x80 }, /* "matrix coefficient 2" */ 420 { 0x51, 0 }, /* vb */ 421 { 0x52, 0x22 }, /* "matrix coefficient 4" */ 422 { 0x53, 0x5e }, /* "matrix coefficient 5" */ 423 { 0x54, 0x80 }, /* "matrix coefficient 6" */ 424 { REG_COM13, COM13_GAMMA|COM13_UVSAT }, 425 { 0xff, 0xff }, 426 }; 427 428 static struct regval_list ov7670_fmt_rgb565[] = { 429 { REG_COM7, COM7_RGB }, /* Selects RGB mode */ 430 { REG_RGB444, 0 }, /* No RGB444 please */ 431 { REG_COM1, 0x0 }, /* CCIR601 */ 432 { REG_COM15, COM15_RGB565 }, 433 { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */ 434 { 0x4f, 0xb3 }, /* "matrix coefficient 1" */ 435 { 0x50, 0xb3 }, /* "matrix coefficient 2" */ 436 { 0x51, 0 }, /* vb */ 437 { 0x52, 0x3d }, /* "matrix coefficient 4" */ 438 { 0x53, 0xa7 }, /* "matrix coefficient 5" */ 439 { 0x54, 0xe4 }, /* "matrix coefficient 6" */ 440 { REG_COM13, COM13_GAMMA|COM13_UVSAT }, 441 { 0xff, 0xff }, 442 }; 443 444 static struct regval_list ov7670_fmt_rgb444[] = { 445 { REG_COM7, COM7_RGB }, /* Selects RGB mode */ 446 { REG_RGB444, R444_ENABLE }, /* Enable xxxxrrrr ggggbbbb */ 447 { REG_COM1, 0x0 }, /* CCIR601 */ 448 { REG_COM15, COM15_R01FE|COM15_RGB565 }, /* Data range needed? */ 449 { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */ 450 { 0x4f, 0xb3 }, /* "matrix coefficient 1" */ 451 { 0x50, 0xb3 }, /* "matrix coefficient 2" */ 452 { 0x51, 0 }, /* vb */ 453 { 0x52, 0x3d }, /* "matrix coefficient 4" */ 454 { 0x53, 0xa7 }, /* "matrix coefficient 5" */ 455 { 0x54, 0xe4 }, /* "matrix coefficient 6" */ 456 { REG_COM13, COM13_GAMMA|COM13_UVSAT|0x2 }, /* Magic rsvd bit */ 457 { 0xff, 0xff }, 458 }; 459 460 static struct regval_list ov7670_fmt_raw[] = { 461 { REG_COM7, COM7_BAYER }, 462 { REG_COM13, 0x08 }, /* No gamma, magic rsvd bit */ 463 { REG_COM16, 0x3d }, /* Edge enhancement, denoise */ 464 { REG_REG76, 0xe1 }, /* Pix correction, magic rsvd */ 465 { 0xff, 0xff }, 466 }; 467 468 469 470 /* 471 * Low-level register I/O. 472 * 473 * Note that there are two versions of these. On the XO 1, the 474 * i2c controller only does SMBUS, so that's what we use. The 475 * ov7670 is not really an SMBUS device, though, so the communication 476 * is not always entirely reliable. 477 */ 478 static int ov7670_read_smbus(struct v4l2_subdev *sd, unsigned char reg, 479 unsigned char *value) 480 { 481 struct i2c_client *client = v4l2_get_subdevdata(sd); 482 int ret; 483 484 ret = i2c_smbus_read_byte_data(client, reg); 485 if (ret >= 0) { 486 *value = (unsigned char)ret; 487 ret = 0; 488 } 489 return ret; 490 } 491 492 493 static int ov7670_write_smbus(struct v4l2_subdev *sd, unsigned char reg, 494 unsigned char value) 495 { 496 struct i2c_client *client = v4l2_get_subdevdata(sd); 497 int ret = i2c_smbus_write_byte_data(client, reg, value); 498 499 if (reg == REG_COM7 && (value & COM7_RESET)) 500 msleep(5); /* Wait for reset to run */ 501 return ret; 502 } 503 504 /* 505 * On most platforms, we'd rather do straight i2c I/O. 506 */ 507 static int ov7670_read_i2c(struct v4l2_subdev *sd, unsigned char reg, 508 unsigned char *value) 509 { 510 struct i2c_client *client = v4l2_get_subdevdata(sd); 511 u8 data = reg; 512 struct i2c_msg msg; 513 int ret; 514 515 /* 516 * Send out the register address... 517 */ 518 msg.addr = client->addr; 519 msg.flags = 0; 520 msg.len = 1; 521 msg.buf = &data; 522 ret = i2c_transfer(client->adapter, &msg, 1); 523 if (ret < 0) { 524 printk(KERN_ERR "Error %d on register write\n", ret); 525 return ret; 526 } 527 /* 528 * ...then read back the result. 529 */ 530 msg.flags = I2C_M_RD; 531 ret = i2c_transfer(client->adapter, &msg, 1); 532 if (ret >= 0) { 533 *value = data; 534 ret = 0; 535 } 536 return ret; 537 } 538 539 540 static int ov7670_write_i2c(struct v4l2_subdev *sd, unsigned char reg, 541 unsigned char value) 542 { 543 struct i2c_client *client = v4l2_get_subdevdata(sd); 544 struct i2c_msg msg; 545 unsigned char data[2] = { reg, value }; 546 int ret; 547 548 msg.addr = client->addr; 549 msg.flags = 0; 550 msg.len = 2; 551 msg.buf = data; 552 ret = i2c_transfer(client->adapter, &msg, 1); 553 if (ret > 0) 554 ret = 0; 555 if (reg == REG_COM7 && (value & COM7_RESET)) 556 msleep(5); /* Wait for reset to run */ 557 return ret; 558 } 559 560 static int ov7670_read(struct v4l2_subdev *sd, unsigned char reg, 561 unsigned char *value) 562 { 563 struct ov7670_info *info = to_state(sd); 564 if (info->use_smbus) 565 return ov7670_read_smbus(sd, reg, value); 566 else 567 return ov7670_read_i2c(sd, reg, value); 568 } 569 570 static int ov7670_write(struct v4l2_subdev *sd, unsigned char reg, 571 unsigned char value) 572 { 573 struct ov7670_info *info = to_state(sd); 574 if (info->use_smbus) 575 return ov7670_write_smbus(sd, reg, value); 576 else 577 return ov7670_write_i2c(sd, reg, value); 578 } 579 580 static int ov7670_update_bits(struct v4l2_subdev *sd, unsigned char reg, 581 unsigned char mask, unsigned char value) 582 { 583 unsigned char orig; 584 int ret; 585 586 ret = ov7670_read(sd, reg, &orig); 587 if (ret) 588 return ret; 589 590 return ov7670_write(sd, reg, (orig & ~mask) | (value & mask)); 591 } 592 593 /* 594 * Write a list of register settings; ff/ff stops the process. 595 */ 596 static int ov7670_write_array(struct v4l2_subdev *sd, struct regval_list *vals) 597 { 598 while (vals->reg_num != 0xff || vals->value != 0xff) { 599 int ret = ov7670_write(sd, vals->reg_num, vals->value); 600 if (ret < 0) 601 return ret; 602 vals++; 603 } 604 return 0; 605 } 606 607 608 /* 609 * Stuff that knows about the sensor. 610 */ 611 static int ov7670_reset(struct v4l2_subdev *sd, u32 val) 612 { 613 ov7670_write(sd, REG_COM7, COM7_RESET); 614 msleep(1); 615 return 0; 616 } 617 618 619 static int ov7670_init(struct v4l2_subdev *sd, u32 val) 620 { 621 return ov7670_write_array(sd, ov7670_default_regs); 622 } 623 624 static int ov7670_detect(struct v4l2_subdev *sd) 625 { 626 unsigned char v; 627 int ret; 628 629 ret = ov7670_init(sd, 0); 630 if (ret < 0) 631 return ret; 632 ret = ov7670_read(sd, REG_MIDH, &v); 633 if (ret < 0) 634 return ret; 635 if (v != 0x7f) /* OV manuf. id. */ 636 return -ENODEV; 637 ret = ov7670_read(sd, REG_MIDL, &v); 638 if (ret < 0) 639 return ret; 640 if (v != 0xa2) 641 return -ENODEV; 642 /* 643 * OK, we know we have an OmniVision chip...but which one? 644 */ 645 ret = ov7670_read(sd, REG_PID, &v); 646 if (ret < 0) 647 return ret; 648 if (v != 0x76) /* PID + VER = 0x76 / 0x73 */ 649 return -ENODEV; 650 ret = ov7670_read(sd, REG_VER, &v); 651 if (ret < 0) 652 return ret; 653 if (v != 0x73) /* PID + VER = 0x76 / 0x73 */ 654 return -ENODEV; 655 return 0; 656 } 657 658 659 /* 660 * Store information about the video data format. The color matrix 661 * is deeply tied into the format, so keep the relevant values here. 662 * The magic matrix numbers come from OmniVision. 663 */ 664 static struct ov7670_format_struct { 665 u32 mbus_code; 666 enum v4l2_colorspace colorspace; 667 struct regval_list *regs; 668 int cmatrix[CMATRIX_LEN]; 669 } ov7670_formats[] = { 670 { 671 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, 672 .colorspace = V4L2_COLORSPACE_SRGB, 673 .regs = ov7670_fmt_yuv422, 674 .cmatrix = { 128, -128, 0, -34, -94, 128 }, 675 }, 676 { 677 .mbus_code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE, 678 .colorspace = V4L2_COLORSPACE_SRGB, 679 .regs = ov7670_fmt_rgb444, 680 .cmatrix = { 179, -179, 0, -61, -176, 228 }, 681 }, 682 { 683 .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE, 684 .colorspace = V4L2_COLORSPACE_SRGB, 685 .regs = ov7670_fmt_rgb565, 686 .cmatrix = { 179, -179, 0, -61, -176, 228 }, 687 }, 688 { 689 .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8, 690 .colorspace = V4L2_COLORSPACE_SRGB, 691 .regs = ov7670_fmt_raw, 692 .cmatrix = { 0, 0, 0, 0, 0, 0 }, 693 }, 694 }; 695 #define N_OV7670_FMTS ARRAY_SIZE(ov7670_formats) 696 697 698 /* 699 * Then there is the issue of window sizes. Try to capture the info here. 700 */ 701 702 /* 703 * QCIF mode is done (by OV) in a very strange way - it actually looks like 704 * VGA with weird scaling options - they do *not* use the canned QCIF mode 705 * which is allegedly provided by the sensor. So here's the weird register 706 * settings. 707 */ 708 static struct regval_list ov7670_qcif_regs[] = { 709 { REG_COM3, COM3_SCALEEN|COM3_DCWEN }, 710 { REG_COM3, COM3_DCWEN }, 711 { REG_COM14, COM14_DCWEN | 0x01}, 712 { 0x73, 0xf1 }, 713 { 0xa2, 0x52 }, 714 { 0x7b, 0x1c }, 715 { 0x7c, 0x28 }, 716 { 0x7d, 0x3c }, 717 { 0x7f, 0x69 }, 718 { REG_COM9, 0x38 }, 719 { 0xa1, 0x0b }, 720 { 0x74, 0x19 }, 721 { 0x9a, 0x80 }, 722 { 0x43, 0x14 }, 723 { REG_COM13, 0xc0 }, 724 { 0xff, 0xff }, 725 }; 726 727 static struct ov7670_win_size ov7670_win_sizes[] = { 728 /* VGA */ 729 { 730 .width = VGA_WIDTH, 731 .height = VGA_HEIGHT, 732 .com7_bit = COM7_FMT_VGA, 733 .hstart = 158, /* These values from */ 734 .hstop = 14, /* Omnivision */ 735 .vstart = 10, 736 .vstop = 490, 737 .regs = NULL, 738 }, 739 /* CIF */ 740 { 741 .width = CIF_WIDTH, 742 .height = CIF_HEIGHT, 743 .com7_bit = COM7_FMT_CIF, 744 .hstart = 170, /* Empirically determined */ 745 .hstop = 90, 746 .vstart = 14, 747 .vstop = 494, 748 .regs = NULL, 749 }, 750 /* QVGA */ 751 { 752 .width = QVGA_WIDTH, 753 .height = QVGA_HEIGHT, 754 .com7_bit = COM7_FMT_QVGA, 755 .hstart = 168, /* Empirically determined */ 756 .hstop = 24, 757 .vstart = 12, 758 .vstop = 492, 759 .regs = NULL, 760 }, 761 /* QCIF */ 762 { 763 .width = QCIF_WIDTH, 764 .height = QCIF_HEIGHT, 765 .com7_bit = COM7_FMT_VGA, /* see comment above */ 766 .hstart = 456, /* Empirically determined */ 767 .hstop = 24, 768 .vstart = 14, 769 .vstop = 494, 770 .regs = ov7670_qcif_regs, 771 } 772 }; 773 774 static struct ov7670_win_size ov7675_win_sizes[] = { 775 /* 776 * Currently, only VGA is supported. Theoretically it could be possible 777 * to support CIF, QVGA and QCIF too. Taking values for ov7670 as a 778 * base and tweak them empirically could be required. 779 */ 780 { 781 .width = VGA_WIDTH, 782 .height = VGA_HEIGHT, 783 .com7_bit = COM7_FMT_VGA, 784 .hstart = 158, /* These values from */ 785 .hstop = 14, /* Omnivision */ 786 .vstart = 14, /* Empirically determined */ 787 .vstop = 494, 788 .regs = NULL, 789 } 790 }; 791 792 static void ov7675_get_framerate(struct v4l2_subdev *sd, 793 struct v4l2_fract *tpf) 794 { 795 struct ov7670_info *info = to_state(sd); 796 u32 clkrc = info->clkrc; 797 int pll_factor; 798 799 if (info->pll_bypass) 800 pll_factor = 1; 801 else 802 pll_factor = PLL_FACTOR; 803 804 clkrc++; 805 if (info->fmt->mbus_code == MEDIA_BUS_FMT_SBGGR8_1X8) 806 clkrc = (clkrc >> 1); 807 808 tpf->numerator = 1; 809 tpf->denominator = (5 * pll_factor * info->clock_speed) / 810 (4 * clkrc); 811 } 812 813 static int ov7675_set_framerate(struct v4l2_subdev *sd, 814 struct v4l2_fract *tpf) 815 { 816 struct ov7670_info *info = to_state(sd); 817 u32 clkrc; 818 int pll_factor; 819 int ret; 820 821 /* 822 * The formula is fps = 5/4*pixclk for YUV/RGB and 823 * fps = 5/2*pixclk for RAW. 824 * 825 * pixclk = clock_speed / (clkrc + 1) * PLLfactor 826 * 827 */ 828 if (info->pll_bypass) { 829 pll_factor = 1; 830 ret = ov7670_write(sd, REG_DBLV, DBLV_BYPASS); 831 } else { 832 pll_factor = PLL_FACTOR; 833 ret = ov7670_write(sd, REG_DBLV, DBLV_X4); 834 } 835 if (ret < 0) 836 return ret; 837 838 if (tpf->numerator == 0 || tpf->denominator == 0) { 839 clkrc = 0; 840 } else { 841 clkrc = (5 * pll_factor * info->clock_speed * tpf->numerator) / 842 (4 * tpf->denominator); 843 if (info->fmt->mbus_code == MEDIA_BUS_FMT_SBGGR8_1X8) 844 clkrc = (clkrc << 1); 845 clkrc--; 846 } 847 848 /* 849 * The datasheet claims that clkrc = 0 will divide the input clock by 1 850 * but we've checked with an oscilloscope that it divides by 2 instead. 851 * So, if clkrc = 0 just bypass the divider. 852 */ 853 if (clkrc <= 0) 854 clkrc = CLK_EXT; 855 else if (clkrc > CLK_SCALE) 856 clkrc = CLK_SCALE; 857 info->clkrc = clkrc; 858 859 /* Recalculate frame rate */ 860 ov7675_get_framerate(sd, tpf); 861 862 ret = ov7670_write(sd, REG_CLKRC, info->clkrc); 863 if (ret < 0) 864 return ret; 865 866 return 0; 867 } 868 869 static void ov7670_get_framerate_legacy(struct v4l2_subdev *sd, 870 struct v4l2_fract *tpf) 871 { 872 struct ov7670_info *info = to_state(sd); 873 874 tpf->numerator = 1; 875 tpf->denominator = info->clock_speed; 876 if ((info->clkrc & CLK_EXT) == 0 && (info->clkrc & CLK_SCALE) > 1) 877 tpf->denominator /= (info->clkrc & CLK_SCALE); 878 } 879 880 static int ov7670_set_framerate_legacy(struct v4l2_subdev *sd, 881 struct v4l2_fract *tpf) 882 { 883 struct ov7670_info *info = to_state(sd); 884 int div; 885 886 if (tpf->numerator == 0 || tpf->denominator == 0) 887 div = 1; /* Reset to full rate */ 888 else 889 div = (tpf->numerator * info->clock_speed) / tpf->denominator; 890 if (div == 0) 891 div = 1; 892 else if (div > CLK_SCALE) 893 div = CLK_SCALE; 894 info->clkrc = (info->clkrc & 0x80) | div; 895 tpf->numerator = 1; 896 tpf->denominator = info->clock_speed / div; 897 return ov7670_write(sd, REG_CLKRC, info->clkrc); 898 } 899 900 /* 901 * Store a set of start/stop values into the camera. 902 */ 903 static int ov7670_set_hw(struct v4l2_subdev *sd, int hstart, int hstop, 904 int vstart, int vstop) 905 { 906 int ret; 907 unsigned char v; 908 /* 909 * Horizontal: 11 bits, top 8 live in hstart and hstop. Bottom 3 of 910 * hstart are in href[2:0], bottom 3 of hstop in href[5:3]. There is 911 * a mystery "edge offset" value in the top two bits of href. 912 */ 913 ret = ov7670_write(sd, REG_HSTART, (hstart >> 3) & 0xff); 914 ret += ov7670_write(sd, REG_HSTOP, (hstop >> 3) & 0xff); 915 ret += ov7670_read(sd, REG_HREF, &v); 916 v = (v & 0xc0) | ((hstop & 0x7) << 3) | (hstart & 0x7); 917 msleep(10); 918 ret += ov7670_write(sd, REG_HREF, v); 919 /* 920 * Vertical: similar arrangement, but only 10 bits. 921 */ 922 ret += ov7670_write(sd, REG_VSTART, (vstart >> 2) & 0xff); 923 ret += ov7670_write(sd, REG_VSTOP, (vstop >> 2) & 0xff); 924 ret += ov7670_read(sd, REG_VREF, &v); 925 v = (v & 0xf0) | ((vstop & 0x3) << 2) | (vstart & 0x3); 926 msleep(10); 927 ret += ov7670_write(sd, REG_VREF, v); 928 return ret; 929 } 930 931 932 static int ov7670_enum_mbus_code(struct v4l2_subdev *sd, 933 struct v4l2_subdev_pad_config *cfg, 934 struct v4l2_subdev_mbus_code_enum *code) 935 { 936 if (code->pad || code->index >= N_OV7670_FMTS) 937 return -EINVAL; 938 939 code->code = ov7670_formats[code->index].mbus_code; 940 return 0; 941 } 942 943 static int ov7670_try_fmt_internal(struct v4l2_subdev *sd, 944 struct v4l2_mbus_framefmt *fmt, 945 struct ov7670_format_struct **ret_fmt, 946 struct ov7670_win_size **ret_wsize) 947 { 948 int index, i; 949 struct ov7670_win_size *wsize; 950 struct ov7670_info *info = to_state(sd); 951 unsigned int n_win_sizes = info->devtype->n_win_sizes; 952 unsigned int win_sizes_limit = n_win_sizes; 953 954 for (index = 0; index < N_OV7670_FMTS; index++) 955 if (ov7670_formats[index].mbus_code == fmt->code) 956 break; 957 if (index >= N_OV7670_FMTS) { 958 /* default to first format */ 959 index = 0; 960 fmt->code = ov7670_formats[0].mbus_code; 961 } 962 if (ret_fmt != NULL) 963 *ret_fmt = ov7670_formats + index; 964 /* 965 * Fields: the OV devices claim to be progressive. 966 */ 967 fmt->field = V4L2_FIELD_NONE; 968 969 /* 970 * Don't consider values that don't match min_height and min_width 971 * constraints. 972 */ 973 if (info->min_width || info->min_height) 974 for (i = 0; i < n_win_sizes; i++) { 975 wsize = info->devtype->win_sizes + i; 976 977 if (wsize->width < info->min_width || 978 wsize->height < info->min_height) { 979 win_sizes_limit = i; 980 break; 981 } 982 } 983 /* 984 * Round requested image size down to the nearest 985 * we support, but not below the smallest. 986 */ 987 for (wsize = info->devtype->win_sizes; 988 wsize < info->devtype->win_sizes + win_sizes_limit; wsize++) 989 if (fmt->width >= wsize->width && fmt->height >= wsize->height) 990 break; 991 if (wsize >= info->devtype->win_sizes + win_sizes_limit) 992 wsize--; /* Take the smallest one */ 993 if (ret_wsize != NULL) 994 *ret_wsize = wsize; 995 /* 996 * Note the size we'll actually handle. 997 */ 998 fmt->width = wsize->width; 999 fmt->height = wsize->height; 1000 fmt->colorspace = ov7670_formats[index].colorspace; 1001 1002 info->format = *fmt; 1003 1004 return 0; 1005 } 1006 1007 /* 1008 * Set a format. 1009 */ 1010 static int ov7670_set_fmt(struct v4l2_subdev *sd, 1011 struct v4l2_subdev_pad_config *cfg, 1012 struct v4l2_subdev_format *format) 1013 { 1014 struct ov7670_format_struct *ovfmt; 1015 struct ov7670_win_size *wsize; 1016 struct ov7670_info *info = to_state(sd); 1017 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1018 struct v4l2_mbus_framefmt *mbus_fmt; 1019 #endif 1020 unsigned char com7, com10 = 0; 1021 int ret; 1022 1023 if (format->pad) 1024 return -EINVAL; 1025 1026 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 1027 ret = ov7670_try_fmt_internal(sd, &format->format, NULL, NULL); 1028 if (ret) 1029 return ret; 1030 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1031 mbus_fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad); 1032 *mbus_fmt = format->format; 1033 return 0; 1034 #else 1035 return -ENOTTY; 1036 #endif 1037 } 1038 1039 ret = ov7670_try_fmt_internal(sd, &format->format, &ovfmt, &wsize); 1040 if (ret) 1041 return ret; 1042 /* 1043 * COM7 is a pain in the ass, it doesn't like to be read then 1044 * quickly written afterward. But we have everything we need 1045 * to set it absolutely here, as long as the format-specific 1046 * register sets list it first. 1047 */ 1048 com7 = ovfmt->regs[0].value; 1049 com7 |= wsize->com7_bit; 1050 ret = ov7670_write(sd, REG_COM7, com7); 1051 if (ret) 1052 return ret; 1053 1054 /* 1055 * Configure the media bus through COM10 register 1056 */ 1057 if (info->mbus_config & V4L2_MBUS_VSYNC_ACTIVE_LOW) 1058 com10 |= COM10_VS_NEG; 1059 if (info->mbus_config & V4L2_MBUS_HSYNC_ACTIVE_LOW) 1060 com10 |= COM10_HREF_REV; 1061 if (info->pclk_hb_disable) 1062 com10 |= COM10_PCLK_HB; 1063 ret = ov7670_write(sd, REG_COM10, com10); 1064 if (ret) 1065 return ret; 1066 1067 /* 1068 * Now write the rest of the array. Also store start/stops 1069 */ 1070 ret = ov7670_write_array(sd, ovfmt->regs + 1); 1071 if (ret) 1072 return ret; 1073 1074 ret = ov7670_set_hw(sd, wsize->hstart, wsize->hstop, wsize->vstart, 1075 wsize->vstop); 1076 if (ret) 1077 return ret; 1078 1079 if (wsize->regs) { 1080 ret = ov7670_write_array(sd, wsize->regs); 1081 if (ret) 1082 return ret; 1083 } 1084 1085 info->fmt = ovfmt; 1086 1087 /* 1088 * If we're running RGB565, we must rewrite clkrc after setting 1089 * the other parameters or the image looks poor. If we're *not* 1090 * doing RGB565, we must not rewrite clkrc or the image looks 1091 * *really* poor. 1092 * 1093 * (Update) Now that we retain clkrc state, we should be able 1094 * to write it unconditionally, and that will make the frame 1095 * rate persistent too. 1096 */ 1097 ret = ov7670_write(sd, REG_CLKRC, info->clkrc); 1098 if (ret) 1099 return ret; 1100 1101 return 0; 1102 } 1103 1104 static int ov7670_get_fmt(struct v4l2_subdev *sd, 1105 struct v4l2_subdev_pad_config *cfg, 1106 struct v4l2_subdev_format *format) 1107 { 1108 struct ov7670_info *info = to_state(sd); 1109 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1110 struct v4l2_mbus_framefmt *mbus_fmt; 1111 #endif 1112 1113 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 1114 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1115 mbus_fmt = v4l2_subdev_get_try_format(sd, cfg, 0); 1116 format->format = *mbus_fmt; 1117 return 0; 1118 #else 1119 return -ENOTTY; 1120 #endif 1121 } else { 1122 format->format = info->format; 1123 } 1124 1125 return 0; 1126 } 1127 1128 /* 1129 * Implement G/S_PARM. There is a "high quality" mode we could try 1130 * to do someday; for now, we just do the frame rate tweak. 1131 */ 1132 static int ov7670_g_frame_interval(struct v4l2_subdev *sd, 1133 struct v4l2_subdev_frame_interval *ival) 1134 { 1135 struct ov7670_info *info = to_state(sd); 1136 1137 1138 info->devtype->get_framerate(sd, &ival->interval); 1139 1140 return 0; 1141 } 1142 1143 static int ov7670_s_frame_interval(struct v4l2_subdev *sd, 1144 struct v4l2_subdev_frame_interval *ival) 1145 { 1146 struct v4l2_fract *tpf = &ival->interval; 1147 struct ov7670_info *info = to_state(sd); 1148 1149 1150 return info->devtype->set_framerate(sd, tpf); 1151 } 1152 1153 1154 /* 1155 * Frame intervals. Since frame rates are controlled with the clock 1156 * divider, we can only do 30/n for integer n values. So no continuous 1157 * or stepwise options. Here we just pick a handful of logical values. 1158 */ 1159 1160 static int ov7670_frame_rates[] = { 30, 15, 10, 5, 1 }; 1161 1162 static int ov7670_enum_frame_interval(struct v4l2_subdev *sd, 1163 struct v4l2_subdev_pad_config *cfg, 1164 struct v4l2_subdev_frame_interval_enum *fie) 1165 { 1166 struct ov7670_info *info = to_state(sd); 1167 unsigned int n_win_sizes = info->devtype->n_win_sizes; 1168 int i; 1169 1170 if (fie->pad) 1171 return -EINVAL; 1172 if (fie->index >= ARRAY_SIZE(ov7670_frame_rates)) 1173 return -EINVAL; 1174 1175 /* 1176 * Check if the width/height is valid. 1177 * 1178 * If a minimum width/height was requested, filter out the capture 1179 * windows that fall outside that. 1180 */ 1181 for (i = 0; i < n_win_sizes; i++) { 1182 struct ov7670_win_size *win = &info->devtype->win_sizes[i]; 1183 1184 if (info->min_width && win->width < info->min_width) 1185 continue; 1186 if (info->min_height && win->height < info->min_height) 1187 continue; 1188 if (fie->width == win->width && fie->height == win->height) 1189 break; 1190 } 1191 if (i == n_win_sizes) 1192 return -EINVAL; 1193 fie->interval.numerator = 1; 1194 fie->interval.denominator = ov7670_frame_rates[fie->index]; 1195 return 0; 1196 } 1197 1198 /* 1199 * Frame size enumeration 1200 */ 1201 static int ov7670_enum_frame_size(struct v4l2_subdev *sd, 1202 struct v4l2_subdev_pad_config *cfg, 1203 struct v4l2_subdev_frame_size_enum *fse) 1204 { 1205 struct ov7670_info *info = to_state(sd); 1206 int i; 1207 int num_valid = -1; 1208 __u32 index = fse->index; 1209 unsigned int n_win_sizes = info->devtype->n_win_sizes; 1210 1211 if (fse->pad) 1212 return -EINVAL; 1213 1214 /* 1215 * If a minimum width/height was requested, filter out the capture 1216 * windows that fall outside that. 1217 */ 1218 for (i = 0; i < n_win_sizes; i++) { 1219 struct ov7670_win_size *win = &info->devtype->win_sizes[i]; 1220 if (info->min_width && win->width < info->min_width) 1221 continue; 1222 if (info->min_height && win->height < info->min_height) 1223 continue; 1224 if (index == ++num_valid) { 1225 fse->min_width = fse->max_width = win->width; 1226 fse->min_height = fse->max_height = win->height; 1227 return 0; 1228 } 1229 } 1230 1231 return -EINVAL; 1232 } 1233 1234 /* 1235 * Code for dealing with controls. 1236 */ 1237 1238 static int ov7670_store_cmatrix(struct v4l2_subdev *sd, 1239 int matrix[CMATRIX_LEN]) 1240 { 1241 int i, ret; 1242 unsigned char signbits = 0; 1243 1244 /* 1245 * Weird crap seems to exist in the upper part of 1246 * the sign bits register, so let's preserve it. 1247 */ 1248 ret = ov7670_read(sd, REG_CMATRIX_SIGN, &signbits); 1249 signbits &= 0xc0; 1250 1251 for (i = 0; i < CMATRIX_LEN; i++) { 1252 unsigned char raw; 1253 1254 if (matrix[i] < 0) { 1255 signbits |= (1 << i); 1256 if (matrix[i] < -255) 1257 raw = 0xff; 1258 else 1259 raw = (-1 * matrix[i]) & 0xff; 1260 } 1261 else { 1262 if (matrix[i] > 255) 1263 raw = 0xff; 1264 else 1265 raw = matrix[i] & 0xff; 1266 } 1267 ret += ov7670_write(sd, REG_CMATRIX_BASE + i, raw); 1268 } 1269 ret += ov7670_write(sd, REG_CMATRIX_SIGN, signbits); 1270 return ret; 1271 } 1272 1273 1274 /* 1275 * Hue also requires messing with the color matrix. It also requires 1276 * trig functions, which tend not to be well supported in the kernel. 1277 * So here is a simple table of sine values, 0-90 degrees, in steps 1278 * of five degrees. Values are multiplied by 1000. 1279 * 1280 * The following naive approximate trig functions require an argument 1281 * carefully limited to -180 <= theta <= 180. 1282 */ 1283 #define SIN_STEP 5 1284 static const int ov7670_sin_table[] = { 1285 0, 87, 173, 258, 342, 422, 1286 499, 573, 642, 707, 766, 819, 1287 866, 906, 939, 965, 984, 996, 1288 1000 1289 }; 1290 1291 static int ov7670_sine(int theta) 1292 { 1293 int chs = 1; 1294 int sine; 1295 1296 if (theta < 0) { 1297 theta = -theta; 1298 chs = -1; 1299 } 1300 if (theta <= 90) 1301 sine = ov7670_sin_table[theta/SIN_STEP]; 1302 else { 1303 theta -= 90; 1304 sine = 1000 - ov7670_sin_table[theta/SIN_STEP]; 1305 } 1306 return sine*chs; 1307 } 1308 1309 static int ov7670_cosine(int theta) 1310 { 1311 theta = 90 - theta; 1312 if (theta > 180) 1313 theta -= 360; 1314 else if (theta < -180) 1315 theta += 360; 1316 return ov7670_sine(theta); 1317 } 1318 1319 1320 1321 1322 static void ov7670_calc_cmatrix(struct ov7670_info *info, 1323 int matrix[CMATRIX_LEN], int sat, int hue) 1324 { 1325 int i; 1326 /* 1327 * Apply the current saturation setting first. 1328 */ 1329 for (i = 0; i < CMATRIX_LEN; i++) 1330 matrix[i] = (info->fmt->cmatrix[i] * sat) >> 7; 1331 /* 1332 * Then, if need be, rotate the hue value. 1333 */ 1334 if (hue != 0) { 1335 int sinth, costh, tmpmatrix[CMATRIX_LEN]; 1336 1337 memcpy(tmpmatrix, matrix, CMATRIX_LEN*sizeof(int)); 1338 sinth = ov7670_sine(hue); 1339 costh = ov7670_cosine(hue); 1340 1341 matrix[0] = (matrix[3]*sinth + matrix[0]*costh)/1000; 1342 matrix[1] = (matrix[4]*sinth + matrix[1]*costh)/1000; 1343 matrix[2] = (matrix[5]*sinth + matrix[2]*costh)/1000; 1344 matrix[3] = (matrix[3]*costh - matrix[0]*sinth)/1000; 1345 matrix[4] = (matrix[4]*costh - matrix[1]*sinth)/1000; 1346 matrix[5] = (matrix[5]*costh - matrix[2]*sinth)/1000; 1347 } 1348 } 1349 1350 1351 1352 static int ov7670_s_sat_hue(struct v4l2_subdev *sd, int sat, int hue) 1353 { 1354 struct ov7670_info *info = to_state(sd); 1355 int matrix[CMATRIX_LEN]; 1356 int ret; 1357 1358 ov7670_calc_cmatrix(info, matrix, sat, hue); 1359 ret = ov7670_store_cmatrix(sd, matrix); 1360 return ret; 1361 } 1362 1363 1364 /* 1365 * Some weird registers seem to store values in a sign/magnitude format! 1366 */ 1367 1368 static unsigned char ov7670_abs_to_sm(unsigned char v) 1369 { 1370 if (v > 127) 1371 return v & 0x7f; 1372 return (128 - v) | 0x80; 1373 } 1374 1375 static int ov7670_s_brightness(struct v4l2_subdev *sd, int value) 1376 { 1377 unsigned char com8 = 0, v; 1378 int ret; 1379 1380 ov7670_read(sd, REG_COM8, &com8); 1381 com8 &= ~COM8_AEC; 1382 ov7670_write(sd, REG_COM8, com8); 1383 v = ov7670_abs_to_sm(value); 1384 ret = ov7670_write(sd, REG_BRIGHT, v); 1385 return ret; 1386 } 1387 1388 static int ov7670_s_contrast(struct v4l2_subdev *sd, int value) 1389 { 1390 return ov7670_write(sd, REG_CONTRAS, (unsigned char) value); 1391 } 1392 1393 static int ov7670_s_hflip(struct v4l2_subdev *sd, int value) 1394 { 1395 unsigned char v = 0; 1396 int ret; 1397 1398 ret = ov7670_read(sd, REG_MVFP, &v); 1399 if (value) 1400 v |= MVFP_MIRROR; 1401 else 1402 v &= ~MVFP_MIRROR; 1403 msleep(10); /* FIXME */ 1404 ret += ov7670_write(sd, REG_MVFP, v); 1405 return ret; 1406 } 1407 1408 static int ov7670_s_vflip(struct v4l2_subdev *sd, int value) 1409 { 1410 unsigned char v = 0; 1411 int ret; 1412 1413 ret = ov7670_read(sd, REG_MVFP, &v); 1414 if (value) 1415 v |= MVFP_FLIP; 1416 else 1417 v &= ~MVFP_FLIP; 1418 msleep(10); /* FIXME */ 1419 ret += ov7670_write(sd, REG_MVFP, v); 1420 return ret; 1421 } 1422 1423 /* 1424 * GAIN is split between REG_GAIN and REG_VREF[7:6]. If one believes 1425 * the data sheet, the VREF parts should be the most significant, but 1426 * experience shows otherwise. There seems to be little value in 1427 * messing with the VREF bits, so we leave them alone. 1428 */ 1429 static int ov7670_g_gain(struct v4l2_subdev *sd, __s32 *value) 1430 { 1431 int ret; 1432 unsigned char gain; 1433 1434 ret = ov7670_read(sd, REG_GAIN, &gain); 1435 *value = gain; 1436 return ret; 1437 } 1438 1439 static int ov7670_s_gain(struct v4l2_subdev *sd, int value) 1440 { 1441 int ret; 1442 unsigned char com8; 1443 1444 ret = ov7670_write(sd, REG_GAIN, value & 0xff); 1445 /* Have to turn off AGC as well */ 1446 if (ret == 0) { 1447 ret = ov7670_read(sd, REG_COM8, &com8); 1448 ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AGC); 1449 } 1450 return ret; 1451 } 1452 1453 /* 1454 * Tweak autogain. 1455 */ 1456 static int ov7670_s_autogain(struct v4l2_subdev *sd, int value) 1457 { 1458 int ret; 1459 unsigned char com8; 1460 1461 ret = ov7670_read(sd, REG_COM8, &com8); 1462 if (ret == 0) { 1463 if (value) 1464 com8 |= COM8_AGC; 1465 else 1466 com8 &= ~COM8_AGC; 1467 ret = ov7670_write(sd, REG_COM8, com8); 1468 } 1469 return ret; 1470 } 1471 1472 static int ov7670_s_exp(struct v4l2_subdev *sd, int value) 1473 { 1474 int ret; 1475 unsigned char com1, com8, aech, aechh; 1476 1477 ret = ov7670_read(sd, REG_COM1, &com1) + 1478 ov7670_read(sd, REG_COM8, &com8) + 1479 ov7670_read(sd, REG_AECHH, &aechh); 1480 if (ret) 1481 return ret; 1482 1483 com1 = (com1 & 0xfc) | (value & 0x03); 1484 aech = (value >> 2) & 0xff; 1485 aechh = (aechh & 0xc0) | ((value >> 10) & 0x3f); 1486 ret = ov7670_write(sd, REG_COM1, com1) + 1487 ov7670_write(sd, REG_AECH, aech) + 1488 ov7670_write(sd, REG_AECHH, aechh); 1489 /* Have to turn off AEC as well */ 1490 if (ret == 0) 1491 ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AEC); 1492 return ret; 1493 } 1494 1495 /* 1496 * Tweak autoexposure. 1497 */ 1498 static int ov7670_s_autoexp(struct v4l2_subdev *sd, 1499 enum v4l2_exposure_auto_type value) 1500 { 1501 int ret; 1502 unsigned char com8; 1503 1504 ret = ov7670_read(sd, REG_COM8, &com8); 1505 if (ret == 0) { 1506 if (value == V4L2_EXPOSURE_AUTO) 1507 com8 |= COM8_AEC; 1508 else 1509 com8 &= ~COM8_AEC; 1510 ret = ov7670_write(sd, REG_COM8, com8); 1511 } 1512 return ret; 1513 } 1514 1515 static const char * const ov7670_test_pattern_menu[] = { 1516 "No test output", 1517 "Shifting \"1\"", 1518 "8-bar color bar", 1519 "Fade to gray color bar", 1520 }; 1521 1522 static int ov7670_s_test_pattern(struct v4l2_subdev *sd, int value) 1523 { 1524 int ret; 1525 1526 ret = ov7670_update_bits(sd, REG_SCALING_XSC, TEST_PATTTERN_0, 1527 value & BIT(0) ? TEST_PATTTERN_0 : 0); 1528 if (ret) 1529 return ret; 1530 1531 return ov7670_update_bits(sd, REG_SCALING_YSC, TEST_PATTTERN_1, 1532 value & BIT(1) ? TEST_PATTTERN_1 : 0); 1533 } 1534 1535 static int ov7670_g_volatile_ctrl(struct v4l2_ctrl *ctrl) 1536 { 1537 struct v4l2_subdev *sd = to_sd(ctrl); 1538 struct ov7670_info *info = to_state(sd); 1539 1540 switch (ctrl->id) { 1541 case V4L2_CID_AUTOGAIN: 1542 return ov7670_g_gain(sd, &info->gain->val); 1543 } 1544 return -EINVAL; 1545 } 1546 1547 static int ov7670_s_ctrl(struct v4l2_ctrl *ctrl) 1548 { 1549 struct v4l2_subdev *sd = to_sd(ctrl); 1550 struct ov7670_info *info = to_state(sd); 1551 1552 switch (ctrl->id) { 1553 case V4L2_CID_BRIGHTNESS: 1554 return ov7670_s_brightness(sd, ctrl->val); 1555 case V4L2_CID_CONTRAST: 1556 return ov7670_s_contrast(sd, ctrl->val); 1557 case V4L2_CID_SATURATION: 1558 return ov7670_s_sat_hue(sd, 1559 info->saturation->val, info->hue->val); 1560 case V4L2_CID_VFLIP: 1561 return ov7670_s_vflip(sd, ctrl->val); 1562 case V4L2_CID_HFLIP: 1563 return ov7670_s_hflip(sd, ctrl->val); 1564 case V4L2_CID_AUTOGAIN: 1565 /* Only set manual gain if auto gain is not explicitly 1566 turned on. */ 1567 if (!ctrl->val) { 1568 /* ov7670_s_gain turns off auto gain */ 1569 return ov7670_s_gain(sd, info->gain->val); 1570 } 1571 return ov7670_s_autogain(sd, ctrl->val); 1572 case V4L2_CID_EXPOSURE_AUTO: 1573 /* Only set manual exposure if auto exposure is not explicitly 1574 turned on. */ 1575 if (ctrl->val == V4L2_EXPOSURE_MANUAL) { 1576 /* ov7670_s_exp turns off auto exposure */ 1577 return ov7670_s_exp(sd, info->exposure->val); 1578 } 1579 return ov7670_s_autoexp(sd, ctrl->val); 1580 case V4L2_CID_TEST_PATTERN: 1581 return ov7670_s_test_pattern(sd, ctrl->val); 1582 } 1583 return -EINVAL; 1584 } 1585 1586 static const struct v4l2_ctrl_ops ov7670_ctrl_ops = { 1587 .s_ctrl = ov7670_s_ctrl, 1588 .g_volatile_ctrl = ov7670_g_volatile_ctrl, 1589 }; 1590 1591 #ifdef CONFIG_VIDEO_ADV_DEBUG 1592 static int ov7670_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) 1593 { 1594 unsigned char val = 0; 1595 int ret; 1596 1597 ret = ov7670_read(sd, reg->reg & 0xff, &val); 1598 reg->val = val; 1599 reg->size = 1; 1600 return ret; 1601 } 1602 1603 static int ov7670_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg) 1604 { 1605 ov7670_write(sd, reg->reg & 0xff, reg->val & 0xff); 1606 return 0; 1607 } 1608 #endif 1609 1610 static int ov7670_s_power(struct v4l2_subdev *sd, int on) 1611 { 1612 struct ov7670_info *info = to_state(sd); 1613 1614 if (info->pwdn_gpio) 1615 gpiod_set_value(info->pwdn_gpio, !on); 1616 if (on && info->resetb_gpio) { 1617 gpiod_set_value(info->resetb_gpio, 1); 1618 usleep_range(500, 1000); 1619 gpiod_set_value(info->resetb_gpio, 0); 1620 usleep_range(3000, 5000); 1621 } 1622 1623 return 0; 1624 } 1625 1626 static void ov7670_get_default_format(struct v4l2_subdev *sd, 1627 struct v4l2_mbus_framefmt *format) 1628 { 1629 struct ov7670_info *info = to_state(sd); 1630 1631 format->width = info->devtype->win_sizes[0].width; 1632 format->height = info->devtype->win_sizes[0].height; 1633 format->colorspace = info->fmt->colorspace; 1634 format->code = info->fmt->mbus_code; 1635 format->field = V4L2_FIELD_NONE; 1636 } 1637 1638 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1639 static int ov7670_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) 1640 { 1641 struct v4l2_mbus_framefmt *format = 1642 v4l2_subdev_get_try_format(sd, fh->pad, 0); 1643 1644 ov7670_get_default_format(sd, format); 1645 1646 return 0; 1647 } 1648 #endif 1649 1650 /* ----------------------------------------------------------------------- */ 1651 1652 static const struct v4l2_subdev_core_ops ov7670_core_ops = { 1653 .reset = ov7670_reset, 1654 .init = ov7670_init, 1655 .log_status = v4l2_ctrl_subdev_log_status, 1656 .subscribe_event = v4l2_ctrl_subdev_subscribe_event, 1657 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 1658 #ifdef CONFIG_VIDEO_ADV_DEBUG 1659 .g_register = ov7670_g_register, 1660 .s_register = ov7670_s_register, 1661 #endif 1662 }; 1663 1664 static const struct v4l2_subdev_video_ops ov7670_video_ops = { 1665 .s_frame_interval = ov7670_s_frame_interval, 1666 .g_frame_interval = ov7670_g_frame_interval, 1667 }; 1668 1669 static const struct v4l2_subdev_pad_ops ov7670_pad_ops = { 1670 .enum_frame_interval = ov7670_enum_frame_interval, 1671 .enum_frame_size = ov7670_enum_frame_size, 1672 .enum_mbus_code = ov7670_enum_mbus_code, 1673 .get_fmt = ov7670_get_fmt, 1674 .set_fmt = ov7670_set_fmt, 1675 }; 1676 1677 static const struct v4l2_subdev_ops ov7670_ops = { 1678 .core = &ov7670_core_ops, 1679 .video = &ov7670_video_ops, 1680 .pad = &ov7670_pad_ops, 1681 }; 1682 1683 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1684 static const struct v4l2_subdev_internal_ops ov7670_subdev_internal_ops = { 1685 .open = ov7670_open, 1686 }; 1687 #endif 1688 1689 /* ----------------------------------------------------------------------- */ 1690 1691 static const struct ov7670_devtype ov7670_devdata[] = { 1692 [MODEL_OV7670] = { 1693 .win_sizes = ov7670_win_sizes, 1694 .n_win_sizes = ARRAY_SIZE(ov7670_win_sizes), 1695 .set_framerate = ov7670_set_framerate_legacy, 1696 .get_framerate = ov7670_get_framerate_legacy, 1697 }, 1698 [MODEL_OV7675] = { 1699 .win_sizes = ov7675_win_sizes, 1700 .n_win_sizes = ARRAY_SIZE(ov7675_win_sizes), 1701 .set_framerate = ov7675_set_framerate, 1702 .get_framerate = ov7675_get_framerate, 1703 }, 1704 }; 1705 1706 static int ov7670_init_gpio(struct i2c_client *client, struct ov7670_info *info) 1707 { 1708 info->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown", 1709 GPIOD_OUT_LOW); 1710 if (IS_ERR(info->pwdn_gpio)) { 1711 dev_info(&client->dev, "can't get %s GPIO\n", "powerdown"); 1712 return PTR_ERR(info->pwdn_gpio); 1713 } 1714 1715 info->resetb_gpio = devm_gpiod_get_optional(&client->dev, "reset", 1716 GPIOD_OUT_LOW); 1717 if (IS_ERR(info->resetb_gpio)) { 1718 dev_info(&client->dev, "can't get %s GPIO\n", "reset"); 1719 return PTR_ERR(info->resetb_gpio); 1720 } 1721 1722 usleep_range(3000, 5000); 1723 1724 return 0; 1725 } 1726 1727 /* 1728 * ov7670_parse_dt() - Parse device tree to collect mbus configuration 1729 * properties 1730 */ 1731 static int ov7670_parse_dt(struct device *dev, 1732 struct ov7670_info *info) 1733 { 1734 struct fwnode_handle *fwnode = dev_fwnode(dev); 1735 struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 }; 1736 struct fwnode_handle *ep; 1737 int ret; 1738 1739 if (!fwnode) 1740 return -EINVAL; 1741 1742 info->pclk_hb_disable = false; 1743 if (fwnode_property_present(fwnode, "ov7670,pclk-hb-disable")) 1744 info->pclk_hb_disable = true; 1745 1746 ep = fwnode_graph_get_next_endpoint(fwnode, NULL); 1747 if (!ep) 1748 return -EINVAL; 1749 1750 ret = v4l2_fwnode_endpoint_parse(ep, &bus_cfg); 1751 fwnode_handle_put(ep); 1752 if (ret) 1753 return ret; 1754 1755 if (bus_cfg.bus_type != V4L2_MBUS_PARALLEL) { 1756 dev_err(dev, "Unsupported media bus type\n"); 1757 return ret; 1758 } 1759 info->mbus_config = bus_cfg.bus.parallel.flags; 1760 1761 return 0; 1762 } 1763 1764 static int ov7670_probe(struct i2c_client *client, 1765 const struct i2c_device_id *id) 1766 { 1767 struct v4l2_fract tpf; 1768 struct v4l2_subdev *sd; 1769 struct ov7670_info *info; 1770 int ret; 1771 1772 info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL); 1773 if (info == NULL) 1774 return -ENOMEM; 1775 sd = &info->sd; 1776 v4l2_i2c_subdev_init(sd, client, &ov7670_ops); 1777 1778 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1779 sd->internal_ops = &ov7670_subdev_internal_ops; 1780 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; 1781 #endif 1782 1783 info->clock_speed = 30; /* default: a guess */ 1784 1785 if (dev_fwnode(&client->dev)) { 1786 ret = ov7670_parse_dt(&client->dev, info); 1787 if (ret) 1788 return ret; 1789 1790 } else if (client->dev.platform_data) { 1791 struct ov7670_config *config = client->dev.platform_data; 1792 1793 /* 1794 * Must apply configuration before initializing device, because it 1795 * selects I/O method. 1796 */ 1797 info->min_width = config->min_width; 1798 info->min_height = config->min_height; 1799 info->use_smbus = config->use_smbus; 1800 1801 if (config->clock_speed) 1802 info->clock_speed = config->clock_speed; 1803 1804 if (config->pll_bypass) 1805 info->pll_bypass = true; 1806 1807 if (config->pclk_hb_disable) 1808 info->pclk_hb_disable = true; 1809 } 1810 1811 info->clk = devm_clk_get(&client->dev, "xclk"); /* optional */ 1812 if (IS_ERR(info->clk)) { 1813 ret = PTR_ERR(info->clk); 1814 if (ret == -ENOENT) 1815 info->clk = NULL; 1816 else 1817 return ret; 1818 } 1819 if (info->clk) { 1820 ret = clk_prepare_enable(info->clk); 1821 if (ret) 1822 return ret; 1823 1824 info->clock_speed = clk_get_rate(info->clk) / 1000000; 1825 if (info->clock_speed < 10 || info->clock_speed > 48) { 1826 ret = -EINVAL; 1827 goto clk_disable; 1828 } 1829 } 1830 1831 ret = ov7670_init_gpio(client, info); 1832 if (ret) 1833 goto clk_disable; 1834 1835 ov7670_s_power(sd, 1); 1836 1837 /* Make sure it's an ov7670 */ 1838 ret = ov7670_detect(sd); 1839 if (ret) { 1840 v4l_dbg(1, debug, client, 1841 "chip found @ 0x%x (%s) is not an ov7670 chip.\n", 1842 client->addr << 1, client->adapter->name); 1843 goto power_off; 1844 } 1845 v4l_info(client, "chip found @ 0x%02x (%s)\n", 1846 client->addr << 1, client->adapter->name); 1847 1848 info->devtype = &ov7670_devdata[id->driver_data]; 1849 info->fmt = &ov7670_formats[0]; 1850 1851 ov7670_get_default_format(sd, &info->format); 1852 1853 info->clkrc = 0; 1854 1855 /* Set default frame rate to 30 fps */ 1856 tpf.numerator = 1; 1857 tpf.denominator = 30; 1858 info->devtype->set_framerate(sd, &tpf); 1859 1860 v4l2_ctrl_handler_init(&info->hdl, 10); 1861 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1862 V4L2_CID_BRIGHTNESS, 0, 255, 1, 128); 1863 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1864 V4L2_CID_CONTRAST, 0, 127, 1, 64); 1865 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1866 V4L2_CID_VFLIP, 0, 1, 1, 0); 1867 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1868 V4L2_CID_HFLIP, 0, 1, 1, 0); 1869 info->saturation = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1870 V4L2_CID_SATURATION, 0, 256, 1, 128); 1871 info->hue = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1872 V4L2_CID_HUE, -180, 180, 5, 0); 1873 info->gain = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1874 V4L2_CID_GAIN, 0, 255, 1, 128); 1875 info->auto_gain = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1876 V4L2_CID_AUTOGAIN, 0, 1, 1, 1); 1877 info->exposure = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1878 V4L2_CID_EXPOSURE, 0, 65535, 1, 500); 1879 info->auto_exposure = v4l2_ctrl_new_std_menu(&info->hdl, &ov7670_ctrl_ops, 1880 V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL, 0, 1881 V4L2_EXPOSURE_AUTO); 1882 v4l2_ctrl_new_std_menu_items(&info->hdl, &ov7670_ctrl_ops, 1883 V4L2_CID_TEST_PATTERN, 1884 ARRAY_SIZE(ov7670_test_pattern_menu) - 1, 0, 0, 1885 ov7670_test_pattern_menu); 1886 sd->ctrl_handler = &info->hdl; 1887 if (info->hdl.error) { 1888 ret = info->hdl.error; 1889 1890 goto hdl_free; 1891 } 1892 /* 1893 * We have checked empirically that hw allows to read back the gain 1894 * value chosen by auto gain but that's not the case for auto exposure. 1895 */ 1896 v4l2_ctrl_auto_cluster(2, &info->auto_gain, 0, true); 1897 v4l2_ctrl_auto_cluster(2, &info->auto_exposure, 1898 V4L2_EXPOSURE_MANUAL, false); 1899 v4l2_ctrl_cluster(2, &info->saturation); 1900 1901 #if defined(CONFIG_MEDIA_CONTROLLER) 1902 info->pad.flags = MEDIA_PAD_FL_SOURCE; 1903 info->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1904 ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad); 1905 if (ret < 0) 1906 goto hdl_free; 1907 #endif 1908 1909 v4l2_ctrl_handler_setup(&info->hdl); 1910 1911 ret = v4l2_async_register_subdev(&info->sd); 1912 if (ret < 0) 1913 goto entity_cleanup; 1914 1915 return 0; 1916 1917 entity_cleanup: 1918 media_entity_cleanup(&info->sd.entity); 1919 hdl_free: 1920 v4l2_ctrl_handler_free(&info->hdl); 1921 power_off: 1922 ov7670_s_power(sd, 0); 1923 clk_disable: 1924 clk_disable_unprepare(info->clk); 1925 return ret; 1926 } 1927 1928 1929 static int ov7670_remove(struct i2c_client *client) 1930 { 1931 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1932 struct ov7670_info *info = to_state(sd); 1933 1934 v4l2_async_unregister_subdev(sd); 1935 v4l2_ctrl_handler_free(&info->hdl); 1936 clk_disable_unprepare(info->clk); 1937 media_entity_cleanup(&info->sd.entity); 1938 ov7670_s_power(sd, 0); 1939 return 0; 1940 } 1941 1942 static const struct i2c_device_id ov7670_id[] = { 1943 { "ov7670", MODEL_OV7670 }, 1944 { "ov7675", MODEL_OV7675 }, 1945 { } 1946 }; 1947 MODULE_DEVICE_TABLE(i2c, ov7670_id); 1948 1949 #if IS_ENABLED(CONFIG_OF) 1950 static const struct of_device_id ov7670_of_match[] = { 1951 { .compatible = "ovti,ov7670", }, 1952 { /* sentinel */ }, 1953 }; 1954 MODULE_DEVICE_TABLE(of, ov7670_of_match); 1955 #endif 1956 1957 static struct i2c_driver ov7670_driver = { 1958 .driver = { 1959 .name = "ov7670", 1960 .of_match_table = of_match_ptr(ov7670_of_match), 1961 }, 1962 .probe = ov7670_probe, 1963 .remove = ov7670_remove, 1964 .id_table = ov7670_id, 1965 }; 1966 1967 module_i2c_driver(ov7670_driver); 1968