1 /* 2 * A V4L2 driver for OmniVision OV7670 cameras. 3 * 4 * Copyright 2006 One Laptop Per Child Association, Inc. Written 5 * by Jonathan Corbet with substantial inspiration from Mark 6 * McClelland's ovcamchip code. 7 * 8 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net> 9 * 10 * This file may be distributed under the terms of the GNU General 11 * Public License, version 2. 12 */ 13 #include <linux/clk.h> 14 #include <linux/init.h> 15 #include <linux/module.h> 16 #include <linux/slab.h> 17 #include <linux/i2c.h> 18 #include <linux/delay.h> 19 #include <linux/videodev2.h> 20 #include <linux/gpio.h> 21 #include <linux/gpio/consumer.h> 22 #include <media/v4l2-device.h> 23 #include <media/v4l2-ctrls.h> 24 #include <media/v4l2-mediabus.h> 25 #include <media/v4l2-image-sizes.h> 26 #include <media/i2c/ov7670.h> 27 28 MODULE_AUTHOR("Jonathan Corbet <corbet@lwn.net>"); 29 MODULE_DESCRIPTION("A low-level driver for OmniVision ov7670 sensors"); 30 MODULE_LICENSE("GPL"); 31 32 static bool debug; 33 module_param(debug, bool, 0644); 34 MODULE_PARM_DESC(debug, "Debug level (0-1)"); 35 36 /* 37 * The 7670 sits on i2c with ID 0x42 38 */ 39 #define OV7670_I2C_ADDR 0x42 40 41 #define PLL_FACTOR 4 42 43 /* Registers */ 44 #define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */ 45 #define REG_BLUE 0x01 /* blue gain */ 46 #define REG_RED 0x02 /* red gain */ 47 #define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */ 48 #define REG_COM1 0x04 /* Control 1 */ 49 #define COM1_CCIR656 0x40 /* CCIR656 enable */ 50 #define REG_BAVE 0x05 /* U/B Average level */ 51 #define REG_GbAVE 0x06 /* Y/Gb Average level */ 52 #define REG_AECHH 0x07 /* AEC MS 5 bits */ 53 #define REG_RAVE 0x08 /* V/R Average level */ 54 #define REG_COM2 0x09 /* Control 2 */ 55 #define COM2_SSLEEP 0x10 /* Soft sleep mode */ 56 #define REG_PID 0x0a /* Product ID MSB */ 57 #define REG_VER 0x0b /* Product ID LSB */ 58 #define REG_COM3 0x0c /* Control 3 */ 59 #define COM3_SWAP 0x40 /* Byte swap */ 60 #define COM3_SCALEEN 0x08 /* Enable scaling */ 61 #define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */ 62 #define REG_COM4 0x0d /* Control 4 */ 63 #define REG_COM5 0x0e /* All "reserved" */ 64 #define REG_COM6 0x0f /* Control 6 */ 65 #define REG_AECH 0x10 /* More bits of AEC value */ 66 #define REG_CLKRC 0x11 /* Clocl control */ 67 #define CLK_EXT 0x40 /* Use external clock directly */ 68 #define CLK_SCALE 0x3f /* Mask for internal clock scale */ 69 #define REG_COM7 0x12 /* Control 7 */ 70 #define COM7_RESET 0x80 /* Register reset */ 71 #define COM7_FMT_MASK 0x38 72 #define COM7_FMT_VGA 0x00 73 #define COM7_FMT_CIF 0x20 /* CIF format */ 74 #define COM7_FMT_QVGA 0x10 /* QVGA format */ 75 #define COM7_FMT_QCIF 0x08 /* QCIF format */ 76 #define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */ 77 #define COM7_YUV 0x00 /* YUV */ 78 #define COM7_BAYER 0x01 /* Bayer format */ 79 #define COM7_PBAYER 0x05 /* "Processed bayer" */ 80 #define REG_COM8 0x13 /* Control 8 */ 81 #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */ 82 #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */ 83 #define COM8_BFILT 0x20 /* Band filter enable */ 84 #define COM8_AGC 0x04 /* Auto gain enable */ 85 #define COM8_AWB 0x02 /* White balance enable */ 86 #define COM8_AEC 0x01 /* Auto exposure enable */ 87 #define REG_COM9 0x14 /* Control 9 - gain ceiling */ 88 #define REG_COM10 0x15 /* Control 10 */ 89 #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */ 90 #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */ 91 #define COM10_HREF_REV 0x08 /* Reverse HREF */ 92 #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */ 93 #define COM10_VS_NEG 0x02 /* VSYNC negative */ 94 #define COM10_HS_NEG 0x01 /* HSYNC negative */ 95 #define REG_HSTART 0x17 /* Horiz start high bits */ 96 #define REG_HSTOP 0x18 /* Horiz stop high bits */ 97 #define REG_VSTART 0x19 /* Vert start high bits */ 98 #define REG_VSTOP 0x1a /* Vert stop high bits */ 99 #define REG_PSHFT 0x1b /* Pixel delay after HREF */ 100 #define REG_MIDH 0x1c /* Manuf. ID high */ 101 #define REG_MIDL 0x1d /* Manuf. ID low */ 102 #define REG_MVFP 0x1e /* Mirror / vflip */ 103 #define MVFP_MIRROR 0x20 /* Mirror image */ 104 #define MVFP_FLIP 0x10 /* Vertical flip */ 105 106 #define REG_AEW 0x24 /* AGC upper limit */ 107 #define REG_AEB 0x25 /* AGC lower limit */ 108 #define REG_VPT 0x26 /* AGC/AEC fast mode op region */ 109 #define REG_HSYST 0x30 /* HSYNC rising edge delay */ 110 #define REG_HSYEN 0x31 /* HSYNC falling edge delay */ 111 #define REG_HREF 0x32 /* HREF pieces */ 112 #define REG_TSLB 0x3a /* lots of stuff */ 113 #define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */ 114 #define REG_COM11 0x3b /* Control 11 */ 115 #define COM11_NIGHT 0x80 /* NIght mode enable */ 116 #define COM11_NMFR 0x60 /* Two bit NM frame rate */ 117 #define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */ 118 #define COM11_50HZ 0x08 /* Manual 50Hz select */ 119 #define COM11_EXP 0x02 120 #define REG_COM12 0x3c /* Control 12 */ 121 #define COM12_HREF 0x80 /* HREF always */ 122 #define REG_COM13 0x3d /* Control 13 */ 123 #define COM13_GAMMA 0x80 /* Gamma enable */ 124 #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */ 125 #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */ 126 #define REG_COM14 0x3e /* Control 14 */ 127 #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */ 128 #define REG_EDGE 0x3f /* Edge enhancement factor */ 129 #define REG_COM15 0x40 /* Control 15 */ 130 #define COM15_R10F0 0x00 /* Data range 10 to F0 */ 131 #define COM15_R01FE 0x80 /* 01 to FE */ 132 #define COM15_R00FF 0xc0 /* 00 to FF */ 133 #define COM15_RGB565 0x10 /* RGB565 output */ 134 #define COM15_RGB555 0x30 /* RGB555 output */ 135 #define REG_COM16 0x41 /* Control 16 */ 136 #define COM16_AWBGAIN 0x08 /* AWB gain enable */ 137 #define REG_COM17 0x42 /* Control 17 */ 138 #define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */ 139 #define COM17_CBAR 0x08 /* DSP Color bar */ 140 141 /* 142 * This matrix defines how the colors are generated, must be 143 * tweaked to adjust hue and saturation. 144 * 145 * Order: v-red, v-green, v-blue, u-red, u-green, u-blue 146 * 147 * They are nine-bit signed quantities, with the sign bit 148 * stored in 0x58. Sign for v-red is bit 0, and up from there. 149 */ 150 #define REG_CMATRIX_BASE 0x4f 151 #define CMATRIX_LEN 6 152 #define REG_CMATRIX_SIGN 0x58 153 154 155 #define REG_BRIGHT 0x55 /* Brightness */ 156 #define REG_CONTRAS 0x56 /* Contrast control */ 157 158 #define REG_GFIX 0x69 /* Fix gain control */ 159 160 #define REG_DBLV 0x6b /* PLL control an debugging */ 161 #define DBLV_BYPASS 0x00 /* Bypass PLL */ 162 #define DBLV_X4 0x01 /* clock x4 */ 163 #define DBLV_X6 0x10 /* clock x6 */ 164 #define DBLV_X8 0x11 /* clock x8 */ 165 166 #define REG_SCALING_XSC 0x70 /* Test pattern and horizontal scale factor */ 167 #define TEST_PATTTERN_0 0x80 168 #define REG_SCALING_YSC 0x71 /* Test pattern and vertical scale factor */ 169 #define TEST_PATTTERN_1 0x80 170 171 #define REG_REG76 0x76 /* OV's name */ 172 #define R76_BLKPCOR 0x80 /* Black pixel correction enable */ 173 #define R76_WHTPCOR 0x40 /* White pixel correction enable */ 174 175 #define REG_RGB444 0x8c /* RGB 444 control */ 176 #define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */ 177 #define R444_RGBX 0x01 /* Empty nibble at end */ 178 179 #define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */ 180 #define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */ 181 182 #define REG_BD50MAX 0xa5 /* 50hz banding step limit */ 183 #define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */ 184 #define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */ 185 #define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */ 186 #define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */ 187 #define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */ 188 #define REG_BD60MAX 0xab /* 60hz banding step limit */ 189 190 enum ov7670_model { 191 MODEL_OV7670 = 0, 192 MODEL_OV7675, 193 }; 194 195 struct ov7670_win_size { 196 int width; 197 int height; 198 unsigned char com7_bit; 199 int hstart; /* Start/stop values for the camera. Note */ 200 int hstop; /* that they do not always make complete */ 201 int vstart; /* sense to humans, but evidently the sensor */ 202 int vstop; /* will do the right thing... */ 203 struct regval_list *regs; /* Regs to tweak */ 204 }; 205 206 struct ov7670_devtype { 207 /* formats supported for each model */ 208 struct ov7670_win_size *win_sizes; 209 unsigned int n_win_sizes; 210 /* callbacks for frame rate control */ 211 int (*set_framerate)(struct v4l2_subdev *, struct v4l2_fract *); 212 void (*get_framerate)(struct v4l2_subdev *, struct v4l2_fract *); 213 }; 214 215 /* 216 * Information we maintain about a known sensor. 217 */ 218 struct ov7670_format_struct; /* coming later */ 219 struct ov7670_info { 220 struct v4l2_subdev sd; 221 #if defined(CONFIG_MEDIA_CONTROLLER) 222 struct media_pad pad; 223 #endif 224 struct v4l2_ctrl_handler hdl; 225 struct { 226 /* gain cluster */ 227 struct v4l2_ctrl *auto_gain; 228 struct v4l2_ctrl *gain; 229 }; 230 struct { 231 /* exposure cluster */ 232 struct v4l2_ctrl *auto_exposure; 233 struct v4l2_ctrl *exposure; 234 }; 235 struct { 236 /* saturation/hue cluster */ 237 struct v4l2_ctrl *saturation; 238 struct v4l2_ctrl *hue; 239 }; 240 struct v4l2_mbus_framefmt format; 241 struct ov7670_format_struct *fmt; /* Current format */ 242 struct clk *clk; 243 struct gpio_desc *resetb_gpio; 244 struct gpio_desc *pwdn_gpio; 245 int min_width; /* Filter out smaller sizes */ 246 int min_height; /* Filter out smaller sizes */ 247 int clock_speed; /* External clock speed (MHz) */ 248 u8 clkrc; /* Clock divider value */ 249 bool use_smbus; /* Use smbus I/O instead of I2C */ 250 bool pll_bypass; 251 bool pclk_hb_disable; 252 const struct ov7670_devtype *devtype; /* Device specifics */ 253 }; 254 255 static inline struct ov7670_info *to_state(struct v4l2_subdev *sd) 256 { 257 return container_of(sd, struct ov7670_info, sd); 258 } 259 260 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) 261 { 262 return &container_of(ctrl->handler, struct ov7670_info, hdl)->sd; 263 } 264 265 266 267 /* 268 * The default register settings, as obtained from OmniVision. There 269 * is really no making sense of most of these - lots of "reserved" values 270 * and such. 271 * 272 * These settings give VGA YUYV. 273 */ 274 275 struct regval_list { 276 unsigned char reg_num; 277 unsigned char value; 278 }; 279 280 static struct regval_list ov7670_default_regs[] = { 281 { REG_COM7, COM7_RESET }, 282 /* 283 * Clock scale: 3 = 15fps 284 * 2 = 20fps 285 * 1 = 30fps 286 */ 287 { REG_CLKRC, 0x1 }, /* OV: clock scale (30 fps) */ 288 { REG_TSLB, 0x04 }, /* OV */ 289 { REG_COM7, 0 }, /* VGA */ 290 /* 291 * Set the hardware window. These values from OV don't entirely 292 * make sense - hstop is less than hstart. But they work... 293 */ 294 { REG_HSTART, 0x13 }, { REG_HSTOP, 0x01 }, 295 { REG_HREF, 0xb6 }, { REG_VSTART, 0x02 }, 296 { REG_VSTOP, 0x7a }, { REG_VREF, 0x0a }, 297 298 { REG_COM3, 0 }, { REG_COM14, 0 }, 299 /* Mystery scaling numbers */ 300 { REG_SCALING_XSC, 0x3a }, 301 { REG_SCALING_YSC, 0x35 }, 302 { 0x72, 0x11 }, { 0x73, 0xf0 }, 303 { 0xa2, 0x02 }, { REG_COM10, 0x0 }, 304 305 /* Gamma curve values */ 306 { 0x7a, 0x20 }, { 0x7b, 0x10 }, 307 { 0x7c, 0x1e }, { 0x7d, 0x35 }, 308 { 0x7e, 0x5a }, { 0x7f, 0x69 }, 309 { 0x80, 0x76 }, { 0x81, 0x80 }, 310 { 0x82, 0x88 }, { 0x83, 0x8f }, 311 { 0x84, 0x96 }, { 0x85, 0xa3 }, 312 { 0x86, 0xaf }, { 0x87, 0xc4 }, 313 { 0x88, 0xd7 }, { 0x89, 0xe8 }, 314 315 /* AGC and AEC parameters. Note we start by disabling those features, 316 then turn them only after tweaking the values. */ 317 { REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_BFILT }, 318 { REG_GAIN, 0 }, { REG_AECH, 0 }, 319 { REG_COM4, 0x40 }, /* magic reserved bit */ 320 { REG_COM9, 0x18 }, /* 4x gain + magic rsvd bit */ 321 { REG_BD50MAX, 0x05 }, { REG_BD60MAX, 0x07 }, 322 { REG_AEW, 0x95 }, { REG_AEB, 0x33 }, 323 { REG_VPT, 0xe3 }, { REG_HAECC1, 0x78 }, 324 { REG_HAECC2, 0x68 }, { 0xa1, 0x03 }, /* magic */ 325 { REG_HAECC3, 0xd8 }, { REG_HAECC4, 0xd8 }, 326 { REG_HAECC5, 0xf0 }, { REG_HAECC6, 0x90 }, 327 { REG_HAECC7, 0x94 }, 328 { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC }, 329 330 /* Almost all of these are magic "reserved" values. */ 331 { REG_COM5, 0x61 }, { REG_COM6, 0x4b }, 332 { 0x16, 0x02 }, { REG_MVFP, 0x07 }, 333 { 0x21, 0x02 }, { 0x22, 0x91 }, 334 { 0x29, 0x07 }, { 0x33, 0x0b }, 335 { 0x35, 0x0b }, { 0x37, 0x1d }, 336 { 0x38, 0x71 }, { 0x39, 0x2a }, 337 { REG_COM12, 0x78 }, { 0x4d, 0x40 }, 338 { 0x4e, 0x20 }, { REG_GFIX, 0 }, 339 { 0x6b, 0x4a }, { 0x74, 0x10 }, 340 { 0x8d, 0x4f }, { 0x8e, 0 }, 341 { 0x8f, 0 }, { 0x90, 0 }, 342 { 0x91, 0 }, { 0x96, 0 }, 343 { 0x9a, 0 }, { 0xb0, 0x84 }, 344 { 0xb1, 0x0c }, { 0xb2, 0x0e }, 345 { 0xb3, 0x82 }, { 0xb8, 0x0a }, 346 347 /* More reserved magic, some of which tweaks white balance */ 348 { 0x43, 0x0a }, { 0x44, 0xf0 }, 349 { 0x45, 0x34 }, { 0x46, 0x58 }, 350 { 0x47, 0x28 }, { 0x48, 0x3a }, 351 { 0x59, 0x88 }, { 0x5a, 0x88 }, 352 { 0x5b, 0x44 }, { 0x5c, 0x67 }, 353 { 0x5d, 0x49 }, { 0x5e, 0x0e }, 354 { 0x6c, 0x0a }, { 0x6d, 0x55 }, 355 { 0x6e, 0x11 }, { 0x6f, 0x9f }, /* "9e for advance AWB" */ 356 { 0x6a, 0x40 }, { REG_BLUE, 0x40 }, 357 { REG_RED, 0x60 }, 358 { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC|COM8_AWB }, 359 360 /* Matrix coefficients */ 361 { 0x4f, 0x80 }, { 0x50, 0x80 }, 362 { 0x51, 0 }, { 0x52, 0x22 }, 363 { 0x53, 0x5e }, { 0x54, 0x80 }, 364 { 0x58, 0x9e }, 365 366 { REG_COM16, COM16_AWBGAIN }, { REG_EDGE, 0 }, 367 { 0x75, 0x05 }, { 0x76, 0xe1 }, 368 { 0x4c, 0 }, { 0x77, 0x01 }, 369 { REG_COM13, 0xc3 }, { 0x4b, 0x09 }, 370 { 0xc9, 0x60 }, { REG_COM16, 0x38 }, 371 { 0x56, 0x40 }, 372 373 { 0x34, 0x11 }, { REG_COM11, COM11_EXP|COM11_HZAUTO }, 374 { 0xa4, 0x88 }, { 0x96, 0 }, 375 { 0x97, 0x30 }, { 0x98, 0x20 }, 376 { 0x99, 0x30 }, { 0x9a, 0x84 }, 377 { 0x9b, 0x29 }, { 0x9c, 0x03 }, 378 { 0x9d, 0x4c }, { 0x9e, 0x3f }, 379 { 0x78, 0x04 }, 380 381 /* Extra-weird stuff. Some sort of multiplexor register */ 382 { 0x79, 0x01 }, { 0xc8, 0xf0 }, 383 { 0x79, 0x0f }, { 0xc8, 0x00 }, 384 { 0x79, 0x10 }, { 0xc8, 0x7e }, 385 { 0x79, 0x0a }, { 0xc8, 0x80 }, 386 { 0x79, 0x0b }, { 0xc8, 0x01 }, 387 { 0x79, 0x0c }, { 0xc8, 0x0f }, 388 { 0x79, 0x0d }, { 0xc8, 0x20 }, 389 { 0x79, 0x09 }, { 0xc8, 0x80 }, 390 { 0x79, 0x02 }, { 0xc8, 0xc0 }, 391 { 0x79, 0x03 }, { 0xc8, 0x40 }, 392 { 0x79, 0x05 }, { 0xc8, 0x30 }, 393 { 0x79, 0x26 }, 394 395 { 0xff, 0xff }, /* END MARKER */ 396 }; 397 398 399 /* 400 * Here we'll try to encapsulate the changes for just the output 401 * video format. 402 * 403 * RGB656 and YUV422 come from OV; RGB444 is homebrewed. 404 * 405 * IMPORTANT RULE: the first entry must be for COM7, see ov7670_s_fmt for why. 406 */ 407 408 409 static struct regval_list ov7670_fmt_yuv422[] = { 410 { REG_COM7, 0x0 }, /* Selects YUV mode */ 411 { REG_RGB444, 0 }, /* No RGB444 please */ 412 { REG_COM1, 0 }, /* CCIR601 */ 413 { REG_COM15, COM15_R00FF }, 414 { REG_COM9, 0x48 }, /* 32x gain ceiling; 0x8 is reserved bit */ 415 { 0x4f, 0x80 }, /* "matrix coefficient 1" */ 416 { 0x50, 0x80 }, /* "matrix coefficient 2" */ 417 { 0x51, 0 }, /* vb */ 418 { 0x52, 0x22 }, /* "matrix coefficient 4" */ 419 { 0x53, 0x5e }, /* "matrix coefficient 5" */ 420 { 0x54, 0x80 }, /* "matrix coefficient 6" */ 421 { REG_COM13, COM13_GAMMA|COM13_UVSAT }, 422 { 0xff, 0xff }, 423 }; 424 425 static struct regval_list ov7670_fmt_rgb565[] = { 426 { REG_COM7, COM7_RGB }, /* Selects RGB mode */ 427 { REG_RGB444, 0 }, /* No RGB444 please */ 428 { REG_COM1, 0x0 }, /* CCIR601 */ 429 { REG_COM15, COM15_RGB565 }, 430 { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */ 431 { 0x4f, 0xb3 }, /* "matrix coefficient 1" */ 432 { 0x50, 0xb3 }, /* "matrix coefficient 2" */ 433 { 0x51, 0 }, /* vb */ 434 { 0x52, 0x3d }, /* "matrix coefficient 4" */ 435 { 0x53, 0xa7 }, /* "matrix coefficient 5" */ 436 { 0x54, 0xe4 }, /* "matrix coefficient 6" */ 437 { REG_COM13, COM13_GAMMA|COM13_UVSAT }, 438 { 0xff, 0xff }, 439 }; 440 441 static struct regval_list ov7670_fmt_rgb444[] = { 442 { REG_COM7, COM7_RGB }, /* Selects RGB mode */ 443 { REG_RGB444, R444_ENABLE }, /* Enable xxxxrrrr ggggbbbb */ 444 { REG_COM1, 0x0 }, /* CCIR601 */ 445 { REG_COM15, COM15_R01FE|COM15_RGB565 }, /* Data range needed? */ 446 { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */ 447 { 0x4f, 0xb3 }, /* "matrix coefficient 1" */ 448 { 0x50, 0xb3 }, /* "matrix coefficient 2" */ 449 { 0x51, 0 }, /* vb */ 450 { 0x52, 0x3d }, /* "matrix coefficient 4" */ 451 { 0x53, 0xa7 }, /* "matrix coefficient 5" */ 452 { 0x54, 0xe4 }, /* "matrix coefficient 6" */ 453 { REG_COM13, COM13_GAMMA|COM13_UVSAT|0x2 }, /* Magic rsvd bit */ 454 { 0xff, 0xff }, 455 }; 456 457 static struct regval_list ov7670_fmt_raw[] = { 458 { REG_COM7, COM7_BAYER }, 459 { REG_COM13, 0x08 }, /* No gamma, magic rsvd bit */ 460 { REG_COM16, 0x3d }, /* Edge enhancement, denoise */ 461 { REG_REG76, 0xe1 }, /* Pix correction, magic rsvd */ 462 { 0xff, 0xff }, 463 }; 464 465 466 467 /* 468 * Low-level register I/O. 469 * 470 * Note that there are two versions of these. On the XO 1, the 471 * i2c controller only does SMBUS, so that's what we use. The 472 * ov7670 is not really an SMBUS device, though, so the communication 473 * is not always entirely reliable. 474 */ 475 static int ov7670_read_smbus(struct v4l2_subdev *sd, unsigned char reg, 476 unsigned char *value) 477 { 478 struct i2c_client *client = v4l2_get_subdevdata(sd); 479 int ret; 480 481 ret = i2c_smbus_read_byte_data(client, reg); 482 if (ret >= 0) { 483 *value = (unsigned char)ret; 484 ret = 0; 485 } 486 return ret; 487 } 488 489 490 static int ov7670_write_smbus(struct v4l2_subdev *sd, unsigned char reg, 491 unsigned char value) 492 { 493 struct i2c_client *client = v4l2_get_subdevdata(sd); 494 int ret = i2c_smbus_write_byte_data(client, reg, value); 495 496 if (reg == REG_COM7 && (value & COM7_RESET)) 497 msleep(5); /* Wait for reset to run */ 498 return ret; 499 } 500 501 /* 502 * On most platforms, we'd rather do straight i2c I/O. 503 */ 504 static int ov7670_read_i2c(struct v4l2_subdev *sd, unsigned char reg, 505 unsigned char *value) 506 { 507 struct i2c_client *client = v4l2_get_subdevdata(sd); 508 u8 data = reg; 509 struct i2c_msg msg; 510 int ret; 511 512 /* 513 * Send out the register address... 514 */ 515 msg.addr = client->addr; 516 msg.flags = 0; 517 msg.len = 1; 518 msg.buf = &data; 519 ret = i2c_transfer(client->adapter, &msg, 1); 520 if (ret < 0) { 521 printk(KERN_ERR "Error %d on register write\n", ret); 522 return ret; 523 } 524 /* 525 * ...then read back the result. 526 */ 527 msg.flags = I2C_M_RD; 528 ret = i2c_transfer(client->adapter, &msg, 1); 529 if (ret >= 0) { 530 *value = data; 531 ret = 0; 532 } 533 return ret; 534 } 535 536 537 static int ov7670_write_i2c(struct v4l2_subdev *sd, unsigned char reg, 538 unsigned char value) 539 { 540 struct i2c_client *client = v4l2_get_subdevdata(sd); 541 struct i2c_msg msg; 542 unsigned char data[2] = { reg, value }; 543 int ret; 544 545 msg.addr = client->addr; 546 msg.flags = 0; 547 msg.len = 2; 548 msg.buf = data; 549 ret = i2c_transfer(client->adapter, &msg, 1); 550 if (ret > 0) 551 ret = 0; 552 if (reg == REG_COM7 && (value & COM7_RESET)) 553 msleep(5); /* Wait for reset to run */ 554 return ret; 555 } 556 557 static int ov7670_read(struct v4l2_subdev *sd, unsigned char reg, 558 unsigned char *value) 559 { 560 struct ov7670_info *info = to_state(sd); 561 if (info->use_smbus) 562 return ov7670_read_smbus(sd, reg, value); 563 else 564 return ov7670_read_i2c(sd, reg, value); 565 } 566 567 static int ov7670_write(struct v4l2_subdev *sd, unsigned char reg, 568 unsigned char value) 569 { 570 struct ov7670_info *info = to_state(sd); 571 if (info->use_smbus) 572 return ov7670_write_smbus(sd, reg, value); 573 else 574 return ov7670_write_i2c(sd, reg, value); 575 } 576 577 static int ov7670_update_bits(struct v4l2_subdev *sd, unsigned char reg, 578 unsigned char mask, unsigned char value) 579 { 580 unsigned char orig; 581 int ret; 582 583 ret = ov7670_read(sd, reg, &orig); 584 if (ret) 585 return ret; 586 587 return ov7670_write(sd, reg, (orig & ~mask) | (value & mask)); 588 } 589 590 /* 591 * Write a list of register settings; ff/ff stops the process. 592 */ 593 static int ov7670_write_array(struct v4l2_subdev *sd, struct regval_list *vals) 594 { 595 while (vals->reg_num != 0xff || vals->value != 0xff) { 596 int ret = ov7670_write(sd, vals->reg_num, vals->value); 597 if (ret < 0) 598 return ret; 599 vals++; 600 } 601 return 0; 602 } 603 604 605 /* 606 * Stuff that knows about the sensor. 607 */ 608 static int ov7670_reset(struct v4l2_subdev *sd, u32 val) 609 { 610 ov7670_write(sd, REG_COM7, COM7_RESET); 611 msleep(1); 612 return 0; 613 } 614 615 616 static int ov7670_init(struct v4l2_subdev *sd, u32 val) 617 { 618 return ov7670_write_array(sd, ov7670_default_regs); 619 } 620 621 static int ov7670_detect(struct v4l2_subdev *sd) 622 { 623 unsigned char v; 624 int ret; 625 626 ret = ov7670_init(sd, 0); 627 if (ret < 0) 628 return ret; 629 ret = ov7670_read(sd, REG_MIDH, &v); 630 if (ret < 0) 631 return ret; 632 if (v != 0x7f) /* OV manuf. id. */ 633 return -ENODEV; 634 ret = ov7670_read(sd, REG_MIDL, &v); 635 if (ret < 0) 636 return ret; 637 if (v != 0xa2) 638 return -ENODEV; 639 /* 640 * OK, we know we have an OmniVision chip...but which one? 641 */ 642 ret = ov7670_read(sd, REG_PID, &v); 643 if (ret < 0) 644 return ret; 645 if (v != 0x76) /* PID + VER = 0x76 / 0x73 */ 646 return -ENODEV; 647 ret = ov7670_read(sd, REG_VER, &v); 648 if (ret < 0) 649 return ret; 650 if (v != 0x73) /* PID + VER = 0x76 / 0x73 */ 651 return -ENODEV; 652 return 0; 653 } 654 655 656 /* 657 * Store information about the video data format. The color matrix 658 * is deeply tied into the format, so keep the relevant values here. 659 * The magic matrix numbers come from OmniVision. 660 */ 661 static struct ov7670_format_struct { 662 u32 mbus_code; 663 enum v4l2_colorspace colorspace; 664 struct regval_list *regs; 665 int cmatrix[CMATRIX_LEN]; 666 } ov7670_formats[] = { 667 { 668 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, 669 .colorspace = V4L2_COLORSPACE_SRGB, 670 .regs = ov7670_fmt_yuv422, 671 .cmatrix = { 128, -128, 0, -34, -94, 128 }, 672 }, 673 { 674 .mbus_code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE, 675 .colorspace = V4L2_COLORSPACE_SRGB, 676 .regs = ov7670_fmt_rgb444, 677 .cmatrix = { 179, -179, 0, -61, -176, 228 }, 678 }, 679 { 680 .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE, 681 .colorspace = V4L2_COLORSPACE_SRGB, 682 .regs = ov7670_fmt_rgb565, 683 .cmatrix = { 179, -179, 0, -61, -176, 228 }, 684 }, 685 { 686 .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8, 687 .colorspace = V4L2_COLORSPACE_SRGB, 688 .regs = ov7670_fmt_raw, 689 .cmatrix = { 0, 0, 0, 0, 0, 0 }, 690 }, 691 }; 692 #define N_OV7670_FMTS ARRAY_SIZE(ov7670_formats) 693 694 695 /* 696 * Then there is the issue of window sizes. Try to capture the info here. 697 */ 698 699 /* 700 * QCIF mode is done (by OV) in a very strange way - it actually looks like 701 * VGA with weird scaling options - they do *not* use the canned QCIF mode 702 * which is allegedly provided by the sensor. So here's the weird register 703 * settings. 704 */ 705 static struct regval_list ov7670_qcif_regs[] = { 706 { REG_COM3, COM3_SCALEEN|COM3_DCWEN }, 707 { REG_COM3, COM3_DCWEN }, 708 { REG_COM14, COM14_DCWEN | 0x01}, 709 { 0x73, 0xf1 }, 710 { 0xa2, 0x52 }, 711 { 0x7b, 0x1c }, 712 { 0x7c, 0x28 }, 713 { 0x7d, 0x3c }, 714 { 0x7f, 0x69 }, 715 { REG_COM9, 0x38 }, 716 { 0xa1, 0x0b }, 717 { 0x74, 0x19 }, 718 { 0x9a, 0x80 }, 719 { 0x43, 0x14 }, 720 { REG_COM13, 0xc0 }, 721 { 0xff, 0xff }, 722 }; 723 724 static struct ov7670_win_size ov7670_win_sizes[] = { 725 /* VGA */ 726 { 727 .width = VGA_WIDTH, 728 .height = VGA_HEIGHT, 729 .com7_bit = COM7_FMT_VGA, 730 .hstart = 158, /* These values from */ 731 .hstop = 14, /* Omnivision */ 732 .vstart = 10, 733 .vstop = 490, 734 .regs = NULL, 735 }, 736 /* CIF */ 737 { 738 .width = CIF_WIDTH, 739 .height = CIF_HEIGHT, 740 .com7_bit = COM7_FMT_CIF, 741 .hstart = 170, /* Empirically determined */ 742 .hstop = 90, 743 .vstart = 14, 744 .vstop = 494, 745 .regs = NULL, 746 }, 747 /* QVGA */ 748 { 749 .width = QVGA_WIDTH, 750 .height = QVGA_HEIGHT, 751 .com7_bit = COM7_FMT_QVGA, 752 .hstart = 168, /* Empirically determined */ 753 .hstop = 24, 754 .vstart = 12, 755 .vstop = 492, 756 .regs = NULL, 757 }, 758 /* QCIF */ 759 { 760 .width = QCIF_WIDTH, 761 .height = QCIF_HEIGHT, 762 .com7_bit = COM7_FMT_VGA, /* see comment above */ 763 .hstart = 456, /* Empirically determined */ 764 .hstop = 24, 765 .vstart = 14, 766 .vstop = 494, 767 .regs = ov7670_qcif_regs, 768 } 769 }; 770 771 static struct ov7670_win_size ov7675_win_sizes[] = { 772 /* 773 * Currently, only VGA is supported. Theoretically it could be possible 774 * to support CIF, QVGA and QCIF too. Taking values for ov7670 as a 775 * base and tweak them empirically could be required. 776 */ 777 { 778 .width = VGA_WIDTH, 779 .height = VGA_HEIGHT, 780 .com7_bit = COM7_FMT_VGA, 781 .hstart = 158, /* These values from */ 782 .hstop = 14, /* Omnivision */ 783 .vstart = 14, /* Empirically determined */ 784 .vstop = 494, 785 .regs = NULL, 786 } 787 }; 788 789 static void ov7675_get_framerate(struct v4l2_subdev *sd, 790 struct v4l2_fract *tpf) 791 { 792 struct ov7670_info *info = to_state(sd); 793 u32 clkrc = info->clkrc; 794 int pll_factor; 795 796 if (info->pll_bypass) 797 pll_factor = 1; 798 else 799 pll_factor = PLL_FACTOR; 800 801 clkrc++; 802 if (info->fmt->mbus_code == MEDIA_BUS_FMT_SBGGR8_1X8) 803 clkrc = (clkrc >> 1); 804 805 tpf->numerator = 1; 806 tpf->denominator = (5 * pll_factor * info->clock_speed) / 807 (4 * clkrc); 808 } 809 810 static int ov7675_set_framerate(struct v4l2_subdev *sd, 811 struct v4l2_fract *tpf) 812 { 813 struct ov7670_info *info = to_state(sd); 814 u32 clkrc; 815 int pll_factor; 816 int ret; 817 818 /* 819 * The formula is fps = 5/4*pixclk for YUV/RGB and 820 * fps = 5/2*pixclk for RAW. 821 * 822 * pixclk = clock_speed / (clkrc + 1) * PLLfactor 823 * 824 */ 825 if (info->pll_bypass) { 826 pll_factor = 1; 827 ret = ov7670_write(sd, REG_DBLV, DBLV_BYPASS); 828 } else { 829 pll_factor = PLL_FACTOR; 830 ret = ov7670_write(sd, REG_DBLV, DBLV_X4); 831 } 832 if (ret < 0) 833 return ret; 834 835 if (tpf->numerator == 0 || tpf->denominator == 0) { 836 clkrc = 0; 837 } else { 838 clkrc = (5 * pll_factor * info->clock_speed * tpf->numerator) / 839 (4 * tpf->denominator); 840 if (info->fmt->mbus_code == MEDIA_BUS_FMT_SBGGR8_1X8) 841 clkrc = (clkrc << 1); 842 clkrc--; 843 } 844 845 /* 846 * The datasheet claims that clkrc = 0 will divide the input clock by 1 847 * but we've checked with an oscilloscope that it divides by 2 instead. 848 * So, if clkrc = 0 just bypass the divider. 849 */ 850 if (clkrc <= 0) 851 clkrc = CLK_EXT; 852 else if (clkrc > CLK_SCALE) 853 clkrc = CLK_SCALE; 854 info->clkrc = clkrc; 855 856 /* Recalculate frame rate */ 857 ov7675_get_framerate(sd, tpf); 858 859 ret = ov7670_write(sd, REG_CLKRC, info->clkrc); 860 if (ret < 0) 861 return ret; 862 863 return ov7670_write(sd, REG_DBLV, DBLV_X4); 864 } 865 866 static void ov7670_get_framerate_legacy(struct v4l2_subdev *sd, 867 struct v4l2_fract *tpf) 868 { 869 struct ov7670_info *info = to_state(sd); 870 871 tpf->numerator = 1; 872 tpf->denominator = info->clock_speed; 873 if ((info->clkrc & CLK_EXT) == 0 && (info->clkrc & CLK_SCALE) > 1) 874 tpf->denominator /= (info->clkrc & CLK_SCALE); 875 } 876 877 static int ov7670_set_framerate_legacy(struct v4l2_subdev *sd, 878 struct v4l2_fract *tpf) 879 { 880 struct ov7670_info *info = to_state(sd); 881 int div; 882 883 if (tpf->numerator == 0 || tpf->denominator == 0) 884 div = 1; /* Reset to full rate */ 885 else 886 div = (tpf->numerator * info->clock_speed) / tpf->denominator; 887 if (div == 0) 888 div = 1; 889 else if (div > CLK_SCALE) 890 div = CLK_SCALE; 891 info->clkrc = (info->clkrc & 0x80) | div; 892 tpf->numerator = 1; 893 tpf->denominator = info->clock_speed / div; 894 return ov7670_write(sd, REG_CLKRC, info->clkrc); 895 } 896 897 /* 898 * Store a set of start/stop values into the camera. 899 */ 900 static int ov7670_set_hw(struct v4l2_subdev *sd, int hstart, int hstop, 901 int vstart, int vstop) 902 { 903 int ret; 904 unsigned char v; 905 /* 906 * Horizontal: 11 bits, top 8 live in hstart and hstop. Bottom 3 of 907 * hstart are in href[2:0], bottom 3 of hstop in href[5:3]. There is 908 * a mystery "edge offset" value in the top two bits of href. 909 */ 910 ret = ov7670_write(sd, REG_HSTART, (hstart >> 3) & 0xff); 911 ret += ov7670_write(sd, REG_HSTOP, (hstop >> 3) & 0xff); 912 ret += ov7670_read(sd, REG_HREF, &v); 913 v = (v & 0xc0) | ((hstop & 0x7) << 3) | (hstart & 0x7); 914 msleep(10); 915 ret += ov7670_write(sd, REG_HREF, v); 916 /* 917 * Vertical: similar arrangement, but only 10 bits. 918 */ 919 ret += ov7670_write(sd, REG_VSTART, (vstart >> 2) & 0xff); 920 ret += ov7670_write(sd, REG_VSTOP, (vstop >> 2) & 0xff); 921 ret += ov7670_read(sd, REG_VREF, &v); 922 v = (v & 0xf0) | ((vstop & 0x3) << 2) | (vstart & 0x3); 923 msleep(10); 924 ret += ov7670_write(sd, REG_VREF, v); 925 return ret; 926 } 927 928 929 static int ov7670_enum_mbus_code(struct v4l2_subdev *sd, 930 struct v4l2_subdev_pad_config *cfg, 931 struct v4l2_subdev_mbus_code_enum *code) 932 { 933 if (code->pad || code->index >= N_OV7670_FMTS) 934 return -EINVAL; 935 936 code->code = ov7670_formats[code->index].mbus_code; 937 return 0; 938 } 939 940 static int ov7670_try_fmt_internal(struct v4l2_subdev *sd, 941 struct v4l2_mbus_framefmt *fmt, 942 struct ov7670_format_struct **ret_fmt, 943 struct ov7670_win_size **ret_wsize) 944 { 945 int index, i; 946 struct ov7670_win_size *wsize; 947 struct ov7670_info *info = to_state(sd); 948 unsigned int n_win_sizes = info->devtype->n_win_sizes; 949 unsigned int win_sizes_limit = n_win_sizes; 950 951 for (index = 0; index < N_OV7670_FMTS; index++) 952 if (ov7670_formats[index].mbus_code == fmt->code) 953 break; 954 if (index >= N_OV7670_FMTS) { 955 /* default to first format */ 956 index = 0; 957 fmt->code = ov7670_formats[0].mbus_code; 958 } 959 if (ret_fmt != NULL) 960 *ret_fmt = ov7670_formats + index; 961 /* 962 * Fields: the OV devices claim to be progressive. 963 */ 964 fmt->field = V4L2_FIELD_NONE; 965 966 /* 967 * Don't consider values that don't match min_height and min_width 968 * constraints. 969 */ 970 if (info->min_width || info->min_height) 971 for (i = 0; i < n_win_sizes; i++) { 972 wsize = info->devtype->win_sizes + i; 973 974 if (wsize->width < info->min_width || 975 wsize->height < info->min_height) { 976 win_sizes_limit = i; 977 break; 978 } 979 } 980 /* 981 * Round requested image size down to the nearest 982 * we support, but not below the smallest. 983 */ 984 for (wsize = info->devtype->win_sizes; 985 wsize < info->devtype->win_sizes + win_sizes_limit; wsize++) 986 if (fmt->width >= wsize->width && fmt->height >= wsize->height) 987 break; 988 if (wsize >= info->devtype->win_sizes + win_sizes_limit) 989 wsize--; /* Take the smallest one */ 990 if (ret_wsize != NULL) 991 *ret_wsize = wsize; 992 /* 993 * Note the size we'll actually handle. 994 */ 995 fmt->width = wsize->width; 996 fmt->height = wsize->height; 997 fmt->colorspace = ov7670_formats[index].colorspace; 998 999 info->format = *fmt; 1000 1001 return 0; 1002 } 1003 1004 /* 1005 * Set a format. 1006 */ 1007 static int ov7670_set_fmt(struct v4l2_subdev *sd, 1008 struct v4l2_subdev_pad_config *cfg, 1009 struct v4l2_subdev_format *format) 1010 { 1011 struct ov7670_format_struct *ovfmt; 1012 struct ov7670_win_size *wsize; 1013 struct ov7670_info *info = to_state(sd); 1014 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1015 struct v4l2_mbus_framefmt *mbus_fmt; 1016 #endif 1017 unsigned char com7; 1018 int ret; 1019 1020 if (format->pad) 1021 return -EINVAL; 1022 1023 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 1024 ret = ov7670_try_fmt_internal(sd, &format->format, NULL, NULL); 1025 if (ret) 1026 return ret; 1027 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1028 mbus_fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad); 1029 *mbus_fmt = format->format; 1030 return 0; 1031 #else 1032 return -ENOTTY; 1033 #endif 1034 } 1035 1036 ret = ov7670_try_fmt_internal(sd, &format->format, &ovfmt, &wsize); 1037 1038 if (ret) 1039 return ret; 1040 /* 1041 * COM7 is a pain in the ass, it doesn't like to be read then 1042 * quickly written afterward. But we have everything we need 1043 * to set it absolutely here, as long as the format-specific 1044 * register sets list it first. 1045 */ 1046 com7 = ovfmt->regs[0].value; 1047 com7 |= wsize->com7_bit; 1048 ov7670_write(sd, REG_COM7, com7); 1049 /* 1050 * Now write the rest of the array. Also store start/stops 1051 */ 1052 ov7670_write_array(sd, ovfmt->regs + 1); 1053 ov7670_set_hw(sd, wsize->hstart, wsize->hstop, wsize->vstart, 1054 wsize->vstop); 1055 ret = 0; 1056 if (wsize->regs) 1057 ret = ov7670_write_array(sd, wsize->regs); 1058 info->fmt = ovfmt; 1059 1060 /* 1061 * If we're running RGB565, we must rewrite clkrc after setting 1062 * the other parameters or the image looks poor. If we're *not* 1063 * doing RGB565, we must not rewrite clkrc or the image looks 1064 * *really* poor. 1065 * 1066 * (Update) Now that we retain clkrc state, we should be able 1067 * to write it unconditionally, and that will make the frame 1068 * rate persistent too. 1069 */ 1070 if (ret == 0) 1071 ret = ov7670_write(sd, REG_CLKRC, info->clkrc); 1072 return 0; 1073 } 1074 1075 static int ov7670_get_fmt(struct v4l2_subdev *sd, 1076 struct v4l2_subdev_pad_config *cfg, 1077 struct v4l2_subdev_format *format) 1078 { 1079 struct ov7670_info *info = to_state(sd); 1080 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1081 struct v4l2_mbus_framefmt *mbus_fmt; 1082 #endif 1083 1084 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 1085 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1086 mbus_fmt = v4l2_subdev_get_try_format(sd, cfg, 0); 1087 format->format = *mbus_fmt; 1088 return 0; 1089 #else 1090 return -ENOTTY; 1091 #endif 1092 } else { 1093 format->format = info->format; 1094 } 1095 1096 return 0; 1097 } 1098 1099 /* 1100 * Implement G/S_PARM. There is a "high quality" mode we could try 1101 * to do someday; for now, we just do the frame rate tweak. 1102 */ 1103 static int ov7670_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms) 1104 { 1105 struct v4l2_captureparm *cp = &parms->parm.capture; 1106 struct ov7670_info *info = to_state(sd); 1107 1108 if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) 1109 return -EINVAL; 1110 1111 cp->capability = V4L2_CAP_TIMEPERFRAME; 1112 info->devtype->get_framerate(sd, &cp->timeperframe); 1113 1114 return 0; 1115 } 1116 1117 static int ov7670_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms) 1118 { 1119 struct v4l2_captureparm *cp = &parms->parm.capture; 1120 struct v4l2_fract *tpf = &cp->timeperframe; 1121 struct ov7670_info *info = to_state(sd); 1122 1123 if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) 1124 return -EINVAL; 1125 1126 cp->capability = V4L2_CAP_TIMEPERFRAME; 1127 return info->devtype->set_framerate(sd, tpf); 1128 } 1129 1130 1131 /* 1132 * Frame intervals. Since frame rates are controlled with the clock 1133 * divider, we can only do 30/n for integer n values. So no continuous 1134 * or stepwise options. Here we just pick a handful of logical values. 1135 */ 1136 1137 static int ov7670_frame_rates[] = { 30, 15, 10, 5, 1 }; 1138 1139 static int ov7670_enum_frame_interval(struct v4l2_subdev *sd, 1140 struct v4l2_subdev_pad_config *cfg, 1141 struct v4l2_subdev_frame_interval_enum *fie) 1142 { 1143 struct ov7670_info *info = to_state(sd); 1144 unsigned int n_win_sizes = info->devtype->n_win_sizes; 1145 int i; 1146 1147 if (fie->pad) 1148 return -EINVAL; 1149 if (fie->index >= ARRAY_SIZE(ov7670_frame_rates)) 1150 return -EINVAL; 1151 1152 /* 1153 * Check if the width/height is valid. 1154 * 1155 * If a minimum width/height was requested, filter out the capture 1156 * windows that fall outside that. 1157 */ 1158 for (i = 0; i < n_win_sizes; i++) { 1159 struct ov7670_win_size *win = &info->devtype->win_sizes[i]; 1160 1161 if (info->min_width && win->width < info->min_width) 1162 continue; 1163 if (info->min_height && win->height < info->min_height) 1164 continue; 1165 if (fie->width == win->width && fie->height == win->height) 1166 break; 1167 } 1168 if (i == n_win_sizes) 1169 return -EINVAL; 1170 fie->interval.numerator = 1; 1171 fie->interval.denominator = ov7670_frame_rates[fie->index]; 1172 return 0; 1173 } 1174 1175 /* 1176 * Frame size enumeration 1177 */ 1178 static int ov7670_enum_frame_size(struct v4l2_subdev *sd, 1179 struct v4l2_subdev_pad_config *cfg, 1180 struct v4l2_subdev_frame_size_enum *fse) 1181 { 1182 struct ov7670_info *info = to_state(sd); 1183 int i; 1184 int num_valid = -1; 1185 __u32 index = fse->index; 1186 unsigned int n_win_sizes = info->devtype->n_win_sizes; 1187 1188 if (fse->pad) 1189 return -EINVAL; 1190 1191 /* 1192 * If a minimum width/height was requested, filter out the capture 1193 * windows that fall outside that. 1194 */ 1195 for (i = 0; i < n_win_sizes; i++) { 1196 struct ov7670_win_size *win = &info->devtype->win_sizes[i]; 1197 if (info->min_width && win->width < info->min_width) 1198 continue; 1199 if (info->min_height && win->height < info->min_height) 1200 continue; 1201 if (index == ++num_valid) { 1202 fse->min_width = fse->max_width = win->width; 1203 fse->min_height = fse->max_height = win->height; 1204 return 0; 1205 } 1206 } 1207 1208 return -EINVAL; 1209 } 1210 1211 /* 1212 * Code for dealing with controls. 1213 */ 1214 1215 static int ov7670_store_cmatrix(struct v4l2_subdev *sd, 1216 int matrix[CMATRIX_LEN]) 1217 { 1218 int i, ret; 1219 unsigned char signbits = 0; 1220 1221 /* 1222 * Weird crap seems to exist in the upper part of 1223 * the sign bits register, so let's preserve it. 1224 */ 1225 ret = ov7670_read(sd, REG_CMATRIX_SIGN, &signbits); 1226 signbits &= 0xc0; 1227 1228 for (i = 0; i < CMATRIX_LEN; i++) { 1229 unsigned char raw; 1230 1231 if (matrix[i] < 0) { 1232 signbits |= (1 << i); 1233 if (matrix[i] < -255) 1234 raw = 0xff; 1235 else 1236 raw = (-1 * matrix[i]) & 0xff; 1237 } 1238 else { 1239 if (matrix[i] > 255) 1240 raw = 0xff; 1241 else 1242 raw = matrix[i] & 0xff; 1243 } 1244 ret += ov7670_write(sd, REG_CMATRIX_BASE + i, raw); 1245 } 1246 ret += ov7670_write(sd, REG_CMATRIX_SIGN, signbits); 1247 return ret; 1248 } 1249 1250 1251 /* 1252 * Hue also requires messing with the color matrix. It also requires 1253 * trig functions, which tend not to be well supported in the kernel. 1254 * So here is a simple table of sine values, 0-90 degrees, in steps 1255 * of five degrees. Values are multiplied by 1000. 1256 * 1257 * The following naive approximate trig functions require an argument 1258 * carefully limited to -180 <= theta <= 180. 1259 */ 1260 #define SIN_STEP 5 1261 static const int ov7670_sin_table[] = { 1262 0, 87, 173, 258, 342, 422, 1263 499, 573, 642, 707, 766, 819, 1264 866, 906, 939, 965, 984, 996, 1265 1000 1266 }; 1267 1268 static int ov7670_sine(int theta) 1269 { 1270 int chs = 1; 1271 int sine; 1272 1273 if (theta < 0) { 1274 theta = -theta; 1275 chs = -1; 1276 } 1277 if (theta <= 90) 1278 sine = ov7670_sin_table[theta/SIN_STEP]; 1279 else { 1280 theta -= 90; 1281 sine = 1000 - ov7670_sin_table[theta/SIN_STEP]; 1282 } 1283 return sine*chs; 1284 } 1285 1286 static int ov7670_cosine(int theta) 1287 { 1288 theta = 90 - theta; 1289 if (theta > 180) 1290 theta -= 360; 1291 else if (theta < -180) 1292 theta += 360; 1293 return ov7670_sine(theta); 1294 } 1295 1296 1297 1298 1299 static void ov7670_calc_cmatrix(struct ov7670_info *info, 1300 int matrix[CMATRIX_LEN], int sat, int hue) 1301 { 1302 int i; 1303 /* 1304 * Apply the current saturation setting first. 1305 */ 1306 for (i = 0; i < CMATRIX_LEN; i++) 1307 matrix[i] = (info->fmt->cmatrix[i] * sat) >> 7; 1308 /* 1309 * Then, if need be, rotate the hue value. 1310 */ 1311 if (hue != 0) { 1312 int sinth, costh, tmpmatrix[CMATRIX_LEN]; 1313 1314 memcpy(tmpmatrix, matrix, CMATRIX_LEN*sizeof(int)); 1315 sinth = ov7670_sine(hue); 1316 costh = ov7670_cosine(hue); 1317 1318 matrix[0] = (matrix[3]*sinth + matrix[0]*costh)/1000; 1319 matrix[1] = (matrix[4]*sinth + matrix[1]*costh)/1000; 1320 matrix[2] = (matrix[5]*sinth + matrix[2]*costh)/1000; 1321 matrix[3] = (matrix[3]*costh - matrix[0]*sinth)/1000; 1322 matrix[4] = (matrix[4]*costh - matrix[1]*sinth)/1000; 1323 matrix[5] = (matrix[5]*costh - matrix[2]*sinth)/1000; 1324 } 1325 } 1326 1327 1328 1329 static int ov7670_s_sat_hue(struct v4l2_subdev *sd, int sat, int hue) 1330 { 1331 struct ov7670_info *info = to_state(sd); 1332 int matrix[CMATRIX_LEN]; 1333 int ret; 1334 1335 ov7670_calc_cmatrix(info, matrix, sat, hue); 1336 ret = ov7670_store_cmatrix(sd, matrix); 1337 return ret; 1338 } 1339 1340 1341 /* 1342 * Some weird registers seem to store values in a sign/magnitude format! 1343 */ 1344 1345 static unsigned char ov7670_abs_to_sm(unsigned char v) 1346 { 1347 if (v > 127) 1348 return v & 0x7f; 1349 return (128 - v) | 0x80; 1350 } 1351 1352 static int ov7670_s_brightness(struct v4l2_subdev *sd, int value) 1353 { 1354 unsigned char com8 = 0, v; 1355 int ret; 1356 1357 ov7670_read(sd, REG_COM8, &com8); 1358 com8 &= ~COM8_AEC; 1359 ov7670_write(sd, REG_COM8, com8); 1360 v = ov7670_abs_to_sm(value); 1361 ret = ov7670_write(sd, REG_BRIGHT, v); 1362 return ret; 1363 } 1364 1365 static int ov7670_s_contrast(struct v4l2_subdev *sd, int value) 1366 { 1367 return ov7670_write(sd, REG_CONTRAS, (unsigned char) value); 1368 } 1369 1370 static int ov7670_s_hflip(struct v4l2_subdev *sd, int value) 1371 { 1372 unsigned char v = 0; 1373 int ret; 1374 1375 ret = ov7670_read(sd, REG_MVFP, &v); 1376 if (value) 1377 v |= MVFP_MIRROR; 1378 else 1379 v &= ~MVFP_MIRROR; 1380 msleep(10); /* FIXME */ 1381 ret += ov7670_write(sd, REG_MVFP, v); 1382 return ret; 1383 } 1384 1385 static int ov7670_s_vflip(struct v4l2_subdev *sd, int value) 1386 { 1387 unsigned char v = 0; 1388 int ret; 1389 1390 ret = ov7670_read(sd, REG_MVFP, &v); 1391 if (value) 1392 v |= MVFP_FLIP; 1393 else 1394 v &= ~MVFP_FLIP; 1395 msleep(10); /* FIXME */ 1396 ret += ov7670_write(sd, REG_MVFP, v); 1397 return ret; 1398 } 1399 1400 /* 1401 * GAIN is split between REG_GAIN and REG_VREF[7:6]. If one believes 1402 * the data sheet, the VREF parts should be the most significant, but 1403 * experience shows otherwise. There seems to be little value in 1404 * messing with the VREF bits, so we leave them alone. 1405 */ 1406 static int ov7670_g_gain(struct v4l2_subdev *sd, __s32 *value) 1407 { 1408 int ret; 1409 unsigned char gain; 1410 1411 ret = ov7670_read(sd, REG_GAIN, &gain); 1412 *value = gain; 1413 return ret; 1414 } 1415 1416 static int ov7670_s_gain(struct v4l2_subdev *sd, int value) 1417 { 1418 int ret; 1419 unsigned char com8; 1420 1421 ret = ov7670_write(sd, REG_GAIN, value & 0xff); 1422 /* Have to turn off AGC as well */ 1423 if (ret == 0) { 1424 ret = ov7670_read(sd, REG_COM8, &com8); 1425 ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AGC); 1426 } 1427 return ret; 1428 } 1429 1430 /* 1431 * Tweak autogain. 1432 */ 1433 static int ov7670_s_autogain(struct v4l2_subdev *sd, int value) 1434 { 1435 int ret; 1436 unsigned char com8; 1437 1438 ret = ov7670_read(sd, REG_COM8, &com8); 1439 if (ret == 0) { 1440 if (value) 1441 com8 |= COM8_AGC; 1442 else 1443 com8 &= ~COM8_AGC; 1444 ret = ov7670_write(sd, REG_COM8, com8); 1445 } 1446 return ret; 1447 } 1448 1449 static int ov7670_s_exp(struct v4l2_subdev *sd, int value) 1450 { 1451 int ret; 1452 unsigned char com1, com8, aech, aechh; 1453 1454 ret = ov7670_read(sd, REG_COM1, &com1) + 1455 ov7670_read(sd, REG_COM8, &com8) + 1456 ov7670_read(sd, REG_AECHH, &aechh); 1457 if (ret) 1458 return ret; 1459 1460 com1 = (com1 & 0xfc) | (value & 0x03); 1461 aech = (value >> 2) & 0xff; 1462 aechh = (aechh & 0xc0) | ((value >> 10) & 0x3f); 1463 ret = ov7670_write(sd, REG_COM1, com1) + 1464 ov7670_write(sd, REG_AECH, aech) + 1465 ov7670_write(sd, REG_AECHH, aechh); 1466 /* Have to turn off AEC as well */ 1467 if (ret == 0) 1468 ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AEC); 1469 return ret; 1470 } 1471 1472 /* 1473 * Tweak autoexposure. 1474 */ 1475 static int ov7670_s_autoexp(struct v4l2_subdev *sd, 1476 enum v4l2_exposure_auto_type value) 1477 { 1478 int ret; 1479 unsigned char com8; 1480 1481 ret = ov7670_read(sd, REG_COM8, &com8); 1482 if (ret == 0) { 1483 if (value == V4L2_EXPOSURE_AUTO) 1484 com8 |= COM8_AEC; 1485 else 1486 com8 &= ~COM8_AEC; 1487 ret = ov7670_write(sd, REG_COM8, com8); 1488 } 1489 return ret; 1490 } 1491 1492 static const char * const ov7670_test_pattern_menu[] = { 1493 "No test output", 1494 "Shifting \"1\"", 1495 "8-bar color bar", 1496 "Fade to gray color bar", 1497 }; 1498 1499 static int ov7670_s_test_pattern(struct v4l2_subdev *sd, int value) 1500 { 1501 int ret; 1502 1503 ret = ov7670_update_bits(sd, REG_SCALING_XSC, TEST_PATTTERN_0, 1504 value & BIT(0) ? TEST_PATTTERN_0 : 0); 1505 if (ret) 1506 return ret; 1507 1508 return ov7670_update_bits(sd, REG_SCALING_YSC, TEST_PATTTERN_1, 1509 value & BIT(1) ? TEST_PATTTERN_1 : 0); 1510 } 1511 1512 static int ov7670_g_volatile_ctrl(struct v4l2_ctrl *ctrl) 1513 { 1514 struct v4l2_subdev *sd = to_sd(ctrl); 1515 struct ov7670_info *info = to_state(sd); 1516 1517 switch (ctrl->id) { 1518 case V4L2_CID_AUTOGAIN: 1519 return ov7670_g_gain(sd, &info->gain->val); 1520 } 1521 return -EINVAL; 1522 } 1523 1524 static int ov7670_s_ctrl(struct v4l2_ctrl *ctrl) 1525 { 1526 struct v4l2_subdev *sd = to_sd(ctrl); 1527 struct ov7670_info *info = to_state(sd); 1528 1529 switch (ctrl->id) { 1530 case V4L2_CID_BRIGHTNESS: 1531 return ov7670_s_brightness(sd, ctrl->val); 1532 case V4L2_CID_CONTRAST: 1533 return ov7670_s_contrast(sd, ctrl->val); 1534 case V4L2_CID_SATURATION: 1535 return ov7670_s_sat_hue(sd, 1536 info->saturation->val, info->hue->val); 1537 case V4L2_CID_VFLIP: 1538 return ov7670_s_vflip(sd, ctrl->val); 1539 case V4L2_CID_HFLIP: 1540 return ov7670_s_hflip(sd, ctrl->val); 1541 case V4L2_CID_AUTOGAIN: 1542 /* Only set manual gain if auto gain is not explicitly 1543 turned on. */ 1544 if (!ctrl->val) { 1545 /* ov7670_s_gain turns off auto gain */ 1546 return ov7670_s_gain(sd, info->gain->val); 1547 } 1548 return ov7670_s_autogain(sd, ctrl->val); 1549 case V4L2_CID_EXPOSURE_AUTO: 1550 /* Only set manual exposure if auto exposure is not explicitly 1551 turned on. */ 1552 if (ctrl->val == V4L2_EXPOSURE_MANUAL) { 1553 /* ov7670_s_exp turns off auto exposure */ 1554 return ov7670_s_exp(sd, info->exposure->val); 1555 } 1556 return ov7670_s_autoexp(sd, ctrl->val); 1557 case V4L2_CID_TEST_PATTERN: 1558 return ov7670_s_test_pattern(sd, ctrl->val); 1559 } 1560 return -EINVAL; 1561 } 1562 1563 static const struct v4l2_ctrl_ops ov7670_ctrl_ops = { 1564 .s_ctrl = ov7670_s_ctrl, 1565 .g_volatile_ctrl = ov7670_g_volatile_ctrl, 1566 }; 1567 1568 #ifdef CONFIG_VIDEO_ADV_DEBUG 1569 static int ov7670_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) 1570 { 1571 unsigned char val = 0; 1572 int ret; 1573 1574 ret = ov7670_read(sd, reg->reg & 0xff, &val); 1575 reg->val = val; 1576 reg->size = 1; 1577 return ret; 1578 } 1579 1580 static int ov7670_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg) 1581 { 1582 ov7670_write(sd, reg->reg & 0xff, reg->val & 0xff); 1583 return 0; 1584 } 1585 #endif 1586 1587 static int ov7670_s_power(struct v4l2_subdev *sd, int on) 1588 { 1589 struct ov7670_info *info = to_state(sd); 1590 1591 if (info->pwdn_gpio) 1592 gpiod_set_value(info->pwdn_gpio, !on); 1593 if (on && info->resetb_gpio) { 1594 gpiod_set_value(info->resetb_gpio, 1); 1595 usleep_range(500, 1000); 1596 gpiod_set_value(info->resetb_gpio, 0); 1597 usleep_range(3000, 5000); 1598 } 1599 1600 return 0; 1601 } 1602 1603 static void ov7670_get_default_format(struct v4l2_subdev *sd, 1604 struct v4l2_mbus_framefmt *format) 1605 { 1606 struct ov7670_info *info = to_state(sd); 1607 1608 format->width = info->devtype->win_sizes[0].width; 1609 format->height = info->devtype->win_sizes[0].height; 1610 format->colorspace = info->fmt->colorspace; 1611 format->code = info->fmt->mbus_code; 1612 format->field = V4L2_FIELD_NONE; 1613 } 1614 1615 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1616 static int ov7670_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) 1617 { 1618 struct v4l2_mbus_framefmt *format = 1619 v4l2_subdev_get_try_format(sd, fh->pad, 0); 1620 1621 ov7670_get_default_format(sd, format); 1622 1623 return 0; 1624 } 1625 #endif 1626 1627 /* ----------------------------------------------------------------------- */ 1628 1629 static const struct v4l2_subdev_core_ops ov7670_core_ops = { 1630 .reset = ov7670_reset, 1631 .init = ov7670_init, 1632 #ifdef CONFIG_VIDEO_ADV_DEBUG 1633 .g_register = ov7670_g_register, 1634 .s_register = ov7670_s_register, 1635 #endif 1636 }; 1637 1638 static const struct v4l2_subdev_video_ops ov7670_video_ops = { 1639 .s_parm = ov7670_s_parm, 1640 .g_parm = ov7670_g_parm, 1641 }; 1642 1643 static const struct v4l2_subdev_pad_ops ov7670_pad_ops = { 1644 .enum_frame_interval = ov7670_enum_frame_interval, 1645 .enum_frame_size = ov7670_enum_frame_size, 1646 .enum_mbus_code = ov7670_enum_mbus_code, 1647 .get_fmt = ov7670_get_fmt, 1648 .set_fmt = ov7670_set_fmt, 1649 }; 1650 1651 static const struct v4l2_subdev_ops ov7670_ops = { 1652 .core = &ov7670_core_ops, 1653 .video = &ov7670_video_ops, 1654 .pad = &ov7670_pad_ops, 1655 }; 1656 1657 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1658 static const struct v4l2_subdev_internal_ops ov7670_subdev_internal_ops = { 1659 .open = ov7670_open, 1660 }; 1661 #endif 1662 1663 /* ----------------------------------------------------------------------- */ 1664 1665 static const struct ov7670_devtype ov7670_devdata[] = { 1666 [MODEL_OV7670] = { 1667 .win_sizes = ov7670_win_sizes, 1668 .n_win_sizes = ARRAY_SIZE(ov7670_win_sizes), 1669 .set_framerate = ov7670_set_framerate_legacy, 1670 .get_framerate = ov7670_get_framerate_legacy, 1671 }, 1672 [MODEL_OV7675] = { 1673 .win_sizes = ov7675_win_sizes, 1674 .n_win_sizes = ARRAY_SIZE(ov7675_win_sizes), 1675 .set_framerate = ov7675_set_framerate, 1676 .get_framerate = ov7675_get_framerate, 1677 }, 1678 }; 1679 1680 static int ov7670_init_gpio(struct i2c_client *client, struct ov7670_info *info) 1681 { 1682 info->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown", 1683 GPIOD_OUT_LOW); 1684 if (IS_ERR(info->pwdn_gpio)) { 1685 dev_info(&client->dev, "can't get %s GPIO\n", "powerdown"); 1686 return PTR_ERR(info->pwdn_gpio); 1687 } 1688 1689 info->resetb_gpio = devm_gpiod_get_optional(&client->dev, "reset", 1690 GPIOD_OUT_LOW); 1691 if (IS_ERR(info->resetb_gpio)) { 1692 dev_info(&client->dev, "can't get %s GPIO\n", "reset"); 1693 return PTR_ERR(info->resetb_gpio); 1694 } 1695 1696 usleep_range(3000, 5000); 1697 1698 return 0; 1699 } 1700 1701 static int ov7670_probe(struct i2c_client *client, 1702 const struct i2c_device_id *id) 1703 { 1704 struct v4l2_fract tpf; 1705 struct v4l2_subdev *sd; 1706 struct ov7670_info *info; 1707 int ret; 1708 1709 info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL); 1710 if (info == NULL) 1711 return -ENOMEM; 1712 sd = &info->sd; 1713 v4l2_i2c_subdev_init(sd, client, &ov7670_ops); 1714 1715 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1716 sd->internal_ops = &ov7670_subdev_internal_ops; 1717 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1718 #endif 1719 1720 info->clock_speed = 30; /* default: a guess */ 1721 if (client->dev.platform_data) { 1722 struct ov7670_config *config = client->dev.platform_data; 1723 1724 /* 1725 * Must apply configuration before initializing device, because it 1726 * selects I/O method. 1727 */ 1728 info->min_width = config->min_width; 1729 info->min_height = config->min_height; 1730 info->use_smbus = config->use_smbus; 1731 1732 if (config->clock_speed) 1733 info->clock_speed = config->clock_speed; 1734 1735 /* 1736 * It should be allowed for ov7670 too when it is migrated to 1737 * the new frame rate formula. 1738 */ 1739 if (config->pll_bypass && id->driver_data != MODEL_OV7670) 1740 info->pll_bypass = true; 1741 1742 if (config->pclk_hb_disable) 1743 info->pclk_hb_disable = true; 1744 } 1745 1746 info->clk = devm_clk_get(&client->dev, "xclk"); 1747 if (IS_ERR(info->clk)) 1748 return PTR_ERR(info->clk); 1749 ret = clk_prepare_enable(info->clk); 1750 if (ret) 1751 return ret; 1752 1753 info->clock_speed = clk_get_rate(info->clk) / 1000000; 1754 if (info->clock_speed < 10 || info->clock_speed > 48) { 1755 ret = -EINVAL; 1756 goto clk_disable; 1757 } 1758 1759 ret = ov7670_init_gpio(client, info); 1760 if (ret) 1761 goto clk_disable; 1762 1763 ov7670_s_power(sd, 1); 1764 1765 /* Make sure it's an ov7670 */ 1766 ret = ov7670_detect(sd); 1767 if (ret) { 1768 v4l_dbg(1, debug, client, 1769 "chip found @ 0x%x (%s) is not an ov7670 chip.\n", 1770 client->addr << 1, client->adapter->name); 1771 goto power_off; 1772 } 1773 v4l_info(client, "chip found @ 0x%02x (%s)\n", 1774 client->addr << 1, client->adapter->name); 1775 1776 info->devtype = &ov7670_devdata[id->driver_data]; 1777 info->fmt = &ov7670_formats[0]; 1778 1779 ov7670_get_default_format(sd, &info->format); 1780 1781 info->clkrc = 0; 1782 1783 /* Set default frame rate to 30 fps */ 1784 tpf.numerator = 1; 1785 tpf.denominator = 30; 1786 info->devtype->set_framerate(sd, &tpf); 1787 1788 if (info->pclk_hb_disable) 1789 ov7670_write(sd, REG_COM10, COM10_PCLK_HB); 1790 1791 v4l2_ctrl_handler_init(&info->hdl, 10); 1792 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1793 V4L2_CID_BRIGHTNESS, 0, 255, 1, 128); 1794 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1795 V4L2_CID_CONTRAST, 0, 127, 1, 64); 1796 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1797 V4L2_CID_VFLIP, 0, 1, 1, 0); 1798 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1799 V4L2_CID_HFLIP, 0, 1, 1, 0); 1800 info->saturation = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1801 V4L2_CID_SATURATION, 0, 256, 1, 128); 1802 info->hue = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1803 V4L2_CID_HUE, -180, 180, 5, 0); 1804 info->gain = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1805 V4L2_CID_GAIN, 0, 255, 1, 128); 1806 info->auto_gain = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1807 V4L2_CID_AUTOGAIN, 0, 1, 1, 1); 1808 info->exposure = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1809 V4L2_CID_EXPOSURE, 0, 65535, 1, 500); 1810 info->auto_exposure = v4l2_ctrl_new_std_menu(&info->hdl, &ov7670_ctrl_ops, 1811 V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL, 0, 1812 V4L2_EXPOSURE_AUTO); 1813 v4l2_ctrl_new_std_menu_items(&info->hdl, &ov7670_ctrl_ops, 1814 V4L2_CID_TEST_PATTERN, 1815 ARRAY_SIZE(ov7670_test_pattern_menu) - 1, 0, 0, 1816 ov7670_test_pattern_menu); 1817 sd->ctrl_handler = &info->hdl; 1818 if (info->hdl.error) { 1819 ret = info->hdl.error; 1820 1821 goto hdl_free; 1822 } 1823 /* 1824 * We have checked empirically that hw allows to read back the gain 1825 * value chosen by auto gain but that's not the case for auto exposure. 1826 */ 1827 v4l2_ctrl_auto_cluster(2, &info->auto_gain, 0, true); 1828 v4l2_ctrl_auto_cluster(2, &info->auto_exposure, 1829 V4L2_EXPOSURE_MANUAL, false); 1830 v4l2_ctrl_cluster(2, &info->saturation); 1831 1832 #if defined(CONFIG_MEDIA_CONTROLLER) 1833 info->pad.flags = MEDIA_PAD_FL_SOURCE; 1834 info->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1835 ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad); 1836 if (ret < 0) 1837 goto hdl_free; 1838 #endif 1839 1840 v4l2_ctrl_handler_setup(&info->hdl); 1841 1842 ret = v4l2_async_register_subdev(&info->sd); 1843 if (ret < 0) 1844 goto entity_cleanup; 1845 1846 return 0; 1847 1848 entity_cleanup: 1849 media_entity_cleanup(&info->sd.entity); 1850 hdl_free: 1851 v4l2_ctrl_handler_free(&info->hdl); 1852 power_off: 1853 ov7670_s_power(sd, 0); 1854 clk_disable: 1855 clk_disable_unprepare(info->clk); 1856 return ret; 1857 } 1858 1859 1860 static int ov7670_remove(struct i2c_client *client) 1861 { 1862 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1863 struct ov7670_info *info = to_state(sd); 1864 1865 v4l2_async_unregister_subdev(sd); 1866 v4l2_ctrl_handler_free(&info->hdl); 1867 clk_disable_unprepare(info->clk); 1868 media_entity_cleanup(&info->sd.entity); 1869 ov7670_s_power(sd, 0); 1870 return 0; 1871 } 1872 1873 static const struct i2c_device_id ov7670_id[] = { 1874 { "ov7670", MODEL_OV7670 }, 1875 { "ov7675", MODEL_OV7675 }, 1876 { } 1877 }; 1878 MODULE_DEVICE_TABLE(i2c, ov7670_id); 1879 1880 #if IS_ENABLED(CONFIG_OF) 1881 static const struct of_device_id ov7670_of_match[] = { 1882 { .compatible = "ovti,ov7670", }, 1883 { /* sentinel */ }, 1884 }; 1885 MODULE_DEVICE_TABLE(of, ov7670_of_match); 1886 #endif 1887 1888 static struct i2c_driver ov7670_driver = { 1889 .driver = { 1890 .name = "ov7670", 1891 .of_match_table = of_match_ptr(ov7670_of_match), 1892 }, 1893 .probe = ov7670_probe, 1894 .remove = ov7670_remove, 1895 .id_table = ov7670_id, 1896 }; 1897 1898 module_i2c_driver(ov7670_driver); 1899