1 /* 2 * A V4L2 driver for OmniVision OV7670 cameras. 3 * 4 * Copyright 2006 One Laptop Per Child Association, Inc. Written 5 * by Jonathan Corbet with substantial inspiration from Mark 6 * McClelland's ovcamchip code. 7 * 8 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net> 9 * 10 * This file may be distributed under the terms of the GNU General 11 * Public License, version 2. 12 */ 13 #include <linux/clk.h> 14 #include <linux/init.h> 15 #include <linux/module.h> 16 #include <linux/slab.h> 17 #include <linux/i2c.h> 18 #include <linux/delay.h> 19 #include <linux/videodev2.h> 20 #include <linux/gpio.h> 21 #include <linux/gpio/consumer.h> 22 #include <media/v4l2-device.h> 23 #include <media/v4l2-event.h> 24 #include <media/v4l2-ctrls.h> 25 #include <media/v4l2-fwnode.h> 26 #include <media/v4l2-mediabus.h> 27 #include <media/v4l2-image-sizes.h> 28 #include <media/i2c/ov7670.h> 29 30 MODULE_AUTHOR("Jonathan Corbet <corbet@lwn.net>"); 31 MODULE_DESCRIPTION("A low-level driver for OmniVision ov7670 sensors"); 32 MODULE_LICENSE("GPL"); 33 34 static bool debug; 35 module_param(debug, bool, 0644); 36 MODULE_PARM_DESC(debug, "Debug level (0-1)"); 37 38 /* 39 * The 7670 sits on i2c with ID 0x42 40 */ 41 #define OV7670_I2C_ADDR 0x42 42 43 #define PLL_FACTOR 4 44 45 /* Registers */ 46 #define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */ 47 #define REG_BLUE 0x01 /* blue gain */ 48 #define REG_RED 0x02 /* red gain */ 49 #define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */ 50 #define REG_COM1 0x04 /* Control 1 */ 51 #define COM1_CCIR656 0x40 /* CCIR656 enable */ 52 #define REG_BAVE 0x05 /* U/B Average level */ 53 #define REG_GbAVE 0x06 /* Y/Gb Average level */ 54 #define REG_AECHH 0x07 /* AEC MS 5 bits */ 55 #define REG_RAVE 0x08 /* V/R Average level */ 56 #define REG_COM2 0x09 /* Control 2 */ 57 #define COM2_SSLEEP 0x10 /* Soft sleep mode */ 58 #define REG_PID 0x0a /* Product ID MSB */ 59 #define REG_VER 0x0b /* Product ID LSB */ 60 #define REG_COM3 0x0c /* Control 3 */ 61 #define COM3_SWAP 0x40 /* Byte swap */ 62 #define COM3_SCALEEN 0x08 /* Enable scaling */ 63 #define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */ 64 #define REG_COM4 0x0d /* Control 4 */ 65 #define REG_COM5 0x0e /* All "reserved" */ 66 #define REG_COM6 0x0f /* Control 6 */ 67 #define REG_AECH 0x10 /* More bits of AEC value */ 68 #define REG_CLKRC 0x11 /* Clocl control */ 69 #define CLK_EXT 0x40 /* Use external clock directly */ 70 #define CLK_SCALE 0x3f /* Mask for internal clock scale */ 71 #define REG_COM7 0x12 /* Control 7 */ 72 #define COM7_RESET 0x80 /* Register reset */ 73 #define COM7_FMT_MASK 0x38 74 #define COM7_FMT_VGA 0x00 75 #define COM7_FMT_CIF 0x20 /* CIF format */ 76 #define COM7_FMT_QVGA 0x10 /* QVGA format */ 77 #define COM7_FMT_QCIF 0x08 /* QCIF format */ 78 #define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */ 79 #define COM7_YUV 0x00 /* YUV */ 80 #define COM7_BAYER 0x01 /* Bayer format */ 81 #define COM7_PBAYER 0x05 /* "Processed bayer" */ 82 #define REG_COM8 0x13 /* Control 8 */ 83 #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */ 84 #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */ 85 #define COM8_BFILT 0x20 /* Band filter enable */ 86 #define COM8_AGC 0x04 /* Auto gain enable */ 87 #define COM8_AWB 0x02 /* White balance enable */ 88 #define COM8_AEC 0x01 /* Auto exposure enable */ 89 #define REG_COM9 0x14 /* Control 9 - gain ceiling */ 90 #define REG_COM10 0x15 /* Control 10 */ 91 #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */ 92 #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */ 93 #define COM10_HREF_REV 0x08 /* Reverse HREF */ 94 #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */ 95 #define COM10_VS_NEG 0x02 /* VSYNC negative */ 96 #define COM10_HS_NEG 0x01 /* HSYNC negative */ 97 #define REG_HSTART 0x17 /* Horiz start high bits */ 98 #define REG_HSTOP 0x18 /* Horiz stop high bits */ 99 #define REG_VSTART 0x19 /* Vert start high bits */ 100 #define REG_VSTOP 0x1a /* Vert stop high bits */ 101 #define REG_PSHFT 0x1b /* Pixel delay after HREF */ 102 #define REG_MIDH 0x1c /* Manuf. ID high */ 103 #define REG_MIDL 0x1d /* Manuf. ID low */ 104 #define REG_MVFP 0x1e /* Mirror / vflip */ 105 #define MVFP_MIRROR 0x20 /* Mirror image */ 106 #define MVFP_FLIP 0x10 /* Vertical flip */ 107 108 #define REG_AEW 0x24 /* AGC upper limit */ 109 #define REG_AEB 0x25 /* AGC lower limit */ 110 #define REG_VPT 0x26 /* AGC/AEC fast mode op region */ 111 #define REG_HSYST 0x30 /* HSYNC rising edge delay */ 112 #define REG_HSYEN 0x31 /* HSYNC falling edge delay */ 113 #define REG_HREF 0x32 /* HREF pieces */ 114 #define REG_TSLB 0x3a /* lots of stuff */ 115 #define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */ 116 #define REG_COM11 0x3b /* Control 11 */ 117 #define COM11_NIGHT 0x80 /* NIght mode enable */ 118 #define COM11_NMFR 0x60 /* Two bit NM frame rate */ 119 #define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */ 120 #define COM11_50HZ 0x08 /* Manual 50Hz select */ 121 #define COM11_EXP 0x02 122 #define REG_COM12 0x3c /* Control 12 */ 123 #define COM12_HREF 0x80 /* HREF always */ 124 #define REG_COM13 0x3d /* Control 13 */ 125 #define COM13_GAMMA 0x80 /* Gamma enable */ 126 #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */ 127 #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */ 128 #define REG_COM14 0x3e /* Control 14 */ 129 #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */ 130 #define REG_EDGE 0x3f /* Edge enhancement factor */ 131 #define REG_COM15 0x40 /* Control 15 */ 132 #define COM15_R10F0 0x00 /* Data range 10 to F0 */ 133 #define COM15_R01FE 0x80 /* 01 to FE */ 134 #define COM15_R00FF 0xc0 /* 00 to FF */ 135 #define COM15_RGB565 0x10 /* RGB565 output */ 136 #define COM15_RGB555 0x30 /* RGB555 output */ 137 #define REG_COM16 0x41 /* Control 16 */ 138 #define COM16_AWBGAIN 0x08 /* AWB gain enable */ 139 #define REG_COM17 0x42 /* Control 17 */ 140 #define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */ 141 #define COM17_CBAR 0x08 /* DSP Color bar */ 142 143 /* 144 * This matrix defines how the colors are generated, must be 145 * tweaked to adjust hue and saturation. 146 * 147 * Order: v-red, v-green, v-blue, u-red, u-green, u-blue 148 * 149 * They are nine-bit signed quantities, with the sign bit 150 * stored in 0x58. Sign for v-red is bit 0, and up from there. 151 */ 152 #define REG_CMATRIX_BASE 0x4f 153 #define CMATRIX_LEN 6 154 #define REG_CMATRIX_SIGN 0x58 155 156 157 #define REG_BRIGHT 0x55 /* Brightness */ 158 #define REG_CONTRAS 0x56 /* Contrast control */ 159 160 #define REG_GFIX 0x69 /* Fix gain control */ 161 162 #define REG_DBLV 0x6b /* PLL control an debugging */ 163 #define DBLV_BYPASS 0x0a /* Bypass PLL */ 164 #define DBLV_X4 0x4a /* clock x4 */ 165 #define DBLV_X6 0x8a /* clock x6 */ 166 #define DBLV_X8 0xca /* clock x8 */ 167 168 #define REG_SCALING_XSC 0x70 /* Test pattern and horizontal scale factor */ 169 #define TEST_PATTTERN_0 0x80 170 #define REG_SCALING_YSC 0x71 /* Test pattern and vertical scale factor */ 171 #define TEST_PATTTERN_1 0x80 172 173 #define REG_REG76 0x76 /* OV's name */ 174 #define R76_BLKPCOR 0x80 /* Black pixel correction enable */ 175 #define R76_WHTPCOR 0x40 /* White pixel correction enable */ 176 177 #define REG_RGB444 0x8c /* RGB 444 control */ 178 #define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */ 179 #define R444_RGBX 0x01 /* Empty nibble at end */ 180 181 #define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */ 182 #define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */ 183 184 #define REG_BD50MAX 0xa5 /* 50hz banding step limit */ 185 #define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */ 186 #define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */ 187 #define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */ 188 #define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */ 189 #define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */ 190 #define REG_BD60MAX 0xab /* 60hz banding step limit */ 191 192 enum ov7670_model { 193 MODEL_OV7670 = 0, 194 MODEL_OV7675, 195 }; 196 197 struct ov7670_win_size { 198 int width; 199 int height; 200 unsigned char com7_bit; 201 int hstart; /* Start/stop values for the camera. Note */ 202 int hstop; /* that they do not always make complete */ 203 int vstart; /* sense to humans, but evidently the sensor */ 204 int vstop; /* will do the right thing... */ 205 struct regval_list *regs; /* Regs to tweak */ 206 }; 207 208 struct ov7670_devtype { 209 /* formats supported for each model */ 210 struct ov7670_win_size *win_sizes; 211 unsigned int n_win_sizes; 212 /* callbacks for frame rate control */ 213 int (*set_framerate)(struct v4l2_subdev *, struct v4l2_fract *); 214 void (*get_framerate)(struct v4l2_subdev *, struct v4l2_fract *); 215 }; 216 217 /* 218 * Information we maintain about a known sensor. 219 */ 220 struct ov7670_format_struct; /* coming later */ 221 struct ov7670_info { 222 struct v4l2_subdev sd; 223 #if defined(CONFIG_MEDIA_CONTROLLER) 224 struct media_pad pad; 225 #endif 226 struct v4l2_ctrl_handler hdl; 227 struct { 228 /* gain cluster */ 229 struct v4l2_ctrl *auto_gain; 230 struct v4l2_ctrl *gain; 231 }; 232 struct { 233 /* exposure cluster */ 234 struct v4l2_ctrl *auto_exposure; 235 struct v4l2_ctrl *exposure; 236 }; 237 struct { 238 /* saturation/hue cluster */ 239 struct v4l2_ctrl *saturation; 240 struct v4l2_ctrl *hue; 241 }; 242 struct v4l2_mbus_framefmt format; 243 struct ov7670_format_struct *fmt; /* Current format */ 244 struct ov7670_win_size *wsize; 245 struct clk *clk; 246 int on; 247 struct gpio_desc *resetb_gpio; 248 struct gpio_desc *pwdn_gpio; 249 unsigned int mbus_config; /* Media bus configuration flags */ 250 int min_width; /* Filter out smaller sizes */ 251 int min_height; /* Filter out smaller sizes */ 252 int clock_speed; /* External clock speed (MHz) */ 253 u8 clkrc; /* Clock divider value */ 254 bool use_smbus; /* Use smbus I/O instead of I2C */ 255 bool pll_bypass; 256 bool pclk_hb_disable; 257 const struct ov7670_devtype *devtype; /* Device specifics */ 258 }; 259 260 static inline struct ov7670_info *to_state(struct v4l2_subdev *sd) 261 { 262 return container_of(sd, struct ov7670_info, sd); 263 } 264 265 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) 266 { 267 return &container_of(ctrl->handler, struct ov7670_info, hdl)->sd; 268 } 269 270 271 272 /* 273 * The default register settings, as obtained from OmniVision. There 274 * is really no making sense of most of these - lots of "reserved" values 275 * and such. 276 * 277 * These settings give VGA YUYV. 278 */ 279 280 struct regval_list { 281 unsigned char reg_num; 282 unsigned char value; 283 }; 284 285 static struct regval_list ov7670_default_regs[] = { 286 { REG_COM7, COM7_RESET }, 287 /* 288 * Clock scale: 3 = 15fps 289 * 2 = 20fps 290 * 1 = 30fps 291 */ 292 { REG_CLKRC, 0x1 }, /* OV: clock scale (30 fps) */ 293 { REG_TSLB, 0x04 }, /* OV */ 294 { REG_COM7, 0 }, /* VGA */ 295 /* 296 * Set the hardware window. These values from OV don't entirely 297 * make sense - hstop is less than hstart. But they work... 298 */ 299 { REG_HSTART, 0x13 }, { REG_HSTOP, 0x01 }, 300 { REG_HREF, 0xb6 }, { REG_VSTART, 0x02 }, 301 { REG_VSTOP, 0x7a }, { REG_VREF, 0x0a }, 302 303 { REG_COM3, 0 }, { REG_COM14, 0 }, 304 /* Mystery scaling numbers */ 305 { REG_SCALING_XSC, 0x3a }, 306 { REG_SCALING_YSC, 0x35 }, 307 { 0x72, 0x11 }, { 0x73, 0xf0 }, 308 { 0xa2, 0x02 }, { REG_COM10, 0x0 }, 309 310 /* Gamma curve values */ 311 { 0x7a, 0x20 }, { 0x7b, 0x10 }, 312 { 0x7c, 0x1e }, { 0x7d, 0x35 }, 313 { 0x7e, 0x5a }, { 0x7f, 0x69 }, 314 { 0x80, 0x76 }, { 0x81, 0x80 }, 315 { 0x82, 0x88 }, { 0x83, 0x8f }, 316 { 0x84, 0x96 }, { 0x85, 0xa3 }, 317 { 0x86, 0xaf }, { 0x87, 0xc4 }, 318 { 0x88, 0xd7 }, { 0x89, 0xe8 }, 319 320 /* AGC and AEC parameters. Note we start by disabling those features, 321 then turn them only after tweaking the values. */ 322 { REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_BFILT }, 323 { REG_GAIN, 0 }, { REG_AECH, 0 }, 324 { REG_COM4, 0x40 }, /* magic reserved bit */ 325 { REG_COM9, 0x18 }, /* 4x gain + magic rsvd bit */ 326 { REG_BD50MAX, 0x05 }, { REG_BD60MAX, 0x07 }, 327 { REG_AEW, 0x95 }, { REG_AEB, 0x33 }, 328 { REG_VPT, 0xe3 }, { REG_HAECC1, 0x78 }, 329 { REG_HAECC2, 0x68 }, { 0xa1, 0x03 }, /* magic */ 330 { REG_HAECC3, 0xd8 }, { REG_HAECC4, 0xd8 }, 331 { REG_HAECC5, 0xf0 }, { REG_HAECC6, 0x90 }, 332 { REG_HAECC7, 0x94 }, 333 { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC }, 334 335 /* Almost all of these are magic "reserved" values. */ 336 { REG_COM5, 0x61 }, { REG_COM6, 0x4b }, 337 { 0x16, 0x02 }, { REG_MVFP, 0x07 }, 338 { 0x21, 0x02 }, { 0x22, 0x91 }, 339 { 0x29, 0x07 }, { 0x33, 0x0b }, 340 { 0x35, 0x0b }, { 0x37, 0x1d }, 341 { 0x38, 0x71 }, { 0x39, 0x2a }, 342 { REG_COM12, 0x78 }, { 0x4d, 0x40 }, 343 { 0x4e, 0x20 }, { REG_GFIX, 0 }, 344 { 0x6b, 0x4a }, { 0x74, 0x10 }, 345 { 0x8d, 0x4f }, { 0x8e, 0 }, 346 { 0x8f, 0 }, { 0x90, 0 }, 347 { 0x91, 0 }, { 0x96, 0 }, 348 { 0x9a, 0 }, { 0xb0, 0x84 }, 349 { 0xb1, 0x0c }, { 0xb2, 0x0e }, 350 { 0xb3, 0x82 }, { 0xb8, 0x0a }, 351 352 /* More reserved magic, some of which tweaks white balance */ 353 { 0x43, 0x0a }, { 0x44, 0xf0 }, 354 { 0x45, 0x34 }, { 0x46, 0x58 }, 355 { 0x47, 0x28 }, { 0x48, 0x3a }, 356 { 0x59, 0x88 }, { 0x5a, 0x88 }, 357 { 0x5b, 0x44 }, { 0x5c, 0x67 }, 358 { 0x5d, 0x49 }, { 0x5e, 0x0e }, 359 { 0x6c, 0x0a }, { 0x6d, 0x55 }, 360 { 0x6e, 0x11 }, { 0x6f, 0x9f }, /* "9e for advance AWB" */ 361 { 0x6a, 0x40 }, { REG_BLUE, 0x40 }, 362 { REG_RED, 0x60 }, 363 { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC|COM8_AWB }, 364 365 /* Matrix coefficients */ 366 { 0x4f, 0x80 }, { 0x50, 0x80 }, 367 { 0x51, 0 }, { 0x52, 0x22 }, 368 { 0x53, 0x5e }, { 0x54, 0x80 }, 369 { 0x58, 0x9e }, 370 371 { REG_COM16, COM16_AWBGAIN }, { REG_EDGE, 0 }, 372 { 0x75, 0x05 }, { 0x76, 0xe1 }, 373 { 0x4c, 0 }, { 0x77, 0x01 }, 374 { REG_COM13, 0xc3 }, { 0x4b, 0x09 }, 375 { 0xc9, 0x60 }, { REG_COM16, 0x38 }, 376 { 0x56, 0x40 }, 377 378 { 0x34, 0x11 }, { REG_COM11, COM11_EXP|COM11_HZAUTO }, 379 { 0xa4, 0x88 }, { 0x96, 0 }, 380 { 0x97, 0x30 }, { 0x98, 0x20 }, 381 { 0x99, 0x30 }, { 0x9a, 0x84 }, 382 { 0x9b, 0x29 }, { 0x9c, 0x03 }, 383 { 0x9d, 0x4c }, { 0x9e, 0x3f }, 384 { 0x78, 0x04 }, 385 386 /* Extra-weird stuff. Some sort of multiplexor register */ 387 { 0x79, 0x01 }, { 0xc8, 0xf0 }, 388 { 0x79, 0x0f }, { 0xc8, 0x00 }, 389 { 0x79, 0x10 }, { 0xc8, 0x7e }, 390 { 0x79, 0x0a }, { 0xc8, 0x80 }, 391 { 0x79, 0x0b }, { 0xc8, 0x01 }, 392 { 0x79, 0x0c }, { 0xc8, 0x0f }, 393 { 0x79, 0x0d }, { 0xc8, 0x20 }, 394 { 0x79, 0x09 }, { 0xc8, 0x80 }, 395 { 0x79, 0x02 }, { 0xc8, 0xc0 }, 396 { 0x79, 0x03 }, { 0xc8, 0x40 }, 397 { 0x79, 0x05 }, { 0xc8, 0x30 }, 398 { 0x79, 0x26 }, 399 400 { 0xff, 0xff }, /* END MARKER */ 401 }; 402 403 404 /* 405 * Here we'll try to encapsulate the changes for just the output 406 * video format. 407 * 408 * RGB656 and YUV422 come from OV; RGB444 is homebrewed. 409 * 410 * IMPORTANT RULE: the first entry must be for COM7, see ov7670_s_fmt for why. 411 */ 412 413 414 static struct regval_list ov7670_fmt_yuv422[] = { 415 { REG_COM7, 0x0 }, /* Selects YUV mode */ 416 { REG_RGB444, 0 }, /* No RGB444 please */ 417 { REG_COM1, 0 }, /* CCIR601 */ 418 { REG_COM15, COM15_R00FF }, 419 { REG_COM9, 0x48 }, /* 32x gain ceiling; 0x8 is reserved bit */ 420 { 0x4f, 0x80 }, /* "matrix coefficient 1" */ 421 { 0x50, 0x80 }, /* "matrix coefficient 2" */ 422 { 0x51, 0 }, /* vb */ 423 { 0x52, 0x22 }, /* "matrix coefficient 4" */ 424 { 0x53, 0x5e }, /* "matrix coefficient 5" */ 425 { 0x54, 0x80 }, /* "matrix coefficient 6" */ 426 { REG_COM13, COM13_GAMMA|COM13_UVSAT }, 427 { 0xff, 0xff }, 428 }; 429 430 static struct regval_list ov7670_fmt_rgb565[] = { 431 { REG_COM7, COM7_RGB }, /* Selects RGB mode */ 432 { REG_RGB444, 0 }, /* No RGB444 please */ 433 { REG_COM1, 0x0 }, /* CCIR601 */ 434 { REG_COM15, COM15_RGB565 }, 435 { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */ 436 { 0x4f, 0xb3 }, /* "matrix coefficient 1" */ 437 { 0x50, 0xb3 }, /* "matrix coefficient 2" */ 438 { 0x51, 0 }, /* vb */ 439 { 0x52, 0x3d }, /* "matrix coefficient 4" */ 440 { 0x53, 0xa7 }, /* "matrix coefficient 5" */ 441 { 0x54, 0xe4 }, /* "matrix coefficient 6" */ 442 { REG_COM13, COM13_GAMMA|COM13_UVSAT }, 443 { 0xff, 0xff }, 444 }; 445 446 static struct regval_list ov7670_fmt_rgb444[] = { 447 { REG_COM7, COM7_RGB }, /* Selects RGB mode */ 448 { REG_RGB444, R444_ENABLE }, /* Enable xxxxrrrr ggggbbbb */ 449 { REG_COM1, 0x0 }, /* CCIR601 */ 450 { REG_COM15, COM15_R01FE|COM15_RGB565 }, /* Data range needed? */ 451 { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */ 452 { 0x4f, 0xb3 }, /* "matrix coefficient 1" */ 453 { 0x50, 0xb3 }, /* "matrix coefficient 2" */ 454 { 0x51, 0 }, /* vb */ 455 { 0x52, 0x3d }, /* "matrix coefficient 4" */ 456 { 0x53, 0xa7 }, /* "matrix coefficient 5" */ 457 { 0x54, 0xe4 }, /* "matrix coefficient 6" */ 458 { REG_COM13, COM13_GAMMA|COM13_UVSAT|0x2 }, /* Magic rsvd bit */ 459 { 0xff, 0xff }, 460 }; 461 462 static struct regval_list ov7670_fmt_raw[] = { 463 { REG_COM7, COM7_BAYER }, 464 { REG_COM13, 0x08 }, /* No gamma, magic rsvd bit */ 465 { REG_COM16, 0x3d }, /* Edge enhancement, denoise */ 466 { REG_REG76, 0xe1 }, /* Pix correction, magic rsvd */ 467 { 0xff, 0xff }, 468 }; 469 470 471 472 /* 473 * Low-level register I/O. 474 * 475 * Note that there are two versions of these. On the XO 1, the 476 * i2c controller only does SMBUS, so that's what we use. The 477 * ov7670 is not really an SMBUS device, though, so the communication 478 * is not always entirely reliable. 479 */ 480 static int ov7670_read_smbus(struct v4l2_subdev *sd, unsigned char reg, 481 unsigned char *value) 482 { 483 struct i2c_client *client = v4l2_get_subdevdata(sd); 484 int ret; 485 486 ret = i2c_smbus_read_byte_data(client, reg); 487 if (ret >= 0) { 488 *value = (unsigned char)ret; 489 ret = 0; 490 } 491 return ret; 492 } 493 494 495 static int ov7670_write_smbus(struct v4l2_subdev *sd, unsigned char reg, 496 unsigned char value) 497 { 498 struct i2c_client *client = v4l2_get_subdevdata(sd); 499 int ret = i2c_smbus_write_byte_data(client, reg, value); 500 501 if (reg == REG_COM7 && (value & COM7_RESET)) 502 msleep(5); /* Wait for reset to run */ 503 return ret; 504 } 505 506 /* 507 * On most platforms, we'd rather do straight i2c I/O. 508 */ 509 static int ov7670_read_i2c(struct v4l2_subdev *sd, unsigned char reg, 510 unsigned char *value) 511 { 512 struct i2c_client *client = v4l2_get_subdevdata(sd); 513 u8 data = reg; 514 struct i2c_msg msg; 515 int ret; 516 517 /* 518 * Send out the register address... 519 */ 520 msg.addr = client->addr; 521 msg.flags = 0; 522 msg.len = 1; 523 msg.buf = &data; 524 ret = i2c_transfer(client->adapter, &msg, 1); 525 if (ret < 0) { 526 printk(KERN_ERR "Error %d on register write\n", ret); 527 return ret; 528 } 529 /* 530 * ...then read back the result. 531 */ 532 msg.flags = I2C_M_RD; 533 ret = i2c_transfer(client->adapter, &msg, 1); 534 if (ret >= 0) { 535 *value = data; 536 ret = 0; 537 } 538 return ret; 539 } 540 541 542 static int ov7670_write_i2c(struct v4l2_subdev *sd, unsigned char reg, 543 unsigned char value) 544 { 545 struct i2c_client *client = v4l2_get_subdevdata(sd); 546 struct i2c_msg msg; 547 unsigned char data[2] = { reg, value }; 548 int ret; 549 550 msg.addr = client->addr; 551 msg.flags = 0; 552 msg.len = 2; 553 msg.buf = data; 554 ret = i2c_transfer(client->adapter, &msg, 1); 555 if (ret > 0) 556 ret = 0; 557 if (reg == REG_COM7 && (value & COM7_RESET)) 558 msleep(5); /* Wait for reset to run */ 559 return ret; 560 } 561 562 static int ov7670_read(struct v4l2_subdev *sd, unsigned char reg, 563 unsigned char *value) 564 { 565 struct ov7670_info *info = to_state(sd); 566 if (info->use_smbus) 567 return ov7670_read_smbus(sd, reg, value); 568 else 569 return ov7670_read_i2c(sd, reg, value); 570 } 571 572 static int ov7670_write(struct v4l2_subdev *sd, unsigned char reg, 573 unsigned char value) 574 { 575 struct ov7670_info *info = to_state(sd); 576 if (info->use_smbus) 577 return ov7670_write_smbus(sd, reg, value); 578 else 579 return ov7670_write_i2c(sd, reg, value); 580 } 581 582 static int ov7670_update_bits(struct v4l2_subdev *sd, unsigned char reg, 583 unsigned char mask, unsigned char value) 584 { 585 unsigned char orig; 586 int ret; 587 588 ret = ov7670_read(sd, reg, &orig); 589 if (ret) 590 return ret; 591 592 return ov7670_write(sd, reg, (orig & ~mask) | (value & mask)); 593 } 594 595 /* 596 * Write a list of register settings; ff/ff stops the process. 597 */ 598 static int ov7670_write_array(struct v4l2_subdev *sd, struct regval_list *vals) 599 { 600 while (vals->reg_num != 0xff || vals->value != 0xff) { 601 int ret = ov7670_write(sd, vals->reg_num, vals->value); 602 if (ret < 0) 603 return ret; 604 vals++; 605 } 606 return 0; 607 } 608 609 610 /* 611 * Stuff that knows about the sensor. 612 */ 613 static int ov7670_reset(struct v4l2_subdev *sd, u32 val) 614 { 615 ov7670_write(sd, REG_COM7, COM7_RESET); 616 msleep(1); 617 return 0; 618 } 619 620 621 static int ov7670_init(struct v4l2_subdev *sd, u32 val) 622 { 623 return ov7670_write_array(sd, ov7670_default_regs); 624 } 625 626 static int ov7670_detect(struct v4l2_subdev *sd) 627 { 628 unsigned char v; 629 int ret; 630 631 ret = ov7670_init(sd, 0); 632 if (ret < 0) 633 return ret; 634 ret = ov7670_read(sd, REG_MIDH, &v); 635 if (ret < 0) 636 return ret; 637 if (v != 0x7f) /* OV manuf. id. */ 638 return -ENODEV; 639 ret = ov7670_read(sd, REG_MIDL, &v); 640 if (ret < 0) 641 return ret; 642 if (v != 0xa2) 643 return -ENODEV; 644 /* 645 * OK, we know we have an OmniVision chip...but which one? 646 */ 647 ret = ov7670_read(sd, REG_PID, &v); 648 if (ret < 0) 649 return ret; 650 if (v != 0x76) /* PID + VER = 0x76 / 0x73 */ 651 return -ENODEV; 652 ret = ov7670_read(sd, REG_VER, &v); 653 if (ret < 0) 654 return ret; 655 if (v != 0x73) /* PID + VER = 0x76 / 0x73 */ 656 return -ENODEV; 657 return 0; 658 } 659 660 661 /* 662 * Store information about the video data format. The color matrix 663 * is deeply tied into the format, so keep the relevant values here. 664 * The magic matrix numbers come from OmniVision. 665 */ 666 static struct ov7670_format_struct { 667 u32 mbus_code; 668 enum v4l2_colorspace colorspace; 669 struct regval_list *regs; 670 int cmatrix[CMATRIX_LEN]; 671 } ov7670_formats[] = { 672 { 673 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, 674 .colorspace = V4L2_COLORSPACE_SRGB, 675 .regs = ov7670_fmt_yuv422, 676 .cmatrix = { 128, -128, 0, -34, -94, 128 }, 677 }, 678 { 679 .mbus_code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE, 680 .colorspace = V4L2_COLORSPACE_SRGB, 681 .regs = ov7670_fmt_rgb444, 682 .cmatrix = { 179, -179, 0, -61, -176, 228 }, 683 }, 684 { 685 .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE, 686 .colorspace = V4L2_COLORSPACE_SRGB, 687 .regs = ov7670_fmt_rgb565, 688 .cmatrix = { 179, -179, 0, -61, -176, 228 }, 689 }, 690 { 691 .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8, 692 .colorspace = V4L2_COLORSPACE_SRGB, 693 .regs = ov7670_fmt_raw, 694 .cmatrix = { 0, 0, 0, 0, 0, 0 }, 695 }, 696 }; 697 #define N_OV7670_FMTS ARRAY_SIZE(ov7670_formats) 698 699 700 /* 701 * Then there is the issue of window sizes. Try to capture the info here. 702 */ 703 704 /* 705 * QCIF mode is done (by OV) in a very strange way - it actually looks like 706 * VGA with weird scaling options - they do *not* use the canned QCIF mode 707 * which is allegedly provided by the sensor. So here's the weird register 708 * settings. 709 */ 710 static struct regval_list ov7670_qcif_regs[] = { 711 { REG_COM3, COM3_SCALEEN|COM3_DCWEN }, 712 { REG_COM3, COM3_DCWEN }, 713 { REG_COM14, COM14_DCWEN | 0x01}, 714 { 0x73, 0xf1 }, 715 { 0xa2, 0x52 }, 716 { 0x7b, 0x1c }, 717 { 0x7c, 0x28 }, 718 { 0x7d, 0x3c }, 719 { 0x7f, 0x69 }, 720 { REG_COM9, 0x38 }, 721 { 0xa1, 0x0b }, 722 { 0x74, 0x19 }, 723 { 0x9a, 0x80 }, 724 { 0x43, 0x14 }, 725 { REG_COM13, 0xc0 }, 726 { 0xff, 0xff }, 727 }; 728 729 static struct ov7670_win_size ov7670_win_sizes[] = { 730 /* VGA */ 731 { 732 .width = VGA_WIDTH, 733 .height = VGA_HEIGHT, 734 .com7_bit = COM7_FMT_VGA, 735 .hstart = 158, /* These values from */ 736 .hstop = 14, /* Omnivision */ 737 .vstart = 10, 738 .vstop = 490, 739 .regs = NULL, 740 }, 741 /* CIF */ 742 { 743 .width = CIF_WIDTH, 744 .height = CIF_HEIGHT, 745 .com7_bit = COM7_FMT_CIF, 746 .hstart = 170, /* Empirically determined */ 747 .hstop = 90, 748 .vstart = 14, 749 .vstop = 494, 750 .regs = NULL, 751 }, 752 /* QVGA */ 753 { 754 .width = QVGA_WIDTH, 755 .height = QVGA_HEIGHT, 756 .com7_bit = COM7_FMT_QVGA, 757 .hstart = 168, /* Empirically determined */ 758 .hstop = 24, 759 .vstart = 12, 760 .vstop = 492, 761 .regs = NULL, 762 }, 763 /* QCIF */ 764 { 765 .width = QCIF_WIDTH, 766 .height = QCIF_HEIGHT, 767 .com7_bit = COM7_FMT_VGA, /* see comment above */ 768 .hstart = 456, /* Empirically determined */ 769 .hstop = 24, 770 .vstart = 14, 771 .vstop = 494, 772 .regs = ov7670_qcif_regs, 773 } 774 }; 775 776 static struct ov7670_win_size ov7675_win_sizes[] = { 777 /* 778 * Currently, only VGA is supported. Theoretically it could be possible 779 * to support CIF, QVGA and QCIF too. Taking values for ov7670 as a 780 * base and tweak them empirically could be required. 781 */ 782 { 783 .width = VGA_WIDTH, 784 .height = VGA_HEIGHT, 785 .com7_bit = COM7_FMT_VGA, 786 .hstart = 158, /* These values from */ 787 .hstop = 14, /* Omnivision */ 788 .vstart = 14, /* Empirically determined */ 789 .vstop = 494, 790 .regs = NULL, 791 } 792 }; 793 794 static void ov7675_get_framerate(struct v4l2_subdev *sd, 795 struct v4l2_fract *tpf) 796 { 797 struct ov7670_info *info = to_state(sd); 798 u32 clkrc = info->clkrc; 799 int pll_factor; 800 801 if (info->pll_bypass) 802 pll_factor = 1; 803 else 804 pll_factor = PLL_FACTOR; 805 806 clkrc++; 807 if (info->fmt->mbus_code == MEDIA_BUS_FMT_SBGGR8_1X8) 808 clkrc = (clkrc >> 1); 809 810 tpf->numerator = 1; 811 tpf->denominator = (5 * pll_factor * info->clock_speed) / 812 (4 * clkrc); 813 } 814 815 static int ov7675_apply_framerate(struct v4l2_subdev *sd) 816 { 817 struct ov7670_info *info = to_state(sd); 818 int ret; 819 820 ret = ov7670_write(sd, REG_CLKRC, info->clkrc); 821 if (ret < 0) 822 return ret; 823 824 return ov7670_write(sd, REG_DBLV, 825 info->pll_bypass ? DBLV_BYPASS : DBLV_X4); 826 } 827 828 static int ov7675_set_framerate(struct v4l2_subdev *sd, 829 struct v4l2_fract *tpf) 830 { 831 struct ov7670_info *info = to_state(sd); 832 u32 clkrc; 833 int pll_factor; 834 835 /* 836 * The formula is fps = 5/4*pixclk for YUV/RGB and 837 * fps = 5/2*pixclk for RAW. 838 * 839 * pixclk = clock_speed / (clkrc + 1) * PLLfactor 840 * 841 */ 842 if (tpf->numerator == 0 || tpf->denominator == 0) { 843 clkrc = 0; 844 } else { 845 pll_factor = info->pll_bypass ? 1 : PLL_FACTOR; 846 clkrc = (5 * pll_factor * info->clock_speed * tpf->numerator) / 847 (4 * tpf->denominator); 848 if (info->fmt->mbus_code == MEDIA_BUS_FMT_SBGGR8_1X8) 849 clkrc = (clkrc << 1); 850 clkrc--; 851 } 852 853 /* 854 * The datasheet claims that clkrc = 0 will divide the input clock by 1 855 * but we've checked with an oscilloscope that it divides by 2 instead. 856 * So, if clkrc = 0 just bypass the divider. 857 */ 858 if (clkrc <= 0) 859 clkrc = CLK_EXT; 860 else if (clkrc > CLK_SCALE) 861 clkrc = CLK_SCALE; 862 info->clkrc = clkrc; 863 864 /* Recalculate frame rate */ 865 ov7675_get_framerate(sd, tpf); 866 867 /* 868 * If the device is not powered up by the host driver do 869 * not apply any changes to H/W at this time. Instead 870 * the framerate will be restored right after power-up. 871 */ 872 if (info->on) 873 return ov7675_apply_framerate(sd); 874 875 return 0; 876 } 877 878 static void ov7670_get_framerate_legacy(struct v4l2_subdev *sd, 879 struct v4l2_fract *tpf) 880 { 881 struct ov7670_info *info = to_state(sd); 882 883 tpf->numerator = 1; 884 tpf->denominator = info->clock_speed; 885 if ((info->clkrc & CLK_EXT) == 0 && (info->clkrc & CLK_SCALE) > 1) 886 tpf->denominator /= (info->clkrc & CLK_SCALE); 887 } 888 889 static int ov7670_set_framerate_legacy(struct v4l2_subdev *sd, 890 struct v4l2_fract *tpf) 891 { 892 struct ov7670_info *info = to_state(sd); 893 int div; 894 895 if (tpf->numerator == 0 || tpf->denominator == 0) 896 div = 1; /* Reset to full rate */ 897 else 898 div = (tpf->numerator * info->clock_speed) / tpf->denominator; 899 if (div == 0) 900 div = 1; 901 else if (div > CLK_SCALE) 902 div = CLK_SCALE; 903 info->clkrc = (info->clkrc & 0x80) | div; 904 tpf->numerator = 1; 905 tpf->denominator = info->clock_speed / div; 906 907 /* 908 * If the device is not powered up by the host driver do 909 * not apply any changes to H/W at this time. Instead 910 * the framerate will be restored right after power-up. 911 */ 912 if (info->on) 913 return ov7670_write(sd, REG_CLKRC, info->clkrc); 914 915 return 0; 916 } 917 918 /* 919 * Store a set of start/stop values into the camera. 920 */ 921 static int ov7670_set_hw(struct v4l2_subdev *sd, int hstart, int hstop, 922 int vstart, int vstop) 923 { 924 int ret; 925 unsigned char v; 926 /* 927 * Horizontal: 11 bits, top 8 live in hstart and hstop. Bottom 3 of 928 * hstart are in href[2:0], bottom 3 of hstop in href[5:3]. There is 929 * a mystery "edge offset" value in the top two bits of href. 930 */ 931 ret = ov7670_write(sd, REG_HSTART, (hstart >> 3) & 0xff); 932 ret += ov7670_write(sd, REG_HSTOP, (hstop >> 3) & 0xff); 933 ret += ov7670_read(sd, REG_HREF, &v); 934 v = (v & 0xc0) | ((hstop & 0x7) << 3) | (hstart & 0x7); 935 msleep(10); 936 ret += ov7670_write(sd, REG_HREF, v); 937 /* 938 * Vertical: similar arrangement, but only 10 bits. 939 */ 940 ret += ov7670_write(sd, REG_VSTART, (vstart >> 2) & 0xff); 941 ret += ov7670_write(sd, REG_VSTOP, (vstop >> 2) & 0xff); 942 ret += ov7670_read(sd, REG_VREF, &v); 943 v = (v & 0xf0) | ((vstop & 0x3) << 2) | (vstart & 0x3); 944 msleep(10); 945 ret += ov7670_write(sd, REG_VREF, v); 946 return ret; 947 } 948 949 950 static int ov7670_enum_mbus_code(struct v4l2_subdev *sd, 951 struct v4l2_subdev_pad_config *cfg, 952 struct v4l2_subdev_mbus_code_enum *code) 953 { 954 if (code->pad || code->index >= N_OV7670_FMTS) 955 return -EINVAL; 956 957 code->code = ov7670_formats[code->index].mbus_code; 958 return 0; 959 } 960 961 static int ov7670_try_fmt_internal(struct v4l2_subdev *sd, 962 struct v4l2_mbus_framefmt *fmt, 963 struct ov7670_format_struct **ret_fmt, 964 struct ov7670_win_size **ret_wsize) 965 { 966 int index, i; 967 struct ov7670_win_size *wsize; 968 struct ov7670_info *info = to_state(sd); 969 unsigned int n_win_sizes = info->devtype->n_win_sizes; 970 unsigned int win_sizes_limit = n_win_sizes; 971 972 for (index = 0; index < N_OV7670_FMTS; index++) 973 if (ov7670_formats[index].mbus_code == fmt->code) 974 break; 975 if (index >= N_OV7670_FMTS) { 976 /* default to first format */ 977 index = 0; 978 fmt->code = ov7670_formats[0].mbus_code; 979 } 980 if (ret_fmt != NULL) 981 *ret_fmt = ov7670_formats + index; 982 /* 983 * Fields: the OV devices claim to be progressive. 984 */ 985 fmt->field = V4L2_FIELD_NONE; 986 987 /* 988 * Don't consider values that don't match min_height and min_width 989 * constraints. 990 */ 991 if (info->min_width || info->min_height) 992 for (i = 0; i < n_win_sizes; i++) { 993 wsize = info->devtype->win_sizes + i; 994 995 if (wsize->width < info->min_width || 996 wsize->height < info->min_height) { 997 win_sizes_limit = i; 998 break; 999 } 1000 } 1001 /* 1002 * Round requested image size down to the nearest 1003 * we support, but not below the smallest. 1004 */ 1005 for (wsize = info->devtype->win_sizes; 1006 wsize < info->devtype->win_sizes + win_sizes_limit; wsize++) 1007 if (fmt->width >= wsize->width && fmt->height >= wsize->height) 1008 break; 1009 if (wsize >= info->devtype->win_sizes + win_sizes_limit) 1010 wsize--; /* Take the smallest one */ 1011 if (ret_wsize != NULL) 1012 *ret_wsize = wsize; 1013 /* 1014 * Note the size we'll actually handle. 1015 */ 1016 fmt->width = wsize->width; 1017 fmt->height = wsize->height; 1018 fmt->colorspace = ov7670_formats[index].colorspace; 1019 1020 info->format = *fmt; 1021 1022 return 0; 1023 } 1024 1025 static int ov7670_apply_fmt(struct v4l2_subdev *sd) 1026 { 1027 struct ov7670_info *info = to_state(sd); 1028 struct ov7670_win_size *wsize = info->wsize; 1029 unsigned char com7, com10 = 0; 1030 int ret; 1031 1032 /* 1033 * COM7 is a pain in the ass, it doesn't like to be read then 1034 * quickly written afterward. But we have everything we need 1035 * to set it absolutely here, as long as the format-specific 1036 * register sets list it first. 1037 */ 1038 com7 = info->fmt->regs[0].value; 1039 com7 |= wsize->com7_bit; 1040 ret = ov7670_write(sd, REG_COM7, com7); 1041 if (ret) 1042 return ret; 1043 1044 /* 1045 * Configure the media bus through COM10 register 1046 */ 1047 if (info->mbus_config & V4L2_MBUS_VSYNC_ACTIVE_LOW) 1048 com10 |= COM10_VS_NEG; 1049 if (info->mbus_config & V4L2_MBUS_HSYNC_ACTIVE_LOW) 1050 com10 |= COM10_HREF_REV; 1051 if (info->pclk_hb_disable) 1052 com10 |= COM10_PCLK_HB; 1053 ret = ov7670_write(sd, REG_COM10, com10); 1054 if (ret) 1055 return ret; 1056 1057 /* 1058 * Now write the rest of the array. Also store start/stops 1059 */ 1060 ret = ov7670_write_array(sd, info->fmt->regs + 1); 1061 if (ret) 1062 return ret; 1063 1064 ret = ov7670_set_hw(sd, wsize->hstart, wsize->hstop, wsize->vstart, 1065 wsize->vstop); 1066 if (ret) 1067 return ret; 1068 1069 if (wsize->regs) { 1070 ret = ov7670_write_array(sd, wsize->regs); 1071 if (ret) 1072 return ret; 1073 } 1074 1075 /* 1076 * If we're running RGB565, we must rewrite clkrc after setting 1077 * the other parameters or the image looks poor. If we're *not* 1078 * doing RGB565, we must not rewrite clkrc or the image looks 1079 * *really* poor. 1080 * 1081 * (Update) Now that we retain clkrc state, we should be able 1082 * to write it unconditionally, and that will make the frame 1083 * rate persistent too. 1084 */ 1085 ret = ov7670_write(sd, REG_CLKRC, info->clkrc); 1086 if (ret) 1087 return ret; 1088 1089 return 0; 1090 } 1091 1092 /* 1093 * Set a format. 1094 */ 1095 static int ov7670_set_fmt(struct v4l2_subdev *sd, 1096 struct v4l2_subdev_pad_config *cfg, 1097 struct v4l2_subdev_format *format) 1098 { 1099 struct ov7670_info *info = to_state(sd); 1100 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1101 struct v4l2_mbus_framefmt *mbus_fmt; 1102 #endif 1103 int ret; 1104 1105 if (format->pad) 1106 return -EINVAL; 1107 1108 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 1109 ret = ov7670_try_fmt_internal(sd, &format->format, NULL, NULL); 1110 if (ret) 1111 return ret; 1112 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1113 mbus_fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad); 1114 *mbus_fmt = format->format; 1115 return 0; 1116 #else 1117 return -ENOTTY; 1118 #endif 1119 } 1120 1121 ret = ov7670_try_fmt_internal(sd, &format->format, &info->fmt, &info->wsize); 1122 if (ret) 1123 return ret; 1124 1125 /* 1126 * If the device is not powered up by the host driver do 1127 * not apply any changes to H/W at this time. Instead 1128 * the frame format will be restored right after power-up. 1129 */ 1130 if (info->on) 1131 return ov7670_apply_fmt(sd); 1132 1133 return 0; 1134 } 1135 1136 static int ov7670_get_fmt(struct v4l2_subdev *sd, 1137 struct v4l2_subdev_pad_config *cfg, 1138 struct v4l2_subdev_format *format) 1139 { 1140 struct ov7670_info *info = to_state(sd); 1141 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1142 struct v4l2_mbus_framefmt *mbus_fmt; 1143 #endif 1144 1145 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 1146 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1147 mbus_fmt = v4l2_subdev_get_try_format(sd, cfg, 0); 1148 format->format = *mbus_fmt; 1149 return 0; 1150 #else 1151 return -ENOTTY; 1152 #endif 1153 } else { 1154 format->format = info->format; 1155 } 1156 1157 return 0; 1158 } 1159 1160 /* 1161 * Implement G/S_PARM. There is a "high quality" mode we could try 1162 * to do someday; for now, we just do the frame rate tweak. 1163 */ 1164 static int ov7670_g_frame_interval(struct v4l2_subdev *sd, 1165 struct v4l2_subdev_frame_interval *ival) 1166 { 1167 struct ov7670_info *info = to_state(sd); 1168 1169 1170 info->devtype->get_framerate(sd, &ival->interval); 1171 1172 return 0; 1173 } 1174 1175 static int ov7670_s_frame_interval(struct v4l2_subdev *sd, 1176 struct v4l2_subdev_frame_interval *ival) 1177 { 1178 struct v4l2_fract *tpf = &ival->interval; 1179 struct ov7670_info *info = to_state(sd); 1180 1181 1182 return info->devtype->set_framerate(sd, tpf); 1183 } 1184 1185 1186 /* 1187 * Frame intervals. Since frame rates are controlled with the clock 1188 * divider, we can only do 30/n for integer n values. So no continuous 1189 * or stepwise options. Here we just pick a handful of logical values. 1190 */ 1191 1192 static int ov7670_frame_rates[] = { 30, 15, 10, 5, 1 }; 1193 1194 static int ov7670_enum_frame_interval(struct v4l2_subdev *sd, 1195 struct v4l2_subdev_pad_config *cfg, 1196 struct v4l2_subdev_frame_interval_enum *fie) 1197 { 1198 struct ov7670_info *info = to_state(sd); 1199 unsigned int n_win_sizes = info->devtype->n_win_sizes; 1200 int i; 1201 1202 if (fie->pad) 1203 return -EINVAL; 1204 if (fie->index >= ARRAY_SIZE(ov7670_frame_rates)) 1205 return -EINVAL; 1206 1207 /* 1208 * Check if the width/height is valid. 1209 * 1210 * If a minimum width/height was requested, filter out the capture 1211 * windows that fall outside that. 1212 */ 1213 for (i = 0; i < n_win_sizes; i++) { 1214 struct ov7670_win_size *win = &info->devtype->win_sizes[i]; 1215 1216 if (info->min_width && win->width < info->min_width) 1217 continue; 1218 if (info->min_height && win->height < info->min_height) 1219 continue; 1220 if (fie->width == win->width && fie->height == win->height) 1221 break; 1222 } 1223 if (i == n_win_sizes) 1224 return -EINVAL; 1225 fie->interval.numerator = 1; 1226 fie->interval.denominator = ov7670_frame_rates[fie->index]; 1227 return 0; 1228 } 1229 1230 /* 1231 * Frame size enumeration 1232 */ 1233 static int ov7670_enum_frame_size(struct v4l2_subdev *sd, 1234 struct v4l2_subdev_pad_config *cfg, 1235 struct v4l2_subdev_frame_size_enum *fse) 1236 { 1237 struct ov7670_info *info = to_state(sd); 1238 int i; 1239 int num_valid = -1; 1240 __u32 index = fse->index; 1241 unsigned int n_win_sizes = info->devtype->n_win_sizes; 1242 1243 if (fse->pad) 1244 return -EINVAL; 1245 1246 /* 1247 * If a minimum width/height was requested, filter out the capture 1248 * windows that fall outside that. 1249 */ 1250 for (i = 0; i < n_win_sizes; i++) { 1251 struct ov7670_win_size *win = &info->devtype->win_sizes[i]; 1252 if (info->min_width && win->width < info->min_width) 1253 continue; 1254 if (info->min_height && win->height < info->min_height) 1255 continue; 1256 if (index == ++num_valid) { 1257 fse->min_width = fse->max_width = win->width; 1258 fse->min_height = fse->max_height = win->height; 1259 return 0; 1260 } 1261 } 1262 1263 return -EINVAL; 1264 } 1265 1266 /* 1267 * Code for dealing with controls. 1268 */ 1269 1270 static int ov7670_store_cmatrix(struct v4l2_subdev *sd, 1271 int matrix[CMATRIX_LEN]) 1272 { 1273 int i, ret; 1274 unsigned char signbits = 0; 1275 1276 /* 1277 * Weird crap seems to exist in the upper part of 1278 * the sign bits register, so let's preserve it. 1279 */ 1280 ret = ov7670_read(sd, REG_CMATRIX_SIGN, &signbits); 1281 signbits &= 0xc0; 1282 1283 for (i = 0; i < CMATRIX_LEN; i++) { 1284 unsigned char raw; 1285 1286 if (matrix[i] < 0) { 1287 signbits |= (1 << i); 1288 if (matrix[i] < -255) 1289 raw = 0xff; 1290 else 1291 raw = (-1 * matrix[i]) & 0xff; 1292 } 1293 else { 1294 if (matrix[i] > 255) 1295 raw = 0xff; 1296 else 1297 raw = matrix[i] & 0xff; 1298 } 1299 ret += ov7670_write(sd, REG_CMATRIX_BASE + i, raw); 1300 } 1301 ret += ov7670_write(sd, REG_CMATRIX_SIGN, signbits); 1302 return ret; 1303 } 1304 1305 1306 /* 1307 * Hue also requires messing with the color matrix. It also requires 1308 * trig functions, which tend not to be well supported in the kernel. 1309 * So here is a simple table of sine values, 0-90 degrees, in steps 1310 * of five degrees. Values are multiplied by 1000. 1311 * 1312 * The following naive approximate trig functions require an argument 1313 * carefully limited to -180 <= theta <= 180. 1314 */ 1315 #define SIN_STEP 5 1316 static const int ov7670_sin_table[] = { 1317 0, 87, 173, 258, 342, 422, 1318 499, 573, 642, 707, 766, 819, 1319 866, 906, 939, 965, 984, 996, 1320 1000 1321 }; 1322 1323 static int ov7670_sine(int theta) 1324 { 1325 int chs = 1; 1326 int sine; 1327 1328 if (theta < 0) { 1329 theta = -theta; 1330 chs = -1; 1331 } 1332 if (theta <= 90) 1333 sine = ov7670_sin_table[theta/SIN_STEP]; 1334 else { 1335 theta -= 90; 1336 sine = 1000 - ov7670_sin_table[theta/SIN_STEP]; 1337 } 1338 return sine*chs; 1339 } 1340 1341 static int ov7670_cosine(int theta) 1342 { 1343 theta = 90 - theta; 1344 if (theta > 180) 1345 theta -= 360; 1346 else if (theta < -180) 1347 theta += 360; 1348 return ov7670_sine(theta); 1349 } 1350 1351 1352 1353 1354 static void ov7670_calc_cmatrix(struct ov7670_info *info, 1355 int matrix[CMATRIX_LEN], int sat, int hue) 1356 { 1357 int i; 1358 /* 1359 * Apply the current saturation setting first. 1360 */ 1361 for (i = 0; i < CMATRIX_LEN; i++) 1362 matrix[i] = (info->fmt->cmatrix[i] * sat) >> 7; 1363 /* 1364 * Then, if need be, rotate the hue value. 1365 */ 1366 if (hue != 0) { 1367 int sinth, costh, tmpmatrix[CMATRIX_LEN]; 1368 1369 memcpy(tmpmatrix, matrix, CMATRIX_LEN*sizeof(int)); 1370 sinth = ov7670_sine(hue); 1371 costh = ov7670_cosine(hue); 1372 1373 matrix[0] = (matrix[3]*sinth + matrix[0]*costh)/1000; 1374 matrix[1] = (matrix[4]*sinth + matrix[1]*costh)/1000; 1375 matrix[2] = (matrix[5]*sinth + matrix[2]*costh)/1000; 1376 matrix[3] = (matrix[3]*costh - matrix[0]*sinth)/1000; 1377 matrix[4] = (matrix[4]*costh - matrix[1]*sinth)/1000; 1378 matrix[5] = (matrix[5]*costh - matrix[2]*sinth)/1000; 1379 } 1380 } 1381 1382 1383 1384 static int ov7670_s_sat_hue(struct v4l2_subdev *sd, int sat, int hue) 1385 { 1386 struct ov7670_info *info = to_state(sd); 1387 int matrix[CMATRIX_LEN]; 1388 int ret; 1389 1390 ov7670_calc_cmatrix(info, matrix, sat, hue); 1391 ret = ov7670_store_cmatrix(sd, matrix); 1392 return ret; 1393 } 1394 1395 1396 /* 1397 * Some weird registers seem to store values in a sign/magnitude format! 1398 */ 1399 1400 static unsigned char ov7670_abs_to_sm(unsigned char v) 1401 { 1402 if (v > 127) 1403 return v & 0x7f; 1404 return (128 - v) | 0x80; 1405 } 1406 1407 static int ov7670_s_brightness(struct v4l2_subdev *sd, int value) 1408 { 1409 unsigned char com8 = 0, v; 1410 int ret; 1411 1412 ov7670_read(sd, REG_COM8, &com8); 1413 com8 &= ~COM8_AEC; 1414 ov7670_write(sd, REG_COM8, com8); 1415 v = ov7670_abs_to_sm(value); 1416 ret = ov7670_write(sd, REG_BRIGHT, v); 1417 return ret; 1418 } 1419 1420 static int ov7670_s_contrast(struct v4l2_subdev *sd, int value) 1421 { 1422 return ov7670_write(sd, REG_CONTRAS, (unsigned char) value); 1423 } 1424 1425 static int ov7670_s_hflip(struct v4l2_subdev *sd, int value) 1426 { 1427 unsigned char v = 0; 1428 int ret; 1429 1430 ret = ov7670_read(sd, REG_MVFP, &v); 1431 if (value) 1432 v |= MVFP_MIRROR; 1433 else 1434 v &= ~MVFP_MIRROR; 1435 msleep(10); /* FIXME */ 1436 ret += ov7670_write(sd, REG_MVFP, v); 1437 return ret; 1438 } 1439 1440 static int ov7670_s_vflip(struct v4l2_subdev *sd, int value) 1441 { 1442 unsigned char v = 0; 1443 int ret; 1444 1445 ret = ov7670_read(sd, REG_MVFP, &v); 1446 if (value) 1447 v |= MVFP_FLIP; 1448 else 1449 v &= ~MVFP_FLIP; 1450 msleep(10); /* FIXME */ 1451 ret += ov7670_write(sd, REG_MVFP, v); 1452 return ret; 1453 } 1454 1455 /* 1456 * GAIN is split between REG_GAIN and REG_VREF[7:6]. If one believes 1457 * the data sheet, the VREF parts should be the most significant, but 1458 * experience shows otherwise. There seems to be little value in 1459 * messing with the VREF bits, so we leave them alone. 1460 */ 1461 static int ov7670_g_gain(struct v4l2_subdev *sd, __s32 *value) 1462 { 1463 int ret; 1464 unsigned char gain; 1465 1466 ret = ov7670_read(sd, REG_GAIN, &gain); 1467 *value = gain; 1468 return ret; 1469 } 1470 1471 static int ov7670_s_gain(struct v4l2_subdev *sd, int value) 1472 { 1473 int ret; 1474 unsigned char com8; 1475 1476 ret = ov7670_write(sd, REG_GAIN, value & 0xff); 1477 /* Have to turn off AGC as well */ 1478 if (ret == 0) { 1479 ret = ov7670_read(sd, REG_COM8, &com8); 1480 ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AGC); 1481 } 1482 return ret; 1483 } 1484 1485 /* 1486 * Tweak autogain. 1487 */ 1488 static int ov7670_s_autogain(struct v4l2_subdev *sd, int value) 1489 { 1490 int ret; 1491 unsigned char com8; 1492 1493 ret = ov7670_read(sd, REG_COM8, &com8); 1494 if (ret == 0) { 1495 if (value) 1496 com8 |= COM8_AGC; 1497 else 1498 com8 &= ~COM8_AGC; 1499 ret = ov7670_write(sd, REG_COM8, com8); 1500 } 1501 return ret; 1502 } 1503 1504 static int ov7670_s_exp(struct v4l2_subdev *sd, int value) 1505 { 1506 int ret; 1507 unsigned char com1, com8, aech, aechh; 1508 1509 ret = ov7670_read(sd, REG_COM1, &com1) + 1510 ov7670_read(sd, REG_COM8, &com8) + 1511 ov7670_read(sd, REG_AECHH, &aechh); 1512 if (ret) 1513 return ret; 1514 1515 com1 = (com1 & 0xfc) | (value & 0x03); 1516 aech = (value >> 2) & 0xff; 1517 aechh = (aechh & 0xc0) | ((value >> 10) & 0x3f); 1518 ret = ov7670_write(sd, REG_COM1, com1) + 1519 ov7670_write(sd, REG_AECH, aech) + 1520 ov7670_write(sd, REG_AECHH, aechh); 1521 /* Have to turn off AEC as well */ 1522 if (ret == 0) 1523 ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AEC); 1524 return ret; 1525 } 1526 1527 /* 1528 * Tweak autoexposure. 1529 */ 1530 static int ov7670_s_autoexp(struct v4l2_subdev *sd, 1531 enum v4l2_exposure_auto_type value) 1532 { 1533 int ret; 1534 unsigned char com8; 1535 1536 ret = ov7670_read(sd, REG_COM8, &com8); 1537 if (ret == 0) { 1538 if (value == V4L2_EXPOSURE_AUTO) 1539 com8 |= COM8_AEC; 1540 else 1541 com8 &= ~COM8_AEC; 1542 ret = ov7670_write(sd, REG_COM8, com8); 1543 } 1544 return ret; 1545 } 1546 1547 static const char * const ov7670_test_pattern_menu[] = { 1548 "No test output", 1549 "Shifting \"1\"", 1550 "8-bar color bar", 1551 "Fade to gray color bar", 1552 }; 1553 1554 static int ov7670_s_test_pattern(struct v4l2_subdev *sd, int value) 1555 { 1556 int ret; 1557 1558 ret = ov7670_update_bits(sd, REG_SCALING_XSC, TEST_PATTTERN_0, 1559 value & BIT(0) ? TEST_PATTTERN_0 : 0); 1560 if (ret) 1561 return ret; 1562 1563 return ov7670_update_bits(sd, REG_SCALING_YSC, TEST_PATTTERN_1, 1564 value & BIT(1) ? TEST_PATTTERN_1 : 0); 1565 } 1566 1567 static int ov7670_g_volatile_ctrl(struct v4l2_ctrl *ctrl) 1568 { 1569 struct v4l2_subdev *sd = to_sd(ctrl); 1570 struct ov7670_info *info = to_state(sd); 1571 1572 switch (ctrl->id) { 1573 case V4L2_CID_AUTOGAIN: 1574 return ov7670_g_gain(sd, &info->gain->val); 1575 } 1576 return -EINVAL; 1577 } 1578 1579 static int ov7670_s_ctrl(struct v4l2_ctrl *ctrl) 1580 { 1581 struct v4l2_subdev *sd = to_sd(ctrl); 1582 struct ov7670_info *info = to_state(sd); 1583 1584 switch (ctrl->id) { 1585 case V4L2_CID_BRIGHTNESS: 1586 return ov7670_s_brightness(sd, ctrl->val); 1587 case V4L2_CID_CONTRAST: 1588 return ov7670_s_contrast(sd, ctrl->val); 1589 case V4L2_CID_SATURATION: 1590 return ov7670_s_sat_hue(sd, 1591 info->saturation->val, info->hue->val); 1592 case V4L2_CID_VFLIP: 1593 return ov7670_s_vflip(sd, ctrl->val); 1594 case V4L2_CID_HFLIP: 1595 return ov7670_s_hflip(sd, ctrl->val); 1596 case V4L2_CID_AUTOGAIN: 1597 /* Only set manual gain if auto gain is not explicitly 1598 turned on. */ 1599 if (!ctrl->val) { 1600 /* ov7670_s_gain turns off auto gain */ 1601 return ov7670_s_gain(sd, info->gain->val); 1602 } 1603 return ov7670_s_autogain(sd, ctrl->val); 1604 case V4L2_CID_EXPOSURE_AUTO: 1605 /* Only set manual exposure if auto exposure is not explicitly 1606 turned on. */ 1607 if (ctrl->val == V4L2_EXPOSURE_MANUAL) { 1608 /* ov7670_s_exp turns off auto exposure */ 1609 return ov7670_s_exp(sd, info->exposure->val); 1610 } 1611 return ov7670_s_autoexp(sd, ctrl->val); 1612 case V4L2_CID_TEST_PATTERN: 1613 return ov7670_s_test_pattern(sd, ctrl->val); 1614 } 1615 return -EINVAL; 1616 } 1617 1618 static const struct v4l2_ctrl_ops ov7670_ctrl_ops = { 1619 .s_ctrl = ov7670_s_ctrl, 1620 .g_volatile_ctrl = ov7670_g_volatile_ctrl, 1621 }; 1622 1623 #ifdef CONFIG_VIDEO_ADV_DEBUG 1624 static int ov7670_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) 1625 { 1626 unsigned char val = 0; 1627 int ret; 1628 1629 ret = ov7670_read(sd, reg->reg & 0xff, &val); 1630 reg->val = val; 1631 reg->size = 1; 1632 return ret; 1633 } 1634 1635 static int ov7670_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg) 1636 { 1637 ov7670_write(sd, reg->reg & 0xff, reg->val & 0xff); 1638 return 0; 1639 } 1640 #endif 1641 1642 static void ov7670_power_on(struct v4l2_subdev *sd) 1643 { 1644 struct ov7670_info *info = to_state(sd); 1645 1646 if (info->on) 1647 return; 1648 1649 clk_prepare_enable(info->clk); 1650 1651 if (info->pwdn_gpio) 1652 gpiod_set_value(info->pwdn_gpio, 0); 1653 if (info->resetb_gpio) { 1654 gpiod_set_value(info->resetb_gpio, 1); 1655 usleep_range(500, 1000); 1656 gpiod_set_value(info->resetb_gpio, 0); 1657 } 1658 if (info->pwdn_gpio || info->resetb_gpio || info->clk) 1659 usleep_range(3000, 5000); 1660 1661 info->on = true; 1662 } 1663 1664 static void ov7670_power_off(struct v4l2_subdev *sd) 1665 { 1666 struct ov7670_info *info = to_state(sd); 1667 1668 if (!info->on) 1669 return; 1670 1671 clk_disable_unprepare(info->clk); 1672 1673 if (info->pwdn_gpio) 1674 gpiod_set_value(info->pwdn_gpio, 1); 1675 1676 info->on = false; 1677 } 1678 1679 static int ov7670_s_power(struct v4l2_subdev *sd, int on) 1680 { 1681 struct ov7670_info *info = to_state(sd); 1682 1683 if (info->on == on) 1684 return 0; 1685 1686 if (on) { 1687 ov7670_power_on (sd); 1688 ov7670_init(sd, 0); 1689 ov7670_apply_fmt(sd); 1690 ov7675_apply_framerate(sd); 1691 v4l2_ctrl_handler_setup(&info->hdl); 1692 } else { 1693 ov7670_power_off (sd); 1694 } 1695 1696 return 0; 1697 } 1698 1699 static void ov7670_get_default_format(struct v4l2_subdev *sd, 1700 struct v4l2_mbus_framefmt *format) 1701 { 1702 struct ov7670_info *info = to_state(sd); 1703 1704 format->width = info->devtype->win_sizes[0].width; 1705 format->height = info->devtype->win_sizes[0].height; 1706 format->colorspace = info->fmt->colorspace; 1707 format->code = info->fmt->mbus_code; 1708 format->field = V4L2_FIELD_NONE; 1709 } 1710 1711 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1712 static int ov7670_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) 1713 { 1714 struct v4l2_mbus_framefmt *format = 1715 v4l2_subdev_get_try_format(sd, fh->pad, 0); 1716 1717 ov7670_get_default_format(sd, format); 1718 1719 return 0; 1720 } 1721 #endif 1722 1723 /* ----------------------------------------------------------------------- */ 1724 1725 static const struct v4l2_subdev_core_ops ov7670_core_ops = { 1726 .reset = ov7670_reset, 1727 .init = ov7670_init, 1728 .s_power = ov7670_s_power, 1729 .log_status = v4l2_ctrl_subdev_log_status, 1730 .subscribe_event = v4l2_ctrl_subdev_subscribe_event, 1731 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 1732 #ifdef CONFIG_VIDEO_ADV_DEBUG 1733 .g_register = ov7670_g_register, 1734 .s_register = ov7670_s_register, 1735 #endif 1736 }; 1737 1738 static const struct v4l2_subdev_video_ops ov7670_video_ops = { 1739 .s_frame_interval = ov7670_s_frame_interval, 1740 .g_frame_interval = ov7670_g_frame_interval, 1741 }; 1742 1743 static const struct v4l2_subdev_pad_ops ov7670_pad_ops = { 1744 .enum_frame_interval = ov7670_enum_frame_interval, 1745 .enum_frame_size = ov7670_enum_frame_size, 1746 .enum_mbus_code = ov7670_enum_mbus_code, 1747 .get_fmt = ov7670_get_fmt, 1748 .set_fmt = ov7670_set_fmt, 1749 }; 1750 1751 static const struct v4l2_subdev_ops ov7670_ops = { 1752 .core = &ov7670_core_ops, 1753 .video = &ov7670_video_ops, 1754 .pad = &ov7670_pad_ops, 1755 }; 1756 1757 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1758 static const struct v4l2_subdev_internal_ops ov7670_subdev_internal_ops = { 1759 .open = ov7670_open, 1760 }; 1761 #endif 1762 1763 /* ----------------------------------------------------------------------- */ 1764 1765 static const struct ov7670_devtype ov7670_devdata[] = { 1766 [MODEL_OV7670] = { 1767 .win_sizes = ov7670_win_sizes, 1768 .n_win_sizes = ARRAY_SIZE(ov7670_win_sizes), 1769 .set_framerate = ov7670_set_framerate_legacy, 1770 .get_framerate = ov7670_get_framerate_legacy, 1771 }, 1772 [MODEL_OV7675] = { 1773 .win_sizes = ov7675_win_sizes, 1774 .n_win_sizes = ARRAY_SIZE(ov7675_win_sizes), 1775 .set_framerate = ov7675_set_framerate, 1776 .get_framerate = ov7675_get_framerate, 1777 }, 1778 }; 1779 1780 static int ov7670_init_gpio(struct i2c_client *client, struct ov7670_info *info) 1781 { 1782 info->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown", 1783 GPIOD_OUT_LOW); 1784 if (IS_ERR(info->pwdn_gpio)) { 1785 dev_info(&client->dev, "can't get %s GPIO\n", "powerdown"); 1786 return PTR_ERR(info->pwdn_gpio); 1787 } 1788 1789 info->resetb_gpio = devm_gpiod_get_optional(&client->dev, "reset", 1790 GPIOD_OUT_LOW); 1791 if (IS_ERR(info->resetb_gpio)) { 1792 dev_info(&client->dev, "can't get %s GPIO\n", "reset"); 1793 return PTR_ERR(info->resetb_gpio); 1794 } 1795 1796 usleep_range(3000, 5000); 1797 1798 return 0; 1799 } 1800 1801 /* 1802 * ov7670_parse_dt() - Parse device tree to collect mbus configuration 1803 * properties 1804 */ 1805 static int ov7670_parse_dt(struct device *dev, 1806 struct ov7670_info *info) 1807 { 1808 struct fwnode_handle *fwnode = dev_fwnode(dev); 1809 struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 }; 1810 struct fwnode_handle *ep; 1811 int ret; 1812 1813 if (!fwnode) 1814 return -EINVAL; 1815 1816 info->pclk_hb_disable = false; 1817 if (fwnode_property_present(fwnode, "ov7670,pclk-hb-disable")) 1818 info->pclk_hb_disable = true; 1819 1820 ep = fwnode_graph_get_next_endpoint(fwnode, NULL); 1821 if (!ep) 1822 return -EINVAL; 1823 1824 ret = v4l2_fwnode_endpoint_parse(ep, &bus_cfg); 1825 fwnode_handle_put(ep); 1826 if (ret) 1827 return ret; 1828 1829 if (bus_cfg.bus_type != V4L2_MBUS_PARALLEL) { 1830 dev_err(dev, "Unsupported media bus type\n"); 1831 return ret; 1832 } 1833 info->mbus_config = bus_cfg.bus.parallel.flags; 1834 1835 return 0; 1836 } 1837 1838 static int ov7670_probe(struct i2c_client *client, 1839 const struct i2c_device_id *id) 1840 { 1841 struct v4l2_fract tpf; 1842 struct v4l2_subdev *sd; 1843 struct ov7670_info *info; 1844 int ret; 1845 1846 info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL); 1847 if (info == NULL) 1848 return -ENOMEM; 1849 sd = &info->sd; 1850 v4l2_i2c_subdev_init(sd, client, &ov7670_ops); 1851 1852 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1853 sd->internal_ops = &ov7670_subdev_internal_ops; 1854 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; 1855 #endif 1856 1857 info->clock_speed = 30; /* default: a guess */ 1858 1859 if (dev_fwnode(&client->dev)) { 1860 ret = ov7670_parse_dt(&client->dev, info); 1861 if (ret) 1862 return ret; 1863 1864 } else if (client->dev.platform_data) { 1865 struct ov7670_config *config = client->dev.platform_data; 1866 1867 /* 1868 * Must apply configuration before initializing device, because it 1869 * selects I/O method. 1870 */ 1871 info->min_width = config->min_width; 1872 info->min_height = config->min_height; 1873 info->use_smbus = config->use_smbus; 1874 1875 if (config->clock_speed) 1876 info->clock_speed = config->clock_speed; 1877 1878 if (config->pll_bypass) 1879 info->pll_bypass = true; 1880 1881 if (config->pclk_hb_disable) 1882 info->pclk_hb_disable = true; 1883 } 1884 1885 info->clk = devm_clk_get(&client->dev, "xclk"); /* optional */ 1886 if (IS_ERR(info->clk)) { 1887 ret = PTR_ERR(info->clk); 1888 if (ret == -ENOENT) 1889 info->clk = NULL; 1890 else 1891 return ret; 1892 } 1893 1894 ret = ov7670_init_gpio(client, info); 1895 if (ret) 1896 return ret; 1897 1898 ov7670_power_on(sd); 1899 1900 if (info->clk) { 1901 info->clock_speed = clk_get_rate(info->clk) / 1000000; 1902 if (info->clock_speed < 10 || info->clock_speed > 48) { 1903 ret = -EINVAL; 1904 goto power_off; 1905 } 1906 } 1907 1908 /* Make sure it's an ov7670 */ 1909 ret = ov7670_detect(sd); 1910 if (ret) { 1911 v4l_dbg(1, debug, client, 1912 "chip found @ 0x%x (%s) is not an ov7670 chip.\n", 1913 client->addr << 1, client->adapter->name); 1914 goto power_off; 1915 } 1916 v4l_info(client, "chip found @ 0x%02x (%s)\n", 1917 client->addr << 1, client->adapter->name); 1918 1919 info->devtype = &ov7670_devdata[id->driver_data]; 1920 info->fmt = &ov7670_formats[0]; 1921 info->wsize = &info->devtype->win_sizes[0]; 1922 1923 ov7670_get_default_format(sd, &info->format); 1924 1925 info->clkrc = 0; 1926 1927 /* Set default frame rate to 30 fps */ 1928 tpf.numerator = 1; 1929 tpf.denominator = 30; 1930 info->devtype->set_framerate(sd, &tpf); 1931 1932 v4l2_ctrl_handler_init(&info->hdl, 10); 1933 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1934 V4L2_CID_BRIGHTNESS, 0, 255, 1, 128); 1935 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1936 V4L2_CID_CONTRAST, 0, 127, 1, 64); 1937 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1938 V4L2_CID_VFLIP, 0, 1, 1, 0); 1939 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1940 V4L2_CID_HFLIP, 0, 1, 1, 0); 1941 info->saturation = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1942 V4L2_CID_SATURATION, 0, 256, 1, 128); 1943 info->hue = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1944 V4L2_CID_HUE, -180, 180, 5, 0); 1945 info->gain = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1946 V4L2_CID_GAIN, 0, 255, 1, 128); 1947 info->auto_gain = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1948 V4L2_CID_AUTOGAIN, 0, 1, 1, 1); 1949 info->exposure = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1950 V4L2_CID_EXPOSURE, 0, 65535, 1, 500); 1951 info->auto_exposure = v4l2_ctrl_new_std_menu(&info->hdl, &ov7670_ctrl_ops, 1952 V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL, 0, 1953 V4L2_EXPOSURE_AUTO); 1954 v4l2_ctrl_new_std_menu_items(&info->hdl, &ov7670_ctrl_ops, 1955 V4L2_CID_TEST_PATTERN, 1956 ARRAY_SIZE(ov7670_test_pattern_menu) - 1, 0, 0, 1957 ov7670_test_pattern_menu); 1958 sd->ctrl_handler = &info->hdl; 1959 if (info->hdl.error) { 1960 ret = info->hdl.error; 1961 1962 goto hdl_free; 1963 } 1964 /* 1965 * We have checked empirically that hw allows to read back the gain 1966 * value chosen by auto gain but that's not the case for auto exposure. 1967 */ 1968 v4l2_ctrl_auto_cluster(2, &info->auto_gain, 0, true); 1969 v4l2_ctrl_auto_cluster(2, &info->auto_exposure, 1970 V4L2_EXPOSURE_MANUAL, false); 1971 v4l2_ctrl_cluster(2, &info->saturation); 1972 1973 #if defined(CONFIG_MEDIA_CONTROLLER) 1974 info->pad.flags = MEDIA_PAD_FL_SOURCE; 1975 info->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1976 ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad); 1977 if (ret < 0) 1978 goto hdl_free; 1979 #endif 1980 1981 v4l2_ctrl_handler_setup(&info->hdl); 1982 1983 ret = v4l2_async_register_subdev(&info->sd); 1984 if (ret < 0) 1985 goto entity_cleanup; 1986 1987 ov7670_power_off(sd); 1988 return 0; 1989 1990 entity_cleanup: 1991 media_entity_cleanup(&info->sd.entity); 1992 hdl_free: 1993 v4l2_ctrl_handler_free(&info->hdl); 1994 power_off: 1995 ov7670_power_off(sd); 1996 return ret; 1997 } 1998 1999 static int ov7670_remove(struct i2c_client *client) 2000 { 2001 struct v4l2_subdev *sd = i2c_get_clientdata(client); 2002 struct ov7670_info *info = to_state(sd); 2003 2004 v4l2_async_unregister_subdev(sd); 2005 v4l2_ctrl_handler_free(&info->hdl); 2006 media_entity_cleanup(&info->sd.entity); 2007 ov7670_power_off(sd); 2008 return 0; 2009 } 2010 2011 static const struct i2c_device_id ov7670_id[] = { 2012 { "ov7670", MODEL_OV7670 }, 2013 { "ov7675", MODEL_OV7675 }, 2014 { } 2015 }; 2016 MODULE_DEVICE_TABLE(i2c, ov7670_id); 2017 2018 #if IS_ENABLED(CONFIG_OF) 2019 static const struct of_device_id ov7670_of_match[] = { 2020 { .compatible = "ovti,ov7670", }, 2021 { /* sentinel */ }, 2022 }; 2023 MODULE_DEVICE_TABLE(of, ov7670_of_match); 2024 #endif 2025 2026 static struct i2c_driver ov7670_driver = { 2027 .driver = { 2028 .name = "ov7670", 2029 .of_match_table = of_match_ptr(ov7670_of_match), 2030 }, 2031 .probe = ov7670_probe, 2032 .remove = ov7670_remove, 2033 .id_table = ov7670_id, 2034 }; 2035 2036 module_i2c_driver(ov7670_driver); 2037