1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * A V4L2 driver for OmniVision OV7670 cameras. 4 * 5 * Copyright 2006 One Laptop Per Child Association, Inc. Written 6 * by Jonathan Corbet with substantial inspiration from Mark 7 * McClelland's ovcamchip code. 8 * 9 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net> 10 */ 11 #include <linux/clk.h> 12 #include <linux/init.h> 13 #include <linux/module.h> 14 #include <linux/slab.h> 15 #include <linux/i2c.h> 16 #include <linux/delay.h> 17 #include <linux/videodev2.h> 18 #include <linux/gpio/consumer.h> 19 #include <media/v4l2-device.h> 20 #include <media/v4l2-event.h> 21 #include <media/v4l2-ctrls.h> 22 #include <media/v4l2-fwnode.h> 23 #include <media/v4l2-mediabus.h> 24 #include <media/v4l2-image-sizes.h> 25 #include <media/i2c/ov7670.h> 26 27 MODULE_AUTHOR("Jonathan Corbet <corbet@lwn.net>"); 28 MODULE_DESCRIPTION("A low-level driver for OmniVision ov7670 sensors"); 29 MODULE_LICENSE("GPL"); 30 31 static bool debug; 32 module_param(debug, bool, 0644); 33 MODULE_PARM_DESC(debug, "Debug level (0-1)"); 34 35 /* 36 * The 7670 sits on i2c with ID 0x42 37 */ 38 #define OV7670_I2C_ADDR 0x42 39 40 #define PLL_FACTOR 4 41 42 /* Registers */ 43 #define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */ 44 #define REG_BLUE 0x01 /* blue gain */ 45 #define REG_RED 0x02 /* red gain */ 46 #define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */ 47 #define REG_COM1 0x04 /* Control 1 */ 48 #define COM1_CCIR656 0x40 /* CCIR656 enable */ 49 #define REG_BAVE 0x05 /* U/B Average level */ 50 #define REG_GbAVE 0x06 /* Y/Gb Average level */ 51 #define REG_AECHH 0x07 /* AEC MS 5 bits */ 52 #define REG_RAVE 0x08 /* V/R Average level */ 53 #define REG_COM2 0x09 /* Control 2 */ 54 #define COM2_SSLEEP 0x10 /* Soft sleep mode */ 55 #define REG_PID 0x0a /* Product ID MSB */ 56 #define REG_VER 0x0b /* Product ID LSB */ 57 #define REG_COM3 0x0c /* Control 3 */ 58 #define COM3_SWAP 0x40 /* Byte swap */ 59 #define COM3_SCALEEN 0x08 /* Enable scaling */ 60 #define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */ 61 #define REG_COM4 0x0d /* Control 4 */ 62 #define REG_COM5 0x0e /* All "reserved" */ 63 #define REG_COM6 0x0f /* Control 6 */ 64 #define REG_AECH 0x10 /* More bits of AEC value */ 65 #define REG_CLKRC 0x11 /* Clocl control */ 66 #define CLK_EXT 0x40 /* Use external clock directly */ 67 #define CLK_SCALE 0x3f /* Mask for internal clock scale */ 68 #define REG_COM7 0x12 /* Control 7 */ 69 #define COM7_RESET 0x80 /* Register reset */ 70 #define COM7_FMT_MASK 0x38 71 #define COM7_FMT_VGA 0x00 72 #define COM7_FMT_CIF 0x20 /* CIF format */ 73 #define COM7_FMT_QVGA 0x10 /* QVGA format */ 74 #define COM7_FMT_QCIF 0x08 /* QCIF format */ 75 #define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */ 76 #define COM7_YUV 0x00 /* YUV */ 77 #define COM7_BAYER 0x01 /* Bayer format */ 78 #define COM7_PBAYER 0x05 /* "Processed bayer" */ 79 #define REG_COM8 0x13 /* Control 8 */ 80 #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */ 81 #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */ 82 #define COM8_BFILT 0x20 /* Band filter enable */ 83 #define COM8_AGC 0x04 /* Auto gain enable */ 84 #define COM8_AWB 0x02 /* White balance enable */ 85 #define COM8_AEC 0x01 /* Auto exposure enable */ 86 #define REG_COM9 0x14 /* Control 9 - gain ceiling */ 87 #define REG_COM10 0x15 /* Control 10 */ 88 #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */ 89 #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */ 90 #define COM10_HREF_REV 0x08 /* Reverse HREF */ 91 #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */ 92 #define COM10_VS_NEG 0x02 /* VSYNC negative */ 93 #define COM10_HS_NEG 0x01 /* HSYNC negative */ 94 #define REG_HSTART 0x17 /* Horiz start high bits */ 95 #define REG_HSTOP 0x18 /* Horiz stop high bits */ 96 #define REG_VSTART 0x19 /* Vert start high bits */ 97 #define REG_VSTOP 0x1a /* Vert stop high bits */ 98 #define REG_PSHFT 0x1b /* Pixel delay after HREF */ 99 #define REG_MIDH 0x1c /* Manuf. ID high */ 100 #define REG_MIDL 0x1d /* Manuf. ID low */ 101 #define REG_MVFP 0x1e /* Mirror / vflip */ 102 #define MVFP_MIRROR 0x20 /* Mirror image */ 103 #define MVFP_FLIP 0x10 /* Vertical flip */ 104 105 #define REG_AEW 0x24 /* AGC upper limit */ 106 #define REG_AEB 0x25 /* AGC lower limit */ 107 #define REG_VPT 0x26 /* AGC/AEC fast mode op region */ 108 #define REG_HSYST 0x30 /* HSYNC rising edge delay */ 109 #define REG_HSYEN 0x31 /* HSYNC falling edge delay */ 110 #define REG_HREF 0x32 /* HREF pieces */ 111 #define REG_TSLB 0x3a /* lots of stuff */ 112 #define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */ 113 #define REG_COM11 0x3b /* Control 11 */ 114 #define COM11_NIGHT 0x80 /* NIght mode enable */ 115 #define COM11_NMFR 0x60 /* Two bit NM frame rate */ 116 #define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */ 117 #define COM11_50HZ 0x08 /* Manual 50Hz select */ 118 #define COM11_EXP 0x02 119 #define REG_COM12 0x3c /* Control 12 */ 120 #define COM12_HREF 0x80 /* HREF always */ 121 #define REG_COM13 0x3d /* Control 13 */ 122 #define COM13_GAMMA 0x80 /* Gamma enable */ 123 #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */ 124 #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */ 125 #define REG_COM14 0x3e /* Control 14 */ 126 #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */ 127 #define REG_EDGE 0x3f /* Edge enhancement factor */ 128 #define REG_COM15 0x40 /* Control 15 */ 129 #define COM15_R10F0 0x00 /* Data range 10 to F0 */ 130 #define COM15_R01FE 0x80 /* 01 to FE */ 131 #define COM15_R00FF 0xc0 /* 00 to FF */ 132 #define COM15_RGB565 0x10 /* RGB565 output */ 133 #define COM15_RGB555 0x30 /* RGB555 output */ 134 #define REG_COM16 0x41 /* Control 16 */ 135 #define COM16_AWBGAIN 0x08 /* AWB gain enable */ 136 #define REG_COM17 0x42 /* Control 17 */ 137 #define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */ 138 #define COM17_CBAR 0x08 /* DSP Color bar */ 139 140 /* 141 * This matrix defines how the colors are generated, must be 142 * tweaked to adjust hue and saturation. 143 * 144 * Order: v-red, v-green, v-blue, u-red, u-green, u-blue 145 * 146 * They are nine-bit signed quantities, with the sign bit 147 * stored in 0x58. Sign for v-red is bit 0, and up from there. 148 */ 149 #define REG_CMATRIX_BASE 0x4f 150 #define CMATRIX_LEN 6 151 #define REG_CMATRIX_SIGN 0x58 152 153 154 #define REG_BRIGHT 0x55 /* Brightness */ 155 #define REG_CONTRAS 0x56 /* Contrast control */ 156 157 #define REG_GFIX 0x69 /* Fix gain control */ 158 159 #define REG_DBLV 0x6b /* PLL control an debugging */ 160 #define DBLV_BYPASS 0x0a /* Bypass PLL */ 161 #define DBLV_X4 0x4a /* clock x4 */ 162 #define DBLV_X6 0x8a /* clock x6 */ 163 #define DBLV_X8 0xca /* clock x8 */ 164 165 #define REG_SCALING_XSC 0x70 /* Test pattern and horizontal scale factor */ 166 #define TEST_PATTTERN_0 0x80 167 #define REG_SCALING_YSC 0x71 /* Test pattern and vertical scale factor */ 168 #define TEST_PATTTERN_1 0x80 169 170 #define REG_REG76 0x76 /* OV's name */ 171 #define R76_BLKPCOR 0x80 /* Black pixel correction enable */ 172 #define R76_WHTPCOR 0x40 /* White pixel correction enable */ 173 174 #define REG_RGB444 0x8c /* RGB 444 control */ 175 #define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */ 176 #define R444_RGBX 0x01 /* Empty nibble at end */ 177 178 #define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */ 179 #define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */ 180 181 #define REG_BD50MAX 0xa5 /* 50hz banding step limit */ 182 #define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */ 183 #define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */ 184 #define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */ 185 #define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */ 186 #define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */ 187 #define REG_BD60MAX 0xab /* 60hz banding step limit */ 188 189 enum ov7670_model { 190 MODEL_OV7670 = 0, 191 MODEL_OV7675, 192 }; 193 194 struct ov7670_win_size { 195 int width; 196 int height; 197 unsigned char com7_bit; 198 int hstart; /* Start/stop values for the camera. Note */ 199 int hstop; /* that they do not always make complete */ 200 int vstart; /* sense to humans, but evidently the sensor */ 201 int vstop; /* will do the right thing... */ 202 struct regval_list *regs; /* Regs to tweak */ 203 }; 204 205 struct ov7670_devtype { 206 /* formats supported for each model */ 207 struct ov7670_win_size *win_sizes; 208 unsigned int n_win_sizes; 209 /* callbacks for frame rate control */ 210 int (*set_framerate)(struct v4l2_subdev *, struct v4l2_fract *); 211 void (*get_framerate)(struct v4l2_subdev *, struct v4l2_fract *); 212 }; 213 214 /* 215 * Information we maintain about a known sensor. 216 */ 217 struct ov7670_format_struct; /* coming later */ 218 struct ov7670_info { 219 struct v4l2_subdev sd; 220 #if defined(CONFIG_MEDIA_CONTROLLER) 221 struct media_pad pad; 222 #endif 223 struct v4l2_ctrl_handler hdl; 224 struct { 225 /* gain cluster */ 226 struct v4l2_ctrl *auto_gain; 227 struct v4l2_ctrl *gain; 228 }; 229 struct { 230 /* exposure cluster */ 231 struct v4l2_ctrl *auto_exposure; 232 struct v4l2_ctrl *exposure; 233 }; 234 struct { 235 /* saturation/hue cluster */ 236 struct v4l2_ctrl *saturation; 237 struct v4l2_ctrl *hue; 238 }; 239 struct v4l2_mbus_framefmt format; 240 struct ov7670_format_struct *fmt; /* Current format */ 241 struct ov7670_win_size *wsize; 242 struct clk *clk; 243 int on; 244 struct gpio_desc *resetb_gpio; 245 struct gpio_desc *pwdn_gpio; 246 unsigned int mbus_config; /* Media bus configuration flags */ 247 int min_width; /* Filter out smaller sizes */ 248 int min_height; /* Filter out smaller sizes */ 249 int clock_speed; /* External clock speed (MHz) */ 250 u8 clkrc; /* Clock divider value */ 251 bool use_smbus; /* Use smbus I/O instead of I2C */ 252 bool pll_bypass; 253 bool pclk_hb_disable; 254 const struct ov7670_devtype *devtype; /* Device specifics */ 255 }; 256 257 static inline struct ov7670_info *to_state(struct v4l2_subdev *sd) 258 { 259 return container_of(sd, struct ov7670_info, sd); 260 } 261 262 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) 263 { 264 return &container_of(ctrl->handler, struct ov7670_info, hdl)->sd; 265 } 266 267 268 269 /* 270 * The default register settings, as obtained from OmniVision. There 271 * is really no making sense of most of these - lots of "reserved" values 272 * and such. 273 * 274 * These settings give VGA YUYV. 275 */ 276 277 struct regval_list { 278 unsigned char reg_num; 279 unsigned char value; 280 }; 281 282 static struct regval_list ov7670_default_regs[] = { 283 { REG_COM7, COM7_RESET }, 284 /* 285 * Clock scale: 3 = 15fps 286 * 2 = 20fps 287 * 1 = 30fps 288 */ 289 { REG_CLKRC, 0x1 }, /* OV: clock scale (30 fps) */ 290 { REG_TSLB, 0x04 }, /* OV */ 291 { REG_COM7, 0 }, /* VGA */ 292 /* 293 * Set the hardware window. These values from OV don't entirely 294 * make sense - hstop is less than hstart. But they work... 295 */ 296 { REG_HSTART, 0x13 }, { REG_HSTOP, 0x01 }, 297 { REG_HREF, 0xb6 }, { REG_VSTART, 0x02 }, 298 { REG_VSTOP, 0x7a }, { REG_VREF, 0x0a }, 299 300 { REG_COM3, 0 }, { REG_COM14, 0 }, 301 /* Mystery scaling numbers */ 302 { REG_SCALING_XSC, 0x3a }, 303 { REG_SCALING_YSC, 0x35 }, 304 { 0x72, 0x11 }, { 0x73, 0xf0 }, 305 { 0xa2, 0x02 }, { REG_COM10, 0x0 }, 306 307 /* Gamma curve values */ 308 { 0x7a, 0x20 }, { 0x7b, 0x10 }, 309 { 0x7c, 0x1e }, { 0x7d, 0x35 }, 310 { 0x7e, 0x5a }, { 0x7f, 0x69 }, 311 { 0x80, 0x76 }, { 0x81, 0x80 }, 312 { 0x82, 0x88 }, { 0x83, 0x8f }, 313 { 0x84, 0x96 }, { 0x85, 0xa3 }, 314 { 0x86, 0xaf }, { 0x87, 0xc4 }, 315 { 0x88, 0xd7 }, { 0x89, 0xe8 }, 316 317 /* AGC and AEC parameters. Note we start by disabling those features, 318 then turn them only after tweaking the values. */ 319 { REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_BFILT }, 320 { REG_GAIN, 0 }, { REG_AECH, 0 }, 321 { REG_COM4, 0x40 }, /* magic reserved bit */ 322 { REG_COM9, 0x18 }, /* 4x gain + magic rsvd bit */ 323 { REG_BD50MAX, 0x05 }, { REG_BD60MAX, 0x07 }, 324 { REG_AEW, 0x95 }, { REG_AEB, 0x33 }, 325 { REG_VPT, 0xe3 }, { REG_HAECC1, 0x78 }, 326 { REG_HAECC2, 0x68 }, { 0xa1, 0x03 }, /* magic */ 327 { REG_HAECC3, 0xd8 }, { REG_HAECC4, 0xd8 }, 328 { REG_HAECC5, 0xf0 }, { REG_HAECC6, 0x90 }, 329 { REG_HAECC7, 0x94 }, 330 { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC }, 331 332 /* Almost all of these are magic "reserved" values. */ 333 { REG_COM5, 0x61 }, { REG_COM6, 0x4b }, 334 { 0x16, 0x02 }, { REG_MVFP, 0x07 }, 335 { 0x21, 0x02 }, { 0x22, 0x91 }, 336 { 0x29, 0x07 }, { 0x33, 0x0b }, 337 { 0x35, 0x0b }, { 0x37, 0x1d }, 338 { 0x38, 0x71 }, { 0x39, 0x2a }, 339 { REG_COM12, 0x78 }, { 0x4d, 0x40 }, 340 { 0x4e, 0x20 }, { REG_GFIX, 0 }, 341 { 0x6b, 0x4a }, { 0x74, 0x10 }, 342 { 0x8d, 0x4f }, { 0x8e, 0 }, 343 { 0x8f, 0 }, { 0x90, 0 }, 344 { 0x91, 0 }, { 0x96, 0 }, 345 { 0x9a, 0 }, { 0xb0, 0x84 }, 346 { 0xb1, 0x0c }, { 0xb2, 0x0e }, 347 { 0xb3, 0x82 }, { 0xb8, 0x0a }, 348 349 /* More reserved magic, some of which tweaks white balance */ 350 { 0x43, 0x0a }, { 0x44, 0xf0 }, 351 { 0x45, 0x34 }, { 0x46, 0x58 }, 352 { 0x47, 0x28 }, { 0x48, 0x3a }, 353 { 0x59, 0x88 }, { 0x5a, 0x88 }, 354 { 0x5b, 0x44 }, { 0x5c, 0x67 }, 355 { 0x5d, 0x49 }, { 0x5e, 0x0e }, 356 { 0x6c, 0x0a }, { 0x6d, 0x55 }, 357 { 0x6e, 0x11 }, { 0x6f, 0x9f }, /* "9e for advance AWB" */ 358 { 0x6a, 0x40 }, { REG_BLUE, 0x40 }, 359 { REG_RED, 0x60 }, 360 { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC|COM8_AWB }, 361 362 /* Matrix coefficients */ 363 { 0x4f, 0x80 }, { 0x50, 0x80 }, 364 { 0x51, 0 }, { 0x52, 0x22 }, 365 { 0x53, 0x5e }, { 0x54, 0x80 }, 366 { 0x58, 0x9e }, 367 368 { REG_COM16, COM16_AWBGAIN }, { REG_EDGE, 0 }, 369 { 0x75, 0x05 }, { 0x76, 0xe1 }, 370 { 0x4c, 0 }, { 0x77, 0x01 }, 371 { REG_COM13, 0xc3 }, { 0x4b, 0x09 }, 372 { 0xc9, 0x60 }, { REG_COM16, 0x38 }, 373 { 0x56, 0x40 }, 374 375 { 0x34, 0x11 }, { REG_COM11, COM11_EXP|COM11_HZAUTO }, 376 { 0xa4, 0x88 }, { 0x96, 0 }, 377 { 0x97, 0x30 }, { 0x98, 0x20 }, 378 { 0x99, 0x30 }, { 0x9a, 0x84 }, 379 { 0x9b, 0x29 }, { 0x9c, 0x03 }, 380 { 0x9d, 0x4c }, { 0x9e, 0x3f }, 381 { 0x78, 0x04 }, 382 383 /* Extra-weird stuff. Some sort of multiplexor register */ 384 { 0x79, 0x01 }, { 0xc8, 0xf0 }, 385 { 0x79, 0x0f }, { 0xc8, 0x00 }, 386 { 0x79, 0x10 }, { 0xc8, 0x7e }, 387 { 0x79, 0x0a }, { 0xc8, 0x80 }, 388 { 0x79, 0x0b }, { 0xc8, 0x01 }, 389 { 0x79, 0x0c }, { 0xc8, 0x0f }, 390 { 0x79, 0x0d }, { 0xc8, 0x20 }, 391 { 0x79, 0x09 }, { 0xc8, 0x80 }, 392 { 0x79, 0x02 }, { 0xc8, 0xc0 }, 393 { 0x79, 0x03 }, { 0xc8, 0x40 }, 394 { 0x79, 0x05 }, { 0xc8, 0x30 }, 395 { 0x79, 0x26 }, 396 397 { 0xff, 0xff }, /* END MARKER */ 398 }; 399 400 401 /* 402 * Here we'll try to encapsulate the changes for just the output 403 * video format. 404 * 405 * RGB656 and YUV422 come from OV; RGB444 is homebrewed. 406 * 407 * IMPORTANT RULE: the first entry must be for COM7, see ov7670_s_fmt for why. 408 */ 409 410 411 static struct regval_list ov7670_fmt_yuv422[] = { 412 { REG_COM7, 0x0 }, /* Selects YUV mode */ 413 { REG_RGB444, 0 }, /* No RGB444 please */ 414 { REG_COM1, 0 }, /* CCIR601 */ 415 { REG_COM15, COM15_R00FF }, 416 { REG_COM9, 0x48 }, /* 32x gain ceiling; 0x8 is reserved bit */ 417 { 0x4f, 0x80 }, /* "matrix coefficient 1" */ 418 { 0x50, 0x80 }, /* "matrix coefficient 2" */ 419 { 0x51, 0 }, /* vb */ 420 { 0x52, 0x22 }, /* "matrix coefficient 4" */ 421 { 0x53, 0x5e }, /* "matrix coefficient 5" */ 422 { 0x54, 0x80 }, /* "matrix coefficient 6" */ 423 { REG_COM13, COM13_GAMMA|COM13_UVSAT }, 424 { 0xff, 0xff }, 425 }; 426 427 static struct regval_list ov7670_fmt_rgb565[] = { 428 { REG_COM7, COM7_RGB }, /* Selects RGB mode */ 429 { REG_RGB444, 0 }, /* No RGB444 please */ 430 { REG_COM1, 0x0 }, /* CCIR601 */ 431 { REG_COM15, COM15_RGB565 }, 432 { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */ 433 { 0x4f, 0xb3 }, /* "matrix coefficient 1" */ 434 { 0x50, 0xb3 }, /* "matrix coefficient 2" */ 435 { 0x51, 0 }, /* vb */ 436 { 0x52, 0x3d }, /* "matrix coefficient 4" */ 437 { 0x53, 0xa7 }, /* "matrix coefficient 5" */ 438 { 0x54, 0xe4 }, /* "matrix coefficient 6" */ 439 { REG_COM13, COM13_GAMMA|COM13_UVSAT }, 440 { 0xff, 0xff }, 441 }; 442 443 static struct regval_list ov7670_fmt_rgb444[] = { 444 { REG_COM7, COM7_RGB }, /* Selects RGB mode */ 445 { REG_RGB444, R444_ENABLE }, /* Enable xxxxrrrr ggggbbbb */ 446 { REG_COM1, 0x0 }, /* CCIR601 */ 447 { REG_COM15, COM15_R01FE|COM15_RGB565 }, /* Data range needed? */ 448 { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */ 449 { 0x4f, 0xb3 }, /* "matrix coefficient 1" */ 450 { 0x50, 0xb3 }, /* "matrix coefficient 2" */ 451 { 0x51, 0 }, /* vb */ 452 { 0x52, 0x3d }, /* "matrix coefficient 4" */ 453 { 0x53, 0xa7 }, /* "matrix coefficient 5" */ 454 { 0x54, 0xe4 }, /* "matrix coefficient 6" */ 455 { REG_COM13, COM13_GAMMA|COM13_UVSAT|0x2 }, /* Magic rsvd bit */ 456 { 0xff, 0xff }, 457 }; 458 459 static struct regval_list ov7670_fmt_raw[] = { 460 { REG_COM7, COM7_BAYER }, 461 { REG_COM13, 0x08 }, /* No gamma, magic rsvd bit */ 462 { REG_COM16, 0x3d }, /* Edge enhancement, denoise */ 463 { REG_REG76, 0xe1 }, /* Pix correction, magic rsvd */ 464 { 0xff, 0xff }, 465 }; 466 467 468 469 /* 470 * Low-level register I/O. 471 * 472 * Note that there are two versions of these. On the XO 1, the 473 * i2c controller only does SMBUS, so that's what we use. The 474 * ov7670 is not really an SMBUS device, though, so the communication 475 * is not always entirely reliable. 476 */ 477 static int ov7670_read_smbus(struct v4l2_subdev *sd, unsigned char reg, 478 unsigned char *value) 479 { 480 struct i2c_client *client = v4l2_get_subdevdata(sd); 481 int ret; 482 483 ret = i2c_smbus_read_byte_data(client, reg); 484 if (ret >= 0) { 485 *value = (unsigned char)ret; 486 ret = 0; 487 } 488 return ret; 489 } 490 491 492 static int ov7670_write_smbus(struct v4l2_subdev *sd, unsigned char reg, 493 unsigned char value) 494 { 495 struct i2c_client *client = v4l2_get_subdevdata(sd); 496 int ret = i2c_smbus_write_byte_data(client, reg, value); 497 498 if (reg == REG_COM7 && (value & COM7_RESET)) 499 msleep(5); /* Wait for reset to run */ 500 return ret; 501 } 502 503 /* 504 * On most platforms, we'd rather do straight i2c I/O. 505 */ 506 static int ov7670_read_i2c(struct v4l2_subdev *sd, unsigned char reg, 507 unsigned char *value) 508 { 509 struct i2c_client *client = v4l2_get_subdevdata(sd); 510 u8 data = reg; 511 struct i2c_msg msg; 512 int ret; 513 514 /* 515 * Send out the register address... 516 */ 517 msg.addr = client->addr; 518 msg.flags = 0; 519 msg.len = 1; 520 msg.buf = &data; 521 ret = i2c_transfer(client->adapter, &msg, 1); 522 if (ret < 0) { 523 printk(KERN_ERR "Error %d on register write\n", ret); 524 return ret; 525 } 526 /* 527 * ...then read back the result. 528 */ 529 msg.flags = I2C_M_RD; 530 ret = i2c_transfer(client->adapter, &msg, 1); 531 if (ret >= 0) { 532 *value = data; 533 ret = 0; 534 } 535 return ret; 536 } 537 538 539 static int ov7670_write_i2c(struct v4l2_subdev *sd, unsigned char reg, 540 unsigned char value) 541 { 542 struct i2c_client *client = v4l2_get_subdevdata(sd); 543 struct i2c_msg msg; 544 unsigned char data[2] = { reg, value }; 545 int ret; 546 547 msg.addr = client->addr; 548 msg.flags = 0; 549 msg.len = 2; 550 msg.buf = data; 551 ret = i2c_transfer(client->adapter, &msg, 1); 552 if (ret > 0) 553 ret = 0; 554 if (reg == REG_COM7 && (value & COM7_RESET)) 555 msleep(5); /* Wait for reset to run */ 556 return ret; 557 } 558 559 static int ov7670_read(struct v4l2_subdev *sd, unsigned char reg, 560 unsigned char *value) 561 { 562 struct ov7670_info *info = to_state(sd); 563 564 if (info->use_smbus) 565 return ov7670_read_smbus(sd, reg, value); 566 else 567 return ov7670_read_i2c(sd, reg, value); 568 } 569 570 static int ov7670_write(struct v4l2_subdev *sd, unsigned char reg, 571 unsigned char value) 572 { 573 struct ov7670_info *info = to_state(sd); 574 575 if (info->use_smbus) 576 return ov7670_write_smbus(sd, reg, value); 577 else 578 return ov7670_write_i2c(sd, reg, value); 579 } 580 581 static int ov7670_update_bits(struct v4l2_subdev *sd, unsigned char reg, 582 unsigned char mask, unsigned char value) 583 { 584 unsigned char orig; 585 int ret; 586 587 ret = ov7670_read(sd, reg, &orig); 588 if (ret) 589 return ret; 590 591 return ov7670_write(sd, reg, (orig & ~mask) | (value & mask)); 592 } 593 594 /* 595 * Write a list of register settings; ff/ff stops the process. 596 */ 597 static int ov7670_write_array(struct v4l2_subdev *sd, struct regval_list *vals) 598 { 599 while (vals->reg_num != 0xff || vals->value != 0xff) { 600 int ret = ov7670_write(sd, vals->reg_num, vals->value); 601 602 if (ret < 0) 603 return ret; 604 vals++; 605 } 606 return 0; 607 } 608 609 610 /* 611 * Stuff that knows about the sensor. 612 */ 613 static int ov7670_reset(struct v4l2_subdev *sd, u32 val) 614 { 615 ov7670_write(sd, REG_COM7, COM7_RESET); 616 msleep(1); 617 return 0; 618 } 619 620 621 static int ov7670_init(struct v4l2_subdev *sd, u32 val) 622 { 623 return ov7670_write_array(sd, ov7670_default_regs); 624 } 625 626 static int ov7670_detect(struct v4l2_subdev *sd) 627 { 628 unsigned char v; 629 int ret; 630 631 ret = ov7670_init(sd, 0); 632 if (ret < 0) 633 return ret; 634 ret = ov7670_read(sd, REG_MIDH, &v); 635 if (ret < 0) 636 return ret; 637 if (v != 0x7f) /* OV manuf. id. */ 638 return -ENODEV; 639 ret = ov7670_read(sd, REG_MIDL, &v); 640 if (ret < 0) 641 return ret; 642 if (v != 0xa2) 643 return -ENODEV; 644 /* 645 * OK, we know we have an OmniVision chip...but which one? 646 */ 647 ret = ov7670_read(sd, REG_PID, &v); 648 if (ret < 0) 649 return ret; 650 if (v != 0x76) /* PID + VER = 0x76 / 0x73 */ 651 return -ENODEV; 652 ret = ov7670_read(sd, REG_VER, &v); 653 if (ret < 0) 654 return ret; 655 if (v != 0x73) /* PID + VER = 0x76 / 0x73 */ 656 return -ENODEV; 657 return 0; 658 } 659 660 661 /* 662 * Store information about the video data format. The color matrix 663 * is deeply tied into the format, so keep the relevant values here. 664 * The magic matrix numbers come from OmniVision. 665 */ 666 static struct ov7670_format_struct { 667 u32 mbus_code; 668 enum v4l2_colorspace colorspace; 669 struct regval_list *regs; 670 int cmatrix[CMATRIX_LEN]; 671 } ov7670_formats[] = { 672 { 673 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, 674 .colorspace = V4L2_COLORSPACE_SRGB, 675 .regs = ov7670_fmt_yuv422, 676 .cmatrix = { 128, -128, 0, -34, -94, 128 }, 677 }, 678 { 679 .mbus_code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE, 680 .colorspace = V4L2_COLORSPACE_SRGB, 681 .regs = ov7670_fmt_rgb444, 682 .cmatrix = { 179, -179, 0, -61, -176, 228 }, 683 }, 684 { 685 .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE, 686 .colorspace = V4L2_COLORSPACE_SRGB, 687 .regs = ov7670_fmt_rgb565, 688 .cmatrix = { 179, -179, 0, -61, -176, 228 }, 689 }, 690 { 691 .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8, 692 .colorspace = V4L2_COLORSPACE_SRGB, 693 .regs = ov7670_fmt_raw, 694 .cmatrix = { 0, 0, 0, 0, 0, 0 }, 695 }, 696 }; 697 #define N_OV7670_FMTS ARRAY_SIZE(ov7670_formats) 698 699 700 /* 701 * Then there is the issue of window sizes. Try to capture the info here. 702 */ 703 704 /* 705 * QCIF mode is done (by OV) in a very strange way - it actually looks like 706 * VGA with weird scaling options - they do *not* use the canned QCIF mode 707 * which is allegedly provided by the sensor. So here's the weird register 708 * settings. 709 */ 710 static struct regval_list ov7670_qcif_regs[] = { 711 { REG_COM3, COM3_SCALEEN|COM3_DCWEN }, 712 { REG_COM3, COM3_DCWEN }, 713 { REG_COM14, COM14_DCWEN | 0x01}, 714 { 0x73, 0xf1 }, 715 { 0xa2, 0x52 }, 716 { 0x7b, 0x1c }, 717 { 0x7c, 0x28 }, 718 { 0x7d, 0x3c }, 719 { 0x7f, 0x69 }, 720 { REG_COM9, 0x38 }, 721 { 0xa1, 0x0b }, 722 { 0x74, 0x19 }, 723 { 0x9a, 0x80 }, 724 { 0x43, 0x14 }, 725 { REG_COM13, 0xc0 }, 726 { 0xff, 0xff }, 727 }; 728 729 static struct ov7670_win_size ov7670_win_sizes[] = { 730 /* VGA */ 731 { 732 .width = VGA_WIDTH, 733 .height = VGA_HEIGHT, 734 .com7_bit = COM7_FMT_VGA, 735 .hstart = 158, /* These values from */ 736 .hstop = 14, /* Omnivision */ 737 .vstart = 10, 738 .vstop = 490, 739 .regs = NULL, 740 }, 741 /* CIF */ 742 { 743 .width = CIF_WIDTH, 744 .height = CIF_HEIGHT, 745 .com7_bit = COM7_FMT_CIF, 746 .hstart = 170, /* Empirically determined */ 747 .hstop = 90, 748 .vstart = 14, 749 .vstop = 494, 750 .regs = NULL, 751 }, 752 /* QVGA */ 753 { 754 .width = QVGA_WIDTH, 755 .height = QVGA_HEIGHT, 756 .com7_bit = COM7_FMT_QVGA, 757 .hstart = 168, /* Empirically determined */ 758 .hstop = 24, 759 .vstart = 12, 760 .vstop = 492, 761 .regs = NULL, 762 }, 763 /* QCIF */ 764 { 765 .width = QCIF_WIDTH, 766 .height = QCIF_HEIGHT, 767 .com7_bit = COM7_FMT_VGA, /* see comment above */ 768 .hstart = 456, /* Empirically determined */ 769 .hstop = 24, 770 .vstart = 14, 771 .vstop = 494, 772 .regs = ov7670_qcif_regs, 773 } 774 }; 775 776 static struct ov7670_win_size ov7675_win_sizes[] = { 777 /* 778 * Currently, only VGA is supported. Theoretically it could be possible 779 * to support CIF, QVGA and QCIF too. Taking values for ov7670 as a 780 * base and tweak them empirically could be required. 781 */ 782 { 783 .width = VGA_WIDTH, 784 .height = VGA_HEIGHT, 785 .com7_bit = COM7_FMT_VGA, 786 .hstart = 158, /* These values from */ 787 .hstop = 14, /* Omnivision */ 788 .vstart = 14, /* Empirically determined */ 789 .vstop = 494, 790 .regs = NULL, 791 } 792 }; 793 794 static void ov7675_get_framerate(struct v4l2_subdev *sd, 795 struct v4l2_fract *tpf) 796 { 797 struct ov7670_info *info = to_state(sd); 798 u32 clkrc = info->clkrc; 799 int pll_factor; 800 801 if (info->pll_bypass) 802 pll_factor = 1; 803 else 804 pll_factor = PLL_FACTOR; 805 806 clkrc++; 807 if (info->fmt->mbus_code == MEDIA_BUS_FMT_SBGGR8_1X8) 808 clkrc = (clkrc >> 1); 809 810 tpf->numerator = 1; 811 tpf->denominator = (5 * pll_factor * info->clock_speed) / 812 (4 * clkrc); 813 } 814 815 static int ov7675_apply_framerate(struct v4l2_subdev *sd) 816 { 817 struct ov7670_info *info = to_state(sd); 818 int ret; 819 820 ret = ov7670_write(sd, REG_CLKRC, info->clkrc); 821 if (ret < 0) 822 return ret; 823 824 return ov7670_write(sd, REG_DBLV, 825 info->pll_bypass ? DBLV_BYPASS : DBLV_X4); 826 } 827 828 static int ov7675_set_framerate(struct v4l2_subdev *sd, 829 struct v4l2_fract *tpf) 830 { 831 struct ov7670_info *info = to_state(sd); 832 u32 clkrc; 833 int pll_factor; 834 835 /* 836 * The formula is fps = 5/4*pixclk for YUV/RGB and 837 * fps = 5/2*pixclk for RAW. 838 * 839 * pixclk = clock_speed / (clkrc + 1) * PLLfactor 840 * 841 */ 842 if (tpf->numerator == 0 || tpf->denominator == 0) { 843 clkrc = 0; 844 } else { 845 pll_factor = info->pll_bypass ? 1 : PLL_FACTOR; 846 clkrc = (5 * pll_factor * info->clock_speed * tpf->numerator) / 847 (4 * tpf->denominator); 848 if (info->fmt->mbus_code == MEDIA_BUS_FMT_SBGGR8_1X8) 849 clkrc = (clkrc << 1); 850 clkrc--; 851 } 852 853 /* 854 * The datasheet claims that clkrc = 0 will divide the input clock by 1 855 * but we've checked with an oscilloscope that it divides by 2 instead. 856 * So, if clkrc = 0 just bypass the divider. 857 */ 858 if (clkrc <= 0) 859 clkrc = CLK_EXT; 860 else if (clkrc > CLK_SCALE) 861 clkrc = CLK_SCALE; 862 info->clkrc = clkrc; 863 864 /* Recalculate frame rate */ 865 ov7675_get_framerate(sd, tpf); 866 867 /* 868 * If the device is not powered up by the host driver do 869 * not apply any changes to H/W at this time. Instead 870 * the framerate will be restored right after power-up. 871 */ 872 if (info->on) 873 return ov7675_apply_framerate(sd); 874 875 return 0; 876 } 877 878 static void ov7670_get_framerate_legacy(struct v4l2_subdev *sd, 879 struct v4l2_fract *tpf) 880 { 881 struct ov7670_info *info = to_state(sd); 882 883 tpf->numerator = 1; 884 tpf->denominator = info->clock_speed; 885 if ((info->clkrc & CLK_EXT) == 0 && (info->clkrc & CLK_SCALE) > 1) 886 tpf->denominator /= (info->clkrc & CLK_SCALE); 887 } 888 889 static int ov7670_set_framerate_legacy(struct v4l2_subdev *sd, 890 struct v4l2_fract *tpf) 891 { 892 struct ov7670_info *info = to_state(sd); 893 int div; 894 895 if (tpf->numerator == 0 || tpf->denominator == 0) 896 div = 1; /* Reset to full rate */ 897 else 898 div = (tpf->numerator * info->clock_speed) / tpf->denominator; 899 if (div == 0) 900 div = 1; 901 else if (div > CLK_SCALE) 902 div = CLK_SCALE; 903 info->clkrc = (info->clkrc & 0x80) | div; 904 tpf->numerator = 1; 905 tpf->denominator = info->clock_speed / div; 906 907 /* 908 * If the device is not powered up by the host driver do 909 * not apply any changes to H/W at this time. Instead 910 * the framerate will be restored right after power-up. 911 */ 912 if (info->on) 913 return ov7670_write(sd, REG_CLKRC, info->clkrc); 914 915 return 0; 916 } 917 918 /* 919 * Store a set of start/stop values into the camera. 920 */ 921 static int ov7670_set_hw(struct v4l2_subdev *sd, int hstart, int hstop, 922 int vstart, int vstop) 923 { 924 int ret; 925 unsigned char v; 926 /* 927 * Horizontal: 11 bits, top 8 live in hstart and hstop. Bottom 3 of 928 * hstart are in href[2:0], bottom 3 of hstop in href[5:3]. There is 929 * a mystery "edge offset" value in the top two bits of href. 930 */ 931 ret = ov7670_write(sd, REG_HSTART, (hstart >> 3) & 0xff); 932 if (ret) 933 return ret; 934 ret = ov7670_write(sd, REG_HSTOP, (hstop >> 3) & 0xff); 935 if (ret) 936 return ret; 937 ret = ov7670_read(sd, REG_HREF, &v); 938 if (ret) 939 return ret; 940 v = (v & 0xc0) | ((hstop & 0x7) << 3) | (hstart & 0x7); 941 msleep(10); 942 ret = ov7670_write(sd, REG_HREF, v); 943 if (ret) 944 return ret; 945 /* Vertical: similar arrangement, but only 10 bits. */ 946 ret = ov7670_write(sd, REG_VSTART, (vstart >> 2) & 0xff); 947 if (ret) 948 return ret; 949 ret = ov7670_write(sd, REG_VSTOP, (vstop >> 2) & 0xff); 950 if (ret) 951 return ret; 952 ret = ov7670_read(sd, REG_VREF, &v); 953 if (ret) 954 return ret; 955 v = (v & 0xf0) | ((vstop & 0x3) << 2) | (vstart & 0x3); 956 msleep(10); 957 return ov7670_write(sd, REG_VREF, v); 958 } 959 960 961 static int ov7670_enum_mbus_code(struct v4l2_subdev *sd, 962 struct v4l2_subdev_state *sd_state, 963 struct v4l2_subdev_mbus_code_enum *code) 964 { 965 if (code->pad || code->index >= N_OV7670_FMTS) 966 return -EINVAL; 967 968 code->code = ov7670_formats[code->index].mbus_code; 969 return 0; 970 } 971 972 static int ov7670_try_fmt_internal(struct v4l2_subdev *sd, 973 struct v4l2_mbus_framefmt *fmt, 974 struct ov7670_format_struct **ret_fmt, 975 struct ov7670_win_size **ret_wsize) 976 { 977 int index, i; 978 struct ov7670_win_size *wsize; 979 struct ov7670_info *info = to_state(sd); 980 unsigned int n_win_sizes = info->devtype->n_win_sizes; 981 unsigned int win_sizes_limit = n_win_sizes; 982 983 for (index = 0; index < N_OV7670_FMTS; index++) 984 if (ov7670_formats[index].mbus_code == fmt->code) 985 break; 986 if (index >= N_OV7670_FMTS) { 987 /* default to first format */ 988 index = 0; 989 fmt->code = ov7670_formats[0].mbus_code; 990 } 991 if (ret_fmt != NULL) 992 *ret_fmt = ov7670_formats + index; 993 /* 994 * Fields: the OV devices claim to be progressive. 995 */ 996 fmt->field = V4L2_FIELD_NONE; 997 998 /* 999 * Don't consider values that don't match min_height and min_width 1000 * constraints. 1001 */ 1002 if (info->min_width || info->min_height) 1003 for (i = 0; i < n_win_sizes; i++) { 1004 wsize = info->devtype->win_sizes + i; 1005 1006 if (wsize->width < info->min_width || 1007 wsize->height < info->min_height) { 1008 win_sizes_limit = i; 1009 break; 1010 } 1011 } 1012 /* 1013 * Round requested image size down to the nearest 1014 * we support, but not below the smallest. 1015 */ 1016 for (wsize = info->devtype->win_sizes; 1017 wsize < info->devtype->win_sizes + win_sizes_limit; wsize++) 1018 if (fmt->width >= wsize->width && fmt->height >= wsize->height) 1019 break; 1020 if (wsize >= info->devtype->win_sizes + win_sizes_limit) 1021 wsize--; /* Take the smallest one */ 1022 if (ret_wsize != NULL) 1023 *ret_wsize = wsize; 1024 /* 1025 * Note the size we'll actually handle. 1026 */ 1027 fmt->width = wsize->width; 1028 fmt->height = wsize->height; 1029 fmt->colorspace = ov7670_formats[index].colorspace; 1030 1031 info->format = *fmt; 1032 1033 return 0; 1034 } 1035 1036 static int ov7670_apply_fmt(struct v4l2_subdev *sd) 1037 { 1038 struct ov7670_info *info = to_state(sd); 1039 struct ov7670_win_size *wsize = info->wsize; 1040 unsigned char com7, com10 = 0; 1041 int ret; 1042 1043 /* 1044 * COM7 is a pain in the ass, it doesn't like to be read then 1045 * quickly written afterward. But we have everything we need 1046 * to set it absolutely here, as long as the format-specific 1047 * register sets list it first. 1048 */ 1049 com7 = info->fmt->regs[0].value; 1050 com7 |= wsize->com7_bit; 1051 ret = ov7670_write(sd, REG_COM7, com7); 1052 if (ret) 1053 return ret; 1054 1055 /* 1056 * Configure the media bus through COM10 register 1057 */ 1058 if (info->mbus_config & V4L2_MBUS_VSYNC_ACTIVE_LOW) 1059 com10 |= COM10_VS_NEG; 1060 if (info->mbus_config & V4L2_MBUS_HSYNC_ACTIVE_LOW) 1061 com10 |= COM10_HREF_REV; 1062 if (info->pclk_hb_disable) 1063 com10 |= COM10_PCLK_HB; 1064 ret = ov7670_write(sd, REG_COM10, com10); 1065 if (ret) 1066 return ret; 1067 1068 /* 1069 * Now write the rest of the array. Also store start/stops 1070 */ 1071 ret = ov7670_write_array(sd, info->fmt->regs + 1); 1072 if (ret) 1073 return ret; 1074 1075 ret = ov7670_set_hw(sd, wsize->hstart, wsize->hstop, wsize->vstart, 1076 wsize->vstop); 1077 if (ret) 1078 return ret; 1079 1080 if (wsize->regs) { 1081 ret = ov7670_write_array(sd, wsize->regs); 1082 if (ret) 1083 return ret; 1084 } 1085 1086 /* 1087 * If we're running RGB565, we must rewrite clkrc after setting 1088 * the other parameters or the image looks poor. If we're *not* 1089 * doing RGB565, we must not rewrite clkrc or the image looks 1090 * *really* poor. 1091 * 1092 * (Update) Now that we retain clkrc state, we should be able 1093 * to write it unconditionally, and that will make the frame 1094 * rate persistent too. 1095 */ 1096 ret = ov7670_write(sd, REG_CLKRC, info->clkrc); 1097 if (ret) 1098 return ret; 1099 1100 return 0; 1101 } 1102 1103 /* 1104 * Set a format. 1105 */ 1106 static int ov7670_set_fmt(struct v4l2_subdev *sd, 1107 struct v4l2_subdev_state *sd_state, 1108 struct v4l2_subdev_format *format) 1109 { 1110 struct ov7670_info *info = to_state(sd); 1111 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1112 struct v4l2_mbus_framefmt *mbus_fmt; 1113 #endif 1114 int ret; 1115 1116 if (format->pad) 1117 return -EINVAL; 1118 1119 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 1120 ret = ov7670_try_fmt_internal(sd, &format->format, NULL, NULL); 1121 if (ret) 1122 return ret; 1123 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1124 mbus_fmt = v4l2_subdev_get_try_format(sd, sd_state, 1125 format->pad); 1126 *mbus_fmt = format->format; 1127 #endif 1128 return 0; 1129 } 1130 1131 ret = ov7670_try_fmt_internal(sd, &format->format, &info->fmt, &info->wsize); 1132 if (ret) 1133 return ret; 1134 1135 /* 1136 * If the device is not powered up by the host driver do 1137 * not apply any changes to H/W at this time. Instead 1138 * the frame format will be restored right after power-up. 1139 */ 1140 if (info->on) 1141 return ov7670_apply_fmt(sd); 1142 1143 return 0; 1144 } 1145 1146 static int ov7670_get_fmt(struct v4l2_subdev *sd, 1147 struct v4l2_subdev_state *sd_state, 1148 struct v4l2_subdev_format *format) 1149 { 1150 struct ov7670_info *info = to_state(sd); 1151 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1152 struct v4l2_mbus_framefmt *mbus_fmt; 1153 #endif 1154 1155 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 1156 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1157 mbus_fmt = v4l2_subdev_get_try_format(sd, sd_state, 0); 1158 format->format = *mbus_fmt; 1159 return 0; 1160 #else 1161 return -EINVAL; 1162 #endif 1163 } else { 1164 format->format = info->format; 1165 } 1166 1167 return 0; 1168 } 1169 1170 /* 1171 * Implement G/S_PARM. There is a "high quality" mode we could try 1172 * to do someday; for now, we just do the frame rate tweak. 1173 */ 1174 static int ov7670_g_frame_interval(struct v4l2_subdev *sd, 1175 struct v4l2_subdev_frame_interval *ival) 1176 { 1177 struct ov7670_info *info = to_state(sd); 1178 1179 1180 info->devtype->get_framerate(sd, &ival->interval); 1181 1182 return 0; 1183 } 1184 1185 static int ov7670_s_frame_interval(struct v4l2_subdev *sd, 1186 struct v4l2_subdev_frame_interval *ival) 1187 { 1188 struct v4l2_fract *tpf = &ival->interval; 1189 struct ov7670_info *info = to_state(sd); 1190 1191 1192 return info->devtype->set_framerate(sd, tpf); 1193 } 1194 1195 1196 /* 1197 * Frame intervals. Since frame rates are controlled with the clock 1198 * divider, we can only do 30/n for integer n values. So no continuous 1199 * or stepwise options. Here we just pick a handful of logical values. 1200 */ 1201 1202 static int ov7670_frame_rates[] = { 30, 15, 10, 5, 1 }; 1203 1204 static int ov7670_enum_frame_interval(struct v4l2_subdev *sd, 1205 struct v4l2_subdev_state *sd_state, 1206 struct v4l2_subdev_frame_interval_enum *fie) 1207 { 1208 struct ov7670_info *info = to_state(sd); 1209 unsigned int n_win_sizes = info->devtype->n_win_sizes; 1210 int i; 1211 1212 if (fie->pad) 1213 return -EINVAL; 1214 if (fie->index >= ARRAY_SIZE(ov7670_frame_rates)) 1215 return -EINVAL; 1216 1217 /* 1218 * Check if the width/height is valid. 1219 * 1220 * If a minimum width/height was requested, filter out the capture 1221 * windows that fall outside that. 1222 */ 1223 for (i = 0; i < n_win_sizes; i++) { 1224 struct ov7670_win_size *win = &info->devtype->win_sizes[i]; 1225 1226 if (info->min_width && win->width < info->min_width) 1227 continue; 1228 if (info->min_height && win->height < info->min_height) 1229 continue; 1230 if (fie->width == win->width && fie->height == win->height) 1231 break; 1232 } 1233 if (i == n_win_sizes) 1234 return -EINVAL; 1235 fie->interval.numerator = 1; 1236 fie->interval.denominator = ov7670_frame_rates[fie->index]; 1237 return 0; 1238 } 1239 1240 /* 1241 * Frame size enumeration 1242 */ 1243 static int ov7670_enum_frame_size(struct v4l2_subdev *sd, 1244 struct v4l2_subdev_state *sd_state, 1245 struct v4l2_subdev_frame_size_enum *fse) 1246 { 1247 struct ov7670_info *info = to_state(sd); 1248 int i; 1249 int num_valid = -1; 1250 __u32 index = fse->index; 1251 unsigned int n_win_sizes = info->devtype->n_win_sizes; 1252 1253 if (fse->pad) 1254 return -EINVAL; 1255 1256 /* 1257 * If a minimum width/height was requested, filter out the capture 1258 * windows that fall outside that. 1259 */ 1260 for (i = 0; i < n_win_sizes; i++) { 1261 struct ov7670_win_size *win = &info->devtype->win_sizes[i]; 1262 1263 if (info->min_width && win->width < info->min_width) 1264 continue; 1265 if (info->min_height && win->height < info->min_height) 1266 continue; 1267 if (index == ++num_valid) { 1268 fse->min_width = fse->max_width = win->width; 1269 fse->min_height = fse->max_height = win->height; 1270 return 0; 1271 } 1272 } 1273 1274 return -EINVAL; 1275 } 1276 1277 /* 1278 * Code for dealing with controls. 1279 */ 1280 1281 static int ov7670_store_cmatrix(struct v4l2_subdev *sd, 1282 int matrix[CMATRIX_LEN]) 1283 { 1284 int i, ret; 1285 unsigned char signbits = 0; 1286 1287 /* 1288 * Weird crap seems to exist in the upper part of 1289 * the sign bits register, so let's preserve it. 1290 */ 1291 ret = ov7670_read(sd, REG_CMATRIX_SIGN, &signbits); 1292 signbits &= 0xc0; 1293 1294 for (i = 0; i < CMATRIX_LEN; i++) { 1295 unsigned char raw; 1296 1297 if (matrix[i] < 0) { 1298 signbits |= (1 << i); 1299 if (matrix[i] < -255) 1300 raw = 0xff; 1301 else 1302 raw = (-1 * matrix[i]) & 0xff; 1303 } else { 1304 if (matrix[i] > 255) 1305 raw = 0xff; 1306 else 1307 raw = matrix[i] & 0xff; 1308 } 1309 ret = ov7670_write(sd, REG_CMATRIX_BASE + i, raw); 1310 if (ret) 1311 return ret; 1312 } 1313 return ov7670_write(sd, REG_CMATRIX_SIGN, signbits); 1314 } 1315 1316 1317 /* 1318 * Hue also requires messing with the color matrix. It also requires 1319 * trig functions, which tend not to be well supported in the kernel. 1320 * So here is a simple table of sine values, 0-90 degrees, in steps 1321 * of five degrees. Values are multiplied by 1000. 1322 * 1323 * The following naive approximate trig functions require an argument 1324 * carefully limited to -180 <= theta <= 180. 1325 */ 1326 #define SIN_STEP 5 1327 static const int ov7670_sin_table[] = { 1328 0, 87, 173, 258, 342, 422, 1329 499, 573, 642, 707, 766, 819, 1330 866, 906, 939, 965, 984, 996, 1331 1000 1332 }; 1333 1334 static int ov7670_sine(int theta) 1335 { 1336 int chs = 1; 1337 int sine; 1338 1339 if (theta < 0) { 1340 theta = -theta; 1341 chs = -1; 1342 } 1343 if (theta <= 90) 1344 sine = ov7670_sin_table[theta/SIN_STEP]; 1345 else { 1346 theta -= 90; 1347 sine = 1000 - ov7670_sin_table[theta/SIN_STEP]; 1348 } 1349 return sine*chs; 1350 } 1351 1352 static int ov7670_cosine(int theta) 1353 { 1354 theta = 90 - theta; 1355 if (theta > 180) 1356 theta -= 360; 1357 else if (theta < -180) 1358 theta += 360; 1359 return ov7670_sine(theta); 1360 } 1361 1362 1363 1364 1365 static void ov7670_calc_cmatrix(struct ov7670_info *info, 1366 int matrix[CMATRIX_LEN], int sat, int hue) 1367 { 1368 int i; 1369 /* 1370 * Apply the current saturation setting first. 1371 */ 1372 for (i = 0; i < CMATRIX_LEN; i++) 1373 matrix[i] = (info->fmt->cmatrix[i] * sat) >> 7; 1374 /* 1375 * Then, if need be, rotate the hue value. 1376 */ 1377 if (hue != 0) { 1378 int sinth, costh, tmpmatrix[CMATRIX_LEN]; 1379 1380 memcpy(tmpmatrix, matrix, CMATRIX_LEN*sizeof(int)); 1381 sinth = ov7670_sine(hue); 1382 costh = ov7670_cosine(hue); 1383 1384 matrix[0] = (matrix[3]*sinth + matrix[0]*costh)/1000; 1385 matrix[1] = (matrix[4]*sinth + matrix[1]*costh)/1000; 1386 matrix[2] = (matrix[5]*sinth + matrix[2]*costh)/1000; 1387 matrix[3] = (matrix[3]*costh - matrix[0]*sinth)/1000; 1388 matrix[4] = (matrix[4]*costh - matrix[1]*sinth)/1000; 1389 matrix[5] = (matrix[5]*costh - matrix[2]*sinth)/1000; 1390 } 1391 } 1392 1393 1394 1395 static int ov7670_s_sat_hue(struct v4l2_subdev *sd, int sat, int hue) 1396 { 1397 struct ov7670_info *info = to_state(sd); 1398 int matrix[CMATRIX_LEN]; 1399 1400 ov7670_calc_cmatrix(info, matrix, sat, hue); 1401 return ov7670_store_cmatrix(sd, matrix); 1402 } 1403 1404 1405 /* 1406 * Some weird registers seem to store values in a sign/magnitude format! 1407 */ 1408 1409 static unsigned char ov7670_abs_to_sm(unsigned char v) 1410 { 1411 if (v > 127) 1412 return v & 0x7f; 1413 return (128 - v) | 0x80; 1414 } 1415 1416 static int ov7670_s_brightness(struct v4l2_subdev *sd, int value) 1417 { 1418 unsigned char com8 = 0, v; 1419 1420 ov7670_read(sd, REG_COM8, &com8); 1421 com8 &= ~COM8_AEC; 1422 ov7670_write(sd, REG_COM8, com8); 1423 v = ov7670_abs_to_sm(value); 1424 return ov7670_write(sd, REG_BRIGHT, v); 1425 } 1426 1427 static int ov7670_s_contrast(struct v4l2_subdev *sd, int value) 1428 { 1429 return ov7670_write(sd, REG_CONTRAS, (unsigned char) value); 1430 } 1431 1432 static int ov7670_s_hflip(struct v4l2_subdev *sd, int value) 1433 { 1434 unsigned char v = 0; 1435 int ret; 1436 1437 ret = ov7670_read(sd, REG_MVFP, &v); 1438 if (ret) 1439 return ret; 1440 if (value) 1441 v |= MVFP_MIRROR; 1442 else 1443 v &= ~MVFP_MIRROR; 1444 msleep(10); /* FIXME */ 1445 return ov7670_write(sd, REG_MVFP, v); 1446 } 1447 1448 static int ov7670_s_vflip(struct v4l2_subdev *sd, int value) 1449 { 1450 unsigned char v = 0; 1451 int ret; 1452 1453 ret = ov7670_read(sd, REG_MVFP, &v); 1454 if (ret) 1455 return ret; 1456 if (value) 1457 v |= MVFP_FLIP; 1458 else 1459 v &= ~MVFP_FLIP; 1460 msleep(10); /* FIXME */ 1461 return ov7670_write(sd, REG_MVFP, v); 1462 } 1463 1464 /* 1465 * GAIN is split between REG_GAIN and REG_VREF[7:6]. If one believes 1466 * the data sheet, the VREF parts should be the most significant, but 1467 * experience shows otherwise. There seems to be little value in 1468 * messing with the VREF bits, so we leave them alone. 1469 */ 1470 static int ov7670_g_gain(struct v4l2_subdev *sd, __s32 *value) 1471 { 1472 int ret; 1473 unsigned char gain; 1474 1475 ret = ov7670_read(sd, REG_GAIN, &gain); 1476 if (ret) 1477 return ret; 1478 *value = gain; 1479 return 0; 1480 } 1481 1482 static int ov7670_s_gain(struct v4l2_subdev *sd, int value) 1483 { 1484 int ret; 1485 unsigned char com8; 1486 1487 ret = ov7670_write(sd, REG_GAIN, value & 0xff); 1488 if (ret) 1489 return ret; 1490 /* Have to turn off AGC as well */ 1491 ret = ov7670_read(sd, REG_COM8, &com8); 1492 if (ret) 1493 return ret; 1494 return ov7670_write(sd, REG_COM8, com8 & ~COM8_AGC); 1495 } 1496 1497 /* 1498 * Tweak autogain. 1499 */ 1500 static int ov7670_s_autogain(struct v4l2_subdev *sd, int value) 1501 { 1502 int ret; 1503 unsigned char com8; 1504 1505 ret = ov7670_read(sd, REG_COM8, &com8); 1506 if (ret == 0) { 1507 if (value) 1508 com8 |= COM8_AGC; 1509 else 1510 com8 &= ~COM8_AGC; 1511 ret = ov7670_write(sd, REG_COM8, com8); 1512 } 1513 return ret; 1514 } 1515 1516 static int ov7670_s_exp(struct v4l2_subdev *sd, int value) 1517 { 1518 int ret; 1519 unsigned char com1, com8, aech, aechh; 1520 1521 ret = ov7670_read(sd, REG_COM1, &com1) + 1522 ov7670_read(sd, REG_COM8, &com8) + 1523 ov7670_read(sd, REG_AECHH, &aechh); 1524 if (ret) 1525 return ret; 1526 1527 com1 = (com1 & 0xfc) | (value & 0x03); 1528 aech = (value >> 2) & 0xff; 1529 aechh = (aechh & 0xc0) | ((value >> 10) & 0x3f); 1530 ret = ov7670_write(sd, REG_COM1, com1) + 1531 ov7670_write(sd, REG_AECH, aech) + 1532 ov7670_write(sd, REG_AECHH, aechh); 1533 /* Have to turn off AEC as well */ 1534 if (ret == 0) 1535 ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AEC); 1536 return ret; 1537 } 1538 1539 /* 1540 * Tweak autoexposure. 1541 */ 1542 static int ov7670_s_autoexp(struct v4l2_subdev *sd, 1543 enum v4l2_exposure_auto_type value) 1544 { 1545 int ret; 1546 unsigned char com8; 1547 1548 ret = ov7670_read(sd, REG_COM8, &com8); 1549 if (ret == 0) { 1550 if (value == V4L2_EXPOSURE_AUTO) 1551 com8 |= COM8_AEC; 1552 else 1553 com8 &= ~COM8_AEC; 1554 ret = ov7670_write(sd, REG_COM8, com8); 1555 } 1556 return ret; 1557 } 1558 1559 static const char * const ov7670_test_pattern_menu[] = { 1560 "No test output", 1561 "Shifting \"1\"", 1562 "8-bar color bar", 1563 "Fade to gray color bar", 1564 }; 1565 1566 static int ov7670_s_test_pattern(struct v4l2_subdev *sd, int value) 1567 { 1568 int ret; 1569 1570 ret = ov7670_update_bits(sd, REG_SCALING_XSC, TEST_PATTTERN_0, 1571 value & BIT(0) ? TEST_PATTTERN_0 : 0); 1572 if (ret) 1573 return ret; 1574 1575 return ov7670_update_bits(sd, REG_SCALING_YSC, TEST_PATTTERN_1, 1576 value & BIT(1) ? TEST_PATTTERN_1 : 0); 1577 } 1578 1579 static int ov7670_g_volatile_ctrl(struct v4l2_ctrl *ctrl) 1580 { 1581 struct v4l2_subdev *sd = to_sd(ctrl); 1582 struct ov7670_info *info = to_state(sd); 1583 1584 switch (ctrl->id) { 1585 case V4L2_CID_AUTOGAIN: 1586 return ov7670_g_gain(sd, &info->gain->val); 1587 } 1588 return -EINVAL; 1589 } 1590 1591 static int ov7670_s_ctrl(struct v4l2_ctrl *ctrl) 1592 { 1593 struct v4l2_subdev *sd = to_sd(ctrl); 1594 struct ov7670_info *info = to_state(sd); 1595 1596 switch (ctrl->id) { 1597 case V4L2_CID_BRIGHTNESS: 1598 return ov7670_s_brightness(sd, ctrl->val); 1599 case V4L2_CID_CONTRAST: 1600 return ov7670_s_contrast(sd, ctrl->val); 1601 case V4L2_CID_SATURATION: 1602 return ov7670_s_sat_hue(sd, 1603 info->saturation->val, info->hue->val); 1604 case V4L2_CID_VFLIP: 1605 return ov7670_s_vflip(sd, ctrl->val); 1606 case V4L2_CID_HFLIP: 1607 return ov7670_s_hflip(sd, ctrl->val); 1608 case V4L2_CID_AUTOGAIN: 1609 /* Only set manual gain if auto gain is not explicitly 1610 turned on. */ 1611 if (!ctrl->val) { 1612 /* ov7670_s_gain turns off auto gain */ 1613 return ov7670_s_gain(sd, info->gain->val); 1614 } 1615 return ov7670_s_autogain(sd, ctrl->val); 1616 case V4L2_CID_EXPOSURE_AUTO: 1617 /* Only set manual exposure if auto exposure is not explicitly 1618 turned on. */ 1619 if (ctrl->val == V4L2_EXPOSURE_MANUAL) { 1620 /* ov7670_s_exp turns off auto exposure */ 1621 return ov7670_s_exp(sd, info->exposure->val); 1622 } 1623 return ov7670_s_autoexp(sd, ctrl->val); 1624 case V4L2_CID_TEST_PATTERN: 1625 return ov7670_s_test_pattern(sd, ctrl->val); 1626 } 1627 return -EINVAL; 1628 } 1629 1630 static const struct v4l2_ctrl_ops ov7670_ctrl_ops = { 1631 .s_ctrl = ov7670_s_ctrl, 1632 .g_volatile_ctrl = ov7670_g_volatile_ctrl, 1633 }; 1634 1635 #ifdef CONFIG_VIDEO_ADV_DEBUG 1636 static int ov7670_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) 1637 { 1638 unsigned char val = 0; 1639 int ret; 1640 1641 ret = ov7670_read(sd, reg->reg & 0xff, &val); 1642 reg->val = val; 1643 reg->size = 1; 1644 return ret; 1645 } 1646 1647 static int ov7670_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg) 1648 { 1649 ov7670_write(sd, reg->reg & 0xff, reg->val & 0xff); 1650 return 0; 1651 } 1652 #endif 1653 1654 static void ov7670_power_on(struct v4l2_subdev *sd) 1655 { 1656 struct ov7670_info *info = to_state(sd); 1657 1658 if (info->on) 1659 return; 1660 1661 clk_prepare_enable(info->clk); 1662 1663 if (info->pwdn_gpio) 1664 gpiod_set_value(info->pwdn_gpio, 0); 1665 if (info->resetb_gpio) { 1666 gpiod_set_value(info->resetb_gpio, 1); 1667 usleep_range(500, 1000); 1668 gpiod_set_value(info->resetb_gpio, 0); 1669 } 1670 if (info->pwdn_gpio || info->resetb_gpio || info->clk) 1671 usleep_range(3000, 5000); 1672 1673 info->on = true; 1674 } 1675 1676 static void ov7670_power_off(struct v4l2_subdev *sd) 1677 { 1678 struct ov7670_info *info = to_state(sd); 1679 1680 if (!info->on) 1681 return; 1682 1683 clk_disable_unprepare(info->clk); 1684 1685 if (info->pwdn_gpio) 1686 gpiod_set_value(info->pwdn_gpio, 1); 1687 1688 info->on = false; 1689 } 1690 1691 static int ov7670_s_power(struct v4l2_subdev *sd, int on) 1692 { 1693 struct ov7670_info *info = to_state(sd); 1694 1695 if (info->on == on) 1696 return 0; 1697 1698 if (on) { 1699 ov7670_power_on(sd); 1700 ov7670_init(sd, 0); 1701 ov7670_apply_fmt(sd); 1702 ov7675_apply_framerate(sd); 1703 v4l2_ctrl_handler_setup(&info->hdl); 1704 } else { 1705 ov7670_power_off(sd); 1706 } 1707 1708 return 0; 1709 } 1710 1711 static void ov7670_get_default_format(struct v4l2_subdev *sd, 1712 struct v4l2_mbus_framefmt *format) 1713 { 1714 struct ov7670_info *info = to_state(sd); 1715 1716 format->width = info->devtype->win_sizes[0].width; 1717 format->height = info->devtype->win_sizes[0].height; 1718 format->colorspace = info->fmt->colorspace; 1719 format->code = info->fmt->mbus_code; 1720 format->field = V4L2_FIELD_NONE; 1721 } 1722 1723 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1724 static int ov7670_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) 1725 { 1726 struct v4l2_mbus_framefmt *format = 1727 v4l2_subdev_get_try_format(sd, fh->state, 0); 1728 1729 ov7670_get_default_format(sd, format); 1730 1731 return 0; 1732 } 1733 #endif 1734 1735 /* ----------------------------------------------------------------------- */ 1736 1737 static const struct v4l2_subdev_core_ops ov7670_core_ops = { 1738 .reset = ov7670_reset, 1739 .init = ov7670_init, 1740 .s_power = ov7670_s_power, 1741 .log_status = v4l2_ctrl_subdev_log_status, 1742 .subscribe_event = v4l2_ctrl_subdev_subscribe_event, 1743 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 1744 #ifdef CONFIG_VIDEO_ADV_DEBUG 1745 .g_register = ov7670_g_register, 1746 .s_register = ov7670_s_register, 1747 #endif 1748 }; 1749 1750 static const struct v4l2_subdev_video_ops ov7670_video_ops = { 1751 .s_frame_interval = ov7670_s_frame_interval, 1752 .g_frame_interval = ov7670_g_frame_interval, 1753 }; 1754 1755 static const struct v4l2_subdev_pad_ops ov7670_pad_ops = { 1756 .enum_frame_interval = ov7670_enum_frame_interval, 1757 .enum_frame_size = ov7670_enum_frame_size, 1758 .enum_mbus_code = ov7670_enum_mbus_code, 1759 .get_fmt = ov7670_get_fmt, 1760 .set_fmt = ov7670_set_fmt, 1761 }; 1762 1763 static const struct v4l2_subdev_ops ov7670_ops = { 1764 .core = &ov7670_core_ops, 1765 .video = &ov7670_video_ops, 1766 .pad = &ov7670_pad_ops, 1767 }; 1768 1769 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1770 static const struct v4l2_subdev_internal_ops ov7670_subdev_internal_ops = { 1771 .open = ov7670_open, 1772 }; 1773 #endif 1774 1775 /* ----------------------------------------------------------------------- */ 1776 1777 static const struct ov7670_devtype ov7670_devdata[] = { 1778 [MODEL_OV7670] = { 1779 .win_sizes = ov7670_win_sizes, 1780 .n_win_sizes = ARRAY_SIZE(ov7670_win_sizes), 1781 .set_framerate = ov7670_set_framerate_legacy, 1782 .get_framerate = ov7670_get_framerate_legacy, 1783 }, 1784 [MODEL_OV7675] = { 1785 .win_sizes = ov7675_win_sizes, 1786 .n_win_sizes = ARRAY_SIZE(ov7675_win_sizes), 1787 .set_framerate = ov7675_set_framerate, 1788 .get_framerate = ov7675_get_framerate, 1789 }, 1790 }; 1791 1792 static int ov7670_init_gpio(struct i2c_client *client, struct ov7670_info *info) 1793 { 1794 info->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown", 1795 GPIOD_OUT_LOW); 1796 if (IS_ERR(info->pwdn_gpio)) { 1797 dev_info(&client->dev, "can't get %s GPIO\n", "powerdown"); 1798 return PTR_ERR(info->pwdn_gpio); 1799 } 1800 1801 info->resetb_gpio = devm_gpiod_get_optional(&client->dev, "reset", 1802 GPIOD_OUT_LOW); 1803 if (IS_ERR(info->resetb_gpio)) { 1804 dev_info(&client->dev, "can't get %s GPIO\n", "reset"); 1805 return PTR_ERR(info->resetb_gpio); 1806 } 1807 1808 usleep_range(3000, 5000); 1809 1810 return 0; 1811 } 1812 1813 /* 1814 * ov7670_parse_dt() - Parse device tree to collect mbus configuration 1815 * properties 1816 */ 1817 static int ov7670_parse_dt(struct device *dev, 1818 struct ov7670_info *info) 1819 { 1820 struct fwnode_handle *fwnode = dev_fwnode(dev); 1821 struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 }; 1822 struct fwnode_handle *ep; 1823 int ret; 1824 1825 if (!fwnode) 1826 return -EINVAL; 1827 1828 info->pclk_hb_disable = false; 1829 if (fwnode_property_present(fwnode, "ov7670,pclk-hb-disable")) 1830 info->pclk_hb_disable = true; 1831 1832 ep = fwnode_graph_get_next_endpoint(fwnode, NULL); 1833 if (!ep) 1834 return -EINVAL; 1835 1836 ret = v4l2_fwnode_endpoint_parse(ep, &bus_cfg); 1837 fwnode_handle_put(ep); 1838 if (ret) 1839 return ret; 1840 1841 if (bus_cfg.bus_type != V4L2_MBUS_PARALLEL) { 1842 dev_err(dev, "Unsupported media bus type\n"); 1843 return ret; 1844 } 1845 info->mbus_config = bus_cfg.bus.parallel.flags; 1846 1847 return 0; 1848 } 1849 1850 static int ov7670_probe(struct i2c_client *client, 1851 const struct i2c_device_id *id) 1852 { 1853 struct v4l2_fract tpf; 1854 struct v4l2_subdev *sd; 1855 struct ov7670_info *info; 1856 int ret; 1857 1858 info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL); 1859 if (info == NULL) 1860 return -ENOMEM; 1861 sd = &info->sd; 1862 v4l2_i2c_subdev_init(sd, client, &ov7670_ops); 1863 1864 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1865 sd->internal_ops = &ov7670_subdev_internal_ops; 1866 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; 1867 #endif 1868 1869 info->clock_speed = 30; /* default: a guess */ 1870 1871 if (dev_fwnode(&client->dev)) { 1872 ret = ov7670_parse_dt(&client->dev, info); 1873 if (ret) 1874 return ret; 1875 1876 } else if (client->dev.platform_data) { 1877 struct ov7670_config *config = client->dev.platform_data; 1878 1879 /* 1880 * Must apply configuration before initializing device, because it 1881 * selects I/O method. 1882 */ 1883 info->min_width = config->min_width; 1884 info->min_height = config->min_height; 1885 info->use_smbus = config->use_smbus; 1886 1887 if (config->clock_speed) 1888 info->clock_speed = config->clock_speed; 1889 1890 if (config->pll_bypass) 1891 info->pll_bypass = true; 1892 1893 if (config->pclk_hb_disable) 1894 info->pclk_hb_disable = true; 1895 } 1896 1897 info->clk = devm_clk_get(&client->dev, "xclk"); /* optional */ 1898 if (IS_ERR(info->clk)) { 1899 ret = PTR_ERR(info->clk); 1900 if (ret == -ENOENT) 1901 info->clk = NULL; 1902 else 1903 return ret; 1904 } 1905 1906 ret = ov7670_init_gpio(client, info); 1907 if (ret) 1908 return ret; 1909 1910 ov7670_power_on(sd); 1911 1912 if (info->clk) { 1913 info->clock_speed = clk_get_rate(info->clk) / 1000000; 1914 if (info->clock_speed < 10 || info->clock_speed > 48) { 1915 ret = -EINVAL; 1916 goto power_off; 1917 } 1918 } 1919 1920 /* Make sure it's an ov7670 */ 1921 ret = ov7670_detect(sd); 1922 if (ret) { 1923 v4l_dbg(1, debug, client, 1924 "chip found @ 0x%x (%s) is not an ov7670 chip.\n", 1925 client->addr << 1, client->adapter->name); 1926 goto power_off; 1927 } 1928 v4l_info(client, "chip found @ 0x%02x (%s)\n", 1929 client->addr << 1, client->adapter->name); 1930 1931 info->devtype = &ov7670_devdata[id->driver_data]; 1932 info->fmt = &ov7670_formats[0]; 1933 info->wsize = &info->devtype->win_sizes[0]; 1934 1935 ov7670_get_default_format(sd, &info->format); 1936 1937 info->clkrc = 0; 1938 1939 /* Set default frame rate to 30 fps */ 1940 tpf.numerator = 1; 1941 tpf.denominator = 30; 1942 info->devtype->set_framerate(sd, &tpf); 1943 1944 v4l2_ctrl_handler_init(&info->hdl, 10); 1945 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1946 V4L2_CID_BRIGHTNESS, 0, 255, 1, 128); 1947 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1948 V4L2_CID_CONTRAST, 0, 127, 1, 64); 1949 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1950 V4L2_CID_VFLIP, 0, 1, 1, 0); 1951 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1952 V4L2_CID_HFLIP, 0, 1, 1, 0); 1953 info->saturation = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1954 V4L2_CID_SATURATION, 0, 256, 1, 128); 1955 info->hue = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1956 V4L2_CID_HUE, -180, 180, 5, 0); 1957 info->gain = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1958 V4L2_CID_GAIN, 0, 255, 1, 128); 1959 info->auto_gain = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1960 V4L2_CID_AUTOGAIN, 0, 1, 1, 1); 1961 info->exposure = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, 1962 V4L2_CID_EXPOSURE, 0, 65535, 1, 500); 1963 info->auto_exposure = v4l2_ctrl_new_std_menu(&info->hdl, &ov7670_ctrl_ops, 1964 V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL, 0, 1965 V4L2_EXPOSURE_AUTO); 1966 v4l2_ctrl_new_std_menu_items(&info->hdl, &ov7670_ctrl_ops, 1967 V4L2_CID_TEST_PATTERN, 1968 ARRAY_SIZE(ov7670_test_pattern_menu) - 1, 0, 0, 1969 ov7670_test_pattern_menu); 1970 sd->ctrl_handler = &info->hdl; 1971 if (info->hdl.error) { 1972 ret = info->hdl.error; 1973 1974 goto hdl_free; 1975 } 1976 /* 1977 * We have checked empirically that hw allows to read back the gain 1978 * value chosen by auto gain but that's not the case for auto exposure. 1979 */ 1980 v4l2_ctrl_auto_cluster(2, &info->auto_gain, 0, true); 1981 v4l2_ctrl_auto_cluster(2, &info->auto_exposure, 1982 V4L2_EXPOSURE_MANUAL, false); 1983 v4l2_ctrl_cluster(2, &info->saturation); 1984 1985 #if defined(CONFIG_MEDIA_CONTROLLER) 1986 info->pad.flags = MEDIA_PAD_FL_SOURCE; 1987 info->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1988 ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad); 1989 if (ret < 0) 1990 goto hdl_free; 1991 #endif 1992 1993 v4l2_ctrl_handler_setup(&info->hdl); 1994 1995 ret = v4l2_async_register_subdev(&info->sd); 1996 if (ret < 0) 1997 goto entity_cleanup; 1998 1999 ov7670_power_off(sd); 2000 return 0; 2001 2002 entity_cleanup: 2003 media_entity_cleanup(&info->sd.entity); 2004 hdl_free: 2005 v4l2_ctrl_handler_free(&info->hdl); 2006 power_off: 2007 ov7670_power_off(sd); 2008 return ret; 2009 } 2010 2011 static void ov7670_remove(struct i2c_client *client) 2012 { 2013 struct v4l2_subdev *sd = i2c_get_clientdata(client); 2014 struct ov7670_info *info = to_state(sd); 2015 2016 v4l2_async_unregister_subdev(sd); 2017 v4l2_ctrl_handler_free(&info->hdl); 2018 media_entity_cleanup(&info->sd.entity); 2019 } 2020 2021 static const struct i2c_device_id ov7670_id[] = { 2022 { "ov7670", MODEL_OV7670 }, 2023 { "ov7675", MODEL_OV7675 }, 2024 { } 2025 }; 2026 MODULE_DEVICE_TABLE(i2c, ov7670_id); 2027 2028 #if IS_ENABLED(CONFIG_OF) 2029 static const struct of_device_id ov7670_of_match[] = { 2030 { .compatible = "ovti,ov7670", }, 2031 { /* sentinel */ }, 2032 }; 2033 MODULE_DEVICE_TABLE(of, ov7670_of_match); 2034 #endif 2035 2036 static struct i2c_driver ov7670_driver = { 2037 .driver = { 2038 .name = "ov7670", 2039 .of_match_table = of_match_ptr(ov7670_of_match), 2040 }, 2041 .probe = ov7670_probe, 2042 .remove = ov7670_remove, 2043 .id_table = ov7670_id, 2044 }; 2045 2046 module_i2c_driver(ov7670_driver); 2047