1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for the OV7251 camera sensor. 4 * 5 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. 6 * Copyright (c) 2017-2018, Linaro Ltd. 7 */ 8 9 #include <linux/bitops.h> 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/i2c.h> 15 #include <linux/init.h> 16 #include <linux/module.h> 17 #include <linux/mod_devicetable.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/slab.h> 20 #include <linux/types.h> 21 #include <media/v4l2-ctrls.h> 22 #include <media/v4l2-fwnode.h> 23 #include <media/v4l2-subdev.h> 24 25 #define OV7251_SC_MODE_SELECT 0x0100 26 #define OV7251_SC_MODE_SELECT_SW_STANDBY 0x0 27 #define OV7251_SC_MODE_SELECT_STREAMING 0x1 28 29 #define OV7251_CHIP_ID_HIGH 0x300a 30 #define OV7251_CHIP_ID_HIGH_BYTE 0x77 31 #define OV7251_CHIP_ID_LOW 0x300b 32 #define OV7251_CHIP_ID_LOW_BYTE 0x50 33 #define OV7251_SC_GP_IO_IN1 0x3029 34 #define OV7251_AEC_EXPO_0 0x3500 35 #define OV7251_AEC_EXPO_1 0x3501 36 #define OV7251_AEC_EXPO_2 0x3502 37 #define OV7251_AEC_AGC_ADJ_0 0x350a 38 #define OV7251_AEC_AGC_ADJ_1 0x350b 39 #define OV7251_TIMING_FORMAT1 0x3820 40 #define OV7251_TIMING_FORMAT1_VFLIP BIT(2) 41 #define OV7251_TIMING_FORMAT2 0x3821 42 #define OV7251_TIMING_FORMAT2_MIRROR BIT(2) 43 #define OV7251_PRE_ISP_00 0x5e00 44 #define OV7251_PRE_ISP_00_TEST_PATTERN BIT(7) 45 46 struct reg_value { 47 u16 reg; 48 u8 val; 49 }; 50 51 struct ov7251_mode_info { 52 u32 width; 53 u32 height; 54 const struct reg_value *data; 55 u32 data_size; 56 u32 pixel_clock; 57 u32 link_freq; 58 u16 exposure_max; 59 u16 exposure_def; 60 struct v4l2_fract timeperframe; 61 }; 62 63 enum supported_link_freqs { 64 OV7251_LINK_FREQ_240_MHZ, 65 OV7251_NUM_SUPPORTED_LINK_FREQS 66 }; 67 68 struct ov7251 { 69 struct i2c_client *i2c_client; 70 struct device *dev; 71 struct v4l2_subdev sd; 72 struct media_pad pad; 73 struct v4l2_fwnode_endpoint ep; 74 struct v4l2_mbus_framefmt fmt; 75 struct v4l2_rect crop; 76 struct clk *xclk; 77 u32 xclk_freq; 78 79 struct regulator *io_regulator; 80 struct regulator *core_regulator; 81 struct regulator *analog_regulator; 82 83 enum supported_link_freqs link_freq_idx; 84 const struct ov7251_mode_info *current_mode; 85 86 struct v4l2_ctrl_handler ctrls; 87 struct v4l2_ctrl *pixel_clock; 88 struct v4l2_ctrl *link_freq; 89 struct v4l2_ctrl *exposure; 90 struct v4l2_ctrl *gain; 91 92 /* Cached register values */ 93 u8 aec_pk_manual; 94 u8 pre_isp_00; 95 u8 timing_format1; 96 u8 timing_format2; 97 98 struct mutex lock; /* lock to protect power state, ctrls and mode */ 99 bool power_on; 100 101 struct gpio_desc *enable_gpio; 102 }; 103 104 static inline struct ov7251 *to_ov7251(struct v4l2_subdev *sd) 105 { 106 return container_of(sd, struct ov7251, sd); 107 } 108 109 static const struct reg_value ov7251_global_init_setting[] = { 110 { 0x0103, 0x01 }, 111 { 0x303b, 0x02 }, 112 }; 113 114 static const struct reg_value ov7251_setting_vga_30fps[] = { 115 { 0x3005, 0x00 }, 116 { 0x3012, 0xc0 }, 117 { 0x3013, 0xd2 }, 118 { 0x3014, 0x04 }, 119 { 0x3016, 0xf0 }, 120 { 0x3017, 0xf0 }, 121 { 0x3018, 0xf0 }, 122 { 0x301a, 0xf0 }, 123 { 0x301b, 0xf0 }, 124 { 0x301c, 0xf0 }, 125 { 0x3023, 0x05 }, 126 { 0x3037, 0xf0 }, 127 { 0x3098, 0x04 }, /* pll2 pre divider */ 128 { 0x3099, 0x28 }, /* pll2 multiplier */ 129 { 0x309a, 0x05 }, /* pll2 sys divider */ 130 { 0x309b, 0x04 }, /* pll2 adc divider */ 131 { 0x309d, 0x00 }, /* pll2 divider */ 132 { 0x30b0, 0x0a }, /* pll1 pix divider */ 133 { 0x30b1, 0x01 }, /* pll1 divider */ 134 { 0x30b3, 0x64 }, /* pll1 multiplier */ 135 { 0x30b4, 0x03 }, /* pll1 pre divider */ 136 { 0x30b5, 0x05 }, /* pll1 mipi divider */ 137 { 0x3106, 0xda }, 138 { 0x3503, 0x07 }, 139 { 0x3509, 0x10 }, 140 { 0x3600, 0x1c }, 141 { 0x3602, 0x62 }, 142 { 0x3620, 0xb7 }, 143 { 0x3622, 0x04 }, 144 { 0x3626, 0x21 }, 145 { 0x3627, 0x30 }, 146 { 0x3630, 0x44 }, 147 { 0x3631, 0x35 }, 148 { 0x3634, 0x60 }, 149 { 0x3636, 0x00 }, 150 { 0x3662, 0x01 }, 151 { 0x3663, 0x70 }, 152 { 0x3664, 0x50 }, 153 { 0x3666, 0x0a }, 154 { 0x3669, 0x1a }, 155 { 0x366a, 0x00 }, 156 { 0x366b, 0x50 }, 157 { 0x3673, 0x01 }, 158 { 0x3674, 0xff }, 159 { 0x3675, 0x03 }, 160 { 0x3705, 0xc1 }, 161 { 0x3709, 0x40 }, 162 { 0x373c, 0x08 }, 163 { 0x3742, 0x00 }, 164 { 0x3757, 0xb3 }, 165 { 0x3788, 0x00 }, 166 { 0x37a8, 0x01 }, 167 { 0x37a9, 0xc0 }, 168 { 0x3800, 0x00 }, 169 { 0x3801, 0x04 }, 170 { 0x3802, 0x00 }, 171 { 0x3803, 0x04 }, 172 { 0x3804, 0x02 }, 173 { 0x3805, 0x8b }, 174 { 0x3806, 0x01 }, 175 { 0x3807, 0xeb }, 176 { 0x3808, 0x02 }, /* width high */ 177 { 0x3809, 0x80 }, /* width low */ 178 { 0x380a, 0x01 }, /* height high */ 179 { 0x380b, 0xe0 }, /* height low */ 180 { 0x380c, 0x03 }, /* total horiz timing high */ 181 { 0x380d, 0xa0 }, /* total horiz timing low */ 182 { 0x380e, 0x06 }, /* total vertical timing high */ 183 { 0x380f, 0xbc }, /* total vertical timing low */ 184 { 0x3810, 0x00 }, 185 { 0x3811, 0x04 }, 186 { 0x3812, 0x00 }, 187 { 0x3813, 0x05 }, 188 { 0x3814, 0x11 }, 189 { 0x3815, 0x11 }, 190 { 0x3820, 0x40 }, 191 { 0x3821, 0x00 }, 192 { 0x382f, 0x0e }, 193 { 0x3832, 0x00 }, 194 { 0x3833, 0x05 }, 195 { 0x3834, 0x00 }, 196 { 0x3835, 0x0c }, 197 { 0x3837, 0x00 }, 198 { 0x3b80, 0x00 }, 199 { 0x3b81, 0xa5 }, 200 { 0x3b82, 0x10 }, 201 { 0x3b83, 0x00 }, 202 { 0x3b84, 0x08 }, 203 { 0x3b85, 0x00 }, 204 { 0x3b86, 0x01 }, 205 { 0x3b87, 0x00 }, 206 { 0x3b88, 0x00 }, 207 { 0x3b89, 0x00 }, 208 { 0x3b8a, 0x00 }, 209 { 0x3b8b, 0x05 }, 210 { 0x3b8c, 0x00 }, 211 { 0x3b8d, 0x00 }, 212 { 0x3b8e, 0x00 }, 213 { 0x3b8f, 0x1a }, 214 { 0x3b94, 0x05 }, 215 { 0x3b95, 0xf2 }, 216 { 0x3b96, 0x40 }, 217 { 0x3c00, 0x89 }, 218 { 0x3c01, 0x63 }, 219 { 0x3c02, 0x01 }, 220 { 0x3c03, 0x00 }, 221 { 0x3c04, 0x00 }, 222 { 0x3c05, 0x03 }, 223 { 0x3c06, 0x00 }, 224 { 0x3c07, 0x06 }, 225 { 0x3c0c, 0x01 }, 226 { 0x3c0d, 0xd0 }, 227 { 0x3c0e, 0x02 }, 228 { 0x3c0f, 0x0a }, 229 { 0x4001, 0x42 }, 230 { 0x4004, 0x04 }, 231 { 0x4005, 0x00 }, 232 { 0x404e, 0x01 }, 233 { 0x4300, 0xff }, 234 { 0x4301, 0x00 }, 235 { 0x4315, 0x00 }, 236 { 0x4501, 0x48 }, 237 { 0x4600, 0x00 }, 238 { 0x4601, 0x4e }, 239 { 0x4801, 0x0f }, 240 { 0x4806, 0x0f }, 241 { 0x4819, 0xaa }, 242 { 0x4823, 0x3e }, 243 { 0x4837, 0x19 }, 244 { 0x4a0d, 0x00 }, 245 { 0x4a47, 0x7f }, 246 { 0x4a49, 0xf0 }, 247 { 0x4a4b, 0x30 }, 248 { 0x5000, 0x85 }, 249 { 0x5001, 0x80 }, 250 }; 251 252 static const struct reg_value ov7251_setting_vga_60fps[] = { 253 { 0x3005, 0x00 }, 254 { 0x3012, 0xc0 }, 255 { 0x3013, 0xd2 }, 256 { 0x3014, 0x04 }, 257 { 0x3016, 0x10 }, 258 { 0x3017, 0x00 }, 259 { 0x3018, 0x00 }, 260 { 0x301a, 0x00 }, 261 { 0x301b, 0x00 }, 262 { 0x301c, 0x00 }, 263 { 0x3023, 0x05 }, 264 { 0x3037, 0xf0 }, 265 { 0x3098, 0x04 }, /* pll2 pre divider */ 266 { 0x3099, 0x28 }, /* pll2 multiplier */ 267 { 0x309a, 0x05 }, /* pll2 sys divider */ 268 { 0x309b, 0x04 }, /* pll2 adc divider */ 269 { 0x309d, 0x00 }, /* pll2 divider */ 270 { 0x30b0, 0x0a }, /* pll1 pix divider */ 271 { 0x30b1, 0x01 }, /* pll1 divider */ 272 { 0x30b3, 0x64 }, /* pll1 multiplier */ 273 { 0x30b4, 0x03 }, /* pll1 pre divider */ 274 { 0x30b5, 0x05 }, /* pll1 mipi divider */ 275 { 0x3106, 0xda }, 276 { 0x3503, 0x07 }, 277 { 0x3509, 0x10 }, 278 { 0x3600, 0x1c }, 279 { 0x3602, 0x62 }, 280 { 0x3620, 0xb7 }, 281 { 0x3622, 0x04 }, 282 { 0x3626, 0x21 }, 283 { 0x3627, 0x30 }, 284 { 0x3630, 0x44 }, 285 { 0x3631, 0x35 }, 286 { 0x3634, 0x60 }, 287 { 0x3636, 0x00 }, 288 { 0x3662, 0x01 }, 289 { 0x3663, 0x70 }, 290 { 0x3664, 0x50 }, 291 { 0x3666, 0x0a }, 292 { 0x3669, 0x1a }, 293 { 0x366a, 0x00 }, 294 { 0x366b, 0x50 }, 295 { 0x3673, 0x01 }, 296 { 0x3674, 0xff }, 297 { 0x3675, 0x03 }, 298 { 0x3705, 0xc1 }, 299 { 0x3709, 0x40 }, 300 { 0x373c, 0x08 }, 301 { 0x3742, 0x00 }, 302 { 0x3757, 0xb3 }, 303 { 0x3788, 0x00 }, 304 { 0x37a8, 0x01 }, 305 { 0x37a9, 0xc0 }, 306 { 0x3800, 0x00 }, 307 { 0x3801, 0x04 }, 308 { 0x3802, 0x00 }, 309 { 0x3803, 0x04 }, 310 { 0x3804, 0x02 }, 311 { 0x3805, 0x8b }, 312 { 0x3806, 0x01 }, 313 { 0x3807, 0xeb }, 314 { 0x3808, 0x02 }, /* width high */ 315 { 0x3809, 0x80 }, /* width low */ 316 { 0x380a, 0x01 }, /* height high */ 317 { 0x380b, 0xe0 }, /* height low */ 318 { 0x380c, 0x03 }, /* total horiz timing high */ 319 { 0x380d, 0xa0 }, /* total horiz timing low */ 320 { 0x380e, 0x03 }, /* total vertical timing high */ 321 { 0x380f, 0x5c }, /* total vertical timing low */ 322 { 0x3810, 0x00 }, 323 { 0x3811, 0x04 }, 324 { 0x3812, 0x00 }, 325 { 0x3813, 0x05 }, 326 { 0x3814, 0x11 }, 327 { 0x3815, 0x11 }, 328 { 0x3820, 0x40 }, 329 { 0x3821, 0x00 }, 330 { 0x382f, 0x0e }, 331 { 0x3832, 0x00 }, 332 { 0x3833, 0x05 }, 333 { 0x3834, 0x00 }, 334 { 0x3835, 0x0c }, 335 { 0x3837, 0x00 }, 336 { 0x3b80, 0x00 }, 337 { 0x3b81, 0xa5 }, 338 { 0x3b82, 0x10 }, 339 { 0x3b83, 0x00 }, 340 { 0x3b84, 0x08 }, 341 { 0x3b85, 0x00 }, 342 { 0x3b86, 0x01 }, 343 { 0x3b87, 0x00 }, 344 { 0x3b88, 0x00 }, 345 { 0x3b89, 0x00 }, 346 { 0x3b8a, 0x00 }, 347 { 0x3b8b, 0x05 }, 348 { 0x3b8c, 0x00 }, 349 { 0x3b8d, 0x00 }, 350 { 0x3b8e, 0x00 }, 351 { 0x3b8f, 0x1a }, 352 { 0x3b94, 0x05 }, 353 { 0x3b95, 0xf2 }, 354 { 0x3b96, 0x40 }, 355 { 0x3c00, 0x89 }, 356 { 0x3c01, 0x63 }, 357 { 0x3c02, 0x01 }, 358 { 0x3c03, 0x00 }, 359 { 0x3c04, 0x00 }, 360 { 0x3c05, 0x03 }, 361 { 0x3c06, 0x00 }, 362 { 0x3c07, 0x06 }, 363 { 0x3c0c, 0x01 }, 364 { 0x3c0d, 0xd0 }, 365 { 0x3c0e, 0x02 }, 366 { 0x3c0f, 0x0a }, 367 { 0x4001, 0x42 }, 368 { 0x4004, 0x04 }, 369 { 0x4005, 0x00 }, 370 { 0x404e, 0x01 }, 371 { 0x4300, 0xff }, 372 { 0x4301, 0x00 }, 373 { 0x4315, 0x00 }, 374 { 0x4501, 0x48 }, 375 { 0x4600, 0x00 }, 376 { 0x4601, 0x4e }, 377 { 0x4801, 0x0f }, 378 { 0x4806, 0x0f }, 379 { 0x4819, 0xaa }, 380 { 0x4823, 0x3e }, 381 { 0x4837, 0x19 }, 382 { 0x4a0d, 0x00 }, 383 { 0x4a47, 0x7f }, 384 { 0x4a49, 0xf0 }, 385 { 0x4a4b, 0x30 }, 386 { 0x5000, 0x85 }, 387 { 0x5001, 0x80 }, 388 }; 389 390 static const struct reg_value ov7251_setting_vga_90fps[] = { 391 { 0x3005, 0x00 }, 392 { 0x3012, 0xc0 }, 393 { 0x3013, 0xd2 }, 394 { 0x3014, 0x04 }, 395 { 0x3016, 0x10 }, 396 { 0x3017, 0x00 }, 397 { 0x3018, 0x00 }, 398 { 0x301a, 0x00 }, 399 { 0x301b, 0x00 }, 400 { 0x301c, 0x00 }, 401 { 0x3023, 0x05 }, 402 { 0x3037, 0xf0 }, 403 { 0x3098, 0x04 }, /* pll2 pre divider */ 404 { 0x3099, 0x28 }, /* pll2 multiplier */ 405 { 0x309a, 0x05 }, /* pll2 sys divider */ 406 { 0x309b, 0x04 }, /* pll2 adc divider */ 407 { 0x309d, 0x00 }, /* pll2 divider */ 408 { 0x30b0, 0x0a }, /* pll1 pix divider */ 409 { 0x30b1, 0x01 }, /* pll1 divider */ 410 { 0x30b3, 0x64 }, /* pll1 multiplier */ 411 { 0x30b4, 0x03 }, /* pll1 pre divider */ 412 { 0x30b5, 0x05 }, /* pll1 mipi divider */ 413 { 0x3106, 0xda }, 414 { 0x3503, 0x07 }, 415 { 0x3509, 0x10 }, 416 { 0x3600, 0x1c }, 417 { 0x3602, 0x62 }, 418 { 0x3620, 0xb7 }, 419 { 0x3622, 0x04 }, 420 { 0x3626, 0x21 }, 421 { 0x3627, 0x30 }, 422 { 0x3630, 0x44 }, 423 { 0x3631, 0x35 }, 424 { 0x3634, 0x60 }, 425 { 0x3636, 0x00 }, 426 { 0x3662, 0x01 }, 427 { 0x3663, 0x70 }, 428 { 0x3664, 0x50 }, 429 { 0x3666, 0x0a }, 430 { 0x3669, 0x1a }, 431 { 0x366a, 0x00 }, 432 { 0x366b, 0x50 }, 433 { 0x3673, 0x01 }, 434 { 0x3674, 0xff }, 435 { 0x3675, 0x03 }, 436 { 0x3705, 0xc1 }, 437 { 0x3709, 0x40 }, 438 { 0x373c, 0x08 }, 439 { 0x3742, 0x00 }, 440 { 0x3757, 0xb3 }, 441 { 0x3788, 0x00 }, 442 { 0x37a8, 0x01 }, 443 { 0x37a9, 0xc0 }, 444 { 0x3800, 0x00 }, 445 { 0x3801, 0x04 }, 446 { 0x3802, 0x00 }, 447 { 0x3803, 0x04 }, 448 { 0x3804, 0x02 }, 449 { 0x3805, 0x8b }, 450 { 0x3806, 0x01 }, 451 { 0x3807, 0xeb }, 452 { 0x3808, 0x02 }, /* width high */ 453 { 0x3809, 0x80 }, /* width low */ 454 { 0x380a, 0x01 }, /* height high */ 455 { 0x380b, 0xe0 }, /* height low */ 456 { 0x380c, 0x03 }, /* total horiz timing high */ 457 { 0x380d, 0xa0 }, /* total horiz timing low */ 458 { 0x380e, 0x02 }, /* total vertical timing high */ 459 { 0x380f, 0x3c }, /* total vertical timing low */ 460 { 0x3810, 0x00 }, 461 { 0x3811, 0x04 }, 462 { 0x3812, 0x00 }, 463 { 0x3813, 0x05 }, 464 { 0x3814, 0x11 }, 465 { 0x3815, 0x11 }, 466 { 0x3820, 0x40 }, 467 { 0x3821, 0x00 }, 468 { 0x382f, 0x0e }, 469 { 0x3832, 0x00 }, 470 { 0x3833, 0x05 }, 471 { 0x3834, 0x00 }, 472 { 0x3835, 0x0c }, 473 { 0x3837, 0x00 }, 474 { 0x3b80, 0x00 }, 475 { 0x3b81, 0xa5 }, 476 { 0x3b82, 0x10 }, 477 { 0x3b83, 0x00 }, 478 { 0x3b84, 0x08 }, 479 { 0x3b85, 0x00 }, 480 { 0x3b86, 0x01 }, 481 { 0x3b87, 0x00 }, 482 { 0x3b88, 0x00 }, 483 { 0x3b89, 0x00 }, 484 { 0x3b8a, 0x00 }, 485 { 0x3b8b, 0x05 }, 486 { 0x3b8c, 0x00 }, 487 { 0x3b8d, 0x00 }, 488 { 0x3b8e, 0x00 }, 489 { 0x3b8f, 0x1a }, 490 { 0x3b94, 0x05 }, 491 { 0x3b95, 0xf2 }, 492 { 0x3b96, 0x40 }, 493 { 0x3c00, 0x89 }, 494 { 0x3c01, 0x63 }, 495 { 0x3c02, 0x01 }, 496 { 0x3c03, 0x00 }, 497 { 0x3c04, 0x00 }, 498 { 0x3c05, 0x03 }, 499 { 0x3c06, 0x00 }, 500 { 0x3c07, 0x06 }, 501 { 0x3c0c, 0x01 }, 502 { 0x3c0d, 0xd0 }, 503 { 0x3c0e, 0x02 }, 504 { 0x3c0f, 0x0a }, 505 { 0x4001, 0x42 }, 506 { 0x4004, 0x04 }, 507 { 0x4005, 0x00 }, 508 { 0x404e, 0x01 }, 509 { 0x4300, 0xff }, 510 { 0x4301, 0x00 }, 511 { 0x4315, 0x00 }, 512 { 0x4501, 0x48 }, 513 { 0x4600, 0x00 }, 514 { 0x4601, 0x4e }, 515 { 0x4801, 0x0f }, 516 { 0x4806, 0x0f }, 517 { 0x4819, 0xaa }, 518 { 0x4823, 0x3e }, 519 { 0x4837, 0x19 }, 520 { 0x4a0d, 0x00 }, 521 { 0x4a47, 0x7f }, 522 { 0x4a49, 0xf0 }, 523 { 0x4a4b, 0x30 }, 524 { 0x5000, 0x85 }, 525 { 0x5001, 0x80 }, 526 }; 527 528 static const s64 link_freq[] = { 529 [OV7251_LINK_FREQ_240_MHZ] = 240000000, 530 }; 531 532 static const s64 pixel_rates[] = { 533 [OV7251_LINK_FREQ_240_MHZ] = 48000000, 534 }; 535 536 static const struct ov7251_mode_info ov7251_mode_info_data[] = { 537 { 538 .width = 640, 539 .height = 480, 540 .data = ov7251_setting_vga_30fps, 541 .data_size = ARRAY_SIZE(ov7251_setting_vga_30fps), 542 .exposure_max = 1704, 543 .exposure_def = 504, 544 .timeperframe = { 545 .numerator = 100, 546 .denominator = 3000 547 } 548 }, 549 { 550 .width = 640, 551 .height = 480, 552 .data = ov7251_setting_vga_60fps, 553 .data_size = ARRAY_SIZE(ov7251_setting_vga_60fps), 554 .exposure_max = 840, 555 .exposure_def = 504, 556 .timeperframe = { 557 .numerator = 100, 558 .denominator = 6014 559 } 560 }, 561 { 562 .width = 640, 563 .height = 480, 564 .data = ov7251_setting_vga_90fps, 565 .data_size = ARRAY_SIZE(ov7251_setting_vga_90fps), 566 .exposure_max = 552, 567 .exposure_def = 504, 568 .timeperframe = { 569 .numerator = 100, 570 .denominator = 9043 571 } 572 }, 573 }; 574 575 static int ov7251_regulators_enable(struct ov7251 *ov7251) 576 { 577 int ret; 578 579 /* OV7251 power up sequence requires core regulator 580 * to be enabled not earlier than io regulator 581 */ 582 583 ret = regulator_enable(ov7251->io_regulator); 584 if (ret < 0) { 585 dev_err(ov7251->dev, "set io voltage failed\n"); 586 return ret; 587 } 588 589 ret = regulator_enable(ov7251->analog_regulator); 590 if (ret) { 591 dev_err(ov7251->dev, "set analog voltage failed\n"); 592 goto err_disable_io; 593 } 594 595 ret = regulator_enable(ov7251->core_regulator); 596 if (ret) { 597 dev_err(ov7251->dev, "set core voltage failed\n"); 598 goto err_disable_analog; 599 } 600 601 return 0; 602 603 err_disable_analog: 604 regulator_disable(ov7251->analog_regulator); 605 606 err_disable_io: 607 regulator_disable(ov7251->io_regulator); 608 609 return ret; 610 } 611 612 static void ov7251_regulators_disable(struct ov7251 *ov7251) 613 { 614 int ret; 615 616 ret = regulator_disable(ov7251->core_regulator); 617 if (ret < 0) 618 dev_err(ov7251->dev, "core regulator disable failed\n"); 619 620 ret = regulator_disable(ov7251->analog_regulator); 621 if (ret < 0) 622 dev_err(ov7251->dev, "analog regulator disable failed\n"); 623 624 ret = regulator_disable(ov7251->io_regulator); 625 if (ret < 0) 626 dev_err(ov7251->dev, "io regulator disable failed\n"); 627 } 628 629 static int ov7251_write_reg(struct ov7251 *ov7251, u16 reg, u8 val) 630 { 631 u8 regbuf[3]; 632 int ret; 633 634 regbuf[0] = reg >> 8; 635 regbuf[1] = reg & 0xff; 636 regbuf[2] = val; 637 638 ret = i2c_master_send(ov7251->i2c_client, regbuf, 3); 639 if (ret < 0) { 640 dev_err(ov7251->dev, "%s: write reg error %d: reg=%x, val=%x\n", 641 __func__, ret, reg, val); 642 return ret; 643 } 644 645 return 0; 646 } 647 648 static int ov7251_write_seq_regs(struct ov7251 *ov7251, u16 reg, u8 *val, 649 u8 num) 650 { 651 u8 regbuf[5]; 652 u8 nregbuf = sizeof(reg) + num * sizeof(*val); 653 int ret = 0; 654 655 if (nregbuf > sizeof(regbuf)) 656 return -EINVAL; 657 658 regbuf[0] = reg >> 8; 659 regbuf[1] = reg & 0xff; 660 661 memcpy(regbuf + 2, val, num); 662 663 ret = i2c_master_send(ov7251->i2c_client, regbuf, nregbuf); 664 if (ret < 0) { 665 dev_err(ov7251->dev, 666 "%s: write seq regs error %d: first reg=%x\n", 667 __func__, ret, reg); 668 return ret; 669 } 670 671 return 0; 672 } 673 674 static int ov7251_read_reg(struct ov7251 *ov7251, u16 reg, u8 *val) 675 { 676 u8 regbuf[2]; 677 int ret; 678 679 regbuf[0] = reg >> 8; 680 regbuf[1] = reg & 0xff; 681 682 ret = i2c_master_send(ov7251->i2c_client, regbuf, 2); 683 if (ret < 0) { 684 dev_err(ov7251->dev, "%s: write reg error %d: reg=%x\n", 685 __func__, ret, reg); 686 return ret; 687 } 688 689 ret = i2c_master_recv(ov7251->i2c_client, val, 1); 690 if (ret < 0) { 691 dev_err(ov7251->dev, "%s: read reg error %d: reg=%x\n", 692 __func__, ret, reg); 693 return ret; 694 } 695 696 return 0; 697 } 698 699 static int ov7251_set_exposure(struct ov7251 *ov7251, s32 exposure) 700 { 701 u16 reg; 702 u8 val[3]; 703 704 reg = OV7251_AEC_EXPO_0; 705 val[0] = (exposure & 0xf000) >> 12; /* goes to OV7251_AEC_EXPO_0 */ 706 val[1] = (exposure & 0x0ff0) >> 4; /* goes to OV7251_AEC_EXPO_1 */ 707 val[2] = (exposure & 0x000f) << 4; /* goes to OV7251_AEC_EXPO_2 */ 708 709 return ov7251_write_seq_regs(ov7251, reg, val, 3); 710 } 711 712 static int ov7251_set_gain(struct ov7251 *ov7251, s32 gain) 713 { 714 u16 reg; 715 u8 val[2]; 716 717 reg = OV7251_AEC_AGC_ADJ_0; 718 val[0] = (gain & 0x0300) >> 8; /* goes to OV7251_AEC_AGC_ADJ_0 */ 719 val[1] = gain & 0xff; /* goes to OV7251_AEC_AGC_ADJ_1 */ 720 721 return ov7251_write_seq_regs(ov7251, reg, val, 2); 722 } 723 724 static int ov7251_set_register_array(struct ov7251 *ov7251, 725 const struct reg_value *settings, 726 unsigned int num_settings) 727 { 728 unsigned int i; 729 int ret; 730 731 for (i = 0; i < num_settings; ++i, ++settings) { 732 ret = ov7251_write_reg(ov7251, settings->reg, settings->val); 733 if (ret < 0) 734 return ret; 735 } 736 737 return 0; 738 } 739 740 static int ov7251_set_power_on(struct ov7251 *ov7251) 741 { 742 int ret; 743 u32 wait_us; 744 745 ret = ov7251_regulators_enable(ov7251); 746 if (ret < 0) 747 return ret; 748 749 ret = clk_prepare_enable(ov7251->xclk); 750 if (ret < 0) { 751 dev_err(ov7251->dev, "clk prepare enable failed\n"); 752 ov7251_regulators_disable(ov7251); 753 return ret; 754 } 755 756 gpiod_set_value_cansleep(ov7251->enable_gpio, 1); 757 758 /* wait at least 65536 external clock cycles */ 759 wait_us = DIV_ROUND_UP(65536 * 1000, 760 DIV_ROUND_UP(ov7251->xclk_freq, 1000)); 761 usleep_range(wait_us, wait_us + 1000); 762 763 return 0; 764 } 765 766 static void ov7251_set_power_off(struct ov7251 *ov7251) 767 { 768 clk_disable_unprepare(ov7251->xclk); 769 gpiod_set_value_cansleep(ov7251->enable_gpio, 0); 770 ov7251_regulators_disable(ov7251); 771 } 772 773 static int ov7251_s_power(struct v4l2_subdev *sd, int on) 774 { 775 struct ov7251 *ov7251 = to_ov7251(sd); 776 int ret = 0; 777 778 mutex_lock(&ov7251->lock); 779 780 /* If the power state is not modified - no work to do. */ 781 if (ov7251->power_on == !!on) 782 goto exit; 783 784 if (on) { 785 ret = ov7251_set_power_on(ov7251); 786 if (ret < 0) 787 goto exit; 788 789 ret = ov7251_set_register_array(ov7251, 790 ov7251_global_init_setting, 791 ARRAY_SIZE(ov7251_global_init_setting)); 792 if (ret < 0) { 793 dev_err(ov7251->dev, "could not set init registers\n"); 794 ov7251_set_power_off(ov7251); 795 goto exit; 796 } 797 798 ov7251->power_on = true; 799 } else { 800 ov7251_set_power_off(ov7251); 801 ov7251->power_on = false; 802 } 803 804 exit: 805 mutex_unlock(&ov7251->lock); 806 807 return ret; 808 } 809 810 static int ov7251_set_hflip(struct ov7251 *ov7251, s32 value) 811 { 812 u8 val = ov7251->timing_format2; 813 int ret; 814 815 if (value) 816 val |= OV7251_TIMING_FORMAT2_MIRROR; 817 else 818 val &= ~OV7251_TIMING_FORMAT2_MIRROR; 819 820 ret = ov7251_write_reg(ov7251, OV7251_TIMING_FORMAT2, val); 821 if (!ret) 822 ov7251->timing_format2 = val; 823 824 return ret; 825 } 826 827 static int ov7251_set_vflip(struct ov7251 *ov7251, s32 value) 828 { 829 u8 val = ov7251->timing_format1; 830 int ret; 831 832 if (value) 833 val |= OV7251_TIMING_FORMAT1_VFLIP; 834 else 835 val &= ~OV7251_TIMING_FORMAT1_VFLIP; 836 837 ret = ov7251_write_reg(ov7251, OV7251_TIMING_FORMAT1, val); 838 if (!ret) 839 ov7251->timing_format1 = val; 840 841 return ret; 842 } 843 844 static int ov7251_set_test_pattern(struct ov7251 *ov7251, s32 value) 845 { 846 u8 val = ov7251->pre_isp_00; 847 int ret; 848 849 if (value) 850 val |= OV7251_PRE_ISP_00_TEST_PATTERN; 851 else 852 val &= ~OV7251_PRE_ISP_00_TEST_PATTERN; 853 854 ret = ov7251_write_reg(ov7251, OV7251_PRE_ISP_00, val); 855 if (!ret) 856 ov7251->pre_isp_00 = val; 857 858 return ret; 859 } 860 861 static const char * const ov7251_test_pattern_menu[] = { 862 "Disabled", 863 "Vertical Pattern Bars", 864 }; 865 866 static int ov7251_s_ctrl(struct v4l2_ctrl *ctrl) 867 { 868 struct ov7251 *ov7251 = container_of(ctrl->handler, 869 struct ov7251, ctrls); 870 int ret; 871 872 /* v4l2_ctrl_lock() locks our mutex */ 873 874 if (!ov7251->power_on) 875 return 0; 876 877 switch (ctrl->id) { 878 case V4L2_CID_EXPOSURE: 879 ret = ov7251_set_exposure(ov7251, ctrl->val); 880 break; 881 case V4L2_CID_GAIN: 882 ret = ov7251_set_gain(ov7251, ctrl->val); 883 break; 884 case V4L2_CID_TEST_PATTERN: 885 ret = ov7251_set_test_pattern(ov7251, ctrl->val); 886 break; 887 case V4L2_CID_HFLIP: 888 ret = ov7251_set_hflip(ov7251, ctrl->val); 889 break; 890 case V4L2_CID_VFLIP: 891 ret = ov7251_set_vflip(ov7251, ctrl->val); 892 break; 893 default: 894 ret = -EINVAL; 895 break; 896 } 897 898 return ret; 899 } 900 901 static const struct v4l2_ctrl_ops ov7251_ctrl_ops = { 902 .s_ctrl = ov7251_s_ctrl, 903 }; 904 905 static int ov7251_enum_mbus_code(struct v4l2_subdev *sd, 906 struct v4l2_subdev_state *sd_state, 907 struct v4l2_subdev_mbus_code_enum *code) 908 { 909 if (code->index > 0) 910 return -EINVAL; 911 912 code->code = MEDIA_BUS_FMT_Y10_1X10; 913 914 return 0; 915 } 916 917 static int ov7251_enum_frame_size(struct v4l2_subdev *subdev, 918 struct v4l2_subdev_state *sd_state, 919 struct v4l2_subdev_frame_size_enum *fse) 920 { 921 if (fse->code != MEDIA_BUS_FMT_Y10_1X10) 922 return -EINVAL; 923 924 if (fse->index >= ARRAY_SIZE(ov7251_mode_info_data)) 925 return -EINVAL; 926 927 fse->min_width = ov7251_mode_info_data[fse->index].width; 928 fse->max_width = ov7251_mode_info_data[fse->index].width; 929 fse->min_height = ov7251_mode_info_data[fse->index].height; 930 fse->max_height = ov7251_mode_info_data[fse->index].height; 931 932 return 0; 933 } 934 935 static int ov7251_enum_frame_ival(struct v4l2_subdev *subdev, 936 struct v4l2_subdev_state *sd_state, 937 struct v4l2_subdev_frame_interval_enum *fie) 938 { 939 unsigned int index = fie->index; 940 unsigned int i; 941 942 for (i = 0; i < ARRAY_SIZE(ov7251_mode_info_data); i++) { 943 if (fie->width != ov7251_mode_info_data[i].width || 944 fie->height != ov7251_mode_info_data[i].height) 945 continue; 946 947 if (index-- == 0) { 948 fie->interval = ov7251_mode_info_data[i].timeperframe; 949 return 0; 950 } 951 } 952 953 return -EINVAL; 954 } 955 956 static struct v4l2_mbus_framefmt * 957 __ov7251_get_pad_format(struct ov7251 *ov7251, 958 struct v4l2_subdev_state *sd_state, 959 unsigned int pad, 960 enum v4l2_subdev_format_whence which) 961 { 962 switch (which) { 963 case V4L2_SUBDEV_FORMAT_TRY: 964 return v4l2_subdev_get_try_format(&ov7251->sd, sd_state, pad); 965 case V4L2_SUBDEV_FORMAT_ACTIVE: 966 return &ov7251->fmt; 967 default: 968 return NULL; 969 } 970 } 971 972 static int ov7251_get_format(struct v4l2_subdev *sd, 973 struct v4l2_subdev_state *sd_state, 974 struct v4l2_subdev_format *format) 975 { 976 struct ov7251 *ov7251 = to_ov7251(sd); 977 978 mutex_lock(&ov7251->lock); 979 format->format = *__ov7251_get_pad_format(ov7251, sd_state, 980 format->pad, 981 format->which); 982 mutex_unlock(&ov7251->lock); 983 984 return 0; 985 } 986 987 static struct v4l2_rect * 988 __ov7251_get_pad_crop(struct ov7251 *ov7251, 989 struct v4l2_subdev_state *sd_state, 990 unsigned int pad, enum v4l2_subdev_format_whence which) 991 { 992 switch (which) { 993 case V4L2_SUBDEV_FORMAT_TRY: 994 return v4l2_subdev_get_try_crop(&ov7251->sd, sd_state, pad); 995 case V4L2_SUBDEV_FORMAT_ACTIVE: 996 return &ov7251->crop; 997 default: 998 return NULL; 999 } 1000 } 1001 1002 static inline u32 avg_fps(const struct v4l2_fract *t) 1003 { 1004 return (t->denominator + (t->numerator >> 1)) / t->numerator; 1005 } 1006 1007 static const struct ov7251_mode_info * 1008 ov7251_find_mode_by_ival(struct ov7251 *ov7251, struct v4l2_fract *timeperframe) 1009 { 1010 const struct ov7251_mode_info *mode = ov7251->current_mode; 1011 unsigned int fps_req = avg_fps(timeperframe); 1012 unsigned int max_dist_match = (unsigned int) -1; 1013 unsigned int i, n = 0; 1014 1015 for (i = 0; i < ARRAY_SIZE(ov7251_mode_info_data); i++) { 1016 unsigned int dist; 1017 unsigned int fps_tmp; 1018 1019 if (mode->width != ov7251_mode_info_data[i].width || 1020 mode->height != ov7251_mode_info_data[i].height) 1021 continue; 1022 1023 fps_tmp = avg_fps(&ov7251_mode_info_data[i].timeperframe); 1024 1025 dist = abs(fps_req - fps_tmp); 1026 1027 if (dist < max_dist_match) { 1028 n = i; 1029 max_dist_match = dist; 1030 } 1031 } 1032 1033 return &ov7251_mode_info_data[n]; 1034 } 1035 1036 static int ov7251_set_format(struct v4l2_subdev *sd, 1037 struct v4l2_subdev_state *sd_state, 1038 struct v4l2_subdev_format *format) 1039 { 1040 struct ov7251 *ov7251 = to_ov7251(sd); 1041 struct v4l2_mbus_framefmt *__format; 1042 struct v4l2_rect *__crop; 1043 const struct ov7251_mode_info *new_mode; 1044 int ret = 0; 1045 1046 mutex_lock(&ov7251->lock); 1047 1048 __crop = __ov7251_get_pad_crop(ov7251, sd_state, format->pad, 1049 format->which); 1050 1051 new_mode = v4l2_find_nearest_size(ov7251_mode_info_data, 1052 ARRAY_SIZE(ov7251_mode_info_data), 1053 width, height, 1054 format->format.width, format->format.height); 1055 1056 __crop->width = new_mode->width; 1057 __crop->height = new_mode->height; 1058 1059 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 1060 ret = __v4l2_ctrl_modify_range(ov7251->exposure, 1061 1, new_mode->exposure_max, 1062 1, new_mode->exposure_def); 1063 if (ret < 0) 1064 goto exit; 1065 1066 ret = __v4l2_ctrl_s_ctrl(ov7251->exposure, 1067 new_mode->exposure_def); 1068 if (ret < 0) 1069 goto exit; 1070 1071 ret = __v4l2_ctrl_s_ctrl(ov7251->gain, 16); 1072 if (ret < 0) 1073 goto exit; 1074 1075 ov7251->current_mode = new_mode; 1076 } 1077 1078 __format = __ov7251_get_pad_format(ov7251, sd_state, format->pad, 1079 format->which); 1080 __format->width = __crop->width; 1081 __format->height = __crop->height; 1082 __format->code = MEDIA_BUS_FMT_Y10_1X10; 1083 __format->field = V4L2_FIELD_NONE; 1084 __format->colorspace = V4L2_COLORSPACE_SRGB; 1085 __format->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(__format->colorspace); 1086 __format->quantization = V4L2_MAP_QUANTIZATION_DEFAULT(true, 1087 __format->colorspace, __format->ycbcr_enc); 1088 __format->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(__format->colorspace); 1089 1090 format->format = *__format; 1091 1092 exit: 1093 mutex_unlock(&ov7251->lock); 1094 1095 return ret; 1096 } 1097 1098 static int ov7251_entity_init_cfg(struct v4l2_subdev *subdev, 1099 struct v4l2_subdev_state *sd_state) 1100 { 1101 struct v4l2_subdev_format fmt = { 1102 .which = sd_state ? V4L2_SUBDEV_FORMAT_TRY 1103 : V4L2_SUBDEV_FORMAT_ACTIVE, 1104 .format = { 1105 .width = 640, 1106 .height = 480 1107 } 1108 }; 1109 1110 ov7251_set_format(subdev, sd_state, &fmt); 1111 1112 return 0; 1113 } 1114 1115 static int ov7251_get_selection(struct v4l2_subdev *sd, 1116 struct v4l2_subdev_state *sd_state, 1117 struct v4l2_subdev_selection *sel) 1118 { 1119 struct ov7251 *ov7251 = to_ov7251(sd); 1120 1121 if (sel->target != V4L2_SEL_TGT_CROP) 1122 return -EINVAL; 1123 1124 mutex_lock(&ov7251->lock); 1125 sel->r = *__ov7251_get_pad_crop(ov7251, sd_state, sel->pad, 1126 sel->which); 1127 mutex_unlock(&ov7251->lock); 1128 1129 return 0; 1130 } 1131 1132 static int ov7251_s_stream(struct v4l2_subdev *subdev, int enable) 1133 { 1134 struct ov7251 *ov7251 = to_ov7251(subdev); 1135 int ret; 1136 1137 mutex_lock(&ov7251->lock); 1138 1139 if (enable) { 1140 ret = ov7251_set_register_array(ov7251, 1141 ov7251->current_mode->data, 1142 ov7251->current_mode->data_size); 1143 if (ret < 0) { 1144 dev_err(ov7251->dev, "could not set mode %dx%d\n", 1145 ov7251->current_mode->width, 1146 ov7251->current_mode->height); 1147 goto exit; 1148 } 1149 ret = __v4l2_ctrl_handler_setup(&ov7251->ctrls); 1150 if (ret < 0) { 1151 dev_err(ov7251->dev, "could not sync v4l2 controls\n"); 1152 goto exit; 1153 } 1154 ret = ov7251_write_reg(ov7251, OV7251_SC_MODE_SELECT, 1155 OV7251_SC_MODE_SELECT_STREAMING); 1156 } else { 1157 ret = ov7251_write_reg(ov7251, OV7251_SC_MODE_SELECT, 1158 OV7251_SC_MODE_SELECT_SW_STANDBY); 1159 } 1160 1161 exit: 1162 mutex_unlock(&ov7251->lock); 1163 1164 return ret; 1165 } 1166 1167 static int ov7251_get_frame_interval(struct v4l2_subdev *subdev, 1168 struct v4l2_subdev_frame_interval *fi) 1169 { 1170 struct ov7251 *ov7251 = to_ov7251(subdev); 1171 1172 mutex_lock(&ov7251->lock); 1173 fi->interval = ov7251->current_mode->timeperframe; 1174 mutex_unlock(&ov7251->lock); 1175 1176 return 0; 1177 } 1178 1179 static int ov7251_set_frame_interval(struct v4l2_subdev *subdev, 1180 struct v4l2_subdev_frame_interval *fi) 1181 { 1182 struct ov7251 *ov7251 = to_ov7251(subdev); 1183 const struct ov7251_mode_info *new_mode; 1184 int ret = 0; 1185 1186 mutex_lock(&ov7251->lock); 1187 new_mode = ov7251_find_mode_by_ival(ov7251, &fi->interval); 1188 1189 if (new_mode != ov7251->current_mode) { 1190 ret = __v4l2_ctrl_modify_range(ov7251->exposure, 1191 1, new_mode->exposure_max, 1192 1, new_mode->exposure_def); 1193 if (ret < 0) 1194 goto exit; 1195 1196 ret = __v4l2_ctrl_s_ctrl(ov7251->exposure, 1197 new_mode->exposure_def); 1198 if (ret < 0) 1199 goto exit; 1200 1201 ret = __v4l2_ctrl_s_ctrl(ov7251->gain, 16); 1202 if (ret < 0) 1203 goto exit; 1204 1205 ov7251->current_mode = new_mode; 1206 } 1207 1208 fi->interval = ov7251->current_mode->timeperframe; 1209 1210 exit: 1211 mutex_unlock(&ov7251->lock); 1212 1213 return ret; 1214 } 1215 1216 static const struct v4l2_subdev_core_ops ov7251_core_ops = { 1217 .s_power = ov7251_s_power, 1218 }; 1219 1220 static const struct v4l2_subdev_video_ops ov7251_video_ops = { 1221 .s_stream = ov7251_s_stream, 1222 .g_frame_interval = ov7251_get_frame_interval, 1223 .s_frame_interval = ov7251_set_frame_interval, 1224 }; 1225 1226 static const struct v4l2_subdev_pad_ops ov7251_subdev_pad_ops = { 1227 .init_cfg = ov7251_entity_init_cfg, 1228 .enum_mbus_code = ov7251_enum_mbus_code, 1229 .enum_frame_size = ov7251_enum_frame_size, 1230 .enum_frame_interval = ov7251_enum_frame_ival, 1231 .get_fmt = ov7251_get_format, 1232 .set_fmt = ov7251_set_format, 1233 .get_selection = ov7251_get_selection, 1234 }; 1235 1236 static const struct v4l2_subdev_ops ov7251_subdev_ops = { 1237 .core = &ov7251_core_ops, 1238 .video = &ov7251_video_ops, 1239 .pad = &ov7251_subdev_pad_ops, 1240 }; 1241 1242 static int ov7251_check_hwcfg(struct ov7251 *ov7251) 1243 { 1244 struct fwnode_handle *fwnode = dev_fwnode(ov7251->dev); 1245 struct v4l2_fwnode_endpoint bus_cfg = { 1246 .bus_type = V4L2_MBUS_CSI2_DPHY, 1247 }; 1248 struct fwnode_handle *endpoint; 1249 unsigned int i, j; 1250 int ret; 1251 1252 endpoint = fwnode_graph_get_next_endpoint(fwnode, NULL); 1253 if (!endpoint) 1254 return -EPROBE_DEFER; /* could be provided by cio2-bridge */ 1255 1256 ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &bus_cfg); 1257 fwnode_handle_put(endpoint); 1258 if (ret) 1259 return dev_err_probe(ov7251->dev, ret, 1260 "parsing endpoint node failed\n"); 1261 1262 if (!bus_cfg.nr_of_link_frequencies) { 1263 ret = dev_err_probe(ov7251->dev, -EINVAL, 1264 "no link frequencies defined\n"); 1265 goto out_free_bus_cfg; 1266 } 1267 1268 for (i = 0; i < bus_cfg.nr_of_link_frequencies; i++) { 1269 for (j = 0; j < ARRAY_SIZE(link_freq); j++) 1270 if (bus_cfg.link_frequencies[i] == link_freq[j]) 1271 break; 1272 1273 if (j < ARRAY_SIZE(link_freq)) 1274 break; 1275 } 1276 1277 if (i == bus_cfg.nr_of_link_frequencies) { 1278 ret = dev_err_probe(ov7251->dev, -EINVAL, 1279 "no supported link freq found\n"); 1280 goto out_free_bus_cfg; 1281 } 1282 1283 ov7251->link_freq_idx = i; 1284 1285 out_free_bus_cfg: 1286 v4l2_fwnode_endpoint_free(&bus_cfg); 1287 1288 return ret; 1289 } 1290 1291 static int ov7251_probe(struct i2c_client *client) 1292 { 1293 struct device *dev = &client->dev; 1294 struct ov7251 *ov7251; 1295 u8 chip_id_high, chip_id_low, chip_rev; 1296 s64 pixel_rate; 1297 int ret; 1298 1299 ov7251 = devm_kzalloc(dev, sizeof(struct ov7251), GFP_KERNEL); 1300 if (!ov7251) 1301 return -ENOMEM; 1302 1303 ov7251->i2c_client = client; 1304 ov7251->dev = dev; 1305 1306 ret = ov7251_check_hwcfg(ov7251); 1307 if (ret) 1308 return ret; 1309 1310 /* get system clock (xclk) */ 1311 ov7251->xclk = devm_clk_get(dev, "xclk"); 1312 if (IS_ERR(ov7251->xclk)) { 1313 dev_err(dev, "could not get xclk"); 1314 return PTR_ERR(ov7251->xclk); 1315 } 1316 1317 ret = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency", 1318 &ov7251->xclk_freq); 1319 if (ret) { 1320 dev_err(dev, "could not get xclk frequency\n"); 1321 return ret; 1322 } 1323 1324 /* external clock must be 24MHz, allow 1% tolerance */ 1325 if (ov7251->xclk_freq < 23760000 || ov7251->xclk_freq > 24240000) { 1326 dev_err(dev, "external clock frequency %u is not supported\n", 1327 ov7251->xclk_freq); 1328 return -EINVAL; 1329 } 1330 1331 ret = clk_set_rate(ov7251->xclk, ov7251->xclk_freq); 1332 if (ret) { 1333 dev_err(dev, "could not set xclk frequency\n"); 1334 return ret; 1335 } 1336 1337 ov7251->io_regulator = devm_regulator_get(dev, "vdddo"); 1338 if (IS_ERR(ov7251->io_regulator)) { 1339 dev_err(dev, "cannot get io regulator\n"); 1340 return PTR_ERR(ov7251->io_regulator); 1341 } 1342 1343 ov7251->core_regulator = devm_regulator_get(dev, "vddd"); 1344 if (IS_ERR(ov7251->core_regulator)) { 1345 dev_err(dev, "cannot get core regulator\n"); 1346 return PTR_ERR(ov7251->core_regulator); 1347 } 1348 1349 ov7251->analog_regulator = devm_regulator_get(dev, "vdda"); 1350 if (IS_ERR(ov7251->analog_regulator)) { 1351 dev_err(dev, "cannot get analog regulator\n"); 1352 return PTR_ERR(ov7251->analog_regulator); 1353 } 1354 1355 ov7251->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_HIGH); 1356 if (IS_ERR(ov7251->enable_gpio)) { 1357 dev_err(dev, "cannot get enable gpio\n"); 1358 return PTR_ERR(ov7251->enable_gpio); 1359 } 1360 1361 mutex_init(&ov7251->lock); 1362 1363 v4l2_ctrl_handler_init(&ov7251->ctrls, 7); 1364 ov7251->ctrls.lock = &ov7251->lock; 1365 1366 v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops, 1367 V4L2_CID_HFLIP, 0, 1, 1, 0); 1368 v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops, 1369 V4L2_CID_VFLIP, 0, 1, 1, 0); 1370 ov7251->exposure = v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops, 1371 V4L2_CID_EXPOSURE, 1, 32, 1, 32); 1372 ov7251->gain = v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops, 1373 V4L2_CID_GAIN, 16, 1023, 1, 16); 1374 v4l2_ctrl_new_std_menu_items(&ov7251->ctrls, &ov7251_ctrl_ops, 1375 V4L2_CID_TEST_PATTERN, 1376 ARRAY_SIZE(ov7251_test_pattern_menu) - 1, 1377 0, 0, ov7251_test_pattern_menu); 1378 1379 pixel_rate = pixel_rates[ov7251->link_freq_idx]; 1380 ov7251->pixel_clock = v4l2_ctrl_new_std(&ov7251->ctrls, 1381 &ov7251_ctrl_ops, 1382 V4L2_CID_PIXEL_RATE, 1383 pixel_rate, INT_MAX, 1384 pixel_rate, pixel_rate); 1385 ov7251->link_freq = v4l2_ctrl_new_int_menu(&ov7251->ctrls, 1386 &ov7251_ctrl_ops, 1387 V4L2_CID_LINK_FREQ, 1388 ARRAY_SIZE(link_freq) - 1, 1389 ov7251->link_freq_idx, 1390 link_freq); 1391 if (ov7251->link_freq) 1392 ov7251->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1393 if (ov7251->pixel_clock) 1394 ov7251->pixel_clock->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1395 1396 ov7251->sd.ctrl_handler = &ov7251->ctrls; 1397 1398 if (ov7251->ctrls.error) { 1399 dev_err(dev, "%s: control initialization error %d\n", 1400 __func__, ov7251->ctrls.error); 1401 ret = ov7251->ctrls.error; 1402 goto free_ctrl; 1403 } 1404 1405 v4l2_i2c_subdev_init(&ov7251->sd, client, &ov7251_subdev_ops); 1406 ov7251->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1407 ov7251->pad.flags = MEDIA_PAD_FL_SOURCE; 1408 ov7251->sd.dev = &client->dev; 1409 ov7251->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1410 1411 ret = media_entity_pads_init(&ov7251->sd.entity, 1, &ov7251->pad); 1412 if (ret < 0) { 1413 dev_err(dev, "could not register media entity\n"); 1414 goto free_ctrl; 1415 } 1416 1417 ret = ov7251_s_power(&ov7251->sd, true); 1418 if (ret < 0) { 1419 dev_err(dev, "could not power up OV7251\n"); 1420 goto free_entity; 1421 } 1422 1423 ret = ov7251_read_reg(ov7251, OV7251_CHIP_ID_HIGH, &chip_id_high); 1424 if (ret < 0 || chip_id_high != OV7251_CHIP_ID_HIGH_BYTE) { 1425 dev_err(dev, "could not read ID high\n"); 1426 ret = -ENODEV; 1427 goto power_down; 1428 } 1429 ret = ov7251_read_reg(ov7251, OV7251_CHIP_ID_LOW, &chip_id_low); 1430 if (ret < 0 || chip_id_low != OV7251_CHIP_ID_LOW_BYTE) { 1431 dev_err(dev, "could not read ID low\n"); 1432 ret = -ENODEV; 1433 goto power_down; 1434 } 1435 1436 ret = ov7251_read_reg(ov7251, OV7251_SC_GP_IO_IN1, &chip_rev); 1437 if (ret < 0) { 1438 dev_err(dev, "could not read revision\n"); 1439 ret = -ENODEV; 1440 goto power_down; 1441 } 1442 chip_rev >>= 4; 1443 1444 dev_info(dev, "OV7251 revision %x (%s) detected at address 0x%02x\n", 1445 chip_rev, 1446 chip_rev == 0x4 ? "1A / 1B" : 1447 chip_rev == 0x5 ? "1C / 1D" : 1448 chip_rev == 0x6 ? "1E" : 1449 chip_rev == 0x7 ? "1F" : "unknown", 1450 client->addr); 1451 1452 ret = ov7251_read_reg(ov7251, OV7251_PRE_ISP_00, 1453 &ov7251->pre_isp_00); 1454 if (ret < 0) { 1455 dev_err(dev, "could not read test pattern value\n"); 1456 ret = -ENODEV; 1457 goto power_down; 1458 } 1459 1460 ret = ov7251_read_reg(ov7251, OV7251_TIMING_FORMAT1, 1461 &ov7251->timing_format1); 1462 if (ret < 0) { 1463 dev_err(dev, "could not read vflip value\n"); 1464 ret = -ENODEV; 1465 goto power_down; 1466 } 1467 1468 ret = ov7251_read_reg(ov7251, OV7251_TIMING_FORMAT2, 1469 &ov7251->timing_format2); 1470 if (ret < 0) { 1471 dev_err(dev, "could not read hflip value\n"); 1472 ret = -ENODEV; 1473 goto power_down; 1474 } 1475 1476 ov7251_s_power(&ov7251->sd, false); 1477 1478 ret = v4l2_async_register_subdev(&ov7251->sd); 1479 if (ret < 0) { 1480 dev_err(dev, "could not register v4l2 device\n"); 1481 goto free_entity; 1482 } 1483 1484 ov7251_entity_init_cfg(&ov7251->sd, NULL); 1485 1486 return 0; 1487 1488 power_down: 1489 ov7251_s_power(&ov7251->sd, false); 1490 free_entity: 1491 media_entity_cleanup(&ov7251->sd.entity); 1492 free_ctrl: 1493 v4l2_ctrl_handler_free(&ov7251->ctrls); 1494 mutex_destroy(&ov7251->lock); 1495 1496 return ret; 1497 } 1498 1499 static int ov7251_remove(struct i2c_client *client) 1500 { 1501 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1502 struct ov7251 *ov7251 = to_ov7251(sd); 1503 1504 v4l2_async_unregister_subdev(&ov7251->sd); 1505 media_entity_cleanup(&ov7251->sd.entity); 1506 v4l2_ctrl_handler_free(&ov7251->ctrls); 1507 mutex_destroy(&ov7251->lock); 1508 1509 return 0; 1510 } 1511 1512 static const struct of_device_id ov7251_of_match[] = { 1513 { .compatible = "ovti,ov7251" }, 1514 { /* sentinel */ } 1515 }; 1516 MODULE_DEVICE_TABLE(of, ov7251_of_match); 1517 1518 static const struct acpi_device_id ov7251_acpi_match[] = { 1519 { "INT347E" }, 1520 { } 1521 }; 1522 MODULE_DEVICE_TABLE(acpi, ov7251_acpi_match); 1523 1524 static struct i2c_driver ov7251_i2c_driver = { 1525 .driver = { 1526 .of_match_table = ov7251_of_match, 1527 .acpi_match_table = ov7251_acpi_match, 1528 .name = "ov7251", 1529 }, 1530 .probe_new = ov7251_probe, 1531 .remove = ov7251_remove, 1532 }; 1533 1534 module_i2c_driver(ov7251_i2c_driver); 1535 1536 MODULE_DESCRIPTION("Omnivision OV7251 Camera Driver"); 1537 MODULE_AUTHOR("Todor Tomov <todor.tomov@linaro.org>"); 1538 MODULE_LICENSE("GPL v2"); 1539