1d30bb512STodor Tomov // SPDX-License-Identifier: GPL-2.0 2d30bb512STodor Tomov /* 3d30bb512STodor Tomov * Driver for the OV7251 camera sensor. 4d30bb512STodor Tomov * 5d30bb512STodor Tomov * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. 6d30bb512STodor Tomov * Copyright (c) 2017-2018, Linaro Ltd. 7d30bb512STodor Tomov */ 8d30bb512STodor Tomov 9d30bb512STodor Tomov #include <linux/bitops.h> 10d30bb512STodor Tomov #include <linux/clk.h> 11d30bb512STodor Tomov #include <linux/delay.h> 12d30bb512STodor Tomov #include <linux/device.h> 13d30bb512STodor Tomov #include <linux/gpio/consumer.h> 14d30bb512STodor Tomov #include <linux/i2c.h> 15d30bb512STodor Tomov #include <linux/init.h> 16d30bb512STodor Tomov #include <linux/module.h> 176766cff6SDaniel Scally #include <linux/mod_devicetable.h> 18207f4162SDaniel Scally #include <linux/pm_runtime.h> 19d30bb512STodor Tomov #include <linux/regulator/consumer.h> 20d30bb512STodor Tomov #include <linux/slab.h> 21d30bb512STodor Tomov #include <linux/types.h> 22d30bb512STodor Tomov #include <media/v4l2-ctrls.h> 23d30bb512STodor Tomov #include <media/v4l2-fwnode.h> 24d30bb512STodor Tomov #include <media/v4l2-subdev.h> 25d30bb512STodor Tomov 26d30bb512STodor Tomov #define OV7251_SC_MODE_SELECT 0x0100 27d30bb512STodor Tomov #define OV7251_SC_MODE_SELECT_SW_STANDBY 0x0 28d30bb512STodor Tomov #define OV7251_SC_MODE_SELECT_STREAMING 0x1 29d30bb512STodor Tomov 30d30bb512STodor Tomov #define OV7251_CHIP_ID_HIGH 0x300a 31d30bb512STodor Tomov #define OV7251_CHIP_ID_HIGH_BYTE 0x77 32d30bb512STodor Tomov #define OV7251_CHIP_ID_LOW 0x300b 33d30bb512STodor Tomov #define OV7251_CHIP_ID_LOW_BYTE 0x50 34d30bb512STodor Tomov #define OV7251_SC_GP_IO_IN1 0x3029 35d30bb512STodor Tomov #define OV7251_AEC_EXPO_0 0x3500 36d30bb512STodor Tomov #define OV7251_AEC_EXPO_1 0x3501 37d30bb512STodor Tomov #define OV7251_AEC_EXPO_2 0x3502 38d30bb512STodor Tomov #define OV7251_AEC_AGC_ADJ_0 0x350a 39d30bb512STodor Tomov #define OV7251_AEC_AGC_ADJ_1 0x350b 40d30bb512STodor Tomov #define OV7251_TIMING_FORMAT1 0x3820 41d30bb512STodor Tomov #define OV7251_TIMING_FORMAT1_VFLIP BIT(2) 42d30bb512STodor Tomov #define OV7251_TIMING_FORMAT2 0x3821 43d30bb512STodor Tomov #define OV7251_TIMING_FORMAT2_MIRROR BIT(2) 44d30bb512STodor Tomov #define OV7251_PRE_ISP_00 0x5e00 45d30bb512STodor Tomov #define OV7251_PRE_ISP_00_TEST_PATTERN BIT(7) 46df057b0dSDaniel Scally #define OV7251_PLL1_PRE_DIV_REG 0x30b4 47df057b0dSDaniel Scally #define OV7251_PLL1_MULT_REG 0x30b3 48df057b0dSDaniel Scally #define OV7251_PLL1_DIVIDER_REG 0x30b1 49df057b0dSDaniel Scally #define OV7251_PLL1_PIX_DIV_REG 0x30b0 50df057b0dSDaniel Scally #define OV7251_PLL1_MIPI_DIV_REG 0x30b5 51df057b0dSDaniel Scally #define OV7251_PLL2_PRE_DIV_REG 0x3098 52df057b0dSDaniel Scally #define OV7251_PLL2_MULT_REG 0x3099 53df057b0dSDaniel Scally #define OV7251_PLL2_DIVIDER_REG 0x309d 54df057b0dSDaniel Scally #define OV7251_PLL2_SYS_DIV_REG 0x309a 55df057b0dSDaniel Scally #define OV7251_PLL2_ADC_DIV_REG 0x309b 56d30bb512STodor Tomov 5777ec83cdSDaniel Scally #define OV7251_NATIVE_WIDTH 656 5877ec83cdSDaniel Scally #define OV7251_NATIVE_HEIGHT 496 5977ec83cdSDaniel Scally #define OV7251_ACTIVE_START_LEFT 4 6077ec83cdSDaniel Scally #define OV7251_ACTIVE_START_TOP 4 6177ec83cdSDaniel Scally #define OV7251_ACTIVE_WIDTH 648 6277ec83cdSDaniel Scally #define OV7251_ACTIVE_HEIGHT 488 6377ec83cdSDaniel Scally 64*26066ae6SDaniel Scally #define OV7251_FIXED_PPL 928 65*26066ae6SDaniel Scally 66d30bb512STodor Tomov struct reg_value { 67d30bb512STodor Tomov u16 reg; 68d30bb512STodor Tomov u8 val; 69d30bb512STodor Tomov }; 70d30bb512STodor Tomov 71d30bb512STodor Tomov struct ov7251_mode_info { 72d30bb512STodor Tomov u32 width; 73d30bb512STodor Tomov u32 height; 74d30bb512STodor Tomov const struct reg_value *data; 75d30bb512STodor Tomov u32 data_size; 76d30bb512STodor Tomov u32 pixel_clock; 77d30bb512STodor Tomov u32 link_freq; 78d30bb512STodor Tomov u16 exposure_max; 79d30bb512STodor Tomov u16 exposure_def; 80d30bb512STodor Tomov struct v4l2_fract timeperframe; 81d30bb512STodor Tomov }; 82d30bb512STodor Tomov 83df057b0dSDaniel Scally struct ov7251_pll1_cfg { 84df057b0dSDaniel Scally unsigned int pre_div; 85df057b0dSDaniel Scally unsigned int mult; 86df057b0dSDaniel Scally unsigned int div; 87df057b0dSDaniel Scally unsigned int pix_div; 88df057b0dSDaniel Scally unsigned int mipi_div; 89df057b0dSDaniel Scally }; 90df057b0dSDaniel Scally 91df057b0dSDaniel Scally struct ov7251_pll2_cfg { 92df057b0dSDaniel Scally unsigned int pre_div; 93df057b0dSDaniel Scally unsigned int mult; 94df057b0dSDaniel Scally unsigned int div; 95df057b0dSDaniel Scally unsigned int sys_div; 96df057b0dSDaniel Scally unsigned int adc_div; 97df057b0dSDaniel Scally }; 98df057b0dSDaniel Scally 99df057b0dSDaniel Scally /* 100df057b0dSDaniel Scally * Rubbish ordering, but only PLL1 needs to have a separate configuration per 101df057b0dSDaniel Scally * link frequency and the array member needs to be last. 102df057b0dSDaniel Scally */ 103df057b0dSDaniel Scally struct ov7251_pll_cfgs { 104df057b0dSDaniel Scally const struct ov7251_pll2_cfg *pll2; 105df057b0dSDaniel Scally const struct ov7251_pll1_cfg *pll1[]; 106df057b0dSDaniel Scally }; 107df057b0dSDaniel Scally 108df057b0dSDaniel Scally enum xclk_rate { 109ed9566ceSDaniel Scally OV7251_19_2_MHZ, 110df057b0dSDaniel Scally OV7251_24_MHZ, 111df057b0dSDaniel Scally OV7251_NUM_SUPPORTED_RATES 112df057b0dSDaniel Scally }; 113df057b0dSDaniel Scally 114cc125aaaSDaniel Scally enum supported_link_freqs { 115cc125aaaSDaniel Scally OV7251_LINK_FREQ_240_MHZ, 116ed9566ceSDaniel Scally OV7251_LINK_FREQ_319_2_MHZ, 117cc125aaaSDaniel Scally OV7251_NUM_SUPPORTED_LINK_FREQS 118cc125aaaSDaniel Scally }; 119cc125aaaSDaniel Scally 120d30bb512STodor Tomov struct ov7251 { 121d30bb512STodor Tomov struct i2c_client *i2c_client; 122d30bb512STodor Tomov struct device *dev; 123d30bb512STodor Tomov struct v4l2_subdev sd; 124d30bb512STodor Tomov struct media_pad pad; 125d30bb512STodor Tomov struct v4l2_fwnode_endpoint ep; 126d30bb512STodor Tomov struct v4l2_mbus_framefmt fmt; 127d30bb512STodor Tomov struct v4l2_rect crop; 128d30bb512STodor Tomov struct clk *xclk; 129d30bb512STodor Tomov u32 xclk_freq; 130d30bb512STodor Tomov 131d30bb512STodor Tomov struct regulator *io_regulator; 132d30bb512STodor Tomov struct regulator *core_regulator; 133d30bb512STodor Tomov struct regulator *analog_regulator; 134d30bb512STodor Tomov 135df057b0dSDaniel Scally const struct ov7251_pll_cfgs *pll_cfgs; 136cc125aaaSDaniel Scally enum supported_link_freqs link_freq_idx; 137d30bb512STodor Tomov const struct ov7251_mode_info *current_mode; 138d30bb512STodor Tomov 139d30bb512STodor Tomov struct v4l2_ctrl_handler ctrls; 140d30bb512STodor Tomov struct v4l2_ctrl *pixel_clock; 141d30bb512STodor Tomov struct v4l2_ctrl *link_freq; 142d30bb512STodor Tomov struct v4l2_ctrl *exposure; 143d30bb512STodor Tomov struct v4l2_ctrl *gain; 144*26066ae6SDaniel Scally struct v4l2_ctrl *hblank; 145d30bb512STodor Tomov 146d30bb512STodor Tomov /* Cached register values */ 147d30bb512STodor Tomov u8 aec_pk_manual; 148d30bb512STodor Tomov u8 pre_isp_00; 149d30bb512STodor Tomov u8 timing_format1; 150d30bb512STodor Tomov u8 timing_format2; 151d30bb512STodor Tomov 152d30bb512STodor Tomov struct mutex lock; /* lock to protect power state, ctrls and mode */ 153d30bb512STodor Tomov bool power_on; 154d30bb512STodor Tomov 155d30bb512STodor Tomov struct gpio_desc *enable_gpio; 156d30bb512STodor Tomov }; 157d30bb512STodor Tomov 158d30bb512STodor Tomov static inline struct ov7251 *to_ov7251(struct v4l2_subdev *sd) 159d30bb512STodor Tomov { 160d30bb512STodor Tomov return container_of(sd, struct ov7251, sd); 161d30bb512STodor Tomov } 162d30bb512STodor Tomov 163ed9566ceSDaniel Scally static const struct ov7251_pll1_cfg ov7251_pll1_cfg_19_2_mhz_240_mhz = { 164ed9566ceSDaniel Scally .pre_div = 0x03, 165ed9566ceSDaniel Scally .mult = 0x4b, 166ed9566ceSDaniel Scally .div = 0x01, 167ed9566ceSDaniel Scally .pix_div = 0x0a, 168ed9566ceSDaniel Scally .mipi_div = 0x05, 169ed9566ceSDaniel Scally }; 170ed9566ceSDaniel Scally 171ed9566ceSDaniel Scally static const struct ov7251_pll1_cfg ov7251_pll1_cfg_19_2_mhz_319_2_mhz = { 172ed9566ceSDaniel Scally .pre_div = 0x01, 173ed9566ceSDaniel Scally .mult = 0x85, 174ed9566ceSDaniel Scally .div = 0x04, 175ed9566ceSDaniel Scally .pix_div = 0x0a, 176ed9566ceSDaniel Scally .mipi_div = 0x05, 177ed9566ceSDaniel Scally }; 178ed9566ceSDaniel Scally 179df057b0dSDaniel Scally static const struct ov7251_pll1_cfg ov7251_pll1_cfg_24_mhz_240_mhz = { 180df057b0dSDaniel Scally .pre_div = 0x03, 181df057b0dSDaniel Scally .mult = 0x64, 182df057b0dSDaniel Scally .div = 0x01, 183df057b0dSDaniel Scally .pix_div = 0x0a, 184df057b0dSDaniel Scally .mipi_div = 0x05, 185df057b0dSDaniel Scally }; 186df057b0dSDaniel Scally 187ed9566ceSDaniel Scally static const struct ov7251_pll1_cfg ov7251_pll1_cfg_24_mhz_319_2_mhz = { 188ed9566ceSDaniel Scally .pre_div = 0x05, 189ed9566ceSDaniel Scally .mult = 0x85, 190ed9566ceSDaniel Scally .div = 0x02, 191ed9566ceSDaniel Scally .pix_div = 0x0a, 192ed9566ceSDaniel Scally .mipi_div = 0x05, 193ed9566ceSDaniel Scally }; 194ed9566ceSDaniel Scally 195ed9566ceSDaniel Scally static const struct ov7251_pll2_cfg ov7251_pll2_cfg_19_2_mhz = { 196ed9566ceSDaniel Scally .pre_div = 0x04, 197ed9566ceSDaniel Scally .mult = 0x32, 198ed9566ceSDaniel Scally .div = 0x00, 199ed9566ceSDaniel Scally .sys_div = 0x05, 200ed9566ceSDaniel Scally .adc_div = 0x04, 201ed9566ceSDaniel Scally }; 202ed9566ceSDaniel Scally 203df057b0dSDaniel Scally static const struct ov7251_pll2_cfg ov7251_pll2_cfg_24_mhz = { 204df057b0dSDaniel Scally .pre_div = 0x04, 205df057b0dSDaniel Scally .mult = 0x28, 206df057b0dSDaniel Scally .div = 0x00, 207df057b0dSDaniel Scally .sys_div = 0x05, 208df057b0dSDaniel Scally .adc_div = 0x04, 209df057b0dSDaniel Scally }; 210df057b0dSDaniel Scally 211ed9566ceSDaniel Scally static const struct ov7251_pll_cfgs ov7251_pll_cfgs_19_2_mhz = { 212ed9566ceSDaniel Scally .pll2 = &ov7251_pll2_cfg_19_2_mhz, 213ed9566ceSDaniel Scally .pll1 = { 214ed9566ceSDaniel Scally [OV7251_LINK_FREQ_240_MHZ] = &ov7251_pll1_cfg_19_2_mhz_240_mhz, 215ed9566ceSDaniel Scally [OV7251_LINK_FREQ_319_2_MHZ] = &ov7251_pll1_cfg_19_2_mhz_319_2_mhz, 216ed9566ceSDaniel Scally }, 217ed9566ceSDaniel Scally }; 218ed9566ceSDaniel Scally 219df057b0dSDaniel Scally static const struct ov7251_pll_cfgs ov7251_pll_cfgs_24_mhz = { 220df057b0dSDaniel Scally .pll2 = &ov7251_pll2_cfg_24_mhz, 221df057b0dSDaniel Scally .pll1 = { 222df057b0dSDaniel Scally [OV7251_LINK_FREQ_240_MHZ] = &ov7251_pll1_cfg_24_mhz_240_mhz, 223ed9566ceSDaniel Scally [OV7251_LINK_FREQ_319_2_MHZ] = &ov7251_pll1_cfg_24_mhz_319_2_mhz, 224df057b0dSDaniel Scally }, 225df057b0dSDaniel Scally }; 226df057b0dSDaniel Scally 227df057b0dSDaniel Scally static const struct ov7251_pll_cfgs *ov7251_pll_cfgs[] = { 228ed9566ceSDaniel Scally [OV7251_19_2_MHZ] = &ov7251_pll_cfgs_19_2_mhz, 229df057b0dSDaniel Scally [OV7251_24_MHZ] = &ov7251_pll_cfgs_24_mhz, 230df057b0dSDaniel Scally }; 231df057b0dSDaniel Scally 232d30bb512STodor Tomov static const struct reg_value ov7251_global_init_setting[] = { 233d30bb512STodor Tomov { 0x0103, 0x01 }, 234d30bb512STodor Tomov { 0x303b, 0x02 }, 235d30bb512STodor Tomov }; 236d30bb512STodor Tomov 237d30bb512STodor Tomov static const struct reg_value ov7251_setting_vga_30fps[] = { 238d30bb512STodor Tomov { 0x3005, 0x00 }, 239d30bb512STodor Tomov { 0x3012, 0xc0 }, 240d30bb512STodor Tomov { 0x3013, 0xd2 }, 241d30bb512STodor Tomov { 0x3014, 0x04 }, 242d30bb512STodor Tomov { 0x3016, 0xf0 }, 243d30bb512STodor Tomov { 0x3017, 0xf0 }, 244d30bb512STodor Tomov { 0x3018, 0xf0 }, 245d30bb512STodor Tomov { 0x301a, 0xf0 }, 246d30bb512STodor Tomov { 0x301b, 0xf0 }, 247d30bb512STodor Tomov { 0x301c, 0xf0 }, 248d30bb512STodor Tomov { 0x3023, 0x05 }, 249d30bb512STodor Tomov { 0x3037, 0xf0 }, 250d30bb512STodor Tomov { 0x3106, 0xda }, 251d30bb512STodor Tomov { 0x3503, 0x07 }, 252d30bb512STodor Tomov { 0x3509, 0x10 }, 253d30bb512STodor Tomov { 0x3600, 0x1c }, 254d30bb512STodor Tomov { 0x3602, 0x62 }, 255d30bb512STodor Tomov { 0x3620, 0xb7 }, 256d30bb512STodor Tomov { 0x3622, 0x04 }, 257d30bb512STodor Tomov { 0x3626, 0x21 }, 258d30bb512STodor Tomov { 0x3627, 0x30 }, 259d30bb512STodor Tomov { 0x3630, 0x44 }, 260d30bb512STodor Tomov { 0x3631, 0x35 }, 261d30bb512STodor Tomov { 0x3634, 0x60 }, 262d30bb512STodor Tomov { 0x3636, 0x00 }, 263d30bb512STodor Tomov { 0x3662, 0x01 }, 264d30bb512STodor Tomov { 0x3663, 0x70 }, 265d30bb512STodor Tomov { 0x3664, 0x50 }, 266d30bb512STodor Tomov { 0x3666, 0x0a }, 267d30bb512STodor Tomov { 0x3669, 0x1a }, 268d30bb512STodor Tomov { 0x366a, 0x00 }, 269d30bb512STodor Tomov { 0x366b, 0x50 }, 270d30bb512STodor Tomov { 0x3673, 0x01 }, 271d30bb512STodor Tomov { 0x3674, 0xff }, 272d30bb512STodor Tomov { 0x3675, 0x03 }, 273d30bb512STodor Tomov { 0x3705, 0xc1 }, 274d30bb512STodor Tomov { 0x3709, 0x40 }, 275d30bb512STodor Tomov { 0x373c, 0x08 }, 276d30bb512STodor Tomov { 0x3742, 0x00 }, 277d30bb512STodor Tomov { 0x3757, 0xb3 }, 278d30bb512STodor Tomov { 0x3788, 0x00 }, 279d30bb512STodor Tomov { 0x37a8, 0x01 }, 280d30bb512STodor Tomov { 0x37a9, 0xc0 }, 281d30bb512STodor Tomov { 0x3800, 0x00 }, 282d30bb512STodor Tomov { 0x3801, 0x04 }, 283d30bb512STodor Tomov { 0x3802, 0x00 }, 284d30bb512STodor Tomov { 0x3803, 0x04 }, 285d30bb512STodor Tomov { 0x3804, 0x02 }, 286d30bb512STodor Tomov { 0x3805, 0x8b }, 287d30bb512STodor Tomov { 0x3806, 0x01 }, 288d30bb512STodor Tomov { 0x3807, 0xeb }, 289d30bb512STodor Tomov { 0x3808, 0x02 }, /* width high */ 290d30bb512STodor Tomov { 0x3809, 0x80 }, /* width low */ 291d30bb512STodor Tomov { 0x380a, 0x01 }, /* height high */ 292d30bb512STodor Tomov { 0x380b, 0xe0 }, /* height low */ 293d30bb512STodor Tomov { 0x380c, 0x03 }, /* total horiz timing high */ 294d30bb512STodor Tomov { 0x380d, 0xa0 }, /* total horiz timing low */ 295d30bb512STodor Tomov { 0x380e, 0x06 }, /* total vertical timing high */ 296d30bb512STodor Tomov { 0x380f, 0xbc }, /* total vertical timing low */ 297d30bb512STodor Tomov { 0x3810, 0x00 }, 298d30bb512STodor Tomov { 0x3811, 0x04 }, 299d30bb512STodor Tomov { 0x3812, 0x00 }, 300d30bb512STodor Tomov { 0x3813, 0x05 }, 301d30bb512STodor Tomov { 0x3814, 0x11 }, 302d30bb512STodor Tomov { 0x3815, 0x11 }, 303d30bb512STodor Tomov { 0x3820, 0x40 }, 304d30bb512STodor Tomov { 0x3821, 0x00 }, 305d30bb512STodor Tomov { 0x382f, 0x0e }, 306d30bb512STodor Tomov { 0x3832, 0x00 }, 307d30bb512STodor Tomov { 0x3833, 0x05 }, 308d30bb512STodor Tomov { 0x3834, 0x00 }, 309d30bb512STodor Tomov { 0x3835, 0x0c }, 310d30bb512STodor Tomov { 0x3837, 0x00 }, 311d30bb512STodor Tomov { 0x3b80, 0x00 }, 312d30bb512STodor Tomov { 0x3b81, 0xa5 }, 313d30bb512STodor Tomov { 0x3b82, 0x10 }, 314d30bb512STodor Tomov { 0x3b83, 0x00 }, 315d30bb512STodor Tomov { 0x3b84, 0x08 }, 316d30bb512STodor Tomov { 0x3b85, 0x00 }, 317d30bb512STodor Tomov { 0x3b86, 0x01 }, 318d30bb512STodor Tomov { 0x3b87, 0x00 }, 319d30bb512STodor Tomov { 0x3b88, 0x00 }, 320d30bb512STodor Tomov { 0x3b89, 0x00 }, 321d30bb512STodor Tomov { 0x3b8a, 0x00 }, 322d30bb512STodor Tomov { 0x3b8b, 0x05 }, 323d30bb512STodor Tomov { 0x3b8c, 0x00 }, 324d30bb512STodor Tomov { 0x3b8d, 0x00 }, 325d30bb512STodor Tomov { 0x3b8e, 0x00 }, 326d30bb512STodor Tomov { 0x3b8f, 0x1a }, 327d30bb512STodor Tomov { 0x3b94, 0x05 }, 328d30bb512STodor Tomov { 0x3b95, 0xf2 }, 329d30bb512STodor Tomov { 0x3b96, 0x40 }, 330d30bb512STodor Tomov { 0x3c00, 0x89 }, 331d30bb512STodor Tomov { 0x3c01, 0x63 }, 332d30bb512STodor Tomov { 0x3c02, 0x01 }, 333d30bb512STodor Tomov { 0x3c03, 0x00 }, 334d30bb512STodor Tomov { 0x3c04, 0x00 }, 335d30bb512STodor Tomov { 0x3c05, 0x03 }, 336d30bb512STodor Tomov { 0x3c06, 0x00 }, 337d30bb512STodor Tomov { 0x3c07, 0x06 }, 338d30bb512STodor Tomov { 0x3c0c, 0x01 }, 339d30bb512STodor Tomov { 0x3c0d, 0xd0 }, 340d30bb512STodor Tomov { 0x3c0e, 0x02 }, 341d30bb512STodor Tomov { 0x3c0f, 0x0a }, 342d30bb512STodor Tomov { 0x4001, 0x42 }, 343d30bb512STodor Tomov { 0x4004, 0x04 }, 344d30bb512STodor Tomov { 0x4005, 0x00 }, 345d30bb512STodor Tomov { 0x404e, 0x01 }, 346d30bb512STodor Tomov { 0x4300, 0xff }, 347d30bb512STodor Tomov { 0x4301, 0x00 }, 348d30bb512STodor Tomov { 0x4315, 0x00 }, 349d30bb512STodor Tomov { 0x4501, 0x48 }, 350d30bb512STodor Tomov { 0x4600, 0x00 }, 351d30bb512STodor Tomov { 0x4601, 0x4e }, 352d30bb512STodor Tomov { 0x4801, 0x0f }, 353d30bb512STodor Tomov { 0x4806, 0x0f }, 354d30bb512STodor Tomov { 0x4819, 0xaa }, 355d30bb512STodor Tomov { 0x4823, 0x3e }, 356d30bb512STodor Tomov { 0x4837, 0x19 }, 357d30bb512STodor Tomov { 0x4a0d, 0x00 }, 358d30bb512STodor Tomov { 0x4a47, 0x7f }, 359d30bb512STodor Tomov { 0x4a49, 0xf0 }, 360d30bb512STodor Tomov { 0x4a4b, 0x30 }, 361d30bb512STodor Tomov { 0x5000, 0x85 }, 362d30bb512STodor Tomov { 0x5001, 0x80 }, 363d30bb512STodor Tomov }; 364d30bb512STodor Tomov 365d30bb512STodor Tomov static const struct reg_value ov7251_setting_vga_60fps[] = { 366d30bb512STodor Tomov { 0x3005, 0x00 }, 367d30bb512STodor Tomov { 0x3012, 0xc0 }, 368d30bb512STodor Tomov { 0x3013, 0xd2 }, 369d30bb512STodor Tomov { 0x3014, 0x04 }, 370d30bb512STodor Tomov { 0x3016, 0x10 }, 371d30bb512STodor Tomov { 0x3017, 0x00 }, 372d30bb512STodor Tomov { 0x3018, 0x00 }, 373d30bb512STodor Tomov { 0x301a, 0x00 }, 374d30bb512STodor Tomov { 0x301b, 0x00 }, 375d30bb512STodor Tomov { 0x301c, 0x00 }, 376d30bb512STodor Tomov { 0x3023, 0x05 }, 377d30bb512STodor Tomov { 0x3037, 0xf0 }, 378d30bb512STodor Tomov { 0x3106, 0xda }, 379d30bb512STodor Tomov { 0x3503, 0x07 }, 380d30bb512STodor Tomov { 0x3509, 0x10 }, 381d30bb512STodor Tomov { 0x3600, 0x1c }, 382d30bb512STodor Tomov { 0x3602, 0x62 }, 383d30bb512STodor Tomov { 0x3620, 0xb7 }, 384d30bb512STodor Tomov { 0x3622, 0x04 }, 385d30bb512STodor Tomov { 0x3626, 0x21 }, 386d30bb512STodor Tomov { 0x3627, 0x30 }, 387d30bb512STodor Tomov { 0x3630, 0x44 }, 388d30bb512STodor Tomov { 0x3631, 0x35 }, 389d30bb512STodor Tomov { 0x3634, 0x60 }, 390d30bb512STodor Tomov { 0x3636, 0x00 }, 391d30bb512STodor Tomov { 0x3662, 0x01 }, 392d30bb512STodor Tomov { 0x3663, 0x70 }, 393d30bb512STodor Tomov { 0x3664, 0x50 }, 394d30bb512STodor Tomov { 0x3666, 0x0a }, 395d30bb512STodor Tomov { 0x3669, 0x1a }, 396d30bb512STodor Tomov { 0x366a, 0x00 }, 397d30bb512STodor Tomov { 0x366b, 0x50 }, 398d30bb512STodor Tomov { 0x3673, 0x01 }, 399d30bb512STodor Tomov { 0x3674, 0xff }, 400d30bb512STodor Tomov { 0x3675, 0x03 }, 401d30bb512STodor Tomov { 0x3705, 0xc1 }, 402d30bb512STodor Tomov { 0x3709, 0x40 }, 403d30bb512STodor Tomov { 0x373c, 0x08 }, 404d30bb512STodor Tomov { 0x3742, 0x00 }, 405d30bb512STodor Tomov { 0x3757, 0xb3 }, 406d30bb512STodor Tomov { 0x3788, 0x00 }, 407d30bb512STodor Tomov { 0x37a8, 0x01 }, 408d30bb512STodor Tomov { 0x37a9, 0xc0 }, 409d30bb512STodor Tomov { 0x3800, 0x00 }, 410d30bb512STodor Tomov { 0x3801, 0x04 }, 411d30bb512STodor Tomov { 0x3802, 0x00 }, 412d30bb512STodor Tomov { 0x3803, 0x04 }, 413d30bb512STodor Tomov { 0x3804, 0x02 }, 414d30bb512STodor Tomov { 0x3805, 0x8b }, 415d30bb512STodor Tomov { 0x3806, 0x01 }, 416d30bb512STodor Tomov { 0x3807, 0xeb }, 417d30bb512STodor Tomov { 0x3808, 0x02 }, /* width high */ 418d30bb512STodor Tomov { 0x3809, 0x80 }, /* width low */ 419d30bb512STodor Tomov { 0x380a, 0x01 }, /* height high */ 420d30bb512STodor Tomov { 0x380b, 0xe0 }, /* height low */ 421d30bb512STodor Tomov { 0x380c, 0x03 }, /* total horiz timing high */ 422d30bb512STodor Tomov { 0x380d, 0xa0 }, /* total horiz timing low */ 423d30bb512STodor Tomov { 0x380e, 0x03 }, /* total vertical timing high */ 424d30bb512STodor Tomov { 0x380f, 0x5c }, /* total vertical timing low */ 425d30bb512STodor Tomov { 0x3810, 0x00 }, 426d30bb512STodor Tomov { 0x3811, 0x04 }, 427d30bb512STodor Tomov { 0x3812, 0x00 }, 428d30bb512STodor Tomov { 0x3813, 0x05 }, 429d30bb512STodor Tomov { 0x3814, 0x11 }, 430d30bb512STodor Tomov { 0x3815, 0x11 }, 431d30bb512STodor Tomov { 0x3820, 0x40 }, 432d30bb512STodor Tomov { 0x3821, 0x00 }, 433d30bb512STodor Tomov { 0x382f, 0x0e }, 434d30bb512STodor Tomov { 0x3832, 0x00 }, 435d30bb512STodor Tomov { 0x3833, 0x05 }, 436d30bb512STodor Tomov { 0x3834, 0x00 }, 437d30bb512STodor Tomov { 0x3835, 0x0c }, 438d30bb512STodor Tomov { 0x3837, 0x00 }, 439d30bb512STodor Tomov { 0x3b80, 0x00 }, 440d30bb512STodor Tomov { 0x3b81, 0xa5 }, 441d30bb512STodor Tomov { 0x3b82, 0x10 }, 442d30bb512STodor Tomov { 0x3b83, 0x00 }, 443d30bb512STodor Tomov { 0x3b84, 0x08 }, 444d30bb512STodor Tomov { 0x3b85, 0x00 }, 445d30bb512STodor Tomov { 0x3b86, 0x01 }, 446d30bb512STodor Tomov { 0x3b87, 0x00 }, 447d30bb512STodor Tomov { 0x3b88, 0x00 }, 448d30bb512STodor Tomov { 0x3b89, 0x00 }, 449d30bb512STodor Tomov { 0x3b8a, 0x00 }, 450d30bb512STodor Tomov { 0x3b8b, 0x05 }, 451d30bb512STodor Tomov { 0x3b8c, 0x00 }, 452d30bb512STodor Tomov { 0x3b8d, 0x00 }, 453d30bb512STodor Tomov { 0x3b8e, 0x00 }, 454d30bb512STodor Tomov { 0x3b8f, 0x1a }, 455d30bb512STodor Tomov { 0x3b94, 0x05 }, 456d30bb512STodor Tomov { 0x3b95, 0xf2 }, 457d30bb512STodor Tomov { 0x3b96, 0x40 }, 458d30bb512STodor Tomov { 0x3c00, 0x89 }, 459d30bb512STodor Tomov { 0x3c01, 0x63 }, 460d30bb512STodor Tomov { 0x3c02, 0x01 }, 461d30bb512STodor Tomov { 0x3c03, 0x00 }, 462d30bb512STodor Tomov { 0x3c04, 0x00 }, 463d30bb512STodor Tomov { 0x3c05, 0x03 }, 464d30bb512STodor Tomov { 0x3c06, 0x00 }, 465d30bb512STodor Tomov { 0x3c07, 0x06 }, 466d30bb512STodor Tomov { 0x3c0c, 0x01 }, 467d30bb512STodor Tomov { 0x3c0d, 0xd0 }, 468d30bb512STodor Tomov { 0x3c0e, 0x02 }, 469d30bb512STodor Tomov { 0x3c0f, 0x0a }, 470d30bb512STodor Tomov { 0x4001, 0x42 }, 471d30bb512STodor Tomov { 0x4004, 0x04 }, 472d30bb512STodor Tomov { 0x4005, 0x00 }, 473d30bb512STodor Tomov { 0x404e, 0x01 }, 474d30bb512STodor Tomov { 0x4300, 0xff }, 475d30bb512STodor Tomov { 0x4301, 0x00 }, 476d30bb512STodor Tomov { 0x4315, 0x00 }, 477d30bb512STodor Tomov { 0x4501, 0x48 }, 478d30bb512STodor Tomov { 0x4600, 0x00 }, 479d30bb512STodor Tomov { 0x4601, 0x4e }, 480d30bb512STodor Tomov { 0x4801, 0x0f }, 481d30bb512STodor Tomov { 0x4806, 0x0f }, 482d30bb512STodor Tomov { 0x4819, 0xaa }, 483d30bb512STodor Tomov { 0x4823, 0x3e }, 484d30bb512STodor Tomov { 0x4837, 0x19 }, 485d30bb512STodor Tomov { 0x4a0d, 0x00 }, 486d30bb512STodor Tomov { 0x4a47, 0x7f }, 487d30bb512STodor Tomov { 0x4a49, 0xf0 }, 488d30bb512STodor Tomov { 0x4a4b, 0x30 }, 489d30bb512STodor Tomov { 0x5000, 0x85 }, 490d30bb512STodor Tomov { 0x5001, 0x80 }, 491d30bb512STodor Tomov }; 492d30bb512STodor Tomov 493d30bb512STodor Tomov static const struct reg_value ov7251_setting_vga_90fps[] = { 494d30bb512STodor Tomov { 0x3005, 0x00 }, 495d30bb512STodor Tomov { 0x3012, 0xc0 }, 496d30bb512STodor Tomov { 0x3013, 0xd2 }, 497d30bb512STodor Tomov { 0x3014, 0x04 }, 498d30bb512STodor Tomov { 0x3016, 0x10 }, 499d30bb512STodor Tomov { 0x3017, 0x00 }, 500d30bb512STodor Tomov { 0x3018, 0x00 }, 501d30bb512STodor Tomov { 0x301a, 0x00 }, 502d30bb512STodor Tomov { 0x301b, 0x00 }, 503d30bb512STodor Tomov { 0x301c, 0x00 }, 504d30bb512STodor Tomov { 0x3023, 0x05 }, 505d30bb512STodor Tomov { 0x3037, 0xf0 }, 506d30bb512STodor Tomov { 0x3106, 0xda }, 507d30bb512STodor Tomov { 0x3503, 0x07 }, 508d30bb512STodor Tomov { 0x3509, 0x10 }, 509d30bb512STodor Tomov { 0x3600, 0x1c }, 510d30bb512STodor Tomov { 0x3602, 0x62 }, 511d30bb512STodor Tomov { 0x3620, 0xb7 }, 512d30bb512STodor Tomov { 0x3622, 0x04 }, 513d30bb512STodor Tomov { 0x3626, 0x21 }, 514d30bb512STodor Tomov { 0x3627, 0x30 }, 515d30bb512STodor Tomov { 0x3630, 0x44 }, 516d30bb512STodor Tomov { 0x3631, 0x35 }, 517d30bb512STodor Tomov { 0x3634, 0x60 }, 518d30bb512STodor Tomov { 0x3636, 0x00 }, 519d30bb512STodor Tomov { 0x3662, 0x01 }, 520d30bb512STodor Tomov { 0x3663, 0x70 }, 521d30bb512STodor Tomov { 0x3664, 0x50 }, 522d30bb512STodor Tomov { 0x3666, 0x0a }, 523d30bb512STodor Tomov { 0x3669, 0x1a }, 524d30bb512STodor Tomov { 0x366a, 0x00 }, 525d30bb512STodor Tomov { 0x366b, 0x50 }, 526d30bb512STodor Tomov { 0x3673, 0x01 }, 527d30bb512STodor Tomov { 0x3674, 0xff }, 528d30bb512STodor Tomov { 0x3675, 0x03 }, 529d30bb512STodor Tomov { 0x3705, 0xc1 }, 530d30bb512STodor Tomov { 0x3709, 0x40 }, 531d30bb512STodor Tomov { 0x373c, 0x08 }, 532d30bb512STodor Tomov { 0x3742, 0x00 }, 533d30bb512STodor Tomov { 0x3757, 0xb3 }, 534d30bb512STodor Tomov { 0x3788, 0x00 }, 535d30bb512STodor Tomov { 0x37a8, 0x01 }, 536d30bb512STodor Tomov { 0x37a9, 0xc0 }, 537d30bb512STodor Tomov { 0x3800, 0x00 }, 538d30bb512STodor Tomov { 0x3801, 0x04 }, 539d30bb512STodor Tomov { 0x3802, 0x00 }, 540d30bb512STodor Tomov { 0x3803, 0x04 }, 541d30bb512STodor Tomov { 0x3804, 0x02 }, 542d30bb512STodor Tomov { 0x3805, 0x8b }, 543d30bb512STodor Tomov { 0x3806, 0x01 }, 544d30bb512STodor Tomov { 0x3807, 0xeb }, 545d30bb512STodor Tomov { 0x3808, 0x02 }, /* width high */ 546d30bb512STodor Tomov { 0x3809, 0x80 }, /* width low */ 547d30bb512STodor Tomov { 0x380a, 0x01 }, /* height high */ 548d30bb512STodor Tomov { 0x380b, 0xe0 }, /* height low */ 549d30bb512STodor Tomov { 0x380c, 0x03 }, /* total horiz timing high */ 550d30bb512STodor Tomov { 0x380d, 0xa0 }, /* total horiz timing low */ 551d30bb512STodor Tomov { 0x380e, 0x02 }, /* total vertical timing high */ 552d30bb512STodor Tomov { 0x380f, 0x3c }, /* total vertical timing low */ 553d30bb512STodor Tomov { 0x3810, 0x00 }, 554d30bb512STodor Tomov { 0x3811, 0x04 }, 555d30bb512STodor Tomov { 0x3812, 0x00 }, 556d30bb512STodor Tomov { 0x3813, 0x05 }, 557d30bb512STodor Tomov { 0x3814, 0x11 }, 558d30bb512STodor Tomov { 0x3815, 0x11 }, 559d30bb512STodor Tomov { 0x3820, 0x40 }, 560d30bb512STodor Tomov { 0x3821, 0x00 }, 561d30bb512STodor Tomov { 0x382f, 0x0e }, 562d30bb512STodor Tomov { 0x3832, 0x00 }, 563d30bb512STodor Tomov { 0x3833, 0x05 }, 564d30bb512STodor Tomov { 0x3834, 0x00 }, 565d30bb512STodor Tomov { 0x3835, 0x0c }, 566d30bb512STodor Tomov { 0x3837, 0x00 }, 567d30bb512STodor Tomov { 0x3b80, 0x00 }, 568d30bb512STodor Tomov { 0x3b81, 0xa5 }, 569d30bb512STodor Tomov { 0x3b82, 0x10 }, 570d30bb512STodor Tomov { 0x3b83, 0x00 }, 571d30bb512STodor Tomov { 0x3b84, 0x08 }, 572d30bb512STodor Tomov { 0x3b85, 0x00 }, 573d30bb512STodor Tomov { 0x3b86, 0x01 }, 574d30bb512STodor Tomov { 0x3b87, 0x00 }, 575d30bb512STodor Tomov { 0x3b88, 0x00 }, 576d30bb512STodor Tomov { 0x3b89, 0x00 }, 577d30bb512STodor Tomov { 0x3b8a, 0x00 }, 578d30bb512STodor Tomov { 0x3b8b, 0x05 }, 579d30bb512STodor Tomov { 0x3b8c, 0x00 }, 580d30bb512STodor Tomov { 0x3b8d, 0x00 }, 581d30bb512STodor Tomov { 0x3b8e, 0x00 }, 582d30bb512STodor Tomov { 0x3b8f, 0x1a }, 583d30bb512STodor Tomov { 0x3b94, 0x05 }, 584d30bb512STodor Tomov { 0x3b95, 0xf2 }, 585d30bb512STodor Tomov { 0x3b96, 0x40 }, 586d30bb512STodor Tomov { 0x3c00, 0x89 }, 587d30bb512STodor Tomov { 0x3c01, 0x63 }, 588d30bb512STodor Tomov { 0x3c02, 0x01 }, 589d30bb512STodor Tomov { 0x3c03, 0x00 }, 590d30bb512STodor Tomov { 0x3c04, 0x00 }, 591d30bb512STodor Tomov { 0x3c05, 0x03 }, 592d30bb512STodor Tomov { 0x3c06, 0x00 }, 593d30bb512STodor Tomov { 0x3c07, 0x06 }, 594d30bb512STodor Tomov { 0x3c0c, 0x01 }, 595d30bb512STodor Tomov { 0x3c0d, 0xd0 }, 596d30bb512STodor Tomov { 0x3c0e, 0x02 }, 597d30bb512STodor Tomov { 0x3c0f, 0x0a }, 598d30bb512STodor Tomov { 0x4001, 0x42 }, 599d30bb512STodor Tomov { 0x4004, 0x04 }, 600d30bb512STodor Tomov { 0x4005, 0x00 }, 601d30bb512STodor Tomov { 0x404e, 0x01 }, 602d30bb512STodor Tomov { 0x4300, 0xff }, 603d30bb512STodor Tomov { 0x4301, 0x00 }, 604d30bb512STodor Tomov { 0x4315, 0x00 }, 605d30bb512STodor Tomov { 0x4501, 0x48 }, 606d30bb512STodor Tomov { 0x4600, 0x00 }, 607d30bb512STodor Tomov { 0x4601, 0x4e }, 608d30bb512STodor Tomov { 0x4801, 0x0f }, 609d30bb512STodor Tomov { 0x4806, 0x0f }, 610d30bb512STodor Tomov { 0x4819, 0xaa }, 611d30bb512STodor Tomov { 0x4823, 0x3e }, 612d30bb512STodor Tomov { 0x4837, 0x19 }, 613d30bb512STodor Tomov { 0x4a0d, 0x00 }, 614d30bb512STodor Tomov { 0x4a47, 0x7f }, 615d30bb512STodor Tomov { 0x4a49, 0xf0 }, 616d30bb512STodor Tomov { 0x4a4b, 0x30 }, 617d30bb512STodor Tomov { 0x5000, 0x85 }, 618d30bb512STodor Tomov { 0x5001, 0x80 }, 619d30bb512STodor Tomov }; 620d30bb512STodor Tomov 621df057b0dSDaniel Scally static const unsigned long supported_xclk_rates[] = { 622ed9566ceSDaniel Scally [OV7251_19_2_MHZ] = 19200000, 623df057b0dSDaniel Scally [OV7251_24_MHZ] = 24000000, 624df057b0dSDaniel Scally }; 625df057b0dSDaniel Scally 626d30bb512STodor Tomov static const s64 link_freq[] = { 6271757b44eSDaniel Scally [OV7251_LINK_FREQ_240_MHZ] = 240000000, 628ed9566ceSDaniel Scally [OV7251_LINK_FREQ_319_2_MHZ] = 319200000, 6291757b44eSDaniel Scally }; 6301757b44eSDaniel Scally 6311757b44eSDaniel Scally static const s64 pixel_rates[] = { 6321757b44eSDaniel Scally [OV7251_LINK_FREQ_240_MHZ] = 48000000, 633ed9566ceSDaniel Scally [OV7251_LINK_FREQ_319_2_MHZ] = 63840000, 634d30bb512STodor Tomov }; 635d30bb512STodor Tomov 636d30bb512STodor Tomov static const struct ov7251_mode_info ov7251_mode_info_data[] = { 637d30bb512STodor Tomov { 638d30bb512STodor Tomov .width = 640, 639d30bb512STodor Tomov .height = 480, 640d30bb512STodor Tomov .data = ov7251_setting_vga_30fps, 641d30bb512STodor Tomov .data_size = ARRAY_SIZE(ov7251_setting_vga_30fps), 642d30bb512STodor Tomov .exposure_max = 1704, 643d30bb512STodor Tomov .exposure_def = 504, 644d30bb512STodor Tomov .timeperframe = { 645d30bb512STodor Tomov .numerator = 100, 646d30bb512STodor Tomov .denominator = 3000 647d30bb512STodor Tomov } 648d30bb512STodor Tomov }, 649d30bb512STodor Tomov { 650d30bb512STodor Tomov .width = 640, 651d30bb512STodor Tomov .height = 480, 652d30bb512STodor Tomov .data = ov7251_setting_vga_60fps, 653d30bb512STodor Tomov .data_size = ARRAY_SIZE(ov7251_setting_vga_60fps), 654d30bb512STodor Tomov .exposure_max = 840, 655d30bb512STodor Tomov .exposure_def = 504, 656d30bb512STodor Tomov .timeperframe = { 657d30bb512STodor Tomov .numerator = 100, 658d30bb512STodor Tomov .denominator = 6014 659d30bb512STodor Tomov } 660d30bb512STodor Tomov }, 661d30bb512STodor Tomov { 662d30bb512STodor Tomov .width = 640, 663d30bb512STodor Tomov .height = 480, 664d30bb512STodor Tomov .data = ov7251_setting_vga_90fps, 665d30bb512STodor Tomov .data_size = ARRAY_SIZE(ov7251_setting_vga_90fps), 666d30bb512STodor Tomov .exposure_max = 552, 667d30bb512STodor Tomov .exposure_def = 504, 668d30bb512STodor Tomov .timeperframe = { 669d30bb512STodor Tomov .numerator = 100, 670d30bb512STodor Tomov .denominator = 9043 671d30bb512STodor Tomov } 672d30bb512STodor Tomov }, 673d30bb512STodor Tomov }; 674d30bb512STodor Tomov 675d30bb512STodor Tomov static int ov7251_regulators_enable(struct ov7251 *ov7251) 676d30bb512STodor Tomov { 677d30bb512STodor Tomov int ret; 678d30bb512STodor Tomov 679d30bb512STodor Tomov /* OV7251 power up sequence requires core regulator 680d30bb512STodor Tomov * to be enabled not earlier than io regulator 681d30bb512STodor Tomov */ 682d30bb512STodor Tomov 683d30bb512STodor Tomov ret = regulator_enable(ov7251->io_regulator); 684d30bb512STodor Tomov if (ret < 0) { 685d30bb512STodor Tomov dev_err(ov7251->dev, "set io voltage failed\n"); 686d30bb512STodor Tomov return ret; 687d30bb512STodor Tomov } 688d30bb512STodor Tomov 689d30bb512STodor Tomov ret = regulator_enable(ov7251->analog_regulator); 690d30bb512STodor Tomov if (ret) { 691d30bb512STodor Tomov dev_err(ov7251->dev, "set analog voltage failed\n"); 692d30bb512STodor Tomov goto err_disable_io; 693d30bb512STodor Tomov } 694d30bb512STodor Tomov 695d30bb512STodor Tomov ret = regulator_enable(ov7251->core_regulator); 696d30bb512STodor Tomov if (ret) { 697d30bb512STodor Tomov dev_err(ov7251->dev, "set core voltage failed\n"); 698d30bb512STodor Tomov goto err_disable_analog; 699d30bb512STodor Tomov } 700d30bb512STodor Tomov 701d30bb512STodor Tomov return 0; 702d30bb512STodor Tomov 703d30bb512STodor Tomov err_disable_analog: 704d30bb512STodor Tomov regulator_disable(ov7251->analog_regulator); 705d30bb512STodor Tomov 706d30bb512STodor Tomov err_disable_io: 707d30bb512STodor Tomov regulator_disable(ov7251->io_regulator); 708d30bb512STodor Tomov 709d30bb512STodor Tomov return ret; 710d30bb512STodor Tomov } 711d30bb512STodor Tomov 712d30bb512STodor Tomov static void ov7251_regulators_disable(struct ov7251 *ov7251) 713d30bb512STodor Tomov { 714d30bb512STodor Tomov int ret; 715d30bb512STodor Tomov 716d30bb512STodor Tomov ret = regulator_disable(ov7251->core_regulator); 717d30bb512STodor Tomov if (ret < 0) 718d30bb512STodor Tomov dev_err(ov7251->dev, "core regulator disable failed\n"); 719d30bb512STodor Tomov 720d30bb512STodor Tomov ret = regulator_disable(ov7251->analog_regulator); 721d30bb512STodor Tomov if (ret < 0) 722d30bb512STodor Tomov dev_err(ov7251->dev, "analog regulator disable failed\n"); 723d30bb512STodor Tomov 724d30bb512STodor Tomov ret = regulator_disable(ov7251->io_regulator); 725d30bb512STodor Tomov if (ret < 0) 726d30bb512STodor Tomov dev_err(ov7251->dev, "io regulator disable failed\n"); 727d30bb512STodor Tomov } 728d30bb512STodor Tomov 729d30bb512STodor Tomov static int ov7251_write_reg(struct ov7251 *ov7251, u16 reg, u8 val) 730d30bb512STodor Tomov { 731d30bb512STodor Tomov u8 regbuf[3]; 732d30bb512STodor Tomov int ret; 733d30bb512STodor Tomov 734d30bb512STodor Tomov regbuf[0] = reg >> 8; 735d30bb512STodor Tomov regbuf[1] = reg & 0xff; 736d30bb512STodor Tomov regbuf[2] = val; 737d30bb512STodor Tomov 738d30bb512STodor Tomov ret = i2c_master_send(ov7251->i2c_client, regbuf, 3); 739d30bb512STodor Tomov if (ret < 0) { 740d30bb512STodor Tomov dev_err(ov7251->dev, "%s: write reg error %d: reg=%x, val=%x\n", 741d30bb512STodor Tomov __func__, ret, reg, val); 742d30bb512STodor Tomov return ret; 743d30bb512STodor Tomov } 744d30bb512STodor Tomov 745d30bb512STodor Tomov return 0; 746d30bb512STodor Tomov } 747d30bb512STodor Tomov 748d30bb512STodor Tomov static int ov7251_write_seq_regs(struct ov7251 *ov7251, u16 reg, u8 *val, 749d30bb512STodor Tomov u8 num) 750d30bb512STodor Tomov { 751d30bb512STodor Tomov u8 regbuf[5]; 752d30bb512STodor Tomov u8 nregbuf = sizeof(reg) + num * sizeof(*val); 753d30bb512STodor Tomov int ret = 0; 754d30bb512STodor Tomov 755d30bb512STodor Tomov if (nregbuf > sizeof(regbuf)) 756d30bb512STodor Tomov return -EINVAL; 757d30bb512STodor Tomov 758d30bb512STodor Tomov regbuf[0] = reg >> 8; 759d30bb512STodor Tomov regbuf[1] = reg & 0xff; 760d30bb512STodor Tomov 761d30bb512STodor Tomov memcpy(regbuf + 2, val, num); 762d30bb512STodor Tomov 763d30bb512STodor Tomov ret = i2c_master_send(ov7251->i2c_client, regbuf, nregbuf); 764d30bb512STodor Tomov if (ret < 0) { 765d30bb512STodor Tomov dev_err(ov7251->dev, 766d30bb512STodor Tomov "%s: write seq regs error %d: first reg=%x\n", 767d30bb512STodor Tomov __func__, ret, reg); 768d30bb512STodor Tomov return ret; 769d30bb512STodor Tomov } 770d30bb512STodor Tomov 771d30bb512STodor Tomov return 0; 772d30bb512STodor Tomov } 773d30bb512STodor Tomov 774d30bb512STodor Tomov static int ov7251_read_reg(struct ov7251 *ov7251, u16 reg, u8 *val) 775d30bb512STodor Tomov { 776d30bb512STodor Tomov u8 regbuf[2]; 777d30bb512STodor Tomov int ret; 778d30bb512STodor Tomov 779d30bb512STodor Tomov regbuf[0] = reg >> 8; 780d30bb512STodor Tomov regbuf[1] = reg & 0xff; 781d30bb512STodor Tomov 782d30bb512STodor Tomov ret = i2c_master_send(ov7251->i2c_client, regbuf, 2); 783d30bb512STodor Tomov if (ret < 0) { 784d30bb512STodor Tomov dev_err(ov7251->dev, "%s: write reg error %d: reg=%x\n", 785d30bb512STodor Tomov __func__, ret, reg); 786d30bb512STodor Tomov return ret; 787d30bb512STodor Tomov } 788d30bb512STodor Tomov 789d30bb512STodor Tomov ret = i2c_master_recv(ov7251->i2c_client, val, 1); 790d30bb512STodor Tomov if (ret < 0) { 791d30bb512STodor Tomov dev_err(ov7251->dev, "%s: read reg error %d: reg=%x\n", 792d30bb512STodor Tomov __func__, ret, reg); 793d30bb512STodor Tomov return ret; 794d30bb512STodor Tomov } 795d30bb512STodor Tomov 796d30bb512STodor Tomov return 0; 797d30bb512STodor Tomov } 798d30bb512STodor Tomov 799df057b0dSDaniel Scally static int ov7251_pll_configure(struct ov7251 *ov7251) 800df057b0dSDaniel Scally { 801df057b0dSDaniel Scally const struct ov7251_pll_cfgs *configs; 802df057b0dSDaniel Scally int ret; 803df057b0dSDaniel Scally 804df057b0dSDaniel Scally configs = ov7251->pll_cfgs; 805df057b0dSDaniel Scally 806df057b0dSDaniel Scally ret = ov7251_write_reg(ov7251, OV7251_PLL1_PRE_DIV_REG, 807df057b0dSDaniel Scally configs->pll1[ov7251->link_freq_idx]->pre_div); 808df057b0dSDaniel Scally if (ret < 0) 809df057b0dSDaniel Scally return ret; 810df057b0dSDaniel Scally 811df057b0dSDaniel Scally ret = ov7251_write_reg(ov7251, OV7251_PLL1_MULT_REG, 812df057b0dSDaniel Scally configs->pll1[ov7251->link_freq_idx]->mult); 813df057b0dSDaniel Scally if (ret < 0) 814df057b0dSDaniel Scally return ret; 815df057b0dSDaniel Scally ret = ov7251_write_reg(ov7251, OV7251_PLL1_DIVIDER_REG, 816df057b0dSDaniel Scally configs->pll1[ov7251->link_freq_idx]->div); 817df057b0dSDaniel Scally if (ret < 0) 818df057b0dSDaniel Scally return ret; 819df057b0dSDaniel Scally 820df057b0dSDaniel Scally ret = ov7251_write_reg(ov7251, OV7251_PLL1_PIX_DIV_REG, 821df057b0dSDaniel Scally configs->pll1[ov7251->link_freq_idx]->pix_div); 822df057b0dSDaniel Scally if (ret < 0) 823df057b0dSDaniel Scally return ret; 824df057b0dSDaniel Scally 825df057b0dSDaniel Scally ret = ov7251_write_reg(ov7251, OV7251_PLL1_MIPI_DIV_REG, 826df057b0dSDaniel Scally configs->pll1[ov7251->link_freq_idx]->mipi_div); 827df057b0dSDaniel Scally if (ret < 0) 828df057b0dSDaniel Scally return ret; 829df057b0dSDaniel Scally 830df057b0dSDaniel Scally ret = ov7251_write_reg(ov7251, OV7251_PLL2_PRE_DIV_REG, 831df057b0dSDaniel Scally configs->pll2->pre_div); 832df057b0dSDaniel Scally if (ret < 0) 833df057b0dSDaniel Scally return ret; 834df057b0dSDaniel Scally 835df057b0dSDaniel Scally ret = ov7251_write_reg(ov7251, OV7251_PLL2_MULT_REG, 836df057b0dSDaniel Scally configs->pll2->mult); 837df057b0dSDaniel Scally if (ret < 0) 838df057b0dSDaniel Scally return ret; 839df057b0dSDaniel Scally 840df057b0dSDaniel Scally ret = ov7251_write_reg(ov7251, OV7251_PLL2_DIVIDER_REG, 841df057b0dSDaniel Scally configs->pll2->div); 842df057b0dSDaniel Scally if (ret < 0) 843df057b0dSDaniel Scally return ret; 844df057b0dSDaniel Scally 845df057b0dSDaniel Scally ret = ov7251_write_reg(ov7251, OV7251_PLL2_SYS_DIV_REG, 846df057b0dSDaniel Scally configs->pll2->sys_div); 847df057b0dSDaniel Scally if (ret < 0) 848df057b0dSDaniel Scally return ret; 849df057b0dSDaniel Scally 850df057b0dSDaniel Scally ret = ov7251_write_reg(ov7251, OV7251_PLL2_ADC_DIV_REG, 851df057b0dSDaniel Scally configs->pll2->adc_div); 852df057b0dSDaniel Scally 853df057b0dSDaniel Scally return ret; 854df057b0dSDaniel Scally } 855df057b0dSDaniel Scally 856d30bb512STodor Tomov static int ov7251_set_exposure(struct ov7251 *ov7251, s32 exposure) 857d30bb512STodor Tomov { 858d30bb512STodor Tomov u16 reg; 859d30bb512STodor Tomov u8 val[3]; 860d30bb512STodor Tomov 861d30bb512STodor Tomov reg = OV7251_AEC_EXPO_0; 862d30bb512STodor Tomov val[0] = (exposure & 0xf000) >> 12; /* goes to OV7251_AEC_EXPO_0 */ 863d30bb512STodor Tomov val[1] = (exposure & 0x0ff0) >> 4; /* goes to OV7251_AEC_EXPO_1 */ 864d30bb512STodor Tomov val[2] = (exposure & 0x000f) << 4; /* goes to OV7251_AEC_EXPO_2 */ 865d30bb512STodor Tomov 866d30bb512STodor Tomov return ov7251_write_seq_regs(ov7251, reg, val, 3); 867d30bb512STodor Tomov } 868d30bb512STodor Tomov 869d30bb512STodor Tomov static int ov7251_set_gain(struct ov7251 *ov7251, s32 gain) 870d30bb512STodor Tomov { 871d30bb512STodor Tomov u16 reg; 872d30bb512STodor Tomov u8 val[2]; 873d30bb512STodor Tomov 874d30bb512STodor Tomov reg = OV7251_AEC_AGC_ADJ_0; 875d30bb512STodor Tomov val[0] = (gain & 0x0300) >> 8; /* goes to OV7251_AEC_AGC_ADJ_0 */ 876d30bb512STodor Tomov val[1] = gain & 0xff; /* goes to OV7251_AEC_AGC_ADJ_1 */ 877d30bb512STodor Tomov 878d30bb512STodor Tomov return ov7251_write_seq_regs(ov7251, reg, val, 2); 879d30bb512STodor Tomov } 880d30bb512STodor Tomov 881d30bb512STodor Tomov static int ov7251_set_register_array(struct ov7251 *ov7251, 882d30bb512STodor Tomov const struct reg_value *settings, 883d30bb512STodor Tomov unsigned int num_settings) 884d30bb512STodor Tomov { 885d30bb512STodor Tomov unsigned int i; 886d30bb512STodor Tomov int ret; 887d30bb512STodor Tomov 888d30bb512STodor Tomov for (i = 0; i < num_settings; ++i, ++settings) { 889d30bb512STodor Tomov ret = ov7251_write_reg(ov7251, settings->reg, settings->val); 890d30bb512STodor Tomov if (ret < 0) 891d30bb512STodor Tomov return ret; 892d30bb512STodor Tomov } 893d30bb512STodor Tomov 894d30bb512STodor Tomov return 0; 895d30bb512STodor Tomov } 896d30bb512STodor Tomov 897207f4162SDaniel Scally static int ov7251_set_power_on(struct device *dev) 898d30bb512STodor Tomov { 899207f4162SDaniel Scally struct i2c_client *client = container_of(dev, struct i2c_client, dev); 900207f4162SDaniel Scally struct v4l2_subdev *sd = i2c_get_clientdata(client); 901207f4162SDaniel Scally struct ov7251 *ov7251 = to_ov7251(sd); 902d30bb512STodor Tomov int ret; 903d30bb512STodor Tomov u32 wait_us; 904d30bb512STodor Tomov 905d30bb512STodor Tomov ret = ov7251_regulators_enable(ov7251); 906d30bb512STodor Tomov if (ret < 0) 907d30bb512STodor Tomov return ret; 908d30bb512STodor Tomov 909d30bb512STodor Tomov ret = clk_prepare_enable(ov7251->xclk); 910d30bb512STodor Tomov if (ret < 0) { 911d30bb512STodor Tomov dev_err(ov7251->dev, "clk prepare enable failed\n"); 912d30bb512STodor Tomov ov7251_regulators_disable(ov7251); 913d30bb512STodor Tomov return ret; 914d30bb512STodor Tomov } 915d30bb512STodor Tomov 916d30bb512STodor Tomov gpiod_set_value_cansleep(ov7251->enable_gpio, 1); 917d30bb512STodor Tomov 918d30bb512STodor Tomov /* wait at least 65536 external clock cycles */ 919d30bb512STodor Tomov wait_us = DIV_ROUND_UP(65536 * 1000, 920d30bb512STodor Tomov DIV_ROUND_UP(ov7251->xclk_freq, 1000)); 921d30bb512STodor Tomov usleep_range(wait_us, wait_us + 1000); 922d30bb512STodor Tomov 9239e1d3012SDaniel Scally ret = ov7251_set_register_array(ov7251, 9249e1d3012SDaniel Scally ov7251_global_init_setting, 9259e1d3012SDaniel Scally ARRAY_SIZE(ov7251_global_init_setting)); 9269e1d3012SDaniel Scally if (ret < 0) { 9279e1d3012SDaniel Scally dev_err(ov7251->dev, "error during global init\n"); 9289e1d3012SDaniel Scally ov7251_regulators_disable(ov7251); 9299e1d3012SDaniel Scally return ret; 9309e1d3012SDaniel Scally } 9319e1d3012SDaniel Scally 9329e1d3012SDaniel Scally return ret; 933d30bb512STodor Tomov } 934d30bb512STodor Tomov 935207f4162SDaniel Scally static int ov7251_set_power_off(struct device *dev) 936d30bb512STodor Tomov { 937207f4162SDaniel Scally struct i2c_client *client = container_of(dev, struct i2c_client, dev); 938207f4162SDaniel Scally struct v4l2_subdev *sd = i2c_get_clientdata(client); 939207f4162SDaniel Scally struct ov7251 *ov7251 = to_ov7251(sd); 940207f4162SDaniel Scally 941d30bb512STodor Tomov clk_disable_unprepare(ov7251->xclk); 942d30bb512STodor Tomov gpiod_set_value_cansleep(ov7251->enable_gpio, 0); 943d30bb512STodor Tomov ov7251_regulators_disable(ov7251); 944207f4162SDaniel Scally 945207f4162SDaniel Scally return 0; 946d30bb512STodor Tomov } 947d30bb512STodor Tomov 948d30bb512STodor Tomov static int ov7251_set_hflip(struct ov7251 *ov7251, s32 value) 949d30bb512STodor Tomov { 950d30bb512STodor Tomov u8 val = ov7251->timing_format2; 951d30bb512STodor Tomov int ret; 952d30bb512STodor Tomov 953d30bb512STodor Tomov if (value) 954d30bb512STodor Tomov val |= OV7251_TIMING_FORMAT2_MIRROR; 955d30bb512STodor Tomov else 956d30bb512STodor Tomov val &= ~OV7251_TIMING_FORMAT2_MIRROR; 957d30bb512STodor Tomov 958d30bb512STodor Tomov ret = ov7251_write_reg(ov7251, OV7251_TIMING_FORMAT2, val); 959d30bb512STodor Tomov if (!ret) 960d30bb512STodor Tomov ov7251->timing_format2 = val; 961d30bb512STodor Tomov 962d30bb512STodor Tomov return ret; 963d30bb512STodor Tomov } 964d30bb512STodor Tomov 965d30bb512STodor Tomov static int ov7251_set_vflip(struct ov7251 *ov7251, s32 value) 966d30bb512STodor Tomov { 967d30bb512STodor Tomov u8 val = ov7251->timing_format1; 968d30bb512STodor Tomov int ret; 969d30bb512STodor Tomov 970d30bb512STodor Tomov if (value) 971d30bb512STodor Tomov val |= OV7251_TIMING_FORMAT1_VFLIP; 972d30bb512STodor Tomov else 973d30bb512STodor Tomov val &= ~OV7251_TIMING_FORMAT1_VFLIP; 974d30bb512STodor Tomov 975d30bb512STodor Tomov ret = ov7251_write_reg(ov7251, OV7251_TIMING_FORMAT1, val); 976d30bb512STodor Tomov if (!ret) 977d30bb512STodor Tomov ov7251->timing_format1 = val; 978d30bb512STodor Tomov 979d30bb512STodor Tomov return ret; 980d30bb512STodor Tomov } 981d30bb512STodor Tomov 982d30bb512STodor Tomov static int ov7251_set_test_pattern(struct ov7251 *ov7251, s32 value) 983d30bb512STodor Tomov { 984d30bb512STodor Tomov u8 val = ov7251->pre_isp_00; 985d30bb512STodor Tomov int ret; 986d30bb512STodor Tomov 987d30bb512STodor Tomov if (value) 988d30bb512STodor Tomov val |= OV7251_PRE_ISP_00_TEST_PATTERN; 989d30bb512STodor Tomov else 990d30bb512STodor Tomov val &= ~OV7251_PRE_ISP_00_TEST_PATTERN; 991d30bb512STodor Tomov 992d30bb512STodor Tomov ret = ov7251_write_reg(ov7251, OV7251_PRE_ISP_00, val); 993d30bb512STodor Tomov if (!ret) 994d30bb512STodor Tomov ov7251->pre_isp_00 = val; 995d30bb512STodor Tomov 996d30bb512STodor Tomov return ret; 997d30bb512STodor Tomov } 998d30bb512STodor Tomov 999d30bb512STodor Tomov static const char * const ov7251_test_pattern_menu[] = { 1000d30bb512STodor Tomov "Disabled", 1001d30bb512STodor Tomov "Vertical Pattern Bars", 1002d30bb512STodor Tomov }; 1003d30bb512STodor Tomov 1004d30bb512STodor Tomov static int ov7251_s_ctrl(struct v4l2_ctrl *ctrl) 1005d30bb512STodor Tomov { 1006d30bb512STodor Tomov struct ov7251 *ov7251 = container_of(ctrl->handler, 1007d30bb512STodor Tomov struct ov7251, ctrls); 1008d30bb512STodor Tomov int ret; 1009d30bb512STodor Tomov 1010d30bb512STodor Tomov /* v4l2_ctrl_lock() locks our mutex */ 1011d30bb512STodor Tomov 1012207f4162SDaniel Scally if (!pm_runtime_get_if_in_use(ov7251->dev)) 1013d30bb512STodor Tomov return 0; 1014d30bb512STodor Tomov 1015d30bb512STodor Tomov switch (ctrl->id) { 1016d30bb512STodor Tomov case V4L2_CID_EXPOSURE: 1017d30bb512STodor Tomov ret = ov7251_set_exposure(ov7251, ctrl->val); 1018d30bb512STodor Tomov break; 1019d30bb512STodor Tomov case V4L2_CID_GAIN: 1020d30bb512STodor Tomov ret = ov7251_set_gain(ov7251, ctrl->val); 1021d30bb512STodor Tomov break; 1022d30bb512STodor Tomov case V4L2_CID_TEST_PATTERN: 1023d30bb512STodor Tomov ret = ov7251_set_test_pattern(ov7251, ctrl->val); 1024d30bb512STodor Tomov break; 1025d30bb512STodor Tomov case V4L2_CID_HFLIP: 1026d30bb512STodor Tomov ret = ov7251_set_hflip(ov7251, ctrl->val); 1027d30bb512STodor Tomov break; 1028d30bb512STodor Tomov case V4L2_CID_VFLIP: 1029d30bb512STodor Tomov ret = ov7251_set_vflip(ov7251, ctrl->val); 1030d30bb512STodor Tomov break; 1031d30bb512STodor Tomov default: 1032d30bb512STodor Tomov ret = -EINVAL; 1033d30bb512STodor Tomov break; 1034d30bb512STodor Tomov } 1035d30bb512STodor Tomov 1036207f4162SDaniel Scally pm_runtime_put(ov7251->dev); 1037207f4162SDaniel Scally 1038d30bb512STodor Tomov return ret; 1039d30bb512STodor Tomov } 1040d30bb512STodor Tomov 1041d30bb512STodor Tomov static const struct v4l2_ctrl_ops ov7251_ctrl_ops = { 1042d30bb512STodor Tomov .s_ctrl = ov7251_s_ctrl, 1043d30bb512STodor Tomov }; 1044d30bb512STodor Tomov 1045d30bb512STodor Tomov static int ov7251_enum_mbus_code(struct v4l2_subdev *sd, 10460d346d2aSTomi Valkeinen struct v4l2_subdev_state *sd_state, 1047d30bb512STodor Tomov struct v4l2_subdev_mbus_code_enum *code) 1048d30bb512STodor Tomov { 1049d30bb512STodor Tomov if (code->index > 0) 1050d30bb512STodor Tomov return -EINVAL; 1051d30bb512STodor Tomov 1052d30bb512STodor Tomov code->code = MEDIA_BUS_FMT_Y10_1X10; 1053d30bb512STodor Tomov 1054d30bb512STodor Tomov return 0; 1055d30bb512STodor Tomov } 1056d30bb512STodor Tomov 1057d30bb512STodor Tomov static int ov7251_enum_frame_size(struct v4l2_subdev *subdev, 10580d346d2aSTomi Valkeinen struct v4l2_subdev_state *sd_state, 1059d30bb512STodor Tomov struct v4l2_subdev_frame_size_enum *fse) 1060d30bb512STodor Tomov { 1061d30bb512STodor Tomov if (fse->code != MEDIA_BUS_FMT_Y10_1X10) 1062d30bb512STodor Tomov return -EINVAL; 1063d30bb512STodor Tomov 1064d30bb512STodor Tomov if (fse->index >= ARRAY_SIZE(ov7251_mode_info_data)) 1065d30bb512STodor Tomov return -EINVAL; 1066d30bb512STodor Tomov 1067d30bb512STodor Tomov fse->min_width = ov7251_mode_info_data[fse->index].width; 1068d30bb512STodor Tomov fse->max_width = ov7251_mode_info_data[fse->index].width; 1069d30bb512STodor Tomov fse->min_height = ov7251_mode_info_data[fse->index].height; 1070d30bb512STodor Tomov fse->max_height = ov7251_mode_info_data[fse->index].height; 1071d30bb512STodor Tomov 1072d30bb512STodor Tomov return 0; 1073d30bb512STodor Tomov } 1074d30bb512STodor Tomov 1075d30bb512STodor Tomov static int ov7251_enum_frame_ival(struct v4l2_subdev *subdev, 10760d346d2aSTomi Valkeinen struct v4l2_subdev_state *sd_state, 1077d30bb512STodor Tomov struct v4l2_subdev_frame_interval_enum *fie) 1078d30bb512STodor Tomov { 1079d30bb512STodor Tomov unsigned int index = fie->index; 1080d30bb512STodor Tomov unsigned int i; 1081d30bb512STodor Tomov 1082d30bb512STodor Tomov for (i = 0; i < ARRAY_SIZE(ov7251_mode_info_data); i++) { 1083d30bb512STodor Tomov if (fie->width != ov7251_mode_info_data[i].width || 1084d30bb512STodor Tomov fie->height != ov7251_mode_info_data[i].height) 1085d30bb512STodor Tomov continue; 1086d30bb512STodor Tomov 1087d30bb512STodor Tomov if (index-- == 0) { 1088d30bb512STodor Tomov fie->interval = ov7251_mode_info_data[i].timeperframe; 1089d30bb512STodor Tomov return 0; 1090d30bb512STodor Tomov } 1091d30bb512STodor Tomov } 1092d30bb512STodor Tomov 1093d30bb512STodor Tomov return -EINVAL; 1094d30bb512STodor Tomov } 1095d30bb512STodor Tomov 1096d30bb512STodor Tomov static struct v4l2_mbus_framefmt * 1097d30bb512STodor Tomov __ov7251_get_pad_format(struct ov7251 *ov7251, 10980d346d2aSTomi Valkeinen struct v4l2_subdev_state *sd_state, 1099d30bb512STodor Tomov unsigned int pad, 1100d30bb512STodor Tomov enum v4l2_subdev_format_whence which) 1101d30bb512STodor Tomov { 1102d30bb512STodor Tomov switch (which) { 1103d30bb512STodor Tomov case V4L2_SUBDEV_FORMAT_TRY: 11040d346d2aSTomi Valkeinen return v4l2_subdev_get_try_format(&ov7251->sd, sd_state, pad); 1105d30bb512STodor Tomov case V4L2_SUBDEV_FORMAT_ACTIVE: 1106d30bb512STodor Tomov return &ov7251->fmt; 1107d30bb512STodor Tomov default: 1108d30bb512STodor Tomov return NULL; 1109d30bb512STodor Tomov } 1110d30bb512STodor Tomov } 1111d30bb512STodor Tomov 1112d30bb512STodor Tomov static int ov7251_get_format(struct v4l2_subdev *sd, 11130d346d2aSTomi Valkeinen struct v4l2_subdev_state *sd_state, 1114d30bb512STodor Tomov struct v4l2_subdev_format *format) 1115d30bb512STodor Tomov { 1116d30bb512STodor Tomov struct ov7251 *ov7251 = to_ov7251(sd); 1117d30bb512STodor Tomov 1118d30bb512STodor Tomov mutex_lock(&ov7251->lock); 11190d346d2aSTomi Valkeinen format->format = *__ov7251_get_pad_format(ov7251, sd_state, 11200d346d2aSTomi Valkeinen format->pad, 1121d30bb512STodor Tomov format->which); 1122d30bb512STodor Tomov mutex_unlock(&ov7251->lock); 1123d30bb512STodor Tomov 1124d30bb512STodor Tomov return 0; 1125d30bb512STodor Tomov } 1126d30bb512STodor Tomov 1127d30bb512STodor Tomov static struct v4l2_rect * 11280d346d2aSTomi Valkeinen __ov7251_get_pad_crop(struct ov7251 *ov7251, 11290d346d2aSTomi Valkeinen struct v4l2_subdev_state *sd_state, 1130d30bb512STodor Tomov unsigned int pad, enum v4l2_subdev_format_whence which) 1131d30bb512STodor Tomov { 1132d30bb512STodor Tomov switch (which) { 1133d30bb512STodor Tomov case V4L2_SUBDEV_FORMAT_TRY: 11340d346d2aSTomi Valkeinen return v4l2_subdev_get_try_crop(&ov7251->sd, sd_state, pad); 1135d30bb512STodor Tomov case V4L2_SUBDEV_FORMAT_ACTIVE: 1136d30bb512STodor Tomov return &ov7251->crop; 1137d30bb512STodor Tomov default: 1138d30bb512STodor Tomov return NULL; 1139d30bb512STodor Tomov } 1140d30bb512STodor Tomov } 1141d30bb512STodor Tomov 1142d30bb512STodor Tomov static inline u32 avg_fps(const struct v4l2_fract *t) 1143d30bb512STodor Tomov { 1144d30bb512STodor Tomov return (t->denominator + (t->numerator >> 1)) / t->numerator; 1145d30bb512STodor Tomov } 1146d30bb512STodor Tomov 1147d30bb512STodor Tomov static const struct ov7251_mode_info * 1148d30bb512STodor Tomov ov7251_find_mode_by_ival(struct ov7251 *ov7251, struct v4l2_fract *timeperframe) 1149d30bb512STodor Tomov { 1150d30bb512STodor Tomov const struct ov7251_mode_info *mode = ov7251->current_mode; 1151d30bb512STodor Tomov unsigned int fps_req = avg_fps(timeperframe); 1152d30bb512STodor Tomov unsigned int max_dist_match = (unsigned int) -1; 1153d30bb512STodor Tomov unsigned int i, n = 0; 1154d30bb512STodor Tomov 1155d30bb512STodor Tomov for (i = 0; i < ARRAY_SIZE(ov7251_mode_info_data); i++) { 1156d30bb512STodor Tomov unsigned int dist; 1157d30bb512STodor Tomov unsigned int fps_tmp; 1158d30bb512STodor Tomov 1159d30bb512STodor Tomov if (mode->width != ov7251_mode_info_data[i].width || 1160d30bb512STodor Tomov mode->height != ov7251_mode_info_data[i].height) 1161d30bb512STodor Tomov continue; 1162d30bb512STodor Tomov 1163d30bb512STodor Tomov fps_tmp = avg_fps(&ov7251_mode_info_data[i].timeperframe); 1164d30bb512STodor Tomov 1165d30bb512STodor Tomov dist = abs(fps_req - fps_tmp); 1166d30bb512STodor Tomov 1167d30bb512STodor Tomov if (dist < max_dist_match) { 1168d30bb512STodor Tomov n = i; 1169d30bb512STodor Tomov max_dist_match = dist; 1170d30bb512STodor Tomov } 1171d30bb512STodor Tomov } 1172d30bb512STodor Tomov 1173d30bb512STodor Tomov return &ov7251_mode_info_data[n]; 1174d30bb512STodor Tomov } 1175d30bb512STodor Tomov 1176d30bb512STodor Tomov static int ov7251_set_format(struct v4l2_subdev *sd, 11770d346d2aSTomi Valkeinen struct v4l2_subdev_state *sd_state, 1178d30bb512STodor Tomov struct v4l2_subdev_format *format) 1179d30bb512STodor Tomov { 1180d30bb512STodor Tomov struct ov7251 *ov7251 = to_ov7251(sd); 1181d30bb512STodor Tomov struct v4l2_mbus_framefmt *__format; 1182d30bb512STodor Tomov struct v4l2_rect *__crop; 1183d30bb512STodor Tomov const struct ov7251_mode_info *new_mode; 1184d30bb512STodor Tomov int ret = 0; 1185d30bb512STodor Tomov 1186d30bb512STodor Tomov mutex_lock(&ov7251->lock); 1187d30bb512STodor Tomov 11880d346d2aSTomi Valkeinen __crop = __ov7251_get_pad_crop(ov7251, sd_state, format->pad, 11890d346d2aSTomi Valkeinen format->which); 1190d30bb512STodor Tomov 1191d30bb512STodor Tomov new_mode = v4l2_find_nearest_size(ov7251_mode_info_data, 1192d30bb512STodor Tomov ARRAY_SIZE(ov7251_mode_info_data), 1193d30bb512STodor Tomov width, height, 1194d30bb512STodor Tomov format->format.width, format->format.height); 1195d30bb512STodor Tomov 1196d30bb512STodor Tomov __crop->width = new_mode->width; 1197d30bb512STodor Tomov __crop->height = new_mode->height; 1198d30bb512STodor Tomov 1199d30bb512STodor Tomov if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 1200d30bb512STodor Tomov ret = __v4l2_ctrl_modify_range(ov7251->exposure, 1201d30bb512STodor Tomov 1, new_mode->exposure_max, 1202d30bb512STodor Tomov 1, new_mode->exposure_def); 1203d30bb512STodor Tomov if (ret < 0) 1204d30bb512STodor Tomov goto exit; 1205d30bb512STodor Tomov 1206d30bb512STodor Tomov ret = __v4l2_ctrl_s_ctrl(ov7251->exposure, 1207d30bb512STodor Tomov new_mode->exposure_def); 1208d30bb512STodor Tomov if (ret < 0) 1209d30bb512STodor Tomov goto exit; 1210d30bb512STodor Tomov 1211d30bb512STodor Tomov ret = __v4l2_ctrl_s_ctrl(ov7251->gain, 16); 1212d30bb512STodor Tomov if (ret < 0) 1213d30bb512STodor Tomov goto exit; 1214d30bb512STodor Tomov 1215d30bb512STodor Tomov ov7251->current_mode = new_mode; 1216d30bb512STodor Tomov } 1217d30bb512STodor Tomov 12180d346d2aSTomi Valkeinen __format = __ov7251_get_pad_format(ov7251, sd_state, format->pad, 1219d30bb512STodor Tomov format->which); 1220d30bb512STodor Tomov __format->width = __crop->width; 1221d30bb512STodor Tomov __format->height = __crop->height; 1222d30bb512STodor Tomov __format->code = MEDIA_BUS_FMT_Y10_1X10; 1223d30bb512STodor Tomov __format->field = V4L2_FIELD_NONE; 1224d30bb512STodor Tomov __format->colorspace = V4L2_COLORSPACE_SRGB; 1225d30bb512STodor Tomov __format->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(__format->colorspace); 1226d30bb512STodor Tomov __format->quantization = V4L2_MAP_QUANTIZATION_DEFAULT(true, 1227d30bb512STodor Tomov __format->colorspace, __format->ycbcr_enc); 1228d30bb512STodor Tomov __format->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(__format->colorspace); 1229d30bb512STodor Tomov 1230d30bb512STodor Tomov format->format = *__format; 1231d30bb512STodor Tomov 1232d30bb512STodor Tomov exit: 1233d30bb512STodor Tomov mutex_unlock(&ov7251->lock); 1234d30bb512STodor Tomov 1235d30bb512STodor Tomov return ret; 1236d30bb512STodor Tomov } 1237d30bb512STodor Tomov 1238d30bb512STodor Tomov static int ov7251_entity_init_cfg(struct v4l2_subdev *subdev, 12390d346d2aSTomi Valkeinen struct v4l2_subdev_state *sd_state) 1240d30bb512STodor Tomov { 1241d30bb512STodor Tomov struct v4l2_subdev_format fmt = { 12420d346d2aSTomi Valkeinen .which = sd_state ? V4L2_SUBDEV_FORMAT_TRY 1243d30bb512STodor Tomov : V4L2_SUBDEV_FORMAT_ACTIVE, 1244d30bb512STodor Tomov .format = { 1245d30bb512STodor Tomov .width = 640, 1246d30bb512STodor Tomov .height = 480 1247d30bb512STodor Tomov } 1248d30bb512STodor Tomov }; 1249d30bb512STodor Tomov 12500d346d2aSTomi Valkeinen ov7251_set_format(subdev, sd_state, &fmt); 1251d30bb512STodor Tomov 1252d30bb512STodor Tomov return 0; 1253d30bb512STodor Tomov } 1254d30bb512STodor Tomov 1255d30bb512STodor Tomov static int ov7251_get_selection(struct v4l2_subdev *sd, 12560d346d2aSTomi Valkeinen struct v4l2_subdev_state *sd_state, 1257d30bb512STodor Tomov struct v4l2_subdev_selection *sel) 1258d30bb512STodor Tomov { 1259d30bb512STodor Tomov struct ov7251 *ov7251 = to_ov7251(sd); 1260d30bb512STodor Tomov 126177ec83cdSDaniel Scally switch (sel->target) { 126277ec83cdSDaniel Scally case V4L2_SEL_TGT_CROP_DEFAULT: 126377ec83cdSDaniel Scally case V4L2_SEL_TGT_CROP: 1264d30bb512STodor Tomov mutex_lock(&ov7251->lock); 12650d346d2aSTomi Valkeinen sel->r = *__ov7251_get_pad_crop(ov7251, sd_state, sel->pad, 1266d30bb512STodor Tomov sel->which); 1267d30bb512STodor Tomov mutex_unlock(&ov7251->lock); 126877ec83cdSDaniel Scally break; 126977ec83cdSDaniel Scally case V4L2_SEL_TGT_NATIVE_SIZE: 127077ec83cdSDaniel Scally sel->r.top = 0; 127177ec83cdSDaniel Scally sel->r.left = 0; 127277ec83cdSDaniel Scally sel->r.width = OV7251_NATIVE_WIDTH; 127377ec83cdSDaniel Scally sel->r.height = OV7251_NATIVE_HEIGHT; 127477ec83cdSDaniel Scally break; 127577ec83cdSDaniel Scally case V4L2_SEL_TGT_CROP_BOUNDS: 127677ec83cdSDaniel Scally sel->r.top = OV7251_ACTIVE_START_TOP; 127777ec83cdSDaniel Scally sel->r.left = OV7251_ACTIVE_START_LEFT; 127877ec83cdSDaniel Scally sel->r.width = OV7251_ACTIVE_WIDTH; 127977ec83cdSDaniel Scally sel->r.height = OV7251_ACTIVE_HEIGHT; 128077ec83cdSDaniel Scally break; 128177ec83cdSDaniel Scally default: 128277ec83cdSDaniel Scally return -EINVAL; 128377ec83cdSDaniel Scally } 1284d30bb512STodor Tomov 1285d30bb512STodor Tomov return 0; 1286d30bb512STodor Tomov } 1287d30bb512STodor Tomov 1288d30bb512STodor Tomov static int ov7251_s_stream(struct v4l2_subdev *subdev, int enable) 1289d30bb512STodor Tomov { 1290d30bb512STodor Tomov struct ov7251 *ov7251 = to_ov7251(subdev); 1291d30bb512STodor Tomov int ret; 1292d30bb512STodor Tomov 1293d30bb512STodor Tomov mutex_lock(&ov7251->lock); 1294d30bb512STodor Tomov 1295d30bb512STodor Tomov if (enable) { 1296207f4162SDaniel Scally ret = pm_runtime_get_sync(ov7251->dev); 1297207f4162SDaniel Scally if (ret < 0) 1298207f4162SDaniel Scally goto unlock_out; 1299207f4162SDaniel Scally 1300df057b0dSDaniel Scally ret = ov7251_pll_configure(ov7251); 1301207f4162SDaniel Scally if (ret) { 1302207f4162SDaniel Scally dev_err(ov7251->dev, "error configuring PLLs\n"); 1303207f4162SDaniel Scally goto err_power_down; 1304207f4162SDaniel Scally } 1305df057b0dSDaniel Scally 1306d30bb512STodor Tomov ret = ov7251_set_register_array(ov7251, 1307d30bb512STodor Tomov ov7251->current_mode->data, 1308d30bb512STodor Tomov ov7251->current_mode->data_size); 1309d30bb512STodor Tomov if (ret < 0) { 1310d30bb512STodor Tomov dev_err(ov7251->dev, "could not set mode %dx%d\n", 1311d30bb512STodor Tomov ov7251->current_mode->width, 1312d30bb512STodor Tomov ov7251->current_mode->height); 1313207f4162SDaniel Scally goto err_power_down; 1314d30bb512STodor Tomov } 1315d30bb512STodor Tomov ret = __v4l2_ctrl_handler_setup(&ov7251->ctrls); 1316d30bb512STodor Tomov if (ret < 0) { 1317d30bb512STodor Tomov dev_err(ov7251->dev, "could not sync v4l2 controls\n"); 1318207f4162SDaniel Scally goto err_power_down; 1319d30bb512STodor Tomov } 1320d30bb512STodor Tomov ret = ov7251_write_reg(ov7251, OV7251_SC_MODE_SELECT, 1321d30bb512STodor Tomov OV7251_SC_MODE_SELECT_STREAMING); 1322207f4162SDaniel Scally if (ret) 1323207f4162SDaniel Scally goto err_power_down; 1324d30bb512STodor Tomov } else { 1325d30bb512STodor Tomov ret = ov7251_write_reg(ov7251, OV7251_SC_MODE_SELECT, 1326d30bb512STodor Tomov OV7251_SC_MODE_SELECT_SW_STANDBY); 1327207f4162SDaniel Scally pm_runtime_put(ov7251->dev); 1328d30bb512STodor Tomov } 1329d30bb512STodor Tomov 1330207f4162SDaniel Scally unlock_out: 1331d30bb512STodor Tomov mutex_unlock(&ov7251->lock); 1332207f4162SDaniel Scally return ret; 1333d30bb512STodor Tomov 1334207f4162SDaniel Scally err_power_down: 1335207f4162SDaniel Scally pm_runtime_put_noidle(ov7251->dev); 1336d30bb512STodor Tomov return ret; 1337d30bb512STodor Tomov } 1338d30bb512STodor Tomov 1339d30bb512STodor Tomov static int ov7251_get_frame_interval(struct v4l2_subdev *subdev, 1340d30bb512STodor Tomov struct v4l2_subdev_frame_interval *fi) 1341d30bb512STodor Tomov { 1342d30bb512STodor Tomov struct ov7251 *ov7251 = to_ov7251(subdev); 1343d30bb512STodor Tomov 1344d30bb512STodor Tomov mutex_lock(&ov7251->lock); 1345d30bb512STodor Tomov fi->interval = ov7251->current_mode->timeperframe; 1346d30bb512STodor Tomov mutex_unlock(&ov7251->lock); 1347d30bb512STodor Tomov 1348d30bb512STodor Tomov return 0; 1349d30bb512STodor Tomov } 1350d30bb512STodor Tomov 1351d30bb512STodor Tomov static int ov7251_set_frame_interval(struct v4l2_subdev *subdev, 1352d30bb512STodor Tomov struct v4l2_subdev_frame_interval *fi) 1353d30bb512STodor Tomov { 1354d30bb512STodor Tomov struct ov7251 *ov7251 = to_ov7251(subdev); 1355d30bb512STodor Tomov const struct ov7251_mode_info *new_mode; 1356d30bb512STodor Tomov int ret = 0; 1357d30bb512STodor Tomov 1358d30bb512STodor Tomov mutex_lock(&ov7251->lock); 1359d30bb512STodor Tomov new_mode = ov7251_find_mode_by_ival(ov7251, &fi->interval); 1360d30bb512STodor Tomov 1361d30bb512STodor Tomov if (new_mode != ov7251->current_mode) { 1362d30bb512STodor Tomov ret = __v4l2_ctrl_modify_range(ov7251->exposure, 1363d30bb512STodor Tomov 1, new_mode->exposure_max, 1364d30bb512STodor Tomov 1, new_mode->exposure_def); 1365d30bb512STodor Tomov if (ret < 0) 1366d30bb512STodor Tomov goto exit; 1367d30bb512STodor Tomov 1368d30bb512STodor Tomov ret = __v4l2_ctrl_s_ctrl(ov7251->exposure, 1369d30bb512STodor Tomov new_mode->exposure_def); 1370d30bb512STodor Tomov if (ret < 0) 1371d30bb512STodor Tomov goto exit; 1372d30bb512STodor Tomov 1373d30bb512STodor Tomov ret = __v4l2_ctrl_s_ctrl(ov7251->gain, 16); 1374d30bb512STodor Tomov if (ret < 0) 1375d30bb512STodor Tomov goto exit; 1376d30bb512STodor Tomov 1377d30bb512STodor Tomov ov7251->current_mode = new_mode; 1378d30bb512STodor Tomov } 1379d30bb512STodor Tomov 1380d30bb512STodor Tomov fi->interval = ov7251->current_mode->timeperframe; 1381d30bb512STodor Tomov 1382d30bb512STodor Tomov exit: 1383d30bb512STodor Tomov mutex_unlock(&ov7251->lock); 1384d30bb512STodor Tomov 1385d30bb512STodor Tomov return ret; 1386d30bb512STodor Tomov } 1387d30bb512STodor Tomov 1388d30bb512STodor Tomov static const struct v4l2_subdev_video_ops ov7251_video_ops = { 1389d30bb512STodor Tomov .s_stream = ov7251_s_stream, 1390d30bb512STodor Tomov .g_frame_interval = ov7251_get_frame_interval, 1391d30bb512STodor Tomov .s_frame_interval = ov7251_set_frame_interval, 1392d30bb512STodor Tomov }; 1393d30bb512STodor Tomov 1394d30bb512STodor Tomov static const struct v4l2_subdev_pad_ops ov7251_subdev_pad_ops = { 1395d30bb512STodor Tomov .init_cfg = ov7251_entity_init_cfg, 1396d30bb512STodor Tomov .enum_mbus_code = ov7251_enum_mbus_code, 1397d30bb512STodor Tomov .enum_frame_size = ov7251_enum_frame_size, 1398d30bb512STodor Tomov .enum_frame_interval = ov7251_enum_frame_ival, 1399d30bb512STodor Tomov .get_fmt = ov7251_get_format, 1400d30bb512STodor Tomov .set_fmt = ov7251_set_format, 1401d30bb512STodor Tomov .get_selection = ov7251_get_selection, 1402d30bb512STodor Tomov }; 1403d30bb512STodor Tomov 1404d30bb512STodor Tomov static const struct v4l2_subdev_ops ov7251_subdev_ops = { 1405d30bb512STodor Tomov .video = &ov7251_video_ops, 1406d30bb512STodor Tomov .pad = &ov7251_subdev_pad_ops, 1407d30bb512STodor Tomov }; 1408d30bb512STodor Tomov 1409cc125aaaSDaniel Scally static int ov7251_check_hwcfg(struct ov7251 *ov7251) 1410cc125aaaSDaniel Scally { 1411cc125aaaSDaniel Scally struct fwnode_handle *fwnode = dev_fwnode(ov7251->dev); 1412cc125aaaSDaniel Scally struct v4l2_fwnode_endpoint bus_cfg = { 1413cc125aaaSDaniel Scally .bus_type = V4L2_MBUS_CSI2_DPHY, 1414cc125aaaSDaniel Scally }; 1415cc125aaaSDaniel Scally struct fwnode_handle *endpoint; 1416cc125aaaSDaniel Scally unsigned int i, j; 1417cc125aaaSDaniel Scally int ret; 1418cc125aaaSDaniel Scally 1419cc125aaaSDaniel Scally endpoint = fwnode_graph_get_next_endpoint(fwnode, NULL); 1420cc125aaaSDaniel Scally if (!endpoint) 1421cc125aaaSDaniel Scally return -EPROBE_DEFER; /* could be provided by cio2-bridge */ 1422cc125aaaSDaniel Scally 1423cc125aaaSDaniel Scally ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &bus_cfg); 1424cc125aaaSDaniel Scally fwnode_handle_put(endpoint); 1425cc125aaaSDaniel Scally if (ret) 1426cc125aaaSDaniel Scally return dev_err_probe(ov7251->dev, ret, 1427cc125aaaSDaniel Scally "parsing endpoint node failed\n"); 1428cc125aaaSDaniel Scally 1429cc125aaaSDaniel Scally if (!bus_cfg.nr_of_link_frequencies) { 1430cc125aaaSDaniel Scally ret = dev_err_probe(ov7251->dev, -EINVAL, 1431cc125aaaSDaniel Scally "no link frequencies defined\n"); 1432cc125aaaSDaniel Scally goto out_free_bus_cfg; 1433cc125aaaSDaniel Scally } 1434cc125aaaSDaniel Scally 1435cc125aaaSDaniel Scally for (i = 0; i < bus_cfg.nr_of_link_frequencies; i++) { 1436cc125aaaSDaniel Scally for (j = 0; j < ARRAY_SIZE(link_freq); j++) 1437cc125aaaSDaniel Scally if (bus_cfg.link_frequencies[i] == link_freq[j]) 1438cc125aaaSDaniel Scally break; 1439cc125aaaSDaniel Scally 1440cc125aaaSDaniel Scally if (j < ARRAY_SIZE(link_freq)) 1441cc125aaaSDaniel Scally break; 1442cc125aaaSDaniel Scally } 1443cc125aaaSDaniel Scally 1444cc125aaaSDaniel Scally if (i == bus_cfg.nr_of_link_frequencies) { 1445cc125aaaSDaniel Scally ret = dev_err_probe(ov7251->dev, -EINVAL, 1446cc125aaaSDaniel Scally "no supported link freq found\n"); 1447cc125aaaSDaniel Scally goto out_free_bus_cfg; 1448cc125aaaSDaniel Scally } 1449cc125aaaSDaniel Scally 1450cc125aaaSDaniel Scally ov7251->link_freq_idx = i; 1451cc125aaaSDaniel Scally 1452cc125aaaSDaniel Scally out_free_bus_cfg: 1453cc125aaaSDaniel Scally v4l2_fwnode_endpoint_free(&bus_cfg); 1454cc125aaaSDaniel Scally 1455cc125aaaSDaniel Scally return ret; 1456cc125aaaSDaniel Scally } 1457cc125aaaSDaniel Scally 1458e92932c3SDaniel Scally static int ov7251_detect_chip(struct ov7251 *ov7251) 1459e92932c3SDaniel Scally { 1460e92932c3SDaniel Scally u8 chip_id_high, chip_id_low, chip_rev; 1461e92932c3SDaniel Scally int ret; 1462e92932c3SDaniel Scally 1463e92932c3SDaniel Scally ret = ov7251_read_reg(ov7251, OV7251_CHIP_ID_HIGH, &chip_id_high); 1464e92932c3SDaniel Scally if (ret < 0 || chip_id_high != OV7251_CHIP_ID_HIGH_BYTE) 1465e92932c3SDaniel Scally return dev_err_probe(ov7251->dev, -ENODEV, 1466e92932c3SDaniel Scally "could not read ID high\n"); 1467e92932c3SDaniel Scally 1468e92932c3SDaniel Scally ret = ov7251_read_reg(ov7251, OV7251_CHIP_ID_LOW, &chip_id_low); 1469e92932c3SDaniel Scally if (ret < 0 || chip_id_low != OV7251_CHIP_ID_LOW_BYTE) 1470e92932c3SDaniel Scally return dev_err_probe(ov7251->dev, -ENODEV, 1471e92932c3SDaniel Scally "could not read ID low\n"); 1472e92932c3SDaniel Scally 1473e92932c3SDaniel Scally ret = ov7251_read_reg(ov7251, OV7251_SC_GP_IO_IN1, &chip_rev); 1474e92932c3SDaniel Scally if (ret < 0) 1475e92932c3SDaniel Scally return dev_err_probe(ov7251->dev, -ENODEV, 1476e92932c3SDaniel Scally "could not read revision\n"); 1477e92932c3SDaniel Scally chip_rev >>= 4; 1478e92932c3SDaniel Scally 1479e92932c3SDaniel Scally dev_info(ov7251->dev, 1480e92932c3SDaniel Scally "OV7251 revision %x (%s) detected at address 0x%02x\n", 1481e92932c3SDaniel Scally chip_rev, 1482e92932c3SDaniel Scally chip_rev == 0x4 ? "1A / 1B" : 1483e92932c3SDaniel Scally chip_rev == 0x5 ? "1C / 1D" : 1484e92932c3SDaniel Scally chip_rev == 0x6 ? "1E" : 1485e92932c3SDaniel Scally chip_rev == 0x7 ? "1F" : "unknown", 1486e92932c3SDaniel Scally ov7251->i2c_client->addr); 1487e92932c3SDaniel Scally 1488e92932c3SDaniel Scally return 0; 1489e92932c3SDaniel Scally } 1490e92932c3SDaniel Scally 14915aaef13dSDaniel Scally static int ov7251_init_ctrls(struct ov7251 *ov7251) 14925aaef13dSDaniel Scally { 14935aaef13dSDaniel Scally s64 pixel_rate; 1494*26066ae6SDaniel Scally int hblank; 14955aaef13dSDaniel Scally 14965aaef13dSDaniel Scally v4l2_ctrl_handler_init(&ov7251->ctrls, 7); 14975aaef13dSDaniel Scally ov7251->ctrls.lock = &ov7251->lock; 14985aaef13dSDaniel Scally 14995aaef13dSDaniel Scally v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops, 15005aaef13dSDaniel Scally V4L2_CID_HFLIP, 0, 1, 1, 0); 15015aaef13dSDaniel Scally v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops, 15025aaef13dSDaniel Scally V4L2_CID_VFLIP, 0, 1, 1, 0); 15035aaef13dSDaniel Scally ov7251->exposure = v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops, 15045aaef13dSDaniel Scally V4L2_CID_EXPOSURE, 1, 32, 1, 32); 15055aaef13dSDaniel Scally ov7251->gain = v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops, 15065aaef13dSDaniel Scally V4L2_CID_GAIN, 16, 1023, 1, 16); 15075aaef13dSDaniel Scally v4l2_ctrl_new_std_menu_items(&ov7251->ctrls, &ov7251_ctrl_ops, 15085aaef13dSDaniel Scally V4L2_CID_TEST_PATTERN, 15095aaef13dSDaniel Scally ARRAY_SIZE(ov7251_test_pattern_menu) - 1, 15105aaef13dSDaniel Scally 0, 0, ov7251_test_pattern_menu); 15115aaef13dSDaniel Scally 15125aaef13dSDaniel Scally pixel_rate = pixel_rates[ov7251->link_freq_idx]; 15135aaef13dSDaniel Scally ov7251->pixel_clock = v4l2_ctrl_new_std(&ov7251->ctrls, 15145aaef13dSDaniel Scally &ov7251_ctrl_ops, 15155aaef13dSDaniel Scally V4L2_CID_PIXEL_RATE, 15165aaef13dSDaniel Scally pixel_rate, INT_MAX, 15175aaef13dSDaniel Scally pixel_rate, pixel_rate); 15185aaef13dSDaniel Scally ov7251->link_freq = v4l2_ctrl_new_int_menu(&ov7251->ctrls, 15195aaef13dSDaniel Scally &ov7251_ctrl_ops, 15205aaef13dSDaniel Scally V4L2_CID_LINK_FREQ, 15215aaef13dSDaniel Scally ARRAY_SIZE(link_freq) - 1, 15225aaef13dSDaniel Scally ov7251->link_freq_idx, 15235aaef13dSDaniel Scally link_freq); 15245aaef13dSDaniel Scally if (ov7251->link_freq) 15255aaef13dSDaniel Scally ov7251->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 15265aaef13dSDaniel Scally if (ov7251->pixel_clock) 15275aaef13dSDaniel Scally ov7251->pixel_clock->flags |= V4L2_CTRL_FLAG_READ_ONLY; 15285aaef13dSDaniel Scally 1529*26066ae6SDaniel Scally hblank = OV7251_FIXED_PPL - ov7251->current_mode->width; 1530*26066ae6SDaniel Scally ov7251->hblank = v4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops, 1531*26066ae6SDaniel Scally V4L2_CID_HBLANK, hblank, hblank, 1, 1532*26066ae6SDaniel Scally hblank); 1533*26066ae6SDaniel Scally if (ov7251->hblank) 1534*26066ae6SDaniel Scally ov7251->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1535*26066ae6SDaniel Scally 15365aaef13dSDaniel Scally ov7251->sd.ctrl_handler = &ov7251->ctrls; 15375aaef13dSDaniel Scally 15385aaef13dSDaniel Scally if (ov7251->ctrls.error) { 15395aaef13dSDaniel Scally v4l2_ctrl_handler_free(&ov7251->ctrls); 15405aaef13dSDaniel Scally return ov7251->ctrls.error; 15415aaef13dSDaniel Scally } 15425aaef13dSDaniel Scally 15435aaef13dSDaniel Scally return 0; 15445aaef13dSDaniel Scally } 15455aaef13dSDaniel Scally 1546d30bb512STodor Tomov static int ov7251_probe(struct i2c_client *client) 1547d30bb512STodor Tomov { 1548d30bb512STodor Tomov struct device *dev = &client->dev; 1549d30bb512STodor Tomov struct ov7251 *ov7251; 1550ed9566ceSDaniel Scally unsigned int rate = 0, clk_rate = 0; 1551d30bb512STodor Tomov int ret; 1552df057b0dSDaniel Scally int i; 1553d30bb512STodor Tomov 1554d30bb512STodor Tomov ov7251 = devm_kzalloc(dev, sizeof(struct ov7251), GFP_KERNEL); 1555d30bb512STodor Tomov if (!ov7251) 1556d30bb512STodor Tomov return -ENOMEM; 1557d30bb512STodor Tomov 1558d30bb512STodor Tomov ov7251->i2c_client = client; 1559d30bb512STodor Tomov ov7251->dev = dev; 1560d30bb512STodor Tomov 1561cc125aaaSDaniel Scally ret = ov7251_check_hwcfg(ov7251); 1562cc125aaaSDaniel Scally if (ret) 1563d30bb512STodor Tomov return ret; 1564d30bb512STodor Tomov 1565d30bb512STodor Tomov /* get system clock (xclk) */ 1566ed9566ceSDaniel Scally ov7251->xclk = devm_clk_get_optional(dev, NULL); 1567ed9566ceSDaniel Scally if (IS_ERR(ov7251->xclk)) 1568ed9566ceSDaniel Scally return dev_err_probe(dev, PTR_ERR(ov7251->xclk), 1569ed9566ceSDaniel Scally "could not get xclk"); 1570d30bb512STodor Tomov 1571ed9566ceSDaniel Scally /* 1572ed9566ceSDaniel Scally * We could have either a 24MHz or 19.2MHz clock rate from either DT or 1573ed9566ceSDaniel Scally * ACPI. We also need to support the IPU3 case which will have both an 1574ed9566ceSDaniel Scally * external clock AND a clock-frequency property. 1575ed9566ceSDaniel Scally */ 1576d30bb512STodor Tomov ret = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency", 1577ed9566ceSDaniel Scally &rate); 1578ed9566ceSDaniel Scally if (ret && !ov7251->xclk) 1579ed9566ceSDaniel Scally return dev_err_probe(dev, ret, "invalid clock config\n"); 1580ed9566ceSDaniel Scally 1581ed9566ceSDaniel Scally clk_rate = clk_get_rate(ov7251->xclk); 1582ed9566ceSDaniel Scally ov7251->xclk_freq = clk_rate ? clk_rate : rate; 1583ed9566ceSDaniel Scally 1584ed9566ceSDaniel Scally if (ov7251->xclk_freq == 0) 1585ed9566ceSDaniel Scally return dev_err_probe(dev, -EINVAL, "invalid clock frequency\n"); 1586ed9566ceSDaniel Scally 1587ed9566ceSDaniel Scally if (!ret && ov7251->xclk) { 1588ed9566ceSDaniel Scally ret = clk_set_rate(ov7251->xclk, rate); 1589ed9566ceSDaniel Scally if (ret) 1590ed9566ceSDaniel Scally return dev_err_probe(dev, ret, 1591ed9566ceSDaniel Scally "failed to set clock rate\n"); 1592d30bb512STodor Tomov } 1593d30bb512STodor Tomov 1594df057b0dSDaniel Scally for (i = 0; i < ARRAY_SIZE(supported_xclk_rates); i++) 1595df057b0dSDaniel Scally if (ov7251->xclk_freq == supported_xclk_rates[i]) 1596df057b0dSDaniel Scally break; 1597df057b0dSDaniel Scally 1598df057b0dSDaniel Scally if (i == ARRAY_SIZE(supported_xclk_rates)) 1599df057b0dSDaniel Scally return dev_err_probe(dev, -EINVAL, 1600df057b0dSDaniel Scally "clock rate %u Hz is unsupported\n", 1601df057b0dSDaniel Scally ov7251->xclk_freq); 1602df057b0dSDaniel Scally 1603df057b0dSDaniel Scally ov7251->pll_cfgs = ov7251_pll_cfgs[i]; 1604d30bb512STodor Tomov 1605d30bb512STodor Tomov ov7251->io_regulator = devm_regulator_get(dev, "vdddo"); 1606d30bb512STodor Tomov if (IS_ERR(ov7251->io_regulator)) { 1607d30bb512STodor Tomov dev_err(dev, "cannot get io regulator\n"); 1608d30bb512STodor Tomov return PTR_ERR(ov7251->io_regulator); 1609d30bb512STodor Tomov } 1610d30bb512STodor Tomov 1611d30bb512STodor Tomov ov7251->core_regulator = devm_regulator_get(dev, "vddd"); 1612d30bb512STodor Tomov if (IS_ERR(ov7251->core_regulator)) { 1613d30bb512STodor Tomov dev_err(dev, "cannot get core regulator\n"); 1614d30bb512STodor Tomov return PTR_ERR(ov7251->core_regulator); 1615d30bb512STodor Tomov } 1616d30bb512STodor Tomov 1617d30bb512STodor Tomov ov7251->analog_regulator = devm_regulator_get(dev, "vdda"); 1618d30bb512STodor Tomov if (IS_ERR(ov7251->analog_regulator)) { 1619d30bb512STodor Tomov dev_err(dev, "cannot get analog regulator\n"); 1620d30bb512STodor Tomov return PTR_ERR(ov7251->analog_regulator); 1621d30bb512STodor Tomov } 1622d30bb512STodor Tomov 1623d30bb512STodor Tomov ov7251->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_HIGH); 1624d30bb512STodor Tomov if (IS_ERR(ov7251->enable_gpio)) { 1625d30bb512STodor Tomov dev_err(dev, "cannot get enable gpio\n"); 1626d30bb512STodor Tomov return PTR_ERR(ov7251->enable_gpio); 1627d30bb512STodor Tomov } 1628d30bb512STodor Tomov 1629d30bb512STodor Tomov mutex_init(&ov7251->lock); 1630d30bb512STodor Tomov 1631*26066ae6SDaniel Scally ov7251->current_mode = &ov7251_mode_info_data[0]; 16325aaef13dSDaniel Scally ret = ov7251_init_ctrls(ov7251); 16335aaef13dSDaniel Scally if (ret) { 16345aaef13dSDaniel Scally dev_err_probe(dev, ret, "error during v4l2 ctrl init\n"); 16355aaef13dSDaniel Scally goto destroy_mutex; 1636d30bb512STodor Tomov } 1637d30bb512STodor Tomov 1638d30bb512STodor Tomov v4l2_i2c_subdev_init(&ov7251->sd, client, &ov7251_subdev_ops); 1639d30bb512STodor Tomov ov7251->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1640d30bb512STodor Tomov ov7251->pad.flags = MEDIA_PAD_FL_SOURCE; 1641d30bb512STodor Tomov ov7251->sd.dev = &client->dev; 1642d30bb512STodor Tomov ov7251->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1643d30bb512STodor Tomov 1644d30bb512STodor Tomov ret = media_entity_pads_init(&ov7251->sd.entity, 1, &ov7251->pad); 1645d30bb512STodor Tomov if (ret < 0) { 1646d30bb512STodor Tomov dev_err(dev, "could not register media entity\n"); 1647d30bb512STodor Tomov goto free_ctrl; 1648d30bb512STodor Tomov } 1649d30bb512STodor Tomov 1650207f4162SDaniel Scally ret = ov7251_set_power_on(ov7251->dev); 1651207f4162SDaniel Scally if (ret) 1652d30bb512STodor Tomov goto free_entity; 1653d30bb512STodor Tomov 1654e92932c3SDaniel Scally ret = ov7251_detect_chip(ov7251); 1655e92932c3SDaniel Scally if (ret) 1656d30bb512STodor Tomov goto power_down; 1657d30bb512STodor Tomov 1658207f4162SDaniel Scally pm_runtime_set_active(&client->dev); 1659207f4162SDaniel Scally pm_runtime_get_noresume(&client->dev); 1660207f4162SDaniel Scally pm_runtime_enable(&client->dev); 1661d30bb512STodor Tomov 1662d30bb512STodor Tomov ret = ov7251_read_reg(ov7251, OV7251_PRE_ISP_00, 1663d30bb512STodor Tomov &ov7251->pre_isp_00); 1664d30bb512STodor Tomov if (ret < 0) { 1665d30bb512STodor Tomov dev_err(dev, "could not read test pattern value\n"); 1666d30bb512STodor Tomov ret = -ENODEV; 1667207f4162SDaniel Scally goto err_pm_runtime; 1668d30bb512STodor Tomov } 1669d30bb512STodor Tomov 1670d30bb512STodor Tomov ret = ov7251_read_reg(ov7251, OV7251_TIMING_FORMAT1, 1671d30bb512STodor Tomov &ov7251->timing_format1); 1672d30bb512STodor Tomov if (ret < 0) { 1673d30bb512STodor Tomov dev_err(dev, "could not read vflip value\n"); 1674d30bb512STodor Tomov ret = -ENODEV; 1675207f4162SDaniel Scally goto err_pm_runtime; 1676d30bb512STodor Tomov } 1677d30bb512STodor Tomov 1678d30bb512STodor Tomov ret = ov7251_read_reg(ov7251, OV7251_TIMING_FORMAT2, 1679d30bb512STodor Tomov &ov7251->timing_format2); 1680d30bb512STodor Tomov if (ret < 0) { 1681d30bb512STodor Tomov dev_err(dev, "could not read hflip value\n"); 1682d30bb512STodor Tomov ret = -ENODEV; 1683207f4162SDaniel Scally goto err_pm_runtime; 1684d30bb512STodor Tomov } 1685d30bb512STodor Tomov 1686207f4162SDaniel Scally pm_runtime_set_autosuspend_delay(&client->dev, 1000); 1687207f4162SDaniel Scally pm_runtime_use_autosuspend(&client->dev); 1688207f4162SDaniel Scally pm_runtime_put_autosuspend(&client->dev); 1689d30bb512STodor Tomov 1690d30bb512STodor Tomov ret = v4l2_async_register_subdev(&ov7251->sd); 1691d30bb512STodor Tomov if (ret < 0) { 1692d30bb512STodor Tomov dev_err(dev, "could not register v4l2 device\n"); 1693d30bb512STodor Tomov goto free_entity; 1694d30bb512STodor Tomov } 1695d30bb512STodor Tomov 1696d30bb512STodor Tomov ov7251_entity_init_cfg(&ov7251->sd, NULL); 1697d30bb512STodor Tomov 1698d30bb512STodor Tomov return 0; 1699d30bb512STodor Tomov 1700207f4162SDaniel Scally err_pm_runtime: 1701207f4162SDaniel Scally pm_runtime_disable(ov7251->dev); 1702207f4162SDaniel Scally pm_runtime_put_noidle(ov7251->dev); 1703d30bb512STodor Tomov power_down: 1704207f4162SDaniel Scally ov7251_set_power_off(ov7251->dev); 1705d30bb512STodor Tomov free_entity: 1706d30bb512STodor Tomov media_entity_cleanup(&ov7251->sd.entity); 1707d30bb512STodor Tomov free_ctrl: 1708d30bb512STodor Tomov v4l2_ctrl_handler_free(&ov7251->ctrls); 17095aaef13dSDaniel Scally destroy_mutex: 1710d30bb512STodor Tomov mutex_destroy(&ov7251->lock); 1711d30bb512STodor Tomov 1712d30bb512STodor Tomov return ret; 1713d30bb512STodor Tomov } 1714d30bb512STodor Tomov 1715d30bb512STodor Tomov static int ov7251_remove(struct i2c_client *client) 1716d30bb512STodor Tomov { 1717d30bb512STodor Tomov struct v4l2_subdev *sd = i2c_get_clientdata(client); 1718d30bb512STodor Tomov struct ov7251 *ov7251 = to_ov7251(sd); 1719d30bb512STodor Tomov 1720d30bb512STodor Tomov v4l2_async_unregister_subdev(&ov7251->sd); 1721d30bb512STodor Tomov media_entity_cleanup(&ov7251->sd.entity); 1722d30bb512STodor Tomov v4l2_ctrl_handler_free(&ov7251->ctrls); 1723d30bb512STodor Tomov mutex_destroy(&ov7251->lock); 1724d30bb512STodor Tomov 1725207f4162SDaniel Scally pm_runtime_disable(ov7251->dev); 1726207f4162SDaniel Scally if (!pm_runtime_status_suspended(ov7251->dev)) 1727207f4162SDaniel Scally ov7251_set_power_off(ov7251->dev); 1728207f4162SDaniel Scally pm_runtime_set_suspended(ov7251->dev); 1729207f4162SDaniel Scally 1730d30bb512STodor Tomov return 0; 1731d30bb512STodor Tomov } 1732d30bb512STodor Tomov 1733207f4162SDaniel Scally static const struct dev_pm_ops ov7251_pm_ops = { 1734207f4162SDaniel Scally SET_RUNTIME_PM_OPS(ov7251_set_power_off, ov7251_set_power_on, NULL) 1735207f4162SDaniel Scally }; 1736207f4162SDaniel Scally 1737d30bb512STodor Tomov static const struct of_device_id ov7251_of_match[] = { 1738d30bb512STodor Tomov { .compatible = "ovti,ov7251" }, 1739d30bb512STodor Tomov { /* sentinel */ } 1740d30bb512STodor Tomov }; 1741d30bb512STodor Tomov MODULE_DEVICE_TABLE(of, ov7251_of_match); 1742d30bb512STodor Tomov 17436766cff6SDaniel Scally static const struct acpi_device_id ov7251_acpi_match[] = { 17446766cff6SDaniel Scally { "INT347E" }, 17456766cff6SDaniel Scally { } 17466766cff6SDaniel Scally }; 17476766cff6SDaniel Scally MODULE_DEVICE_TABLE(acpi, ov7251_acpi_match); 17486766cff6SDaniel Scally 1749d30bb512STodor Tomov static struct i2c_driver ov7251_i2c_driver = { 1750d30bb512STodor Tomov .driver = { 1751d30bb512STodor Tomov .of_match_table = ov7251_of_match, 17526766cff6SDaniel Scally .acpi_match_table = ov7251_acpi_match, 1753d30bb512STodor Tomov .name = "ov7251", 1754207f4162SDaniel Scally .pm = &ov7251_pm_ops, 1755d30bb512STodor Tomov }, 1756d30bb512STodor Tomov .probe_new = ov7251_probe, 1757d30bb512STodor Tomov .remove = ov7251_remove, 1758d30bb512STodor Tomov }; 1759d30bb512STodor Tomov 1760d30bb512STodor Tomov module_i2c_driver(ov7251_i2c_driver); 1761d30bb512STodor Tomov 1762d30bb512STodor Tomov MODULE_DESCRIPTION("Omnivision OV7251 Camera Driver"); 1763d30bb512STodor Tomov MODULE_AUTHOR("Todor Tomov <todor.tomov@linaro.org>"); 1764d30bb512STodor Tomov MODULE_LICENSE("GPL v2"); 1765