1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2020 Bootlin 4 * Author: Paul Kocialkowski <paul.kocialkowski@bootlin.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/device.h> 10 #include <linux/i2c.h> 11 #include <linux/module.h> 12 #include <linux/of_graph.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/regulator/consumer.h> 15 #include <linux/videodev2.h> 16 #include <media/v4l2-ctrls.h> 17 #include <media/v4l2-device.h> 18 #include <media/v4l2-fwnode.h> 19 #include <media/v4l2-image-sizes.h> 20 #include <media/v4l2-mediabus.h> 21 22 /* Clock rate */ 23 24 #define OV5648_XVCLK_RATE 24000000 25 26 /* Register definitions */ 27 28 /* System */ 29 30 #define OV5648_SW_STANDBY_REG 0x100 31 #define OV5648_SW_STANDBY_STREAM_ON BIT(0) 32 33 #define OV5648_SW_RESET_REG 0x103 34 #define OV5648_SW_RESET_RESET BIT(0) 35 36 #define OV5648_PAD_OEN0_REG 0x3000 37 #define OV5648_PAD_OEN1_REG 0x3001 38 #define OV5648_PAD_OEN2_REG 0x3002 39 #define OV5648_PAD_OUT0_REG 0x3008 40 #define OV5648_PAD_OUT1_REG 0x3009 41 42 #define OV5648_CHIP_ID_H_REG 0x300a 43 #define OV5648_CHIP_ID_H_VALUE 0x56 44 #define OV5648_CHIP_ID_L_REG 0x300b 45 #define OV5648_CHIP_ID_L_VALUE 0x48 46 47 #define OV5648_PAD_OUT2_REG 0x300d 48 #define OV5648_PAD_SEL0_REG 0x300e 49 #define OV5648_PAD_SEL1_REG 0x300f 50 #define OV5648_PAD_SEL2_REG 0x3010 51 #define OV5648_PAD_PK_REG 0x3011 52 #define OV5648_PAD_PK_PD_DATO_EN BIT(7) 53 #define OV5648_PAD_PK_DRIVE_STRENGTH_1X (0 << 5) 54 #define OV5648_PAD_PK_DRIVE_STRENGTH_2X (2 << 5) 55 #define OV5648_PAD_PK_FREX_N BIT(1) 56 57 #define OV5648_A_PWC_PK_O0_REG 0x3013 58 #define OV5648_A_PWC_PK_O0_BP_REGULATOR_N BIT(3) 59 #define OV5648_A_PWC_PK_O1_REG 0x3014 60 61 #define OV5648_MIPI_PHY0_REG 0x3016 62 #define OV5648_MIPI_PHY1_REG 0x3017 63 #define OV5648_MIPI_SC_CTRL0_REG 0x3018 64 #define OV5648_MIPI_SC_CTRL0_MIPI_LANES(v) (((v) << 5) & GENMASK(7, 5)) 65 #define OV5648_MIPI_SC_CTRL0_PHY_HS_TX_PD BIT(4) 66 #define OV5648_MIPI_SC_CTRL0_PHY_LP_RX_PD BIT(3) 67 #define OV5648_MIPI_SC_CTRL0_MIPI_EN BIT(2) 68 #define OV5648_MIPI_SC_CTRL0_MIPI_SUSP BIT(1) 69 #define OV5648_MIPI_SC_CTRL0_LANE_DIS_OP BIT(0) 70 #define OV5648_MIPI_SC_CTRL1_REG 0x3019 71 #define OV5648_MISC_CTRL0_REG 0x3021 72 #define OV5648_MIPI_SC_CTRL2_REG 0x3022 73 #define OV5648_SUB_ID_REG 0x302a 74 75 #define OV5648_PLL_CTRL0_REG 0x3034 76 #define OV5648_PLL_CTRL0_PLL_CHARGE_PUMP(v) (((v) << 4) & GENMASK(6, 4)) 77 #define OV5648_PLL_CTRL0_BITS(v) ((v) & GENMASK(3, 0)) 78 #define OV5648_PLL_CTRL1_REG 0x3035 79 #define OV5648_PLL_CTRL1_SYS_DIV(v) (((v) << 4) & GENMASK(7, 4)) 80 #define OV5648_PLL_CTRL1_MIPI_DIV(v) ((v) & GENMASK(3, 0)) 81 #define OV5648_PLL_MUL_REG 0x3036 82 #define OV5648_PLL_MUL(v) ((v) & GENMASK(7, 0)) 83 #define OV5648_PLL_DIV_REG 0x3037 84 #define OV5648_PLL_DIV_ROOT_DIV(v) ((((v) - 1) << 4) & BIT(4)) 85 #define OV5648_PLL_DIV_PLL_PRE_DIV(v) ((v) & GENMASK(3, 0)) 86 #define OV5648_PLL_DEBUG_REG 0x3038 87 #define OV5648_PLL_BYPASS_REG 0x3039 88 89 #define OV5648_PLLS_BYPASS_REG 0x303a 90 #define OV5648_PLLS_MUL_REG 0x303b 91 #define OV5648_PLLS_MUL(v) ((v) & GENMASK(4, 0)) 92 #define OV5648_PLLS_CTRL_REG 0x303c 93 #define OV5648_PLLS_CTRL_PLL_CHARGE_PUMP(v) (((v) << 4) & GENMASK(6, 4)) 94 #define OV5648_PLLS_CTRL_SYS_DIV(v) ((v) & GENMASK(3, 0)) 95 #define OV5648_PLLS_DIV_REG 0x303d 96 #define OV5648_PLLS_DIV_PLLS_PRE_DIV(v) (((v) << 4) & GENMASK(5, 4)) 97 #define OV5648_PLLS_DIV_PLLS_DIV_R(v) ((((v) - 1) << 2) & BIT(2)) 98 #define OV5648_PLLS_DIV_PLLS_SEL_DIV(v) ((v) & GENMASK(1, 0)) 99 100 #define OV5648_SRB_CTRL_REG 0x3106 101 #define OV5648_SRB_CTRL_SCLK_DIV(v) (((v) << 2) & GENMASK(3, 2)) 102 #define OV5648_SRB_CTRL_RESET_ARBITER_EN BIT(1) 103 #define OV5648_SRB_CTRL_SCLK_ARBITER_EN BIT(0) 104 105 /* Group Hold */ 106 107 #define OV5648_GROUP_ADR0_REG 0x3200 108 #define OV5648_GROUP_ADR1_REG 0x3201 109 #define OV5648_GROUP_ADR2_REG 0x3202 110 #define OV5648_GROUP_ADR3_REG 0x3203 111 #define OV5648_GROUP_LEN0_REG 0x3204 112 #define OV5648_GROUP_LEN1_REG 0x3205 113 #define OV5648_GROUP_LEN2_REG 0x3206 114 #define OV5648_GROUP_LEN3_REG 0x3207 115 #define OV5648_GROUP_ACCESS_REG 0x3208 116 117 /* Exposure/gain/banding */ 118 119 #define OV5648_EXPOSURE_CTRL_HH_REG 0x3500 120 #define OV5648_EXPOSURE_CTRL_HH(v) (((v) & GENMASK(19, 16)) >> 16) 121 #define OV5648_EXPOSURE_CTRL_HH_VALUE(v) (((v) << 16) & GENMASK(19, 16)) 122 #define OV5648_EXPOSURE_CTRL_H_REG 0x3501 123 #define OV5648_EXPOSURE_CTRL_H(v) (((v) & GENMASK(15, 8)) >> 8) 124 #define OV5648_EXPOSURE_CTRL_H_VALUE(v) (((v) << 8) & GENMASK(15, 8)) 125 #define OV5648_EXPOSURE_CTRL_L_REG 0x3502 126 #define OV5648_EXPOSURE_CTRL_L(v) ((v) & GENMASK(7, 0)) 127 #define OV5648_EXPOSURE_CTRL_L_VALUE(v) ((v) & GENMASK(7, 0)) 128 #define OV5648_MANUAL_CTRL_REG 0x3503 129 #define OV5648_MANUAL_CTRL_FRAME_DELAY(v) (((v) << 4) & GENMASK(5, 4)) 130 #define OV5648_MANUAL_CTRL_AGC_MANUAL_EN BIT(1) 131 #define OV5648_MANUAL_CTRL_AEC_MANUAL_EN BIT(0) 132 #define OV5648_GAIN_CTRL_H_REG 0x350a 133 #define OV5648_GAIN_CTRL_H(v) (((v) & GENMASK(9, 8)) >> 8) 134 #define OV5648_GAIN_CTRL_H_VALUE(v) (((v) << 8) & GENMASK(9, 8)) 135 #define OV5648_GAIN_CTRL_L_REG 0x350b 136 #define OV5648_GAIN_CTRL_L(v) ((v) & GENMASK(7, 0)) 137 #define OV5648_GAIN_CTRL_L_VALUE(v) ((v) & GENMASK(7, 0)) 138 139 #define OV5648_ANALOG_CTRL0_REG_BASE 0x3600 140 #define OV5648_ANALOG_CTRL1_REG_BASE 0x3700 141 142 #define OV5648_AEC_CTRL0_REG 0x3a00 143 #define OV5648_AEC_CTRL0_DEBUG BIT(6) 144 #define OV5648_AEC_CTRL0_DEBAND_EN BIT(5) 145 #define OV5648_AEC_CTRL0_DEBAND_LOW_LIMIT_EN BIT(4) 146 #define OV5648_AEC_CTRL0_START_SEL_EN BIT(3) 147 #define OV5648_AEC_CTRL0_NIGHT_MODE_EN BIT(2) 148 #define OV5648_AEC_CTRL0_FREEZE_EN BIT(0) 149 #define OV5648_EXPOSURE_MIN_REG 0x3a01 150 #define OV5648_EXPOSURE_MAX_60_H_REG 0x3a02 151 #define OV5648_EXPOSURE_MAX_60_L_REG 0x3a03 152 #define OV5648_AEC_CTRL5_REG 0x3a05 153 #define OV5648_AEC_CTRL6_REG 0x3a06 154 #define OV5648_AEC_CTRL7_REG 0x3a07 155 #define OV5648_BANDING_STEP_50_H_REG 0x3a08 156 #define OV5648_BANDING_STEP_50_L_REG 0x3a09 157 #define OV5648_BANDING_STEP_60_H_REG 0x3a0a 158 #define OV5648_BANDING_STEP_60_L_REG 0x3a0b 159 #define OV5648_AEC_CTRLC_REG 0x3a0c 160 #define OV5648_BANDING_MAX_60_REG 0x3a0d 161 #define OV5648_BANDING_MAX_50_REG 0x3a0e 162 #define OV5648_WPT_REG 0x3a0f 163 #define OV5648_BPT_REG 0x3a10 164 #define OV5648_VPT_HIGH_REG 0x3a11 165 #define OV5648_AVG_MANUAL_REG 0x3a12 166 #define OV5648_PRE_GAIN_REG 0x3a13 167 #define OV5648_EXPOSURE_MAX_50_H_REG 0x3a14 168 #define OV5648_EXPOSURE_MAX_50_L_REG 0x3a15 169 #define OV5648_GAIN_BASE_NIGHT_REG 0x3a17 170 #define OV5648_AEC_GAIN_CEILING_H_REG 0x3a18 171 #define OV5648_AEC_GAIN_CEILING_L_REG 0x3a19 172 #define OV5648_DIFF_MAX_REG 0x3a1a 173 #define OV5648_WPT2_REG 0x3a1b 174 #define OV5648_LED_ADD_ROW_H_REG 0x3a1c 175 #define OV5648_LED_ADD_ROW_L_REG 0x3a1d 176 #define OV5648_BPT2_REG 0x3a1e 177 #define OV5648_VPT_LOW_REG 0x3a1f 178 #define OV5648_AEC_CTRL20_REG 0x3a20 179 #define OV5648_AEC_CTRL21_REG 0x3a21 180 181 #define OV5648_AVG_START_X_H_REG 0x5680 182 #define OV5648_AVG_START_X_L_REG 0x5681 183 #define OV5648_AVG_START_Y_H_REG 0x5682 184 #define OV5648_AVG_START_Y_L_REG 0x5683 185 #define OV5648_AVG_WINDOW_X_H_REG 0x5684 186 #define OV5648_AVG_WINDOW_X_L_REG 0x5685 187 #define OV5648_AVG_WINDOW_Y_H_REG 0x5686 188 #define OV5648_AVG_WINDOW_Y_L_REG 0x5687 189 #define OV5648_AVG_WEIGHT00_REG 0x5688 190 #define OV5648_AVG_WEIGHT01_REG 0x5689 191 #define OV5648_AVG_WEIGHT02_REG 0x568a 192 #define OV5648_AVG_WEIGHT03_REG 0x568b 193 #define OV5648_AVG_WEIGHT04_REG 0x568c 194 #define OV5648_AVG_WEIGHT05_REG 0x568d 195 #define OV5648_AVG_WEIGHT06_REG 0x568e 196 #define OV5648_AVG_WEIGHT07_REG 0x568f 197 #define OV5648_AVG_CTRL10_REG 0x5690 198 #define OV5648_AVG_WEIGHT_SUM_REG 0x5691 199 #define OV5648_AVG_READOUT_REG 0x5693 200 201 #define OV5648_DIG_CTRL0_REG 0x5a00 202 #define OV5648_DIG_COMP_MAN_H_REG 0x5a02 203 #define OV5648_DIG_COMP_MAN_L_REG 0x5a03 204 205 #define OV5648_GAINC_MAN_H_REG 0x5a20 206 #define OV5648_GAINC_MAN_L_REG 0x5a21 207 #define OV5648_GAINC_DGC_MAN_H_REG 0x5a22 208 #define OV5648_GAINC_DGC_MAN_L_REG 0x5a23 209 #define OV5648_GAINC_CTRL0_REG 0x5a24 210 211 #define OV5648_GAINF_ANA_NUM_REG 0x5a40 212 #define OV5648_GAINF_DIG_GAIN_REG 0x5a41 213 214 /* Timing */ 215 216 #define OV5648_CROP_START_X_H_REG 0x3800 217 #define OV5648_CROP_START_X_H(v) (((v) & GENMASK(11, 8)) >> 8) 218 #define OV5648_CROP_START_X_L_REG 0x3801 219 #define OV5648_CROP_START_X_L(v) ((v) & GENMASK(7, 0)) 220 #define OV5648_CROP_START_Y_H_REG 0x3802 221 #define OV5648_CROP_START_Y_H(v) (((v) & GENMASK(11, 8)) >> 8) 222 #define OV5648_CROP_START_Y_L_REG 0x3803 223 #define OV5648_CROP_START_Y_L(v) ((v) & GENMASK(7, 0)) 224 #define OV5648_CROP_END_X_H_REG 0x3804 225 #define OV5648_CROP_END_X_H(v) (((v) & GENMASK(11, 8)) >> 8) 226 #define OV5648_CROP_END_X_L_REG 0x3805 227 #define OV5648_CROP_END_X_L(v) ((v) & GENMASK(7, 0)) 228 #define OV5648_CROP_END_Y_H_REG 0x3806 229 #define OV5648_CROP_END_Y_H(v) (((v) & GENMASK(11, 8)) >> 8) 230 #define OV5648_CROP_END_Y_L_REG 0x3807 231 #define OV5648_CROP_END_Y_L(v) ((v) & GENMASK(7, 0)) 232 #define OV5648_OUTPUT_SIZE_X_H_REG 0x3808 233 #define OV5648_OUTPUT_SIZE_X_H(v) (((v) & GENMASK(11, 8)) >> 8) 234 #define OV5648_OUTPUT_SIZE_X_L_REG 0x3809 235 #define OV5648_OUTPUT_SIZE_X_L(v) ((v) & GENMASK(7, 0)) 236 #define OV5648_OUTPUT_SIZE_Y_H_REG 0x380a 237 #define OV5648_OUTPUT_SIZE_Y_H(v) (((v) & GENMASK(11, 8)) >> 8) 238 #define OV5648_OUTPUT_SIZE_Y_L_REG 0x380b 239 #define OV5648_OUTPUT_SIZE_Y_L(v) ((v) & GENMASK(7, 0)) 240 #define OV5648_HTS_H_REG 0x380c 241 #define OV5648_HTS_H(v) (((v) & GENMASK(12, 8)) >> 8) 242 #define OV5648_HTS_L_REG 0x380d 243 #define OV5648_HTS_L(v) ((v) & GENMASK(7, 0)) 244 #define OV5648_VTS_H_REG 0x380e 245 #define OV5648_VTS_H(v) (((v) & GENMASK(15, 8)) >> 8) 246 #define OV5648_VTS_L_REG 0x380f 247 #define OV5648_VTS_L(v) ((v) & GENMASK(7, 0)) 248 #define OV5648_OFFSET_X_H_REG 0x3810 249 #define OV5648_OFFSET_X_H(v) (((v) & GENMASK(11, 8)) >> 8) 250 #define OV5648_OFFSET_X_L_REG 0x3811 251 #define OV5648_OFFSET_X_L(v) ((v) & GENMASK(7, 0)) 252 #define OV5648_OFFSET_Y_H_REG 0x3812 253 #define OV5648_OFFSET_Y_H(v) (((v) & GENMASK(11, 8)) >> 8) 254 #define OV5648_OFFSET_Y_L_REG 0x3813 255 #define OV5648_OFFSET_Y_L(v) ((v) & GENMASK(7, 0)) 256 #define OV5648_SUB_INC_X_REG 0x3814 257 #define OV5648_SUB_INC_X_ODD(v) (((v) << 4) & GENMASK(7, 4)) 258 #define OV5648_SUB_INC_X_EVEN(v) ((v) & GENMASK(3, 0)) 259 #define OV5648_SUB_INC_Y_REG 0x3815 260 #define OV5648_SUB_INC_Y_ODD(v) (((v) << 4) & GENMASK(7, 4)) 261 #define OV5648_SUB_INC_Y_EVEN(v) ((v) & GENMASK(3, 0)) 262 #define OV5648_HSYNCST_H_REG 0x3816 263 #define OV5648_HSYNCST_H(v) (((v) >> 8) & 0xf) 264 #define OV5648_HSYNCST_L_REG 0x3817 265 #define OV5648_HSYNCST_L(v) ((v) & GENMASK(7, 0)) 266 #define OV5648_HSYNCW_H_REG 0x3818 267 #define OV5648_HSYNCW_H(v) (((v) >> 8) & 0xf) 268 #define OV5648_HSYNCW_L_REG 0x3819 269 #define OV5648_HSYNCW_L(v) ((v) & GENMASK(7, 0)) 270 271 #define OV5648_TC20_REG 0x3820 272 #define OV5648_TC20_DEBUG BIT(6) 273 #define OV5648_TC20_FLIP_VERT_ISP_EN BIT(2) 274 #define OV5648_TC20_FLIP_VERT_SENSOR_EN BIT(1) 275 #define OV5648_TC20_BINNING_VERT_EN BIT(0) 276 #define OV5648_TC21_REG 0x3821 277 #define OV5648_TC21_FLIP_HORZ_ISP_EN BIT(2) 278 #define OV5648_TC21_FLIP_HORZ_SENSOR_EN BIT(1) 279 #define OV5648_TC21_BINNING_HORZ_EN BIT(0) 280 281 /* Strobe/exposure */ 282 283 #define OV5648_STROBE_REG 0x3b00 284 #define OV5648_FREX_EXP_HH_REG 0x3b01 285 #define OV5648_SHUTTER_DLY_H_REG 0x3b02 286 #define OV5648_SHUTTER_DLY_L_REG 0x3b03 287 #define OV5648_FREX_EXP_H_REG 0x3b04 288 #define OV5648_FREX_EXP_L_REG 0x3b05 289 #define OV5648_FREX_CTRL_REG 0x3b06 290 #define OV5648_FREX_MODE_SEL_REG 0x3b07 291 #define OV5648_FREX_MODE_SEL_FREX_SA1 BIT(4) 292 #define OV5648_FREX_MODE_SEL_FX1_FM_EN BIT(3) 293 #define OV5648_FREX_MODE_SEL_FREX_INV BIT(2) 294 #define OV5648_FREX_MODE_SEL_MODE1 0x0 295 #define OV5648_FREX_MODE_SEL_MODE2 0x1 296 #define OV5648_FREX_MODE_SEL_ROLLING 0x2 297 #define OV5648_FREX_EXP_REQ_REG 0x3b08 298 #define OV5648_FREX_SHUTTER_DLY_REG 0x3b09 299 #define OV5648_FREX_RST_LEN_REG 0x3b0a 300 #define OV5648_STROBE_WIDTH_HH_REG 0x3b0b 301 #define OV5648_STROBE_WIDTH_H_REG 0x3b0c 302 303 /* OTP */ 304 305 #define OV5648_OTP_DATA_REG_BASE 0x3d00 306 #define OV5648_OTP_PROGRAM_CTRL_REG 0x3d80 307 #define OV5648_OTP_LOAD_CTRL_REG 0x3d81 308 309 /* PSRAM */ 310 311 #define OV5648_PSRAM_CTRL1_REG 0x3f01 312 #define OV5648_PSRAM_CTRLF_REG 0x3f0f 313 314 /* Black Level */ 315 316 #define OV5648_BLC_CTRL0_REG 0x4000 317 #define OV5648_BLC_CTRL1_REG 0x4001 318 #define OV5648_BLC_CTRL1_START_LINE(v) ((v) & GENMASK(5, 0)) 319 #define OV5648_BLC_CTRL2_REG 0x4002 320 #define OV5648_BLC_CTRL2_AUTO_EN BIT(6) 321 #define OV5648_BLC_CTRL2_RESET_FRAME_NUM(v) ((v) & GENMASK(5, 0)) 322 #define OV5648_BLC_CTRL3_REG 0x4003 323 #define OV5648_BLC_LINE_NUM_REG 0x4004 324 #define OV5648_BLC_LINE_NUM(v) ((v) & GENMASK(7, 0)) 325 #define OV5648_BLC_CTRL5_REG 0x4005 326 #define OV5648_BLC_CTRL5_UPDATE_EN BIT(1) 327 #define OV5648_BLC_LEVEL_REG 0x4009 328 329 /* Frame */ 330 331 #define OV5648_FRAME_CTRL_REG 0x4200 332 #define OV5648_FRAME_ON_NUM_REG 0x4201 333 #define OV5648_FRAME_OFF_NUM_REG 0x4202 334 335 /* MIPI CSI-2 */ 336 337 #define OV5648_MIPI_CTRL0_REG 0x4800 338 #define OV5648_MIPI_CTRL0_CLK_LANE_AUTOGATE BIT(5) 339 #define OV5648_MIPI_CTRL0_LANE_SYNC_EN BIT(4) 340 #define OV5648_MIPI_CTRL0_LANE_SELECT_LANE1 0 341 #define OV5648_MIPI_CTRL0_LANE_SELECT_LANE2 BIT(3) 342 #define OV5648_MIPI_CTRL0_IDLE_LP00 0 343 #define OV5648_MIPI_CTRL0_IDLE_LP11 BIT(2) 344 345 #define OV5648_MIPI_CTRL1_REG 0x4801 346 #define OV5648_MIPI_CTRL2_REG 0x4802 347 #define OV5648_MIPI_CTRL3_REG 0x4803 348 #define OV5648_MIPI_CTRL4_REG 0x4804 349 #define OV5648_MIPI_CTRL5_REG 0x4805 350 #define OV5648_MIPI_MAX_FRAME_COUNT_H_REG 0x4810 351 #define OV5648_MIPI_MAX_FRAME_COUNT_L_REG 0x4811 352 #define OV5648_MIPI_CTRL14_REG 0x4814 353 #define OV5648_MIPI_DT_SPKT_REG 0x4815 354 #define OV5648_MIPI_HS_ZERO_MIN_H_REG 0x4818 355 #define OV5648_MIPI_HS_ZERO_MIN_L_REG 0x4819 356 #define OV5648_MIPI_HS_TRAIN_MIN_H_REG 0x481a 357 #define OV5648_MIPI_HS_TRAIN_MIN_L_REG 0x481b 358 #define OV5648_MIPI_CLK_ZERO_MIN_H_REG 0x481c 359 #define OV5648_MIPI_CLK_ZERO_MIN_L_REG 0x481d 360 #define OV5648_MIPI_CLK_PREPARE_MIN_H_REG 0x481e 361 #define OV5648_MIPI_CLK_PREPARE_MIN_L_REG 0x481f 362 #define OV5648_MIPI_CLK_POST_MIN_H_REG 0x4820 363 #define OV5648_MIPI_CLK_POST_MIN_L_REG 0x4821 364 #define OV5648_MIPI_CLK_TRAIL_MIN_H_REG 0x4822 365 #define OV5648_MIPI_CLK_TRAIL_MIN_L_REG 0x4823 366 #define OV5648_MIPI_LPX_P_MIN_H_REG 0x4824 367 #define OV5648_MIPI_LPX_P_MIN_L_REG 0x4825 368 #define OV5648_MIPI_HS_PREPARE_MIN_H_REG 0x4826 369 #define OV5648_MIPI_HS_PREPARE_MIN_L_REG 0x4827 370 #define OV5648_MIPI_HS_EXIT_MIN_H_REG 0x4828 371 #define OV5648_MIPI_HS_EXIT_MIN_L_REG 0x4829 372 #define OV5648_MIPI_HS_ZERO_MIN_UI_REG 0x482a 373 #define OV5648_MIPI_HS_TRAIL_MIN_UI_REG 0x482b 374 #define OV5648_MIPI_CLK_ZERO_MIN_UI_REG 0x482c 375 #define OV5648_MIPI_CLK_PREPARE_MIN_UI_REG 0x482d 376 #define OV5648_MIPI_CLK_POST_MIN_UI_REG 0x482e 377 #define OV5648_MIPI_CLK_TRAIL_MIN_UI_REG 0x482f 378 #define OV5648_MIPI_LPX_P_MIN_UI_REG 0x4830 379 #define OV5648_MIPI_HS_PREPARE_MIN_UI_REG 0x4831 380 #define OV5648_MIPI_HS_EXIT_MIN_UI_REG 0x4832 381 #define OV5648_MIPI_REG_MIN_H_REG 0x4833 382 #define OV5648_MIPI_REG_MIN_L_REG 0x4834 383 #define OV5648_MIPI_REG_MAX_H_REG 0x4835 384 #define OV5648_MIPI_REG_MAX_L_REG 0x4836 385 #define OV5648_MIPI_PCLK_PERIOD_REG 0x4837 386 #define OV5648_MIPI_WKUP_DLY_REG 0x4838 387 #define OV5648_MIPI_LP_GPIO_REG 0x483b 388 #define OV5648_MIPI_SNR_PCLK_DIV_REG 0x4843 389 390 /* ISP */ 391 392 #define OV5648_ISP_CTRL0_REG 0x5000 393 #define OV5648_ISP_CTRL0_BLACK_CORRECT_EN BIT(2) 394 #define OV5648_ISP_CTRL0_WHITE_CORRECT_EN BIT(1) 395 #define OV5648_ISP_CTRL1_REG 0x5001 396 #define OV5648_ISP_CTRL1_AWB_EN BIT(0) 397 #define OV5648_ISP_CTRL2_REG 0x5002 398 #define OV5648_ISP_CTRL2_WIN_EN BIT(6) 399 #define OV5648_ISP_CTRL2_OTP_EN BIT(1) 400 #define OV5648_ISP_CTRL2_AWB_GAIN_EN BIT(0) 401 #define OV5648_ISP_CTRL3_REG 0x5003 402 #define OV5648_ISP_CTRL3_BUF_EN BIT(3) 403 #define OV5648_ISP_CTRL3_BIN_MAN_SET BIT(2) 404 #define OV5648_ISP_CTRL3_BIN_AUTO_EN BIT(1) 405 #define OV5648_ISP_CTRL4_REG 0x5004 406 #define OV5648_ISP_CTRL5_REG 0x5005 407 #define OV5648_ISP_CTRL6_REG 0x5006 408 #define OV5648_ISP_CTRL7_REG 0x5007 409 #define OV5648_ISP_MAN_OFFSET_X_H_REG 0x5008 410 #define OV5648_ISP_MAN_OFFSET_X_L_REG 0x5009 411 #define OV5648_ISP_MAN_OFFSET_Y_H_REG 0x500a 412 #define OV5648_ISP_MAN_OFFSET_Y_L_REG 0x500b 413 #define OV5648_ISP_MAN_WIN_OFFSET_X_H_REG 0x500c 414 #define OV5648_ISP_MAN_WIN_OFFSET_X_L_REG 0x500d 415 #define OV5648_ISP_MAN_WIN_OFFSET_Y_H_REG 0x500e 416 #define OV5648_ISP_MAN_WIN_OFFSET_Y_L_REG 0x500f 417 #define OV5648_ISP_MAN_WIN_OUTPUT_X_H_REG 0x5010 418 #define OV5648_ISP_MAN_WIN_OUTPUT_X_L_REG 0x5011 419 #define OV5648_ISP_MAN_WIN_OUTPUT_Y_H_REG 0x5012 420 #define OV5648_ISP_MAN_WIN_OUTPUT_Y_L_REG 0x5013 421 #define OV5648_ISP_MAN_INPUT_X_H_REG 0x5014 422 #define OV5648_ISP_MAN_INPUT_X_L_REG 0x5015 423 #define OV5648_ISP_MAN_INPUT_Y_H_REG 0x5016 424 #define OV5648_ISP_MAN_INPUT_Y_L_REG 0x5017 425 #define OV5648_ISP_CTRL18_REG 0x5018 426 #define OV5648_ISP_CTRL19_REG 0x5019 427 #define OV5648_ISP_CTRL1A_REG 0x501a 428 #define OV5648_ISP_CTRL1D_REG 0x501d 429 #define OV5648_ISP_CTRL1F_REG 0x501f 430 #define OV5648_ISP_CTRL1F_OUTPUT_EN 3 431 #define OV5648_ISP_CTRL25_REG 0x5025 432 433 #define OV5648_ISP_CTRL3D_REG 0x503d 434 #define OV5648_ISP_CTRL3D_PATTERN_EN BIT(7) 435 #define OV5648_ISP_CTRL3D_ROLLING_BAR_EN BIT(6) 436 #define OV5648_ISP_CTRL3D_TRANSPARENT_MODE BIT(5) 437 #define OV5648_ISP_CTRL3D_SQUARES_BW_MODE BIT(4) 438 #define OV5648_ISP_CTRL3D_PATTERN_COLOR_BARS 0 439 #define OV5648_ISP_CTRL3D_PATTERN_RANDOM_DATA 1 440 #define OV5648_ISP_CTRL3D_PATTERN_COLOR_SQUARES 2 441 #define OV5648_ISP_CTRL3D_PATTERN_INPUT 3 442 443 #define OV5648_ISP_CTRL3E_REG 0x503e 444 #define OV5648_ISP_CTRL4B_REG 0x504b 445 #define OV5648_ISP_CTRL4B_POST_BIN_H_EN BIT(5) 446 #define OV5648_ISP_CTRL4B_POST_BIN_V_EN BIT(4) 447 #define OV5648_ISP_CTRL4C_REG 0x504c 448 #define OV5648_ISP_CTRL57_REG 0x5057 449 #define OV5648_ISP_CTRL58_REG 0x5058 450 #define OV5648_ISP_CTRL59_REG 0x5059 451 452 #define OV5648_ISP_WINDOW_START_X_H_REG 0x5980 453 #define OV5648_ISP_WINDOW_START_X_L_REG 0x5981 454 #define OV5648_ISP_WINDOW_START_Y_H_REG 0x5982 455 #define OV5648_ISP_WINDOW_START_Y_L_REG 0x5983 456 #define OV5648_ISP_WINDOW_WIN_X_H_REG 0x5984 457 #define OV5648_ISP_WINDOW_WIN_X_L_REG 0x5985 458 #define OV5648_ISP_WINDOW_WIN_Y_H_REG 0x5986 459 #define OV5648_ISP_WINDOW_WIN_Y_L_REG 0x5987 460 #define OV5648_ISP_WINDOW_MAN_REG 0x5988 461 462 /* White Balance */ 463 464 #define OV5648_AWB_CTRL_REG 0x5180 465 #define OV5648_AWB_CTRL_FAST_AWB BIT(6) 466 #define OV5648_AWB_CTRL_GAIN_FREEZE_EN BIT(5) 467 #define OV5648_AWB_CTRL_SUM_FREEZE_EN BIT(4) 468 #define OV5648_AWB_CTRL_GAIN_MANUAL_EN BIT(3) 469 470 #define OV5648_AWB_DELTA_REG 0x5181 471 #define OV5648_AWB_STABLE_RANGE_REG 0x5182 472 #define OV5648_AWB_STABLE_RANGE_WIDE_REG 0x5183 473 #define OV5648_HSIZE_MAN_REG 0x5185 474 475 #define OV5648_GAIN_RED_MAN_H_REG 0x5186 476 #define OV5648_GAIN_RED_MAN_H(v) (((v) & GENMASK(11, 8)) >> 8) 477 #define OV5648_GAIN_RED_MAN_L_REG 0x5187 478 #define OV5648_GAIN_RED_MAN_L(v) ((v) & GENMASK(7, 0)) 479 #define OV5648_GAIN_GREEN_MAN_H_REG 0x5188 480 #define OV5648_GAIN_GREEN_MAN_H(v) (((v) & GENMASK(11, 8)) >> 8) 481 #define OV5648_GAIN_GREEN_MAN_L_REG 0x5189 482 #define OV5648_GAIN_GREEN_MAN_L(v) ((v) & GENMASK(7, 0)) 483 #define OV5648_GAIN_BLUE_MAN_H_REG 0x518a 484 #define OV5648_GAIN_BLUE_MAN_H(v) (((v) & GENMASK(11, 8)) >> 8) 485 #define OV5648_GAIN_BLUE_MAN_L_REG 0x518b 486 #define OV5648_GAIN_BLUE_MAN_L(v) ((v) & GENMASK(7, 0)) 487 #define OV5648_GAIN_RED_LIMIT_REG 0x518c 488 #define OV5648_GAIN_GREEN_LIMIT_REG 0x518d 489 #define OV5648_GAIN_BLUE_LIMIT_REG 0x518e 490 #define OV5648_AWB_FRAME_COUNT_REG 0x518f 491 #define OV5648_AWB_BASE_MAN_REG 0x51df 492 493 /* Macros */ 494 495 #define ov5648_subdev_sensor(s) \ 496 container_of(s, struct ov5648_sensor, subdev) 497 498 #define ov5648_ctrl_subdev(c) \ 499 (&container_of(c->handler, struct ov5648_sensor, ctrls.handler)->subdev) 500 501 /* Data structures */ 502 503 struct ov5648_register_value { 504 u16 address; 505 u8 value; 506 unsigned int delay_ms; 507 }; 508 509 /* 510 * PLL1 Clock Tree: 511 * 512 * +-< XVCLK 513 * | 514 * +-+ pll_pre_div (0x3037 [3:0], special values: 5: 1.5, 7: 2.5) 515 * | 516 * +-+ pll_mul (0x3036 [7:0]) 517 * | 518 * +-+ sys_div (0x3035 [7:4]) 519 * | 520 * +-+ mipi_div (0x3035 [3:0]) 521 * | | 522 * | +-> MIPI_SCLK 523 * | | 524 * | +-+ mipi_phy_div (2) 525 * | | 526 * | +-> MIPI_CLK 527 * | 528 * +-+ root_div (0x3037 [4]) 529 * | 530 * +-+ bit_div (0x3034 [3:0], 8 bits: 2, 10 bits: 2.5, other: 1) 531 * | 532 * +-+ sclk_div (0x3106 [3:2]) 533 * | 534 * +-> SCLK 535 * | 536 * +-+ mipi_div (0x3035, 1: PCLK = SCLK) 537 * | 538 * +-> PCLK 539 */ 540 541 struct ov5648_pll1_config { 542 unsigned int pll_pre_div; 543 unsigned int pll_mul; 544 unsigned int sys_div; 545 unsigned int root_div; 546 unsigned int sclk_div; 547 unsigned int mipi_div; 548 }; 549 550 /* 551 * PLL2 Clock Tree: 552 * 553 * +-< XVCLK 554 * | 555 * +-+ plls_pre_div (0x303d [5:4], special values: 0: 1, 1: 1.5) 556 * | 557 * +-+ plls_div_r (0x303d [2]) 558 * | 559 * +-+ plls_mul (0x303b [4:0]) 560 * | 561 * +-+ sys_div (0x303c [3:0]) 562 * | 563 * +-+ sel_div (0x303d [1:0], special values: 0: 1, 3: 2.5) 564 * | 565 * +-> ADCLK 566 */ 567 568 struct ov5648_pll2_config { 569 unsigned int plls_pre_div; 570 unsigned int plls_div_r; 571 unsigned int plls_mul; 572 unsigned int sys_div; 573 unsigned int sel_div; 574 }; 575 576 /* 577 * General formulas for (array-centered) mode calculation: 578 * - photo_array_width = 2624 579 * - crop_start_x = (photo_array_width - output_size_x) / 2 580 * - crop_end_x = crop_start_x + offset_x + output_size_x - 1 581 * 582 * - photo_array_height = 1956 583 * - crop_start_y = (photo_array_height - output_size_y) / 2 584 * - crop_end_y = crop_start_y + offset_y + output_size_y - 1 585 */ 586 587 struct ov5648_mode { 588 unsigned int crop_start_x; 589 unsigned int offset_x; 590 unsigned int output_size_x; 591 unsigned int crop_end_x; 592 unsigned int hts; 593 594 unsigned int crop_start_y; 595 unsigned int offset_y; 596 unsigned int output_size_y; 597 unsigned int crop_end_y; 598 unsigned int vts; 599 600 bool binning_x; 601 bool binning_y; 602 603 unsigned int inc_x_odd; 604 unsigned int inc_x_even; 605 unsigned int inc_y_odd; 606 unsigned int inc_y_even; 607 608 /* 8-bit frame interval followed by 10-bit frame interval. */ 609 struct v4l2_fract frame_interval[2]; 610 611 /* 8-bit config followed by 10-bit config. */ 612 const struct ov5648_pll1_config *pll1_config[2]; 613 const struct ov5648_pll2_config *pll2_config; 614 615 const struct ov5648_register_value *register_values; 616 unsigned int register_values_count; 617 }; 618 619 struct ov5648_state { 620 const struct ov5648_mode *mode; 621 u32 mbus_code; 622 623 bool streaming; 624 }; 625 626 struct ov5648_ctrls { 627 struct v4l2_ctrl *exposure_auto; 628 struct v4l2_ctrl *exposure; 629 630 struct v4l2_ctrl *gain_auto; 631 struct v4l2_ctrl *gain; 632 633 struct v4l2_ctrl *white_balance_auto; 634 struct v4l2_ctrl *red_balance; 635 struct v4l2_ctrl *blue_balance; 636 637 struct v4l2_ctrl *link_freq; 638 struct v4l2_ctrl *pixel_rate; 639 640 struct v4l2_ctrl_handler handler; 641 } __packed; 642 643 struct ov5648_sensor { 644 struct device *dev; 645 struct i2c_client *i2c_client; 646 struct gpio_desc *reset; 647 struct gpio_desc *powerdown; 648 struct regulator *avdd; 649 struct regulator *dvdd; 650 struct regulator *dovdd; 651 struct clk *xvclk; 652 653 struct v4l2_fwnode_endpoint endpoint; 654 struct v4l2_subdev subdev; 655 struct media_pad pad; 656 657 struct mutex mutex; 658 659 struct ov5648_state state; 660 struct ov5648_ctrls ctrls; 661 }; 662 663 /* Static definitions */ 664 665 /* 666 * XVCLK = 24 MHz 667 * SCLK = 84 MHz 668 * PCLK = 84 MHz 669 */ 670 static const struct ov5648_pll1_config ov5648_pll1_config_native_8_bits = { 671 .pll_pre_div = 3, 672 .pll_mul = 84, 673 .sys_div = 2, 674 .root_div = 1, 675 .sclk_div = 1, 676 .mipi_div = 1, 677 }; 678 679 /* 680 * XVCLK = 24 MHz 681 * SCLK = 84 MHz 682 * PCLK = 84 MHz 683 */ 684 static const struct ov5648_pll1_config ov5648_pll1_config_native_10_bits = { 685 .pll_pre_div = 3, 686 .pll_mul = 105, 687 .sys_div = 2, 688 .root_div = 1, 689 .sclk_div = 1, 690 .mipi_div = 1, 691 }; 692 693 /* 694 * XVCLK = 24 MHz 695 * ADCLK = 200 MHz 696 */ 697 static const struct ov5648_pll2_config ov5648_pll2_config_native = { 698 .plls_pre_div = 3, 699 .plls_div_r = 1, 700 .plls_mul = 25, 701 .sys_div = 1, 702 .sel_div = 1, 703 }; 704 705 static const struct ov5648_mode ov5648_modes[] = { 706 /* 2592x1944 */ 707 { 708 /* Horizontal */ 709 .crop_start_x = 16, 710 .offset_x = 0, 711 .output_size_x = 2592, 712 .crop_end_x = 2607, 713 .hts = 2816, 714 715 /* Vertical */ 716 .crop_start_y = 6, 717 .offset_y = 0, 718 .output_size_y = 1944, 719 .crop_end_y = 1949, 720 .vts = 1984, 721 722 /* Subsample increase */ 723 .inc_x_odd = 1, 724 .inc_x_even = 1, 725 .inc_y_odd = 1, 726 .inc_y_even = 1, 727 728 /* Frame Interval */ 729 .frame_interval = { 730 { 1, 15 }, 731 { 1, 15 }, 732 }, 733 734 /* PLL */ 735 .pll1_config = { 736 &ov5648_pll1_config_native_8_bits, 737 &ov5648_pll1_config_native_10_bits, 738 }, 739 .pll2_config = &ov5648_pll2_config_native, 740 }, 741 /* 1600x1200 (UXGA) */ 742 { 743 /* Horizontal */ 744 .crop_start_x = 512, 745 .offset_x = 0, 746 .output_size_x = 1600, 747 .crop_end_x = 2111, 748 .hts = 2816, 749 750 /* Vertical */ 751 .crop_start_y = 378, 752 .offset_y = 0, 753 .output_size_y = 1200, 754 .crop_end_y = 1577, 755 .vts = 1984, 756 757 /* Subsample increase */ 758 .inc_x_odd = 1, 759 .inc_x_even = 1, 760 .inc_y_odd = 1, 761 .inc_y_even = 1, 762 763 /* Frame Interval */ 764 .frame_interval = { 765 { 1, 15 }, 766 { 1, 15 }, 767 }, 768 769 /* PLL */ 770 .pll1_config = { 771 &ov5648_pll1_config_native_8_bits, 772 &ov5648_pll1_config_native_10_bits, 773 }, 774 .pll2_config = &ov5648_pll2_config_native, 775 }, 776 /* 1920x1080 (Full HD) */ 777 { 778 /* Horizontal */ 779 .crop_start_x = 352, 780 .offset_x = 0, 781 .output_size_x = 1920, 782 .crop_end_x = 2271, 783 .hts = 2816, 784 785 /* Vertical */ 786 .crop_start_y = 438, 787 .offset_y = 0, 788 .output_size_y = 1080, 789 .crop_end_y = 1517, 790 .vts = 1984, 791 792 /* Subsample increase */ 793 .inc_x_odd = 1, 794 .inc_x_even = 1, 795 .inc_y_odd = 1, 796 .inc_y_even = 1, 797 798 /* Frame Interval */ 799 .frame_interval = { 800 { 1, 15 }, 801 { 1, 15 }, 802 }, 803 804 /* PLL */ 805 .pll1_config = { 806 &ov5648_pll1_config_native_8_bits, 807 &ov5648_pll1_config_native_10_bits, 808 }, 809 .pll2_config = &ov5648_pll2_config_native, 810 }, 811 /* 1280x960 */ 812 { 813 /* Horizontal */ 814 .crop_start_x = 16, 815 .offset_x = 8, 816 .output_size_x = 1280, 817 .crop_end_x = 2607, 818 .hts = 1912, 819 820 /* Vertical */ 821 .crop_start_y = 6, 822 .offset_y = 6, 823 .output_size_y = 960, 824 .crop_end_y = 1949, 825 .vts = 1496, 826 827 /* Binning */ 828 .binning_x = true, 829 830 /* Subsample increase */ 831 .inc_x_odd = 3, 832 .inc_x_even = 1, 833 .inc_y_odd = 3, 834 .inc_y_even = 1, 835 836 /* Frame Interval */ 837 .frame_interval = { 838 { 1, 30 }, 839 { 1, 30 }, 840 }, 841 842 /* PLL */ 843 .pll1_config = { 844 &ov5648_pll1_config_native_8_bits, 845 &ov5648_pll1_config_native_10_bits, 846 }, 847 .pll2_config = &ov5648_pll2_config_native, 848 }, 849 /* 1280x720 (HD) */ 850 { 851 /* Horizontal */ 852 .crop_start_x = 16, 853 .offset_x = 8, 854 .output_size_x = 1280, 855 .crop_end_x = 2607, 856 .hts = 1912, 857 858 /* Vertical */ 859 .crop_start_y = 254, 860 .offset_y = 2, 861 .output_size_y = 720, 862 .crop_end_y = 1701, 863 .vts = 1496, 864 865 /* Binning */ 866 .binning_x = true, 867 868 /* Subsample increase */ 869 .inc_x_odd = 3, 870 .inc_x_even = 1, 871 .inc_y_odd = 3, 872 .inc_y_even = 1, 873 874 /* Frame Interval */ 875 .frame_interval = { 876 { 1, 30 }, 877 { 1, 30 }, 878 }, 879 880 /* PLL */ 881 .pll1_config = { 882 &ov5648_pll1_config_native_8_bits, 883 &ov5648_pll1_config_native_10_bits, 884 }, 885 .pll2_config = &ov5648_pll2_config_native, 886 }, 887 /* 640x480 (VGA) */ 888 { 889 /* Horizontal */ 890 .crop_start_x = 0, 891 .offset_x = 8, 892 .output_size_x = 640, 893 .crop_end_x = 2623, 894 .hts = 1896, 895 896 /* Vertical */ 897 .crop_start_y = 0, 898 .offset_y = 2, 899 .output_size_y = 480, 900 .crop_end_y = 1953, 901 .vts = 984, 902 903 /* Binning */ 904 .binning_x = true, 905 906 /* Subsample increase */ 907 .inc_x_odd = 7, 908 .inc_x_even = 1, 909 .inc_y_odd = 7, 910 .inc_y_even = 1, 911 912 /* Frame Interval */ 913 .frame_interval = { 914 { 1, 30 }, 915 { 1, 30 }, 916 }, 917 918 /* PLL */ 919 .pll1_config = { 920 &ov5648_pll1_config_native_8_bits, 921 &ov5648_pll1_config_native_10_bits, 922 }, 923 .pll2_config = &ov5648_pll2_config_native, 924 }, 925 }; 926 927 static const u32 ov5648_mbus_codes[] = { 928 MEDIA_BUS_FMT_SBGGR8_1X8, 929 MEDIA_BUS_FMT_SBGGR10_1X10, 930 }; 931 932 static const struct ov5648_register_value ov5648_init_sequence[] = { 933 /* PSRAM */ 934 { OV5648_PSRAM_CTRL1_REG, 0x0d }, 935 { OV5648_PSRAM_CTRLF_REG, 0xf5 }, 936 }; 937 938 static const s64 ov5648_link_freq_menu[] = { 939 210000000, 940 168000000, 941 }; 942 943 static const char *const ov5648_test_pattern_menu[] = { 944 "Disabled", 945 "Random data", 946 "Color bars", 947 "Color bars with rolling bar", 948 "Color squares", 949 "Color squares with rolling bar" 950 }; 951 952 static const u8 ov5648_test_pattern_bits[] = { 953 0, 954 OV5648_ISP_CTRL3D_PATTERN_EN | OV5648_ISP_CTRL3D_PATTERN_RANDOM_DATA, 955 OV5648_ISP_CTRL3D_PATTERN_EN | OV5648_ISP_CTRL3D_PATTERN_COLOR_BARS, 956 OV5648_ISP_CTRL3D_PATTERN_EN | OV5648_ISP_CTRL3D_ROLLING_BAR_EN | 957 OV5648_ISP_CTRL3D_PATTERN_COLOR_BARS, 958 OV5648_ISP_CTRL3D_PATTERN_EN | OV5648_ISP_CTRL3D_PATTERN_COLOR_SQUARES, 959 OV5648_ISP_CTRL3D_PATTERN_EN | OV5648_ISP_CTRL3D_ROLLING_BAR_EN | 960 OV5648_ISP_CTRL3D_PATTERN_COLOR_SQUARES, 961 }; 962 963 /* Input/Output */ 964 965 static int ov5648_read(struct ov5648_sensor *sensor, u16 address, u8 *value) 966 { 967 unsigned char data[2] = { address >> 8, address & 0xff }; 968 struct i2c_client *client = sensor->i2c_client; 969 int ret; 970 971 ret = i2c_master_send(client, data, sizeof(data)); 972 if (ret < 0) { 973 dev_dbg(&client->dev, "i2c send error at address %#04x\n", 974 address); 975 return ret; 976 } 977 978 ret = i2c_master_recv(client, value, 1); 979 if (ret < 0) { 980 dev_dbg(&client->dev, "i2c recv error at address %#04x\n", 981 address); 982 return ret; 983 } 984 985 return 0; 986 } 987 988 static int ov5648_write(struct ov5648_sensor *sensor, u16 address, u8 value) 989 { 990 unsigned char data[3] = { address >> 8, address & 0xff, value }; 991 struct i2c_client *client = sensor->i2c_client; 992 int ret; 993 994 ret = i2c_master_send(client, data, sizeof(data)); 995 if (ret < 0) { 996 dev_dbg(&client->dev, "i2c send error at address %#04x\n", 997 address); 998 return ret; 999 } 1000 1001 return 0; 1002 } 1003 1004 static int ov5648_write_sequence(struct ov5648_sensor *sensor, 1005 const struct ov5648_register_value *sequence, 1006 unsigned int sequence_count) 1007 { 1008 unsigned int i; 1009 int ret = 0; 1010 1011 for (i = 0; i < sequence_count; i++) { 1012 ret = ov5648_write(sensor, sequence[i].address, 1013 sequence[i].value); 1014 if (ret) 1015 break; 1016 1017 if (sequence[i].delay_ms) 1018 msleep(sequence[i].delay_ms); 1019 } 1020 1021 return ret; 1022 } 1023 1024 static int ov5648_update_bits(struct ov5648_sensor *sensor, u16 address, 1025 u8 mask, u8 bits) 1026 { 1027 u8 value = 0; 1028 int ret; 1029 1030 ret = ov5648_read(sensor, address, &value); 1031 if (ret) 1032 return ret; 1033 1034 value &= ~mask; 1035 value |= bits; 1036 1037 ret = ov5648_write(sensor, address, value); 1038 if (ret) 1039 return ret; 1040 1041 return 0; 1042 } 1043 1044 /* Sensor */ 1045 1046 static int ov5648_sw_reset(struct ov5648_sensor *sensor) 1047 { 1048 return ov5648_write(sensor, OV5648_SW_RESET_REG, OV5648_SW_RESET_RESET); 1049 } 1050 1051 static int ov5648_sw_standby(struct ov5648_sensor *sensor, int standby) 1052 { 1053 u8 value = 0; 1054 1055 if (!standby) 1056 value = OV5648_SW_STANDBY_STREAM_ON; 1057 1058 return ov5648_write(sensor, OV5648_SW_STANDBY_REG, value); 1059 } 1060 1061 static int ov5648_chip_id_check(struct ov5648_sensor *sensor) 1062 { 1063 u16 regs[] = { OV5648_CHIP_ID_H_REG, OV5648_CHIP_ID_L_REG }; 1064 u8 values[] = { OV5648_CHIP_ID_H_VALUE, OV5648_CHIP_ID_L_VALUE }; 1065 unsigned int i; 1066 u8 value; 1067 int ret; 1068 1069 for (i = 0; i < ARRAY_SIZE(regs); i++) { 1070 ret = ov5648_read(sensor, regs[i], &value); 1071 if (ret < 0) 1072 return ret; 1073 1074 if (value != values[i]) { 1075 dev_err(sensor->dev, 1076 "chip id value mismatch: %#x instead of %#x\n", 1077 value, values[i]); 1078 return -EINVAL; 1079 } 1080 } 1081 1082 return 0; 1083 } 1084 1085 static int ov5648_avdd_internal_power(struct ov5648_sensor *sensor, int on) 1086 { 1087 return ov5648_write(sensor, OV5648_A_PWC_PK_O0_REG, 1088 on ? 0 : OV5648_A_PWC_PK_O0_BP_REGULATOR_N); 1089 } 1090 1091 static int ov5648_pad_configure(struct ov5648_sensor *sensor) 1092 { 1093 int ret; 1094 1095 /* Configure pads as input. */ 1096 1097 ret = ov5648_write(sensor, OV5648_PAD_OEN1_REG, 0); 1098 if (ret) 1099 return ret; 1100 1101 ret = ov5648_write(sensor, OV5648_PAD_OEN2_REG, 0); 1102 if (ret) 1103 return ret; 1104 1105 /* Disable FREX pin. */ 1106 1107 return ov5648_write(sensor, OV5648_PAD_PK_REG, 1108 OV5648_PAD_PK_DRIVE_STRENGTH_1X | 1109 OV5648_PAD_PK_FREX_N); 1110 } 1111 1112 static int ov5648_mipi_configure(struct ov5648_sensor *sensor) 1113 { 1114 struct v4l2_fwnode_bus_mipi_csi2 *bus_mipi_csi2 = 1115 &sensor->endpoint.bus.mipi_csi2; 1116 unsigned int lanes_count = bus_mipi_csi2->num_data_lanes; 1117 int ret; 1118 1119 ret = ov5648_write(sensor, OV5648_MIPI_CTRL0_REG, 1120 OV5648_MIPI_CTRL0_CLK_LANE_AUTOGATE | 1121 OV5648_MIPI_CTRL0_LANE_SELECT_LANE1 | 1122 OV5648_MIPI_CTRL0_IDLE_LP11); 1123 if (ret) 1124 return ret; 1125 1126 return ov5648_write(sensor, OV5648_MIPI_SC_CTRL0_REG, 1127 OV5648_MIPI_SC_CTRL0_MIPI_LANES(lanes_count) | 1128 OV5648_MIPI_SC_CTRL0_PHY_LP_RX_PD | 1129 OV5648_MIPI_SC_CTRL0_MIPI_EN); 1130 } 1131 1132 static int ov5648_black_level_configure(struct ov5648_sensor *sensor) 1133 { 1134 int ret; 1135 1136 /* Up to 6 lines are available for black level calibration. */ 1137 1138 ret = ov5648_write(sensor, OV5648_BLC_CTRL1_REG, 1139 OV5648_BLC_CTRL1_START_LINE(2)); 1140 if (ret) 1141 return ret; 1142 1143 ret = ov5648_write(sensor, OV5648_BLC_CTRL2_REG, 1144 OV5648_BLC_CTRL2_AUTO_EN | 1145 OV5648_BLC_CTRL2_RESET_FRAME_NUM(5)); 1146 if (ret) 1147 return ret; 1148 1149 ret = ov5648_write(sensor, OV5648_BLC_LINE_NUM_REG, 1150 OV5648_BLC_LINE_NUM(4)); 1151 if (ret) 1152 return ret; 1153 1154 return ov5648_update_bits(sensor, OV5648_BLC_CTRL5_REG, 1155 OV5648_BLC_CTRL5_UPDATE_EN, 1156 OV5648_BLC_CTRL5_UPDATE_EN); 1157 } 1158 1159 static int ov5648_isp_configure(struct ov5648_sensor *sensor) 1160 { 1161 u8 bits; 1162 int ret; 1163 1164 /* Enable black and white level correction. */ 1165 bits = OV5648_ISP_CTRL0_BLACK_CORRECT_EN | 1166 OV5648_ISP_CTRL0_WHITE_CORRECT_EN; 1167 1168 ret = ov5648_update_bits(sensor, OV5648_ISP_CTRL0_REG, bits, bits); 1169 if (ret) 1170 return ret; 1171 1172 /* Enable AWB. */ 1173 ret = ov5648_write(sensor, OV5648_ISP_CTRL1_REG, 1174 OV5648_ISP_CTRL1_AWB_EN); 1175 if (ret) 1176 return ret; 1177 1178 /* Enable AWB gain and windowing. */ 1179 ret = ov5648_write(sensor, OV5648_ISP_CTRL2_REG, 1180 OV5648_ISP_CTRL2_WIN_EN | 1181 OV5648_ISP_CTRL2_AWB_GAIN_EN); 1182 if (ret) 1183 return ret; 1184 1185 /* Enable buffering and auto-binning. */ 1186 ret = ov5648_write(sensor, OV5648_ISP_CTRL3_REG, 1187 OV5648_ISP_CTRL3_BUF_EN | 1188 OV5648_ISP_CTRL3_BIN_AUTO_EN); 1189 if (ret) 1190 return ret; 1191 1192 ret = ov5648_write(sensor, OV5648_ISP_CTRL4_REG, 0); 1193 if (ret) 1194 return ret; 1195 1196 ret = ov5648_write(sensor, OV5648_ISP_CTRL1F_REG, 1197 OV5648_ISP_CTRL1F_OUTPUT_EN); 1198 if (ret) 1199 return ret; 1200 1201 /* Enable post-binning filters. */ 1202 ret = ov5648_write(sensor, OV5648_ISP_CTRL4B_REG, 1203 OV5648_ISP_CTRL4B_POST_BIN_H_EN | 1204 OV5648_ISP_CTRL4B_POST_BIN_V_EN); 1205 if (ret) 1206 return ret; 1207 1208 /* Disable debanding and night mode. Debug bit seems necessary. */ 1209 ret = ov5648_write(sensor, OV5648_AEC_CTRL0_REG, 1210 OV5648_AEC_CTRL0_DEBUG | 1211 OV5648_AEC_CTRL0_START_SEL_EN); 1212 if (ret) 1213 return ret; 1214 1215 return ov5648_write(sensor, OV5648_MANUAL_CTRL_REG, 1216 OV5648_MANUAL_CTRL_FRAME_DELAY(1)); 1217 } 1218 1219 static unsigned long ov5648_mode_pll1_rate(struct ov5648_sensor *sensor, 1220 const struct ov5648_pll1_config *config) 1221 { 1222 unsigned long xvclk_rate; 1223 unsigned long pll1_rate; 1224 1225 xvclk_rate = clk_get_rate(sensor->xvclk); 1226 pll1_rate = xvclk_rate * config->pll_mul; 1227 1228 switch (config->pll_pre_div) { 1229 case 5: 1230 pll1_rate *= 3; 1231 pll1_rate /= 2; 1232 break; 1233 case 7: 1234 pll1_rate *= 5; 1235 pll1_rate /= 2; 1236 break; 1237 default: 1238 pll1_rate /= config->pll_pre_div; 1239 break; 1240 } 1241 1242 return pll1_rate; 1243 } 1244 1245 static int ov5648_mode_pll1_configure(struct ov5648_sensor *sensor, 1246 const struct ov5648_mode *mode, 1247 u32 mbus_code) 1248 { 1249 const struct ov5648_pll1_config *config; 1250 u8 value; 1251 int ret; 1252 1253 value = OV5648_PLL_CTRL0_PLL_CHARGE_PUMP(1); 1254 1255 switch (mbus_code) { 1256 case MEDIA_BUS_FMT_SBGGR8_1X8: 1257 config = mode->pll1_config[0]; 1258 value |= OV5648_PLL_CTRL0_BITS(8); 1259 break; 1260 case MEDIA_BUS_FMT_SBGGR10_1X10: 1261 config = mode->pll1_config[1]; 1262 value |= OV5648_PLL_CTRL0_BITS(10); 1263 break; 1264 default: 1265 return -EINVAL; 1266 } 1267 1268 ret = ov5648_write(sensor, OV5648_PLL_CTRL0_REG, value); 1269 if (ret) 1270 return ret; 1271 1272 ret = ov5648_write(sensor, OV5648_PLL_DIV_REG, 1273 OV5648_PLL_DIV_ROOT_DIV(config->root_div) | 1274 OV5648_PLL_DIV_PLL_PRE_DIV(config->pll_pre_div)); 1275 if (ret) 1276 return ret; 1277 1278 ret = ov5648_write(sensor, OV5648_PLL_MUL_REG, 1279 OV5648_PLL_MUL(config->pll_mul)); 1280 if (ret) 1281 return ret; 1282 1283 ret = ov5648_write(sensor, OV5648_PLL_CTRL1_REG, 1284 OV5648_PLL_CTRL1_SYS_DIV(config->sys_div) | 1285 OV5648_PLL_CTRL1_MIPI_DIV(config->mipi_div)); 1286 if (ret) 1287 return ret; 1288 1289 return ov5648_write(sensor, OV5648_SRB_CTRL_REG, 1290 OV5648_SRB_CTRL_SCLK_DIV(config->sclk_div) | 1291 OV5648_SRB_CTRL_SCLK_ARBITER_EN); 1292 } 1293 1294 static int ov5648_mode_pll2_configure(struct ov5648_sensor *sensor, 1295 const struct ov5648_mode *mode) 1296 { 1297 const struct ov5648_pll2_config *config = mode->pll2_config; 1298 int ret; 1299 1300 ret = ov5648_write(sensor, OV5648_PLLS_DIV_REG, 1301 OV5648_PLLS_DIV_PLLS_PRE_DIV(config->plls_pre_div) | 1302 OV5648_PLLS_DIV_PLLS_DIV_R(config->plls_div_r) | 1303 OV5648_PLLS_DIV_PLLS_SEL_DIV(config->sel_div)); 1304 if (ret) 1305 return ret; 1306 1307 ret = ov5648_write(sensor, OV5648_PLLS_MUL_REG, 1308 OV5648_PLLS_MUL(config->plls_mul)); 1309 if (ret) 1310 return ret; 1311 1312 return ov5648_write(sensor, OV5648_PLLS_CTRL_REG, 1313 OV5648_PLLS_CTRL_PLL_CHARGE_PUMP(1) | 1314 OV5648_PLLS_CTRL_SYS_DIV(config->sys_div)); 1315 } 1316 1317 static int ov5648_mode_configure(struct ov5648_sensor *sensor, 1318 const struct ov5648_mode *mode, u32 mbus_code) 1319 { 1320 int ret; 1321 1322 /* Crop Start X */ 1323 1324 ret = ov5648_write(sensor, OV5648_CROP_START_X_H_REG, 1325 OV5648_CROP_START_X_H(mode->crop_start_x)); 1326 if (ret) 1327 return ret; 1328 1329 ret = ov5648_write(sensor, OV5648_CROP_START_X_L_REG, 1330 OV5648_CROP_START_X_L(mode->crop_start_x)); 1331 if (ret) 1332 return ret; 1333 1334 /* Offset X */ 1335 1336 ret = ov5648_write(sensor, OV5648_OFFSET_X_H_REG, 1337 OV5648_OFFSET_X_H(mode->offset_x)); 1338 if (ret) 1339 return ret; 1340 1341 ret = ov5648_write(sensor, OV5648_OFFSET_X_L_REG, 1342 OV5648_OFFSET_X_L(mode->offset_x)); 1343 if (ret) 1344 return ret; 1345 1346 /* Output Size X */ 1347 1348 ret = ov5648_write(sensor, OV5648_OUTPUT_SIZE_X_H_REG, 1349 OV5648_OUTPUT_SIZE_X_H(mode->output_size_x)); 1350 if (ret) 1351 return ret; 1352 1353 ret = ov5648_write(sensor, OV5648_OUTPUT_SIZE_X_L_REG, 1354 OV5648_OUTPUT_SIZE_X_L(mode->output_size_x)); 1355 if (ret) 1356 return ret; 1357 1358 /* Crop End X */ 1359 1360 ret = ov5648_write(sensor, OV5648_CROP_END_X_H_REG, 1361 OV5648_CROP_END_X_H(mode->crop_end_x)); 1362 if (ret) 1363 return ret; 1364 1365 ret = ov5648_write(sensor, OV5648_CROP_END_X_L_REG, 1366 OV5648_CROP_END_X_L(mode->crop_end_x)); 1367 if (ret) 1368 return ret; 1369 1370 /* Horizontal Total Size */ 1371 1372 ret = ov5648_write(sensor, OV5648_HTS_H_REG, OV5648_HTS_H(mode->hts)); 1373 if (ret) 1374 return ret; 1375 1376 ret = ov5648_write(sensor, OV5648_HTS_L_REG, OV5648_HTS_L(mode->hts)); 1377 if (ret) 1378 return ret; 1379 1380 /* Crop Start Y */ 1381 1382 ret = ov5648_write(sensor, OV5648_CROP_START_Y_H_REG, 1383 OV5648_CROP_START_Y_H(mode->crop_start_y)); 1384 if (ret) 1385 return ret; 1386 1387 ret = ov5648_write(sensor, OV5648_CROP_START_Y_L_REG, 1388 OV5648_CROP_START_Y_L(mode->crop_start_y)); 1389 if (ret) 1390 return ret; 1391 1392 /* Offset Y */ 1393 1394 ret = ov5648_write(sensor, OV5648_OFFSET_Y_H_REG, 1395 OV5648_OFFSET_Y_H(mode->offset_y)); 1396 if (ret) 1397 return ret; 1398 1399 ret = ov5648_write(sensor, OV5648_OFFSET_Y_L_REG, 1400 OV5648_OFFSET_Y_L(mode->offset_y)); 1401 if (ret) 1402 return ret; 1403 1404 /* Output Size Y */ 1405 1406 ret = ov5648_write(sensor, OV5648_OUTPUT_SIZE_Y_H_REG, 1407 OV5648_OUTPUT_SIZE_Y_H(mode->output_size_y)); 1408 if (ret) 1409 return ret; 1410 1411 ret = ov5648_write(sensor, OV5648_OUTPUT_SIZE_Y_L_REG, 1412 OV5648_OUTPUT_SIZE_Y_L(mode->output_size_y)); 1413 if (ret) 1414 return ret; 1415 1416 /* Crop End Y */ 1417 1418 ret = ov5648_write(sensor, OV5648_CROP_END_Y_H_REG, 1419 OV5648_CROP_END_Y_H(mode->crop_end_y)); 1420 if (ret) 1421 return ret; 1422 1423 ret = ov5648_write(sensor, OV5648_CROP_END_Y_L_REG, 1424 OV5648_CROP_END_Y_L(mode->crop_end_y)); 1425 if (ret) 1426 return ret; 1427 1428 /* Vertical Total Size */ 1429 1430 ret = ov5648_write(sensor, OV5648_VTS_H_REG, OV5648_VTS_H(mode->vts)); 1431 if (ret) 1432 return ret; 1433 1434 ret = ov5648_write(sensor, OV5648_VTS_L_REG, OV5648_VTS_L(mode->vts)); 1435 if (ret) 1436 return ret; 1437 1438 /* Flip/Mirror/Binning */ 1439 1440 /* 1441 * A debug bit is enabled by default and needs to be cleared for 1442 * subsampling to work. 1443 */ 1444 ret = ov5648_update_bits(sensor, OV5648_TC20_REG, 1445 OV5648_TC20_DEBUG | 1446 OV5648_TC20_BINNING_VERT_EN, 1447 mode->binning_y ? OV5648_TC20_BINNING_VERT_EN : 1448 0); 1449 if (ret) 1450 return ret; 1451 1452 ret = ov5648_update_bits(sensor, OV5648_TC21_REG, 1453 OV5648_TC21_BINNING_HORZ_EN, 1454 mode->binning_x ? OV5648_TC21_BINNING_HORZ_EN : 1455 0); 1456 if (ret) 1457 return ret; 1458 1459 ret = ov5648_write(sensor, OV5648_SUB_INC_X_REG, 1460 OV5648_SUB_INC_X_ODD(mode->inc_x_odd) | 1461 OV5648_SUB_INC_X_EVEN(mode->inc_x_even)); 1462 if (ret) 1463 return ret; 1464 1465 ret = ov5648_write(sensor, OV5648_SUB_INC_Y_REG, 1466 OV5648_SUB_INC_Y_ODD(mode->inc_y_odd) | 1467 OV5648_SUB_INC_Y_EVEN(mode->inc_y_even)); 1468 if (ret) 1469 return ret; 1470 1471 /* PLLs */ 1472 1473 ret = ov5648_mode_pll1_configure(sensor, mode, mbus_code); 1474 if (ret) 1475 return ret; 1476 1477 ret = ov5648_mode_pll2_configure(sensor, mode); 1478 if (ret) 1479 return ret; 1480 1481 /* Extra registers */ 1482 1483 if (mode->register_values) { 1484 ret = ov5648_write_sequence(sensor, mode->register_values, 1485 mode->register_values_count); 1486 if (ret) 1487 return ret; 1488 } 1489 1490 return 0; 1491 } 1492 1493 static unsigned long ov5648_mode_mipi_clk_rate(struct ov5648_sensor *sensor, 1494 const struct ov5648_mode *mode, 1495 u32 mbus_code) 1496 { 1497 const struct ov5648_pll1_config *config; 1498 unsigned long pll1_rate; 1499 1500 switch (mbus_code) { 1501 case MEDIA_BUS_FMT_SBGGR8_1X8: 1502 config = mode->pll1_config[0]; 1503 break; 1504 case MEDIA_BUS_FMT_SBGGR10_1X10: 1505 config = mode->pll1_config[1]; 1506 break; 1507 default: 1508 return 0; 1509 } 1510 1511 pll1_rate = ov5648_mode_pll1_rate(sensor, config); 1512 1513 return pll1_rate / config->sys_div / config->mipi_div / 2; 1514 } 1515 1516 /* Exposure */ 1517 1518 static int ov5648_exposure_auto_configure(struct ov5648_sensor *sensor, 1519 bool enable) 1520 { 1521 return ov5648_update_bits(sensor, OV5648_MANUAL_CTRL_REG, 1522 OV5648_MANUAL_CTRL_AEC_MANUAL_EN, 1523 enable ? 0 : OV5648_MANUAL_CTRL_AEC_MANUAL_EN); 1524 } 1525 1526 static int ov5648_exposure_configure(struct ov5648_sensor *sensor, u32 exposure) 1527 { 1528 struct ov5648_ctrls *ctrls = &sensor->ctrls; 1529 int ret; 1530 1531 if (ctrls->exposure_auto->val != V4L2_EXPOSURE_MANUAL) 1532 return -EINVAL; 1533 1534 ret = ov5648_write(sensor, OV5648_EXPOSURE_CTRL_HH_REG, 1535 OV5648_EXPOSURE_CTRL_HH(exposure)); 1536 if (ret) 1537 return ret; 1538 1539 ret = ov5648_write(sensor, OV5648_EXPOSURE_CTRL_H_REG, 1540 OV5648_EXPOSURE_CTRL_H(exposure)); 1541 if (ret) 1542 return ret; 1543 1544 return ov5648_write(sensor, OV5648_EXPOSURE_CTRL_L_REG, 1545 OV5648_EXPOSURE_CTRL_L(exposure)); 1546 } 1547 1548 static int ov5648_exposure_value(struct ov5648_sensor *sensor, 1549 u32 *exposure) 1550 { 1551 u8 exposure_hh = 0, exposure_h = 0, exposure_l = 0; 1552 int ret; 1553 1554 ret = ov5648_read(sensor, OV5648_EXPOSURE_CTRL_HH_REG, &exposure_hh); 1555 if (ret) 1556 return ret; 1557 1558 ret = ov5648_read(sensor, OV5648_EXPOSURE_CTRL_H_REG, &exposure_h); 1559 if (ret) 1560 return ret; 1561 1562 ret = ov5648_read(sensor, OV5648_EXPOSURE_CTRL_L_REG, &exposure_l); 1563 if (ret) 1564 return ret; 1565 1566 *exposure = OV5648_EXPOSURE_CTRL_HH_VALUE((u32)exposure_hh) | 1567 OV5648_EXPOSURE_CTRL_H_VALUE((u32)exposure_h) | 1568 OV5648_EXPOSURE_CTRL_L_VALUE((u32)exposure_l); 1569 1570 return 0; 1571 } 1572 1573 /* Gain */ 1574 1575 static int ov5648_gain_auto_configure(struct ov5648_sensor *sensor, bool enable) 1576 { 1577 return ov5648_update_bits(sensor, OV5648_MANUAL_CTRL_REG, 1578 OV5648_MANUAL_CTRL_AGC_MANUAL_EN, 1579 enable ? 0 : OV5648_MANUAL_CTRL_AGC_MANUAL_EN); 1580 } 1581 1582 static int ov5648_gain_configure(struct ov5648_sensor *sensor, u32 gain) 1583 { 1584 struct ov5648_ctrls *ctrls = &sensor->ctrls; 1585 int ret; 1586 1587 if (ctrls->gain_auto->val) 1588 return -EINVAL; 1589 1590 ret = ov5648_write(sensor, OV5648_GAIN_CTRL_H_REG, 1591 OV5648_GAIN_CTRL_H(gain)); 1592 if (ret) 1593 return ret; 1594 1595 return ov5648_write(sensor, OV5648_GAIN_CTRL_L_REG, 1596 OV5648_GAIN_CTRL_L(gain)); 1597 } 1598 1599 static int ov5648_gain_value(struct ov5648_sensor *sensor, u32 *gain) 1600 { 1601 u8 gain_h = 0, gain_l = 0; 1602 int ret; 1603 1604 ret = ov5648_read(sensor, OV5648_GAIN_CTRL_H_REG, &gain_h); 1605 if (ret) 1606 return ret; 1607 1608 ret = ov5648_read(sensor, OV5648_GAIN_CTRL_L_REG, &gain_l); 1609 if (ret) 1610 return ret; 1611 1612 *gain = OV5648_GAIN_CTRL_H_VALUE((u32)gain_h) | 1613 OV5648_GAIN_CTRL_L_VALUE((u32)gain_l); 1614 1615 return 0; 1616 } 1617 1618 /* White Balance */ 1619 1620 static int ov5648_white_balance_auto_configure(struct ov5648_sensor *sensor, 1621 bool enable) 1622 { 1623 return ov5648_write(sensor, OV5648_AWB_CTRL_REG, 1624 enable ? 0 : OV5648_AWB_CTRL_GAIN_MANUAL_EN); 1625 } 1626 1627 static int ov5648_white_balance_configure(struct ov5648_sensor *sensor, 1628 u32 red_balance, u32 blue_balance) 1629 { 1630 struct ov5648_ctrls *ctrls = &sensor->ctrls; 1631 int ret; 1632 1633 if (ctrls->white_balance_auto->val) 1634 return -EINVAL; 1635 1636 ret = ov5648_write(sensor, OV5648_GAIN_RED_MAN_H_REG, 1637 OV5648_GAIN_RED_MAN_H(red_balance)); 1638 if (ret) 1639 return ret; 1640 1641 ret = ov5648_write(sensor, OV5648_GAIN_RED_MAN_L_REG, 1642 OV5648_GAIN_RED_MAN_L(red_balance)); 1643 if (ret) 1644 return ret; 1645 1646 ret = ov5648_write(sensor, OV5648_GAIN_BLUE_MAN_H_REG, 1647 OV5648_GAIN_BLUE_MAN_H(blue_balance)); 1648 if (ret) 1649 return ret; 1650 1651 return ov5648_write(sensor, OV5648_GAIN_BLUE_MAN_L_REG, 1652 OV5648_GAIN_BLUE_MAN_L(blue_balance)); 1653 } 1654 1655 /* Flip */ 1656 1657 static int ov5648_flip_vert_configure(struct ov5648_sensor *sensor, bool enable) 1658 { 1659 u8 bits = OV5648_TC20_FLIP_VERT_ISP_EN | 1660 OV5648_TC20_FLIP_VERT_SENSOR_EN; 1661 1662 return ov5648_update_bits(sensor, OV5648_TC20_REG, bits, 1663 enable ? bits : 0); 1664 } 1665 1666 static int ov5648_flip_horz_configure(struct ov5648_sensor *sensor, bool enable) 1667 { 1668 u8 bits = OV5648_TC21_FLIP_HORZ_ISP_EN | 1669 OV5648_TC21_FLIP_HORZ_SENSOR_EN; 1670 1671 return ov5648_update_bits(sensor, OV5648_TC21_REG, bits, 1672 enable ? bits : 0); 1673 } 1674 1675 /* Test Pattern */ 1676 1677 static int ov5648_test_pattern_configure(struct ov5648_sensor *sensor, 1678 unsigned int index) 1679 { 1680 if (index >= ARRAY_SIZE(ov5648_test_pattern_bits)) 1681 return -EINVAL; 1682 1683 return ov5648_write(sensor, OV5648_ISP_CTRL3D_REG, 1684 ov5648_test_pattern_bits[index]); 1685 } 1686 1687 /* State */ 1688 1689 static int ov5648_state_mipi_configure(struct ov5648_sensor *sensor, 1690 const struct ov5648_mode *mode, 1691 u32 mbus_code) 1692 { 1693 struct ov5648_ctrls *ctrls = &sensor->ctrls; 1694 struct v4l2_fwnode_bus_mipi_csi2 *bus_mipi_csi2 = 1695 &sensor->endpoint.bus.mipi_csi2; 1696 unsigned long mipi_clk_rate; 1697 unsigned int bits_per_sample; 1698 unsigned int lanes_count; 1699 unsigned int i, j; 1700 s64 mipi_pixel_rate; 1701 1702 mipi_clk_rate = ov5648_mode_mipi_clk_rate(sensor, mode, mbus_code); 1703 if (!mipi_clk_rate) 1704 return -EINVAL; 1705 1706 for (i = 0; i < ARRAY_SIZE(ov5648_link_freq_menu); i++) { 1707 s64 freq = ov5648_link_freq_menu[i]; 1708 1709 if (freq == mipi_clk_rate) 1710 break; 1711 } 1712 1713 for (j = 0; j < sensor->endpoint.nr_of_link_frequencies; j++) { 1714 u64 freq = sensor->endpoint.link_frequencies[j]; 1715 1716 if (freq == mipi_clk_rate) 1717 break; 1718 } 1719 1720 if (i == ARRAY_SIZE(ov5648_link_freq_menu)) { 1721 dev_err(sensor->dev, 1722 "failed to find %lu clk rate in link freq\n", 1723 mipi_clk_rate); 1724 } else if (j == sensor->endpoint.nr_of_link_frequencies) { 1725 dev_err(sensor->dev, 1726 "failed to find %lu clk rate in endpoint link-frequencies\n", 1727 mipi_clk_rate); 1728 } else { 1729 __v4l2_ctrl_s_ctrl(ctrls->link_freq, i); 1730 } 1731 1732 switch (mbus_code) { 1733 case MEDIA_BUS_FMT_SBGGR8_1X8: 1734 bits_per_sample = 8; 1735 break; 1736 case MEDIA_BUS_FMT_SBGGR10_1X10: 1737 bits_per_sample = 10; 1738 break; 1739 default: 1740 return -EINVAL; 1741 } 1742 1743 lanes_count = bus_mipi_csi2->num_data_lanes; 1744 mipi_pixel_rate = mipi_clk_rate * 2 * lanes_count / bits_per_sample; 1745 1746 __v4l2_ctrl_s_ctrl_int64(ctrls->pixel_rate, mipi_pixel_rate); 1747 1748 return 0; 1749 } 1750 1751 static int ov5648_state_configure(struct ov5648_sensor *sensor, 1752 const struct ov5648_mode *mode, 1753 u32 mbus_code) 1754 { 1755 int ret; 1756 1757 if (sensor->state.streaming) 1758 return -EBUSY; 1759 1760 /* State will be configured at first power on otherwise. */ 1761 if (pm_runtime_enabled(sensor->dev) && 1762 !pm_runtime_suspended(sensor->dev)) { 1763 ret = ov5648_mode_configure(sensor, mode, mbus_code); 1764 if (ret) 1765 return ret; 1766 } 1767 1768 ret = ov5648_state_mipi_configure(sensor, mode, mbus_code); 1769 if (ret) 1770 return ret; 1771 1772 sensor->state.mode = mode; 1773 sensor->state.mbus_code = mbus_code; 1774 1775 return 0; 1776 } 1777 1778 static int ov5648_state_init(struct ov5648_sensor *sensor) 1779 { 1780 return ov5648_state_configure(sensor, &ov5648_modes[0], 1781 ov5648_mbus_codes[0]); 1782 } 1783 1784 /* Sensor Base */ 1785 1786 static int ov5648_sensor_init(struct ov5648_sensor *sensor) 1787 { 1788 int ret; 1789 1790 ret = ov5648_sw_reset(sensor); 1791 if (ret) { 1792 dev_err(sensor->dev, "failed to perform sw reset\n"); 1793 return ret; 1794 } 1795 1796 ret = ov5648_sw_standby(sensor, 1); 1797 if (ret) { 1798 dev_err(sensor->dev, "failed to set sensor standby\n"); 1799 return ret; 1800 } 1801 1802 ret = ov5648_chip_id_check(sensor); 1803 if (ret) { 1804 dev_err(sensor->dev, "failed to check sensor chip id\n"); 1805 return ret; 1806 } 1807 1808 ret = ov5648_avdd_internal_power(sensor, !sensor->avdd); 1809 if (ret) { 1810 dev_err(sensor->dev, "failed to set internal avdd power\n"); 1811 return ret; 1812 } 1813 1814 ret = ov5648_write_sequence(sensor, ov5648_init_sequence, 1815 ARRAY_SIZE(ov5648_init_sequence)); 1816 if (ret) { 1817 dev_err(sensor->dev, "failed to write init sequence\n"); 1818 return ret; 1819 } 1820 1821 ret = ov5648_pad_configure(sensor); 1822 if (ret) { 1823 dev_err(sensor->dev, "failed to configure pad\n"); 1824 return ret; 1825 } 1826 1827 ret = ov5648_mipi_configure(sensor); 1828 if (ret) { 1829 dev_err(sensor->dev, "failed to configure MIPI\n"); 1830 return ret; 1831 } 1832 1833 ret = ov5648_isp_configure(sensor); 1834 if (ret) { 1835 dev_err(sensor->dev, "failed to configure ISP\n"); 1836 return ret; 1837 } 1838 1839 ret = ov5648_black_level_configure(sensor); 1840 if (ret) { 1841 dev_err(sensor->dev, "failed to configure black level\n"); 1842 return ret; 1843 } 1844 1845 /* Configure current mode. */ 1846 ret = ov5648_state_configure(sensor, sensor->state.mode, 1847 sensor->state.mbus_code); 1848 if (ret) { 1849 dev_err(sensor->dev, "failed to configure state\n"); 1850 return ret; 1851 } 1852 1853 return 0; 1854 } 1855 1856 static int ov5648_sensor_power(struct ov5648_sensor *sensor, bool on) 1857 { 1858 /* Keep initialized to zero for disable label. */ 1859 int ret = 0; 1860 1861 /* 1862 * General notes about the power sequence: 1863 * - power-down GPIO must be active (low) during power-on; 1864 * - reset GPIO state does not matter during power-on; 1865 * - XVCLK must be provided 1 ms before register access; 1866 * - 10 ms are needed between power-down deassert and register access. 1867 */ 1868 1869 /* Note that regulator-and-GPIO-based power is untested. */ 1870 if (on) { 1871 gpiod_set_value_cansleep(sensor->reset, 1); 1872 gpiod_set_value_cansleep(sensor->powerdown, 1); 1873 1874 ret = regulator_enable(sensor->dovdd); 1875 if (ret) { 1876 dev_err(sensor->dev, 1877 "failed to enable DOVDD regulator\n"); 1878 goto disable; 1879 } 1880 1881 if (sensor->avdd) { 1882 ret = regulator_enable(sensor->avdd); 1883 if (ret) { 1884 dev_err(sensor->dev, 1885 "failed to enable AVDD regulator\n"); 1886 goto disable; 1887 } 1888 } 1889 1890 ret = regulator_enable(sensor->dvdd); 1891 if (ret) { 1892 dev_err(sensor->dev, 1893 "failed to enable DVDD regulator\n"); 1894 goto disable; 1895 } 1896 1897 /* According to OV5648 power up diagram. */ 1898 usleep_range(5000, 10000); 1899 1900 ret = clk_prepare_enable(sensor->xvclk); 1901 if (ret) { 1902 dev_err(sensor->dev, "failed to enable XVCLK clock\n"); 1903 goto disable; 1904 } 1905 1906 gpiod_set_value_cansleep(sensor->reset, 0); 1907 gpiod_set_value_cansleep(sensor->powerdown, 0); 1908 1909 usleep_range(20000, 25000); 1910 } else { 1911 disable: 1912 gpiod_set_value_cansleep(sensor->powerdown, 1); 1913 gpiod_set_value_cansleep(sensor->reset, 1); 1914 1915 clk_disable_unprepare(sensor->xvclk); 1916 1917 regulator_disable(sensor->dvdd); 1918 1919 if (sensor->avdd) 1920 regulator_disable(sensor->avdd); 1921 1922 regulator_disable(sensor->dovdd); 1923 } 1924 1925 return ret; 1926 } 1927 1928 /* Controls */ 1929 1930 static int ov5648_g_volatile_ctrl(struct v4l2_ctrl *ctrl) 1931 { 1932 struct v4l2_subdev *subdev = ov5648_ctrl_subdev(ctrl); 1933 struct ov5648_sensor *sensor = ov5648_subdev_sensor(subdev); 1934 struct ov5648_ctrls *ctrls = &sensor->ctrls; 1935 int ret; 1936 1937 switch (ctrl->id) { 1938 case V4L2_CID_EXPOSURE_AUTO: 1939 ret = ov5648_exposure_value(sensor, &ctrls->exposure->val); 1940 if (ret) 1941 return ret; 1942 break; 1943 case V4L2_CID_AUTOGAIN: 1944 ret = ov5648_gain_value(sensor, &ctrls->gain->val); 1945 if (ret) 1946 return ret; 1947 break; 1948 default: 1949 return -EINVAL; 1950 } 1951 1952 return 0; 1953 } 1954 1955 static int ov5648_s_ctrl(struct v4l2_ctrl *ctrl) 1956 { 1957 struct v4l2_subdev *subdev = ov5648_ctrl_subdev(ctrl); 1958 struct ov5648_sensor *sensor = ov5648_subdev_sensor(subdev); 1959 struct ov5648_ctrls *ctrls = &sensor->ctrls; 1960 unsigned int index; 1961 bool enable; 1962 int ret; 1963 1964 /* Wait for the sensor to be on before setting controls. */ 1965 if (pm_runtime_suspended(sensor->dev)) 1966 return 0; 1967 1968 switch (ctrl->id) { 1969 case V4L2_CID_EXPOSURE_AUTO: 1970 enable = ctrl->val == V4L2_EXPOSURE_AUTO; 1971 1972 ret = ov5648_exposure_auto_configure(sensor, enable); 1973 if (ret) 1974 return ret; 1975 1976 if (!enable && ctrls->exposure->is_new) { 1977 ret = ov5648_exposure_configure(sensor, 1978 ctrls->exposure->val); 1979 if (ret) 1980 return ret; 1981 } 1982 break; 1983 case V4L2_CID_AUTOGAIN: 1984 enable = !!ctrl->val; 1985 1986 ret = ov5648_gain_auto_configure(sensor, enable); 1987 if (ret) 1988 return ret; 1989 1990 if (!enable) { 1991 ret = ov5648_gain_configure(sensor, ctrls->gain->val); 1992 if (ret) 1993 return ret; 1994 } 1995 break; 1996 case V4L2_CID_AUTO_WHITE_BALANCE: 1997 enable = !!ctrl->val; 1998 1999 ret = ov5648_white_balance_auto_configure(sensor, enable); 2000 if (ret) 2001 return ret; 2002 2003 if (!enable) { 2004 ret = ov5648_white_balance_configure(sensor, 2005 ctrls->red_balance->val, 2006 ctrls->blue_balance->val); 2007 if (ret) 2008 return ret; 2009 } 2010 break; 2011 case V4L2_CID_HFLIP: 2012 enable = !!ctrl->val; 2013 return ov5648_flip_horz_configure(sensor, enable); 2014 case V4L2_CID_VFLIP: 2015 enable = !!ctrl->val; 2016 return ov5648_flip_vert_configure(sensor, enable); 2017 case V4L2_CID_TEST_PATTERN: 2018 index = (unsigned int)ctrl->val; 2019 return ov5648_test_pattern_configure(sensor, index); 2020 default: 2021 return -EINVAL; 2022 } 2023 2024 return 0; 2025 } 2026 2027 static const struct v4l2_ctrl_ops ov5648_ctrl_ops = { 2028 .g_volatile_ctrl = ov5648_g_volatile_ctrl, 2029 .s_ctrl = ov5648_s_ctrl, 2030 }; 2031 2032 static int ov5648_ctrls_init(struct ov5648_sensor *sensor) 2033 { 2034 struct ov5648_ctrls *ctrls = &sensor->ctrls; 2035 struct v4l2_ctrl_handler *handler = &ctrls->handler; 2036 const struct v4l2_ctrl_ops *ops = &ov5648_ctrl_ops; 2037 int ret; 2038 2039 v4l2_ctrl_handler_init(handler, 32); 2040 2041 /* Use our mutex for ctrl locking. */ 2042 handler->lock = &sensor->mutex; 2043 2044 /* Exposure */ 2045 2046 ctrls->exposure_auto = v4l2_ctrl_new_std_menu(handler, ops, 2047 V4L2_CID_EXPOSURE_AUTO, 2048 V4L2_EXPOSURE_MANUAL, 0, 2049 V4L2_EXPOSURE_AUTO); 2050 2051 ctrls->exposure = v4l2_ctrl_new_std(handler, ops, V4L2_CID_EXPOSURE, 2052 16, 1048575, 16, 512); 2053 2054 v4l2_ctrl_auto_cluster(2, &ctrls->exposure_auto, 1, true); 2055 2056 /* Gain */ 2057 2058 ctrls->gain_auto = 2059 v4l2_ctrl_new_std(handler, ops, V4L2_CID_AUTOGAIN, 0, 1, 1, 1); 2060 2061 ctrls->gain = v4l2_ctrl_new_std(handler, ops, V4L2_CID_GAIN, 16, 1023, 2062 16, 16); 2063 2064 v4l2_ctrl_auto_cluster(2, &ctrls->gain_auto, 0, true); 2065 2066 /* White Balance */ 2067 2068 ctrls->white_balance_auto = 2069 v4l2_ctrl_new_std(handler, ops, V4L2_CID_AUTO_WHITE_BALANCE, 0, 2070 1, 1, 1); 2071 2072 ctrls->red_balance = v4l2_ctrl_new_std(handler, ops, 2073 V4L2_CID_RED_BALANCE, 0, 4095, 2074 1, 1024); 2075 2076 ctrls->blue_balance = v4l2_ctrl_new_std(handler, ops, 2077 V4L2_CID_BLUE_BALANCE, 0, 4095, 2078 1, 1024); 2079 2080 v4l2_ctrl_auto_cluster(3, &ctrls->white_balance_auto, 0, false); 2081 2082 /* Flip */ 2083 2084 v4l2_ctrl_new_std(handler, ops, V4L2_CID_HFLIP, 0, 1, 1, 0); 2085 v4l2_ctrl_new_std(handler, ops, V4L2_CID_VFLIP, 0, 1, 1, 0); 2086 2087 /* Test Pattern */ 2088 2089 v4l2_ctrl_new_std_menu_items(handler, ops, V4L2_CID_TEST_PATTERN, 2090 ARRAY_SIZE(ov5648_test_pattern_menu) - 1, 2091 0, 0, ov5648_test_pattern_menu); 2092 2093 /* MIPI CSI-2 */ 2094 2095 ctrls->link_freq = 2096 v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ, 2097 ARRAY_SIZE(ov5648_link_freq_menu) - 1, 2098 0, ov5648_link_freq_menu); 2099 2100 ctrls->pixel_rate = 2101 v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE, 1, 2102 INT_MAX, 1, 1); 2103 2104 if (handler->error) { 2105 ret = handler->error; 2106 goto error_ctrls; 2107 } 2108 2109 ctrls->exposure->flags |= V4L2_CTRL_FLAG_VOLATILE; 2110 ctrls->gain->flags |= V4L2_CTRL_FLAG_VOLATILE; 2111 2112 ctrls->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 2113 ctrls->pixel_rate->flags |= V4L2_CTRL_FLAG_READ_ONLY; 2114 2115 sensor->subdev.ctrl_handler = handler; 2116 2117 return 0; 2118 2119 error_ctrls: 2120 v4l2_ctrl_handler_free(handler); 2121 2122 return ret; 2123 } 2124 2125 /* Subdev Video Operations */ 2126 2127 static int ov5648_s_stream(struct v4l2_subdev *subdev, int enable) 2128 { 2129 struct ov5648_sensor *sensor = ov5648_subdev_sensor(subdev); 2130 struct ov5648_state *state = &sensor->state; 2131 int ret; 2132 2133 if (enable) { 2134 ret = pm_runtime_get_sync(sensor->dev); 2135 if (ret < 0) { 2136 pm_runtime_put_noidle(sensor->dev); 2137 return ret; 2138 } 2139 } 2140 2141 mutex_lock(&sensor->mutex); 2142 ret = ov5648_sw_standby(sensor, !enable); 2143 mutex_unlock(&sensor->mutex); 2144 2145 if (ret) 2146 return ret; 2147 2148 state->streaming = !!enable; 2149 2150 if (!enable) 2151 pm_runtime_put(sensor->dev); 2152 2153 return 0; 2154 } 2155 2156 static int ov5648_g_frame_interval(struct v4l2_subdev *subdev, 2157 struct v4l2_subdev_frame_interval *interval) 2158 { 2159 struct ov5648_sensor *sensor = ov5648_subdev_sensor(subdev); 2160 const struct ov5648_mode *mode; 2161 int ret = 0; 2162 2163 mutex_lock(&sensor->mutex); 2164 2165 mode = sensor->state.mode; 2166 2167 switch (sensor->state.mbus_code) { 2168 case MEDIA_BUS_FMT_SBGGR8_1X8: 2169 interval->interval = mode->frame_interval[0]; 2170 break; 2171 case MEDIA_BUS_FMT_SBGGR10_1X10: 2172 interval->interval = mode->frame_interval[1]; 2173 break; 2174 default: 2175 ret = -EINVAL; 2176 } 2177 2178 mutex_unlock(&sensor->mutex); 2179 2180 return ret; 2181 } 2182 2183 static const struct v4l2_subdev_video_ops ov5648_subdev_video_ops = { 2184 .s_stream = ov5648_s_stream, 2185 .g_frame_interval = ov5648_g_frame_interval, 2186 .s_frame_interval = ov5648_g_frame_interval, 2187 }; 2188 2189 /* Subdev Pad Operations */ 2190 2191 static int ov5648_enum_mbus_code(struct v4l2_subdev *subdev, 2192 struct v4l2_subdev_pad_config *config, 2193 struct v4l2_subdev_mbus_code_enum *code_enum) 2194 { 2195 if (code_enum->index >= ARRAY_SIZE(ov5648_mbus_codes)) 2196 return -EINVAL; 2197 2198 code_enum->code = ov5648_mbus_codes[code_enum->index]; 2199 2200 return 0; 2201 } 2202 2203 static void ov5648_mbus_format_fill(struct v4l2_mbus_framefmt *mbus_format, 2204 u32 mbus_code, 2205 const struct ov5648_mode *mode) 2206 { 2207 mbus_format->width = mode->output_size_x; 2208 mbus_format->height = mode->output_size_y; 2209 mbus_format->code = mbus_code; 2210 2211 mbus_format->field = V4L2_FIELD_NONE; 2212 mbus_format->colorspace = V4L2_COLORSPACE_RAW; 2213 mbus_format->ycbcr_enc = 2214 V4L2_MAP_YCBCR_ENC_DEFAULT(mbus_format->colorspace); 2215 mbus_format->quantization = V4L2_QUANTIZATION_FULL_RANGE; 2216 mbus_format->xfer_func = 2217 V4L2_MAP_XFER_FUNC_DEFAULT(mbus_format->colorspace); 2218 } 2219 2220 static int ov5648_get_fmt(struct v4l2_subdev *subdev, 2221 struct v4l2_subdev_pad_config *config, 2222 struct v4l2_subdev_format *format) 2223 { 2224 struct ov5648_sensor *sensor = ov5648_subdev_sensor(subdev); 2225 struct v4l2_mbus_framefmt *mbus_format = &format->format; 2226 2227 mutex_lock(&sensor->mutex); 2228 2229 if (format->which == V4L2_SUBDEV_FORMAT_TRY) 2230 *mbus_format = *v4l2_subdev_get_try_format(subdev, config, 2231 format->pad); 2232 else 2233 ov5648_mbus_format_fill(mbus_format, sensor->state.mbus_code, 2234 sensor->state.mode); 2235 2236 mutex_unlock(&sensor->mutex); 2237 2238 return 0; 2239 } 2240 2241 static int ov5648_set_fmt(struct v4l2_subdev *subdev, 2242 struct v4l2_subdev_pad_config *config, 2243 struct v4l2_subdev_format *format) 2244 { 2245 struct ov5648_sensor *sensor = ov5648_subdev_sensor(subdev); 2246 struct v4l2_mbus_framefmt *mbus_format = &format->format; 2247 const struct ov5648_mode *mode; 2248 u32 mbus_code = 0; 2249 unsigned int index; 2250 int ret = 0; 2251 2252 mutex_lock(&sensor->mutex); 2253 2254 if (sensor->state.streaming) { 2255 ret = -EBUSY; 2256 goto complete; 2257 } 2258 2259 /* Try to find requested mbus code. */ 2260 for (index = 0; index < ARRAY_SIZE(ov5648_mbus_codes); index++) { 2261 if (ov5648_mbus_codes[index] == mbus_format->code) { 2262 mbus_code = mbus_format->code; 2263 break; 2264 } 2265 } 2266 2267 /* Fallback to default. */ 2268 if (!mbus_code) 2269 mbus_code = ov5648_mbus_codes[0]; 2270 2271 /* Find the mode with nearest dimensions. */ 2272 mode = v4l2_find_nearest_size(ov5648_modes, ARRAY_SIZE(ov5648_modes), 2273 output_size_x, output_size_y, 2274 mbus_format->width, mbus_format->height); 2275 if (!mode) { 2276 ret = -EINVAL; 2277 goto complete; 2278 } 2279 2280 ov5648_mbus_format_fill(mbus_format, mbus_code, mode); 2281 2282 if (format->which == V4L2_SUBDEV_FORMAT_TRY) 2283 *v4l2_subdev_get_try_format(subdev, config, format->pad) = 2284 *mbus_format; 2285 else if (sensor->state.mode != mode || 2286 sensor->state.mbus_code != mbus_code) 2287 ret = ov5648_state_configure(sensor, mode, mbus_code); 2288 2289 complete: 2290 mutex_unlock(&sensor->mutex); 2291 2292 return ret; 2293 } 2294 2295 static int ov5648_enum_frame_size(struct v4l2_subdev *subdev, 2296 struct v4l2_subdev_pad_config *config, 2297 struct v4l2_subdev_frame_size_enum *size_enum) 2298 { 2299 const struct ov5648_mode *mode; 2300 2301 if (size_enum->index >= ARRAY_SIZE(ov5648_modes)) 2302 return -EINVAL; 2303 2304 mode = &ov5648_modes[size_enum->index]; 2305 2306 size_enum->min_width = size_enum->max_width = mode->output_size_x; 2307 size_enum->min_height = size_enum->max_height = mode->output_size_y; 2308 2309 return 0; 2310 } 2311 2312 static int ov5648_enum_frame_interval(struct v4l2_subdev *subdev, 2313 struct v4l2_subdev_pad_config *config, 2314 struct v4l2_subdev_frame_interval_enum *interval_enum) 2315 { 2316 const struct ov5648_mode *mode = NULL; 2317 unsigned int mode_index; 2318 unsigned int interval_index; 2319 2320 if (interval_enum->index > 0) 2321 return -EINVAL; 2322 2323 /* 2324 * Multiple modes with the same dimensions may have different frame 2325 * intervals, so look up each relevant mode. 2326 */ 2327 for (mode_index = 0, interval_index = 0; 2328 mode_index < ARRAY_SIZE(ov5648_modes); mode_index++) { 2329 mode = &ov5648_modes[mode_index]; 2330 2331 if (mode->output_size_x == interval_enum->width && 2332 mode->output_size_y == interval_enum->height) { 2333 if (interval_index == interval_enum->index) 2334 break; 2335 2336 interval_index++; 2337 } 2338 } 2339 2340 if (mode_index == ARRAY_SIZE(ov5648_modes) || !mode) 2341 return -EINVAL; 2342 2343 switch (interval_enum->code) { 2344 case MEDIA_BUS_FMT_SBGGR8_1X8: 2345 interval_enum->interval = mode->frame_interval[0]; 2346 break; 2347 case MEDIA_BUS_FMT_SBGGR10_1X10: 2348 interval_enum->interval = mode->frame_interval[1]; 2349 break; 2350 default: 2351 return -EINVAL; 2352 } 2353 2354 return 0; 2355 } 2356 2357 static const struct v4l2_subdev_pad_ops ov5648_subdev_pad_ops = { 2358 .enum_mbus_code = ov5648_enum_mbus_code, 2359 .get_fmt = ov5648_get_fmt, 2360 .set_fmt = ov5648_set_fmt, 2361 .enum_frame_size = ov5648_enum_frame_size, 2362 .enum_frame_interval = ov5648_enum_frame_interval, 2363 }; 2364 2365 static const struct v4l2_subdev_ops ov5648_subdev_ops = { 2366 .video = &ov5648_subdev_video_ops, 2367 .pad = &ov5648_subdev_pad_ops, 2368 }; 2369 2370 static int ov5648_suspend(struct device *dev) 2371 { 2372 struct i2c_client *client = to_i2c_client(dev); 2373 struct v4l2_subdev *subdev = i2c_get_clientdata(client); 2374 struct ov5648_sensor *sensor = ov5648_subdev_sensor(subdev); 2375 struct ov5648_state *state = &sensor->state; 2376 int ret = 0; 2377 2378 mutex_lock(&sensor->mutex); 2379 2380 if (state->streaming) { 2381 ret = ov5648_sw_standby(sensor, true); 2382 if (ret) 2383 goto complete; 2384 } 2385 2386 ret = ov5648_sensor_power(sensor, false); 2387 if (ret) 2388 ov5648_sw_standby(sensor, false); 2389 2390 complete: 2391 mutex_unlock(&sensor->mutex); 2392 2393 return ret; 2394 } 2395 2396 static int ov5648_resume(struct device *dev) 2397 { 2398 struct i2c_client *client = to_i2c_client(dev); 2399 struct v4l2_subdev *subdev = i2c_get_clientdata(client); 2400 struct ov5648_sensor *sensor = ov5648_subdev_sensor(subdev); 2401 struct ov5648_state *state = &sensor->state; 2402 int ret = 0; 2403 2404 mutex_lock(&sensor->mutex); 2405 2406 ret = ov5648_sensor_power(sensor, true); 2407 if (ret) 2408 goto complete; 2409 2410 ret = ov5648_sensor_init(sensor); 2411 if (ret) 2412 goto error_power; 2413 2414 ret = __v4l2_ctrl_handler_setup(&sensor->ctrls.handler); 2415 if (ret) 2416 goto error_power; 2417 2418 if (state->streaming) { 2419 ret = ov5648_sw_standby(sensor, false); 2420 if (ret) 2421 goto error_power; 2422 } 2423 2424 goto complete; 2425 2426 error_power: 2427 ov5648_sensor_power(sensor, false); 2428 2429 complete: 2430 mutex_unlock(&sensor->mutex); 2431 2432 return ret; 2433 } 2434 2435 static int ov5648_probe(struct i2c_client *client) 2436 { 2437 struct device *dev = &client->dev; 2438 struct fwnode_handle *handle; 2439 struct ov5648_sensor *sensor; 2440 struct v4l2_subdev *subdev; 2441 struct media_pad *pad; 2442 unsigned long rate; 2443 int ret; 2444 2445 sensor = devm_kzalloc(dev, sizeof(*sensor), GFP_KERNEL); 2446 if (!sensor) 2447 return -ENOMEM; 2448 2449 sensor->dev = dev; 2450 sensor->i2c_client = client; 2451 2452 /* Graph Endpoint */ 2453 2454 handle = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL); 2455 if (!handle) { 2456 dev_err(dev, "unable to find enpoint node\n"); 2457 return -EINVAL; 2458 } 2459 2460 sensor->endpoint.bus_type = V4L2_MBUS_CSI2_DPHY; 2461 2462 ret = v4l2_fwnode_endpoint_alloc_parse(handle, &sensor->endpoint); 2463 fwnode_handle_put(handle); 2464 if (ret) { 2465 dev_err(dev, "failed to parse endpoint node\n"); 2466 return ret; 2467 } 2468 2469 /* GPIOs */ 2470 2471 sensor->powerdown = devm_gpiod_get_optional(dev, "powerdown", 2472 GPIOD_OUT_HIGH); 2473 if (IS_ERR(sensor->powerdown)) { 2474 ret = PTR_ERR(sensor->powerdown); 2475 goto error_endpoint; 2476 } 2477 2478 sensor->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); 2479 if (IS_ERR(sensor->reset)) { 2480 ret = PTR_ERR(sensor->reset); 2481 goto error_endpoint; 2482 } 2483 2484 /* Regulators */ 2485 2486 /* DVDD: digital core */ 2487 sensor->dvdd = devm_regulator_get(dev, "dvdd"); 2488 if (IS_ERR(sensor->dvdd)) { 2489 dev_err(dev, "cannot get DVDD (digital core) regulator\n"); 2490 ret = PTR_ERR(sensor->dvdd); 2491 goto error_endpoint; 2492 } 2493 2494 /* DOVDD: digital I/O */ 2495 sensor->dovdd = devm_regulator_get(dev, "dovdd"); 2496 if (IS_ERR(sensor->dvdd)) { 2497 dev_err(dev, "cannot get DOVDD (digital I/O) regulator\n"); 2498 ret = PTR_ERR(sensor->dvdd); 2499 goto error_endpoint; 2500 } 2501 2502 /* AVDD: analog */ 2503 sensor->avdd = devm_regulator_get_optional(dev, "avdd"); 2504 if (IS_ERR(sensor->avdd)) { 2505 dev_info(dev, "no AVDD regulator provided, using internal\n"); 2506 sensor->avdd = NULL; 2507 } 2508 2509 /* External Clock */ 2510 2511 sensor->xvclk = devm_clk_get(dev, NULL); 2512 if (IS_ERR(sensor->xvclk)) { 2513 dev_err(dev, "failed to get external clock\n"); 2514 ret = PTR_ERR(sensor->xvclk); 2515 goto error_endpoint; 2516 } 2517 2518 rate = clk_get_rate(sensor->xvclk); 2519 if (rate != OV5648_XVCLK_RATE) { 2520 dev_err(dev, "clock rate %lu Hz is unsupported\n", rate); 2521 ret = -EINVAL; 2522 goto error_endpoint; 2523 } 2524 2525 /* Subdev, entity and pad */ 2526 2527 subdev = &sensor->subdev; 2528 v4l2_i2c_subdev_init(subdev, client, &ov5648_subdev_ops); 2529 2530 subdev->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 2531 subdev->entity.function = MEDIA_ENT_F_CAM_SENSOR; 2532 2533 pad = &sensor->pad; 2534 pad->flags = MEDIA_PAD_FL_SOURCE; 2535 2536 ret = media_entity_pads_init(&subdev->entity, 1, pad); 2537 if (ret) 2538 goto error_entity; 2539 2540 /* Mutex */ 2541 2542 mutex_init(&sensor->mutex); 2543 2544 /* Sensor */ 2545 2546 ret = ov5648_ctrls_init(sensor); 2547 if (ret) 2548 goto error_mutex; 2549 2550 ret = ov5648_state_init(sensor); 2551 if (ret) 2552 goto error_ctrls; 2553 2554 /* Runtime PM */ 2555 2556 pm_runtime_enable(sensor->dev); 2557 pm_runtime_set_suspended(sensor->dev); 2558 2559 /* V4L2 subdev register */ 2560 2561 ret = v4l2_async_register_subdev_sensor_common(subdev); 2562 if (ret) 2563 goto error_pm; 2564 2565 return 0; 2566 2567 error_pm: 2568 pm_runtime_disable(sensor->dev); 2569 2570 error_ctrls: 2571 v4l2_ctrl_handler_free(&sensor->ctrls.handler); 2572 2573 error_mutex: 2574 mutex_destroy(&sensor->mutex); 2575 2576 error_entity: 2577 media_entity_cleanup(&sensor->subdev.entity); 2578 2579 error_endpoint: 2580 v4l2_fwnode_endpoint_free(&sensor->endpoint); 2581 2582 return ret; 2583 } 2584 2585 static int ov5648_remove(struct i2c_client *client) 2586 { 2587 struct v4l2_subdev *subdev = i2c_get_clientdata(client); 2588 struct ov5648_sensor *sensor = ov5648_subdev_sensor(subdev); 2589 2590 v4l2_async_unregister_subdev(subdev); 2591 pm_runtime_disable(sensor->dev); 2592 v4l2_ctrl_handler_free(&sensor->ctrls.handler); 2593 mutex_destroy(&sensor->mutex); 2594 media_entity_cleanup(&subdev->entity); 2595 2596 return 0; 2597 } 2598 2599 static const struct dev_pm_ops ov5648_pm_ops = { 2600 SET_RUNTIME_PM_OPS(ov5648_suspend, ov5648_resume, NULL) 2601 }; 2602 2603 static const struct of_device_id ov5648_of_match[] = { 2604 { .compatible = "ovti,ov5648" }, 2605 { } 2606 }; 2607 MODULE_DEVICE_TABLE(of, ov5648_of_match); 2608 2609 static struct i2c_driver ov5648_driver = { 2610 .driver = { 2611 .name = "ov5648", 2612 .of_match_table = ov5648_of_match, 2613 .pm = &ov5648_pm_ops, 2614 }, 2615 .probe_new = ov5648_probe, 2616 .remove = ov5648_remove, 2617 }; 2618 2619 module_i2c_driver(ov5648_driver); 2620 2621 MODULE_AUTHOR("Paul Kocialkowski <paul.kocialkowski@bootlin.com>"); 2622 MODULE_DESCRIPTION("V4L2 driver for the OmniVision OV5648 image sensor"); 2623 MODULE_LICENSE("GPL v2"); 2624