1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2020 Intel Corporation. 3 4 #include <asm/unaligned.h> 5 #include <linux/acpi.h> 6 #include <linux/delay.h> 7 #include <linux/i2c.h> 8 #include <linux/module.h> 9 #include <linux/pm_runtime.h> 10 #include <linux/nvmem-provider.h> 11 #include <linux/regmap.h> 12 #include <media/v4l2-ctrls.h> 13 #include <media/v4l2-device.h> 14 #include <media/v4l2-fwnode.h> 15 16 #define OV2740_LINK_FREQ_360MHZ 360000000ULL 17 #define OV2740_SCLK 72000000LL 18 #define OV2740_MCLK 19200000 19 #define OV2740_DATA_LANES 2 20 #define OV2740_RGB_DEPTH 10 21 22 #define OV2740_REG_CHIP_ID 0x300a 23 #define OV2740_CHIP_ID 0x2740 24 25 #define OV2740_REG_MODE_SELECT 0x0100 26 #define OV2740_MODE_STANDBY 0x00 27 #define OV2740_MODE_STREAMING 0x01 28 29 /* vertical-timings from sensor */ 30 #define OV2740_REG_VTS 0x380e 31 #define OV2740_VTS_DEF 0x088a 32 #define OV2740_VTS_MIN 0x0460 33 #define OV2740_VTS_MAX 0x7fff 34 35 /* horizontal-timings from sensor */ 36 #define OV2740_REG_HTS 0x380c 37 38 /* Exposure controls from sensor */ 39 #define OV2740_REG_EXPOSURE 0x3500 40 #define OV2740_EXPOSURE_MIN 4 41 #define OV2740_EXPOSURE_MAX_MARGIN 8 42 #define OV2740_EXPOSURE_STEP 1 43 44 /* Analog gain controls from sensor */ 45 #define OV2740_REG_ANALOG_GAIN 0x3508 46 #define OV2740_ANAL_GAIN_MIN 128 47 #define OV2740_ANAL_GAIN_MAX 1983 48 #define OV2740_ANAL_GAIN_STEP 1 49 50 /* Digital gain controls from sensor */ 51 #define OV2740_REG_MWB_R_GAIN 0x500a 52 #define OV2740_REG_MWB_G_GAIN 0x500c 53 #define OV2740_REG_MWB_B_GAIN 0x500e 54 #define OV2740_DGTL_GAIN_MIN 0 55 #define OV2740_DGTL_GAIN_MAX 4095 56 #define OV2740_DGTL_GAIN_STEP 1 57 #define OV2740_DGTL_GAIN_DEFAULT 1024 58 59 /* Test Pattern Control */ 60 #define OV2740_REG_TEST_PATTERN 0x5040 61 #define OV2740_TEST_PATTERN_ENABLE BIT(7) 62 #define OV2740_TEST_PATTERN_BAR_SHIFT 2 63 64 /* ISP CTRL00 */ 65 #define OV2740_REG_ISP_CTRL00 0x5000 66 /* ISP CTRL01 */ 67 #define OV2740_REG_ISP_CTRL01 0x5001 68 /* Customer Addresses: 0x7010 - 0x710F */ 69 #define CUSTOMER_USE_OTP_SIZE 0x100 70 /* OTP registers from sensor */ 71 #define OV2740_REG_OTP_CUSTOMER 0x7010 72 73 struct nvm_data { 74 struct i2c_client *client; 75 struct nvmem_device *nvmem; 76 struct regmap *regmap; 77 char *nvm_buffer; 78 }; 79 80 enum { 81 OV2740_LINK_FREQ_360MHZ_INDEX, 82 }; 83 84 struct ov2740_reg { 85 u16 address; 86 u8 val; 87 }; 88 89 struct ov2740_reg_list { 90 u32 num_of_regs; 91 const struct ov2740_reg *regs; 92 }; 93 94 struct ov2740_link_freq_config { 95 const struct ov2740_reg_list reg_list; 96 }; 97 98 struct ov2740_mode { 99 /* Frame width in pixels */ 100 u32 width; 101 102 /* Frame height in pixels */ 103 u32 height; 104 105 /* Horizontal timining size */ 106 u32 hts; 107 108 /* Default vertical timining size */ 109 u32 vts_def; 110 111 /* Min vertical timining size */ 112 u32 vts_min; 113 114 /* Link frequency needed for this resolution */ 115 u32 link_freq_index; 116 117 /* Sensor register settings for this resolution */ 118 const struct ov2740_reg_list reg_list; 119 }; 120 121 static const struct ov2740_reg mipi_data_rate_720mbps[] = { 122 {0x0103, 0x01}, 123 {0x0302, 0x4b}, 124 {0x030d, 0x4b}, 125 {0x030e, 0x02}, 126 {0x030a, 0x01}, 127 {0x0312, 0x11}, 128 }; 129 130 static const struct ov2740_reg mode_1932x1092_regs[] = { 131 {0x3000, 0x00}, 132 {0x3018, 0x32}, 133 {0x3031, 0x0a}, 134 {0x3080, 0x08}, 135 {0x3083, 0xB4}, 136 {0x3103, 0x00}, 137 {0x3104, 0x01}, 138 {0x3106, 0x01}, 139 {0x3500, 0x00}, 140 {0x3501, 0x44}, 141 {0x3502, 0x40}, 142 {0x3503, 0x88}, 143 {0x3507, 0x00}, 144 {0x3508, 0x00}, 145 {0x3509, 0x80}, 146 {0x350c, 0x00}, 147 {0x350d, 0x80}, 148 {0x3510, 0x00}, 149 {0x3511, 0x00}, 150 {0x3512, 0x20}, 151 {0x3632, 0x00}, 152 {0x3633, 0x10}, 153 {0x3634, 0x10}, 154 {0x3635, 0x10}, 155 {0x3645, 0x13}, 156 {0x3646, 0x81}, 157 {0x3636, 0x10}, 158 {0x3651, 0x0a}, 159 {0x3656, 0x02}, 160 {0x3659, 0x04}, 161 {0x365a, 0xda}, 162 {0x365b, 0xa2}, 163 {0x365c, 0x04}, 164 {0x365d, 0x1d}, 165 {0x365e, 0x1a}, 166 {0x3662, 0xd7}, 167 {0x3667, 0x78}, 168 {0x3669, 0x0a}, 169 {0x366a, 0x92}, 170 {0x3700, 0x54}, 171 {0x3702, 0x10}, 172 {0x3706, 0x42}, 173 {0x3709, 0x30}, 174 {0x370b, 0xc2}, 175 {0x3714, 0x63}, 176 {0x3715, 0x01}, 177 {0x3716, 0x00}, 178 {0x371a, 0x3e}, 179 {0x3732, 0x0e}, 180 {0x3733, 0x10}, 181 {0x375f, 0x0e}, 182 {0x3768, 0x30}, 183 {0x3769, 0x44}, 184 {0x376a, 0x22}, 185 {0x377b, 0x20}, 186 {0x377c, 0x00}, 187 {0x377d, 0x0c}, 188 {0x3798, 0x00}, 189 {0x37a1, 0x55}, 190 {0x37a8, 0x6d}, 191 {0x37c2, 0x04}, 192 {0x37c5, 0x00}, 193 {0x37c8, 0x00}, 194 {0x3800, 0x00}, 195 {0x3801, 0x00}, 196 {0x3802, 0x00}, 197 {0x3803, 0x00}, 198 {0x3804, 0x07}, 199 {0x3805, 0x8f}, 200 {0x3806, 0x04}, 201 {0x3807, 0x47}, 202 {0x3808, 0x07}, 203 {0x3809, 0x88}, 204 {0x380a, 0x04}, 205 {0x380b, 0x40}, 206 {0x380c, 0x04}, 207 {0x380d, 0x38}, 208 {0x380e, 0x04}, 209 {0x380f, 0x60}, 210 {0x3810, 0x00}, 211 {0x3811, 0x04}, 212 {0x3812, 0x00}, 213 {0x3813, 0x04}, 214 {0x3814, 0x01}, 215 {0x3815, 0x01}, 216 {0x3820, 0x80}, 217 {0x3821, 0x46}, 218 {0x3822, 0x84}, 219 {0x3829, 0x00}, 220 {0x382a, 0x01}, 221 {0x382b, 0x01}, 222 {0x3830, 0x04}, 223 {0x3836, 0x01}, 224 {0x3837, 0x08}, 225 {0x3839, 0x01}, 226 {0x383a, 0x00}, 227 {0x383b, 0x08}, 228 {0x383c, 0x00}, 229 {0x3f0b, 0x00}, 230 {0x4001, 0x20}, 231 {0x4009, 0x07}, 232 {0x4003, 0x10}, 233 {0x4010, 0xe0}, 234 {0x4016, 0x00}, 235 {0x4017, 0x10}, 236 {0x4044, 0x02}, 237 {0x4304, 0x08}, 238 {0x4307, 0x30}, 239 {0x4320, 0x80}, 240 {0x4322, 0x00}, 241 {0x4323, 0x00}, 242 {0x4324, 0x00}, 243 {0x4325, 0x00}, 244 {0x4326, 0x00}, 245 {0x4327, 0x00}, 246 {0x4328, 0x00}, 247 {0x4329, 0x00}, 248 {0x432c, 0x03}, 249 {0x432d, 0x81}, 250 {0x4501, 0x84}, 251 {0x4502, 0x40}, 252 {0x4503, 0x18}, 253 {0x4504, 0x04}, 254 {0x4508, 0x02}, 255 {0x4601, 0x10}, 256 {0x4800, 0x00}, 257 {0x4816, 0x52}, 258 {0x4837, 0x16}, 259 {0x5000, 0x7f}, 260 {0x5001, 0x00}, 261 {0x5005, 0x38}, 262 {0x501e, 0x0d}, 263 {0x5040, 0x00}, 264 {0x5901, 0x00}, 265 {0x3800, 0x00}, 266 {0x3801, 0x00}, 267 {0x3802, 0x00}, 268 {0x3803, 0x00}, 269 {0x3804, 0x07}, 270 {0x3805, 0x8f}, 271 {0x3806, 0x04}, 272 {0x3807, 0x47}, 273 {0x3808, 0x07}, 274 {0x3809, 0x8c}, 275 {0x380a, 0x04}, 276 {0x380b, 0x44}, 277 {0x3810, 0x00}, 278 {0x3811, 0x00}, 279 {0x3812, 0x00}, 280 {0x3813, 0x01}, 281 }; 282 283 static const char * const ov2740_test_pattern_menu[] = { 284 "Disabled", 285 "Color Bar", 286 "Top-Bottom Darker Color Bar", 287 "Right-Left Darker Color Bar", 288 "Bottom-Top Darker Color Bar", 289 }; 290 291 static const s64 link_freq_menu_items[] = { 292 OV2740_LINK_FREQ_360MHZ, 293 }; 294 295 static const struct ov2740_link_freq_config link_freq_configs[] = { 296 [OV2740_LINK_FREQ_360MHZ_INDEX] = { 297 .reg_list = { 298 .num_of_regs = ARRAY_SIZE(mipi_data_rate_720mbps), 299 .regs = mipi_data_rate_720mbps, 300 } 301 }, 302 }; 303 304 static const struct ov2740_mode supported_modes[] = { 305 { 306 .width = 1932, 307 .height = 1092, 308 .hts = 1080, 309 .vts_def = OV2740_VTS_DEF, 310 .vts_min = OV2740_VTS_MIN, 311 .reg_list = { 312 .num_of_regs = ARRAY_SIZE(mode_1932x1092_regs), 313 .regs = mode_1932x1092_regs, 314 }, 315 .link_freq_index = OV2740_LINK_FREQ_360MHZ_INDEX, 316 }, 317 }; 318 319 struct ov2740 { 320 struct v4l2_subdev sd; 321 struct media_pad pad; 322 struct v4l2_ctrl_handler ctrl_handler; 323 324 /* V4L2 Controls */ 325 struct v4l2_ctrl *link_freq; 326 struct v4l2_ctrl *pixel_rate; 327 struct v4l2_ctrl *vblank; 328 struct v4l2_ctrl *hblank; 329 struct v4l2_ctrl *exposure; 330 331 /* Current mode */ 332 const struct ov2740_mode *cur_mode; 333 334 /* To serialize asynchronus callbacks */ 335 struct mutex mutex; 336 337 /* Streaming on/off */ 338 bool streaming; 339 340 /* NVM data inforamtion */ 341 struct nvm_data *nvm; 342 }; 343 344 static inline struct ov2740 *to_ov2740(struct v4l2_subdev *subdev) 345 { 346 return container_of(subdev, struct ov2740, sd); 347 } 348 349 static u64 to_pixel_rate(u32 f_index) 350 { 351 u64 pixel_rate = link_freq_menu_items[f_index] * 2 * OV2740_DATA_LANES; 352 353 do_div(pixel_rate, OV2740_RGB_DEPTH); 354 355 return pixel_rate; 356 } 357 358 static u64 to_pixels_per_line(u32 hts, u32 f_index) 359 { 360 u64 ppl = hts * to_pixel_rate(f_index); 361 362 do_div(ppl, OV2740_SCLK); 363 364 return ppl; 365 } 366 367 static int ov2740_read_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 *val) 368 { 369 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 370 struct i2c_msg msgs[2]; 371 u8 addr_buf[2]; 372 u8 data_buf[4] = {0}; 373 int ret = 0; 374 375 if (len > sizeof(data_buf)) 376 return -EINVAL; 377 378 put_unaligned_be16(reg, addr_buf); 379 msgs[0].addr = client->addr; 380 msgs[0].flags = 0; 381 msgs[0].len = sizeof(addr_buf); 382 msgs[0].buf = addr_buf; 383 msgs[1].addr = client->addr; 384 msgs[1].flags = I2C_M_RD; 385 msgs[1].len = len; 386 msgs[1].buf = &data_buf[sizeof(data_buf) - len]; 387 388 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); 389 if (ret != ARRAY_SIZE(msgs)) 390 return ret < 0 ? ret : -EIO; 391 392 *val = get_unaligned_be32(data_buf); 393 394 return 0; 395 } 396 397 static int ov2740_write_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 val) 398 { 399 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 400 u8 buf[6]; 401 int ret = 0; 402 403 if (len > 4) 404 return -EINVAL; 405 406 put_unaligned_be16(reg, buf); 407 put_unaligned_be32(val << 8 * (4 - len), buf + 2); 408 409 ret = i2c_master_send(client, buf, len + 2); 410 if (ret != len + 2) 411 return ret < 0 ? ret : -EIO; 412 413 return 0; 414 } 415 416 static int ov2740_write_reg_list(struct ov2740 *ov2740, 417 const struct ov2740_reg_list *r_list) 418 { 419 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 420 unsigned int i; 421 int ret = 0; 422 423 for (i = 0; i < r_list->num_of_regs; i++) { 424 ret = ov2740_write_reg(ov2740, r_list->regs[i].address, 1, 425 r_list->regs[i].val); 426 if (ret) { 427 dev_err_ratelimited(&client->dev, 428 "write reg 0x%4.4x return err = %d", 429 r_list->regs[i].address, ret); 430 return ret; 431 } 432 } 433 434 return 0; 435 } 436 437 static int ov2740_update_digital_gain(struct ov2740 *ov2740, u32 d_gain) 438 { 439 int ret = 0; 440 441 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_R_GAIN, 2, d_gain); 442 if (ret) 443 return ret; 444 445 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_G_GAIN, 2, d_gain); 446 if (ret) 447 return ret; 448 449 return ov2740_write_reg(ov2740, OV2740_REG_MWB_B_GAIN, 2, d_gain); 450 } 451 452 static int ov2740_test_pattern(struct ov2740 *ov2740, u32 pattern) 453 { 454 if (pattern) 455 pattern = (pattern - 1) << OV2740_TEST_PATTERN_BAR_SHIFT | 456 OV2740_TEST_PATTERN_ENABLE; 457 458 return ov2740_write_reg(ov2740, OV2740_REG_TEST_PATTERN, 1, pattern); 459 } 460 461 static int ov2740_set_ctrl(struct v4l2_ctrl *ctrl) 462 { 463 struct ov2740 *ov2740 = container_of(ctrl->handler, 464 struct ov2740, ctrl_handler); 465 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 466 s64 exposure_max; 467 int ret = 0; 468 469 /* Propagate change of current control to all related controls */ 470 if (ctrl->id == V4L2_CID_VBLANK) { 471 /* Update max exposure while meeting expected vblanking */ 472 exposure_max = ov2740->cur_mode->height + ctrl->val - 473 OV2740_EXPOSURE_MAX_MARGIN; 474 __v4l2_ctrl_modify_range(ov2740->exposure, 475 ov2740->exposure->minimum, 476 exposure_max, ov2740->exposure->step, 477 exposure_max); 478 } 479 480 /* V4L2 controls values will be applied only when power is already up */ 481 if (!pm_runtime_get_if_in_use(&client->dev)) 482 return 0; 483 484 switch (ctrl->id) { 485 case V4L2_CID_ANALOGUE_GAIN: 486 ret = ov2740_write_reg(ov2740, OV2740_REG_ANALOG_GAIN, 2, 487 ctrl->val); 488 break; 489 490 case V4L2_CID_DIGITAL_GAIN: 491 ret = ov2740_update_digital_gain(ov2740, ctrl->val); 492 break; 493 494 case V4L2_CID_EXPOSURE: 495 /* 4 least significant bits of expsoure are fractional part */ 496 ret = ov2740_write_reg(ov2740, OV2740_REG_EXPOSURE, 3, 497 ctrl->val << 4); 498 break; 499 500 case V4L2_CID_VBLANK: 501 ret = ov2740_write_reg(ov2740, OV2740_REG_VTS, 2, 502 ov2740->cur_mode->height + ctrl->val); 503 break; 504 505 case V4L2_CID_TEST_PATTERN: 506 ret = ov2740_test_pattern(ov2740, ctrl->val); 507 break; 508 509 default: 510 ret = -EINVAL; 511 break; 512 } 513 514 pm_runtime_put(&client->dev); 515 516 return ret; 517 } 518 519 static const struct v4l2_ctrl_ops ov2740_ctrl_ops = { 520 .s_ctrl = ov2740_set_ctrl, 521 }; 522 523 static int ov2740_init_controls(struct ov2740 *ov2740) 524 { 525 struct v4l2_ctrl_handler *ctrl_hdlr; 526 const struct ov2740_mode *cur_mode; 527 s64 exposure_max, h_blank, pixel_rate; 528 u32 vblank_min, vblank_max, vblank_default; 529 int size; 530 int ret = 0; 531 532 ctrl_hdlr = &ov2740->ctrl_handler; 533 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8); 534 if (ret) 535 return ret; 536 537 ctrl_hdlr->lock = &ov2740->mutex; 538 cur_mode = ov2740->cur_mode; 539 size = ARRAY_SIZE(link_freq_menu_items); 540 541 ov2740->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &ov2740_ctrl_ops, 542 V4L2_CID_LINK_FREQ, 543 size - 1, 0, 544 link_freq_menu_items); 545 if (ov2740->link_freq) 546 ov2740->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 547 548 pixel_rate = to_pixel_rate(OV2740_LINK_FREQ_360MHZ_INDEX); 549 ov2740->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, 550 V4L2_CID_PIXEL_RATE, 0, 551 pixel_rate, 1, pixel_rate); 552 553 vblank_min = cur_mode->vts_min - cur_mode->height; 554 vblank_max = OV2740_VTS_MAX - cur_mode->height; 555 vblank_default = cur_mode->vts_def - cur_mode->height; 556 ov2740->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, 557 V4L2_CID_VBLANK, vblank_min, 558 vblank_max, 1, vblank_default); 559 560 h_blank = to_pixels_per_line(cur_mode->hts, cur_mode->link_freq_index); 561 h_blank -= cur_mode->width; 562 ov2740->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, 563 V4L2_CID_HBLANK, h_blank, h_blank, 1, 564 h_blank); 565 if (ov2740->hblank) 566 ov2740->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 567 568 v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, 569 OV2740_ANAL_GAIN_MIN, OV2740_ANAL_GAIN_MAX, 570 OV2740_ANAL_GAIN_STEP, OV2740_ANAL_GAIN_MIN); 571 v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_DIGITAL_GAIN, 572 OV2740_DGTL_GAIN_MIN, OV2740_DGTL_GAIN_MAX, 573 OV2740_DGTL_GAIN_STEP, OV2740_DGTL_GAIN_DEFAULT); 574 exposure_max = cur_mode->vts_def - OV2740_EXPOSURE_MAX_MARGIN; 575 ov2740->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, 576 V4L2_CID_EXPOSURE, 577 OV2740_EXPOSURE_MIN, exposure_max, 578 OV2740_EXPOSURE_STEP, 579 exposure_max); 580 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov2740_ctrl_ops, 581 V4L2_CID_TEST_PATTERN, 582 ARRAY_SIZE(ov2740_test_pattern_menu) - 1, 583 0, 0, ov2740_test_pattern_menu); 584 if (ctrl_hdlr->error) 585 return ctrl_hdlr->error; 586 587 ov2740->sd.ctrl_handler = ctrl_hdlr; 588 589 return 0; 590 } 591 592 static void ov2740_update_pad_format(const struct ov2740_mode *mode, 593 struct v4l2_mbus_framefmt *fmt) 594 { 595 fmt->width = mode->width; 596 fmt->height = mode->height; 597 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; 598 fmt->field = V4L2_FIELD_NONE; 599 } 600 601 static int ov2740_start_streaming(struct ov2740 *ov2740) 602 { 603 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 604 const struct ov2740_reg_list *reg_list; 605 int link_freq_index; 606 int ret = 0; 607 608 link_freq_index = ov2740->cur_mode->link_freq_index; 609 reg_list = &link_freq_configs[link_freq_index].reg_list; 610 ret = ov2740_write_reg_list(ov2740, reg_list); 611 if (ret) { 612 dev_err(&client->dev, "failed to set plls"); 613 return ret; 614 } 615 616 reg_list = &ov2740->cur_mode->reg_list; 617 ret = ov2740_write_reg_list(ov2740, reg_list); 618 if (ret) { 619 dev_err(&client->dev, "failed to set mode"); 620 return ret; 621 } 622 623 ret = __v4l2_ctrl_handler_setup(ov2740->sd.ctrl_handler); 624 if (ret) 625 return ret; 626 627 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1, 628 OV2740_MODE_STREAMING); 629 if (ret) 630 dev_err(&client->dev, "failed to start streaming"); 631 632 return ret; 633 } 634 635 static void ov2740_stop_streaming(struct ov2740 *ov2740) 636 { 637 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 638 639 if (ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1, 640 OV2740_MODE_STANDBY)) 641 dev_err(&client->dev, "failed to stop streaming"); 642 } 643 644 static int ov2740_set_stream(struct v4l2_subdev *sd, int enable) 645 { 646 struct ov2740 *ov2740 = to_ov2740(sd); 647 struct i2c_client *client = v4l2_get_subdevdata(sd); 648 int ret = 0; 649 650 if (ov2740->streaming == enable) 651 return 0; 652 653 mutex_lock(&ov2740->mutex); 654 if (enable) { 655 ret = pm_runtime_get_sync(&client->dev); 656 if (ret < 0) { 657 pm_runtime_put_noidle(&client->dev); 658 mutex_unlock(&ov2740->mutex); 659 return ret; 660 } 661 662 ret = ov2740_start_streaming(ov2740); 663 if (ret) { 664 enable = 0; 665 ov2740_stop_streaming(ov2740); 666 pm_runtime_put(&client->dev); 667 } 668 } else { 669 ov2740_stop_streaming(ov2740); 670 pm_runtime_put(&client->dev); 671 } 672 673 ov2740->streaming = enable; 674 mutex_unlock(&ov2740->mutex); 675 676 return ret; 677 } 678 679 static int __maybe_unused ov2740_suspend(struct device *dev) 680 { 681 struct v4l2_subdev *sd = dev_get_drvdata(dev); 682 struct ov2740 *ov2740 = to_ov2740(sd); 683 684 mutex_lock(&ov2740->mutex); 685 if (ov2740->streaming) 686 ov2740_stop_streaming(ov2740); 687 688 mutex_unlock(&ov2740->mutex); 689 690 return 0; 691 } 692 693 static int __maybe_unused ov2740_resume(struct device *dev) 694 { 695 struct v4l2_subdev *sd = dev_get_drvdata(dev); 696 struct ov2740 *ov2740 = to_ov2740(sd); 697 int ret = 0; 698 699 mutex_lock(&ov2740->mutex); 700 if (!ov2740->streaming) 701 goto exit; 702 703 ret = ov2740_start_streaming(ov2740); 704 if (ret) { 705 ov2740->streaming = false; 706 ov2740_stop_streaming(ov2740); 707 } 708 709 exit: 710 mutex_unlock(&ov2740->mutex); 711 return ret; 712 } 713 714 static int ov2740_set_format(struct v4l2_subdev *sd, 715 struct v4l2_subdev_pad_config *cfg, 716 struct v4l2_subdev_format *fmt) 717 { 718 struct ov2740 *ov2740 = to_ov2740(sd); 719 const struct ov2740_mode *mode; 720 s32 vblank_def, h_blank; 721 722 mode = v4l2_find_nearest_size(supported_modes, 723 ARRAY_SIZE(supported_modes), width, 724 height, fmt->format.width, 725 fmt->format.height); 726 727 mutex_lock(&ov2740->mutex); 728 ov2740_update_pad_format(mode, &fmt->format); 729 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 730 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format; 731 } else { 732 ov2740->cur_mode = mode; 733 __v4l2_ctrl_s_ctrl(ov2740->link_freq, mode->link_freq_index); 734 __v4l2_ctrl_s_ctrl_int64(ov2740->pixel_rate, 735 to_pixel_rate(mode->link_freq_index)); 736 737 /* Update limits and set FPS to default */ 738 vblank_def = mode->vts_def - mode->height; 739 __v4l2_ctrl_modify_range(ov2740->vblank, 740 mode->vts_min - mode->height, 741 OV2740_VTS_MAX - mode->height, 1, 742 vblank_def); 743 __v4l2_ctrl_s_ctrl(ov2740->vblank, vblank_def); 744 h_blank = to_pixels_per_line(mode->hts, mode->link_freq_index) - 745 mode->width; 746 __v4l2_ctrl_modify_range(ov2740->hblank, h_blank, h_blank, 1, 747 h_blank); 748 } 749 mutex_unlock(&ov2740->mutex); 750 751 return 0; 752 } 753 754 static int ov2740_get_format(struct v4l2_subdev *sd, 755 struct v4l2_subdev_pad_config *cfg, 756 struct v4l2_subdev_format *fmt) 757 { 758 struct ov2740 *ov2740 = to_ov2740(sd); 759 760 mutex_lock(&ov2740->mutex); 761 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) 762 fmt->format = *v4l2_subdev_get_try_format(&ov2740->sd, cfg, 763 fmt->pad); 764 else 765 ov2740_update_pad_format(ov2740->cur_mode, &fmt->format); 766 767 mutex_unlock(&ov2740->mutex); 768 769 return 0; 770 } 771 772 static int ov2740_enum_mbus_code(struct v4l2_subdev *sd, 773 struct v4l2_subdev_pad_config *cfg, 774 struct v4l2_subdev_mbus_code_enum *code) 775 { 776 if (code->index > 0) 777 return -EINVAL; 778 779 code->code = MEDIA_BUS_FMT_SGRBG10_1X10; 780 781 return 0; 782 } 783 784 static int ov2740_enum_frame_size(struct v4l2_subdev *sd, 785 struct v4l2_subdev_pad_config *cfg, 786 struct v4l2_subdev_frame_size_enum *fse) 787 { 788 if (fse->index >= ARRAY_SIZE(supported_modes)) 789 return -EINVAL; 790 791 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10) 792 return -EINVAL; 793 794 fse->min_width = supported_modes[fse->index].width; 795 fse->max_width = fse->min_width; 796 fse->min_height = supported_modes[fse->index].height; 797 fse->max_height = fse->min_height; 798 799 return 0; 800 } 801 802 static int ov2740_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) 803 { 804 struct ov2740 *ov2740 = to_ov2740(sd); 805 806 mutex_lock(&ov2740->mutex); 807 ov2740_update_pad_format(&supported_modes[0], 808 v4l2_subdev_get_try_format(sd, fh->pad, 0)); 809 mutex_unlock(&ov2740->mutex); 810 811 return 0; 812 } 813 814 static const struct v4l2_subdev_video_ops ov2740_video_ops = { 815 .s_stream = ov2740_set_stream, 816 }; 817 818 static const struct v4l2_subdev_pad_ops ov2740_pad_ops = { 819 .set_fmt = ov2740_set_format, 820 .get_fmt = ov2740_get_format, 821 .enum_mbus_code = ov2740_enum_mbus_code, 822 .enum_frame_size = ov2740_enum_frame_size, 823 }; 824 825 static const struct v4l2_subdev_ops ov2740_subdev_ops = { 826 .video = &ov2740_video_ops, 827 .pad = &ov2740_pad_ops, 828 }; 829 830 static const struct media_entity_operations ov2740_subdev_entity_ops = { 831 .link_validate = v4l2_subdev_link_validate, 832 }; 833 834 static const struct v4l2_subdev_internal_ops ov2740_internal_ops = { 835 .open = ov2740_open, 836 }; 837 838 static int ov2740_identify_module(struct ov2740 *ov2740) 839 { 840 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 841 int ret; 842 u32 val; 843 844 ret = ov2740_read_reg(ov2740, OV2740_REG_CHIP_ID, 3, &val); 845 if (ret) 846 return ret; 847 848 if (val != OV2740_CHIP_ID) { 849 dev_err(&client->dev, "chip id mismatch: %x!=%x", 850 OV2740_CHIP_ID, val); 851 return -ENXIO; 852 } 853 854 return 0; 855 } 856 857 static int ov2740_check_hwcfg(struct device *dev) 858 { 859 struct fwnode_handle *ep; 860 struct fwnode_handle *fwnode = dev_fwnode(dev); 861 struct v4l2_fwnode_endpoint bus_cfg = { 862 .bus_type = V4L2_MBUS_CSI2_DPHY 863 }; 864 u32 mclk; 865 int ret; 866 unsigned int i, j; 867 868 if (!fwnode) 869 return -ENXIO; 870 871 ret = fwnode_property_read_u32(fwnode, "clock-frequency", &mclk); 872 if (ret) 873 return ret; 874 875 if (mclk != OV2740_MCLK) { 876 dev_err(dev, "external clock %d is not supported", mclk); 877 return -EINVAL; 878 } 879 880 ep = fwnode_graph_get_next_endpoint(fwnode, NULL); 881 if (!ep) 882 return -ENXIO; 883 884 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); 885 fwnode_handle_put(ep); 886 if (ret) 887 return ret; 888 889 if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV2740_DATA_LANES) { 890 dev_err(dev, "number of CSI2 data lanes %d is not supported", 891 bus_cfg.bus.mipi_csi2.num_data_lanes); 892 ret = -EINVAL; 893 goto check_hwcfg_error; 894 } 895 896 if (!bus_cfg.nr_of_link_frequencies) { 897 dev_err(dev, "no link frequencies defined"); 898 ret = -EINVAL; 899 goto check_hwcfg_error; 900 } 901 902 for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) { 903 for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) { 904 if (link_freq_menu_items[i] == 905 bus_cfg.link_frequencies[j]) 906 break; 907 } 908 909 if (j == bus_cfg.nr_of_link_frequencies) { 910 dev_err(dev, "no link frequency %lld supported", 911 link_freq_menu_items[i]); 912 ret = -EINVAL; 913 goto check_hwcfg_error; 914 } 915 } 916 917 check_hwcfg_error: 918 v4l2_fwnode_endpoint_free(&bus_cfg); 919 920 return ret; 921 } 922 923 static int ov2740_remove(struct i2c_client *client) 924 { 925 struct v4l2_subdev *sd = i2c_get_clientdata(client); 926 struct ov2740 *ov2740 = to_ov2740(sd); 927 928 v4l2_async_unregister_subdev(sd); 929 media_entity_cleanup(&sd->entity); 930 v4l2_ctrl_handler_free(sd->ctrl_handler); 931 pm_runtime_disable(&client->dev); 932 mutex_destroy(&ov2740->mutex); 933 934 return 0; 935 } 936 937 static int ov2740_load_otp_data(struct nvm_data *nvm) 938 { 939 struct i2c_client *client = nvm->client; 940 struct ov2740 *ov2740 = to_ov2740(i2c_get_clientdata(client)); 941 u32 isp_ctrl00 = 0; 942 u32 isp_ctrl01 = 0; 943 int ret; 944 945 if (!nvm) 946 return -EINVAL; 947 948 if (nvm->nvm_buffer) 949 return 0; 950 951 nvm->nvm_buffer = kzalloc(CUSTOMER_USE_OTP_SIZE, GFP_KERNEL); 952 if (!nvm->nvm_buffer) 953 return -ENOMEM; 954 955 ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, &isp_ctrl00); 956 if (ret) { 957 dev_err(&client->dev, "failed to read ISP CTRL00\n"); 958 goto err; 959 } 960 961 ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, &isp_ctrl01); 962 if (ret) { 963 dev_err(&client->dev, "failed to read ISP CTRL01\n"); 964 goto err; 965 } 966 967 /* Clear bit 5 of ISP CTRL00 */ 968 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, 969 isp_ctrl00 & ~BIT(5)); 970 if (ret) { 971 dev_err(&client->dev, "failed to set ISP CTRL00\n"); 972 goto err; 973 } 974 975 /* Clear bit 7 of ISP CTRL01 */ 976 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, 977 isp_ctrl01 & ~BIT(7)); 978 if (ret) { 979 dev_err(&client->dev, "failed to set ISP CTRL01\n"); 980 goto err; 981 } 982 983 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1, 984 OV2740_MODE_STREAMING); 985 if (ret) { 986 dev_err(&client->dev, "failed to set streaming mode\n"); 987 goto err; 988 } 989 990 /* 991 * Users are not allowed to access OTP-related registers and memory 992 * during the 20 ms period after streaming starts (0x100 = 0x01). 993 */ 994 msleep(20); 995 996 ret = regmap_bulk_read(nvm->regmap, OV2740_REG_OTP_CUSTOMER, 997 nvm->nvm_buffer, CUSTOMER_USE_OTP_SIZE); 998 if (ret) { 999 dev_err(&client->dev, "failed to read OTP data, ret %d\n", ret); 1000 goto err; 1001 } 1002 1003 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1, 1004 OV2740_MODE_STANDBY); 1005 if (ret) { 1006 dev_err(&client->dev, "failed to set streaming mode\n"); 1007 goto err; 1008 } 1009 1010 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, isp_ctrl01); 1011 if (ret) { 1012 dev_err(&client->dev, "failed to set ISP CTRL01\n"); 1013 goto err; 1014 } 1015 1016 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, isp_ctrl00); 1017 if (ret) { 1018 dev_err(&client->dev, "failed to set ISP CTRL00\n"); 1019 goto err; 1020 } 1021 1022 return 0; 1023 err: 1024 kfree(nvm->nvm_buffer); 1025 nvm->nvm_buffer = NULL; 1026 1027 return ret; 1028 } 1029 1030 static int ov2740_nvmem_read(void *priv, unsigned int off, void *val, 1031 size_t count) 1032 { 1033 struct nvm_data *nvm = priv; 1034 struct v4l2_subdev *sd = i2c_get_clientdata(nvm->client); 1035 struct device *dev = &nvm->client->dev; 1036 struct ov2740 *ov2740 = to_ov2740(sd); 1037 int ret = 0; 1038 1039 mutex_lock(&ov2740->mutex); 1040 1041 if (nvm->nvm_buffer) { 1042 memcpy(val, nvm->nvm_buffer + off, count); 1043 goto exit; 1044 } 1045 1046 ret = pm_runtime_get_sync(dev); 1047 if (ret < 0) { 1048 pm_runtime_put_noidle(dev); 1049 goto exit; 1050 } 1051 1052 ret = ov2740_load_otp_data(nvm); 1053 if (!ret) 1054 memcpy(val, nvm->nvm_buffer + off, count); 1055 1056 pm_runtime_put(dev); 1057 exit: 1058 mutex_unlock(&ov2740->mutex); 1059 return ret; 1060 } 1061 1062 static int ov2740_register_nvmem(struct i2c_client *client, 1063 struct ov2740 *ov2740) 1064 { 1065 struct nvm_data *nvm; 1066 struct regmap_config regmap_config = { }; 1067 struct nvmem_config nvmem_config = { }; 1068 struct regmap *regmap; 1069 struct device *dev = &client->dev; 1070 int ret; 1071 1072 nvm = devm_kzalloc(dev, sizeof(*nvm), GFP_KERNEL); 1073 if (!nvm) 1074 return -ENOMEM; 1075 1076 regmap_config.val_bits = 8; 1077 regmap_config.reg_bits = 16; 1078 regmap_config.disable_locking = true; 1079 regmap = devm_regmap_init_i2c(client, ®map_config); 1080 if (IS_ERR(regmap)) 1081 return PTR_ERR(regmap); 1082 1083 nvm->regmap = regmap; 1084 nvm->client = client; 1085 1086 nvmem_config.name = dev_name(dev); 1087 nvmem_config.dev = dev; 1088 nvmem_config.read_only = true; 1089 nvmem_config.root_only = true; 1090 nvmem_config.owner = THIS_MODULE; 1091 nvmem_config.compat = true; 1092 nvmem_config.base_dev = dev; 1093 nvmem_config.reg_read = ov2740_nvmem_read; 1094 nvmem_config.reg_write = NULL; 1095 nvmem_config.priv = nvm; 1096 nvmem_config.stride = 1; 1097 nvmem_config.word_size = 1; 1098 nvmem_config.size = CUSTOMER_USE_OTP_SIZE; 1099 1100 nvm->nvmem = devm_nvmem_register(dev, &nvmem_config); 1101 1102 ret = PTR_ERR_OR_ZERO(nvm->nvmem); 1103 if (!ret) 1104 ov2740->nvm = nvm; 1105 1106 return ret; 1107 } 1108 1109 static int ov2740_probe(struct i2c_client *client) 1110 { 1111 struct ov2740 *ov2740; 1112 int ret = 0; 1113 1114 ret = ov2740_check_hwcfg(&client->dev); 1115 if (ret) { 1116 dev_err(&client->dev, "failed to check HW configuration: %d", 1117 ret); 1118 return ret; 1119 } 1120 1121 ov2740 = devm_kzalloc(&client->dev, sizeof(*ov2740), GFP_KERNEL); 1122 if (!ov2740) 1123 return -ENOMEM; 1124 1125 v4l2_i2c_subdev_init(&ov2740->sd, client, &ov2740_subdev_ops); 1126 ret = ov2740_identify_module(ov2740); 1127 if (ret) { 1128 dev_err(&client->dev, "failed to find sensor: %d", ret); 1129 return ret; 1130 } 1131 1132 mutex_init(&ov2740->mutex); 1133 ov2740->cur_mode = &supported_modes[0]; 1134 ret = ov2740_init_controls(ov2740); 1135 if (ret) { 1136 dev_err(&client->dev, "failed to init controls: %d", ret); 1137 goto probe_error_v4l2_ctrl_handler_free; 1138 } 1139 1140 ov2740->sd.internal_ops = &ov2740_internal_ops; 1141 ov2740->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1142 ov2740->sd.entity.ops = &ov2740_subdev_entity_ops; 1143 ov2740->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1144 ov2740->pad.flags = MEDIA_PAD_FL_SOURCE; 1145 ret = media_entity_pads_init(&ov2740->sd.entity, 1, &ov2740->pad); 1146 if (ret) { 1147 dev_err(&client->dev, "failed to init entity pads: %d", ret); 1148 goto probe_error_v4l2_ctrl_handler_free; 1149 } 1150 1151 ret = v4l2_async_register_subdev_sensor_common(&ov2740->sd); 1152 if (ret < 0) { 1153 dev_err(&client->dev, "failed to register V4L2 subdev: %d", 1154 ret); 1155 goto probe_error_media_entity_cleanup; 1156 } 1157 1158 ret = ov2740_register_nvmem(client, ov2740); 1159 if (ret) 1160 dev_warn(&client->dev, "register nvmem failed, ret %d\n", ret); 1161 1162 /* 1163 * Device is already turned on by i2c-core with ACPI domain PM. 1164 * Enable runtime PM and turn off the device. 1165 */ 1166 pm_runtime_set_active(&client->dev); 1167 pm_runtime_enable(&client->dev); 1168 pm_runtime_idle(&client->dev); 1169 1170 return 0; 1171 1172 probe_error_media_entity_cleanup: 1173 media_entity_cleanup(&ov2740->sd.entity); 1174 1175 probe_error_v4l2_ctrl_handler_free: 1176 v4l2_ctrl_handler_free(ov2740->sd.ctrl_handler); 1177 mutex_destroy(&ov2740->mutex); 1178 1179 return ret; 1180 } 1181 1182 static const struct dev_pm_ops ov2740_pm_ops = { 1183 SET_SYSTEM_SLEEP_PM_OPS(ov2740_suspend, ov2740_resume) 1184 }; 1185 1186 static const struct acpi_device_id ov2740_acpi_ids[] = { 1187 {"INT3474"}, 1188 {} 1189 }; 1190 1191 MODULE_DEVICE_TABLE(acpi, ov2740_acpi_ids); 1192 1193 static struct i2c_driver ov2740_i2c_driver = { 1194 .driver = { 1195 .name = "ov2740", 1196 .pm = &ov2740_pm_ops, 1197 .acpi_match_table = ov2740_acpi_ids, 1198 }, 1199 .probe_new = ov2740_probe, 1200 .remove = ov2740_remove, 1201 }; 1202 1203 module_i2c_driver(ov2740_i2c_driver); 1204 1205 MODULE_AUTHOR("Qiu, Tianshu <tian.shu.qiu@intel.com>"); 1206 MODULE_AUTHOR("Shawn Tu <shawnx.tu@intel.com>"); 1207 MODULE_AUTHOR("Bingbu Cao <bingbu.cao@intel.com>"); 1208 MODULE_DESCRIPTION("OmniVision OV2740 sensor driver"); 1209 MODULE_LICENSE("GPL v2"); 1210