1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2020 Intel Corporation. 3 4 #include <asm/unaligned.h> 5 #include <linux/acpi.h> 6 #include <linux/delay.h> 7 #include <linux/i2c.h> 8 #include <linux/module.h> 9 #include <linux/pm_runtime.h> 10 #include <media/v4l2-ctrls.h> 11 #include <media/v4l2-device.h> 12 #include <media/v4l2-fwnode.h> 13 14 #define OV2740_LINK_FREQ_360MHZ 360000000ULL 15 #define OV2740_SCLK 72000000LL 16 #define OV2740_MCLK 19200000 17 #define OV2740_DATA_LANES 2 18 #define OV2740_RGB_DEPTH 10 19 20 #define OV2740_REG_CHIP_ID 0x300a 21 #define OV2740_CHIP_ID 0x2740 22 23 #define OV2740_REG_MODE_SELECT 0x0100 24 #define OV2740_MODE_STANDBY 0x00 25 #define OV2740_MODE_STREAMING 0x01 26 27 /* vertical-timings from sensor */ 28 #define OV2740_REG_VTS 0x380e 29 #define OV2740_VTS_DEF 0x088a 30 #define OV2740_VTS_MIN 0x0460 31 #define OV2740_VTS_MAX 0x7fff 32 33 /* horizontal-timings from sensor */ 34 #define OV2740_REG_HTS 0x380c 35 36 /* Exposure controls from sensor */ 37 #define OV2740_REG_EXPOSURE 0x3500 38 #define OV2740_EXPOSURE_MIN 8 39 #define OV2740_EXPOSURE_MAX_MARGIN 8 40 #define OV2740_EXPOSURE_STEP 1 41 42 /* Analog gain controls from sensor */ 43 #define OV2740_REG_ANALOG_GAIN 0x3508 44 #define OV2740_ANAL_GAIN_MIN 128 45 #define OV2740_ANAL_GAIN_MAX 1983 46 #define OV2740_ANAL_GAIN_STEP 1 47 48 /* Digital gain controls from sensor */ 49 #define OV2740_REG_MWB_R_GAIN 0x500a 50 #define OV2740_REG_MWB_G_GAIN 0x500c 51 #define OV2740_REG_MWB_B_GAIN 0x500e 52 #define OV2740_DGTL_GAIN_MIN 0 53 #define OV2740_DGTL_GAIN_MAX 4095 54 #define OV2740_DGTL_GAIN_STEP 1 55 #define OV2740_DGTL_GAIN_DEFAULT 1024 56 57 /* Test Pattern Control */ 58 #define OV2740_REG_TEST_PATTERN 0x5040 59 #define OV2740_TEST_PATTERN_ENABLE BIT(7) 60 #define OV2740_TEST_PATTERN_BAR_SHIFT 2 61 62 enum { 63 OV2740_LINK_FREQ_360MHZ_INDEX, 64 }; 65 66 struct ov2740_reg { 67 u16 address; 68 u8 val; 69 }; 70 71 struct ov2740_reg_list { 72 u32 num_of_regs; 73 const struct ov2740_reg *regs; 74 }; 75 76 struct ov2740_link_freq_config { 77 const struct ov2740_reg_list reg_list; 78 }; 79 80 struct ov2740_mode { 81 /* Frame width in pixels */ 82 u32 width; 83 84 /* Frame height in pixels */ 85 u32 height; 86 87 /* Horizontal timining size */ 88 u32 hts; 89 90 /* Default vertical timining size */ 91 u32 vts_def; 92 93 /* Min vertical timining size */ 94 u32 vts_min; 95 96 /* Link frequency needed for this resolution */ 97 u32 link_freq_index; 98 99 /* Sensor register settings for this resolution */ 100 const struct ov2740_reg_list reg_list; 101 }; 102 103 static const struct ov2740_reg mipi_data_rate_720mbps[] = { 104 {0x0103, 0x01}, 105 {0x0302, 0x4b}, 106 {0x030d, 0x4b}, 107 {0x030e, 0x02}, 108 {0x030a, 0x01}, 109 {0x0312, 0x11}, 110 }; 111 112 static const struct ov2740_reg mode_1932x1092_regs[] = { 113 {0x3000, 0x00}, 114 {0x3018, 0x32}, 115 {0x3031, 0x0a}, 116 {0x3080, 0x08}, 117 {0x3083, 0xB4}, 118 {0x3103, 0x00}, 119 {0x3104, 0x01}, 120 {0x3106, 0x01}, 121 {0x3500, 0x00}, 122 {0x3501, 0x44}, 123 {0x3502, 0x40}, 124 {0x3503, 0x88}, 125 {0x3507, 0x00}, 126 {0x3508, 0x00}, 127 {0x3509, 0x80}, 128 {0x350c, 0x00}, 129 {0x350d, 0x80}, 130 {0x3510, 0x00}, 131 {0x3511, 0x00}, 132 {0x3512, 0x20}, 133 {0x3632, 0x00}, 134 {0x3633, 0x10}, 135 {0x3634, 0x10}, 136 {0x3635, 0x10}, 137 {0x3645, 0x13}, 138 {0x3646, 0x81}, 139 {0x3636, 0x10}, 140 {0x3651, 0x0a}, 141 {0x3656, 0x02}, 142 {0x3659, 0x04}, 143 {0x365a, 0xda}, 144 {0x365b, 0xa2}, 145 {0x365c, 0x04}, 146 {0x365d, 0x1d}, 147 {0x365e, 0x1a}, 148 {0x3662, 0xd7}, 149 {0x3667, 0x78}, 150 {0x3669, 0x0a}, 151 {0x366a, 0x92}, 152 {0x3700, 0x54}, 153 {0x3702, 0x10}, 154 {0x3706, 0x42}, 155 {0x3709, 0x30}, 156 {0x370b, 0xc2}, 157 {0x3714, 0x63}, 158 {0x3715, 0x01}, 159 {0x3716, 0x00}, 160 {0x371a, 0x3e}, 161 {0x3732, 0x0e}, 162 {0x3733, 0x10}, 163 {0x375f, 0x0e}, 164 {0x3768, 0x30}, 165 {0x3769, 0x44}, 166 {0x376a, 0x22}, 167 {0x377b, 0x20}, 168 {0x377c, 0x00}, 169 {0x377d, 0x0c}, 170 {0x3798, 0x00}, 171 {0x37a1, 0x55}, 172 {0x37a8, 0x6d}, 173 {0x37c2, 0x04}, 174 {0x37c5, 0x00}, 175 {0x37c8, 0x00}, 176 {0x3800, 0x00}, 177 {0x3801, 0x00}, 178 {0x3802, 0x00}, 179 {0x3803, 0x00}, 180 {0x3804, 0x07}, 181 {0x3805, 0x8f}, 182 {0x3806, 0x04}, 183 {0x3807, 0x47}, 184 {0x3808, 0x07}, 185 {0x3809, 0x88}, 186 {0x380a, 0x04}, 187 {0x380b, 0x40}, 188 {0x380c, 0x04}, 189 {0x380d, 0x38}, 190 {0x380e, 0x04}, 191 {0x380f, 0x60}, 192 {0x3810, 0x00}, 193 {0x3811, 0x04}, 194 {0x3812, 0x00}, 195 {0x3813, 0x04}, 196 {0x3814, 0x01}, 197 {0x3815, 0x01}, 198 {0x3820, 0x80}, 199 {0x3821, 0x46}, 200 {0x3822, 0x84}, 201 {0x3829, 0x00}, 202 {0x382a, 0x01}, 203 {0x382b, 0x01}, 204 {0x3830, 0x04}, 205 {0x3836, 0x01}, 206 {0x3837, 0x08}, 207 {0x3839, 0x01}, 208 {0x383a, 0x00}, 209 {0x383b, 0x08}, 210 {0x383c, 0x00}, 211 {0x3f0b, 0x00}, 212 {0x4001, 0x20}, 213 {0x4009, 0x07}, 214 {0x4003, 0x10}, 215 {0x4010, 0xe0}, 216 {0x4016, 0x00}, 217 {0x4017, 0x10}, 218 {0x4044, 0x02}, 219 {0x4304, 0x08}, 220 {0x4307, 0x30}, 221 {0x4320, 0x80}, 222 {0x4322, 0x00}, 223 {0x4323, 0x00}, 224 {0x4324, 0x00}, 225 {0x4325, 0x00}, 226 {0x4326, 0x00}, 227 {0x4327, 0x00}, 228 {0x4328, 0x00}, 229 {0x4329, 0x00}, 230 {0x432c, 0x03}, 231 {0x432d, 0x81}, 232 {0x4501, 0x84}, 233 {0x4502, 0x40}, 234 {0x4503, 0x18}, 235 {0x4504, 0x04}, 236 {0x4508, 0x02}, 237 {0x4601, 0x10}, 238 {0x4800, 0x00}, 239 {0x4816, 0x52}, 240 {0x4837, 0x16}, 241 {0x5000, 0x7f}, 242 {0x5001, 0x00}, 243 {0x5005, 0x38}, 244 {0x501e, 0x0d}, 245 {0x5040, 0x00}, 246 {0x5901, 0x00}, 247 {0x3800, 0x00}, 248 {0x3801, 0x00}, 249 {0x3802, 0x00}, 250 {0x3803, 0x00}, 251 {0x3804, 0x07}, 252 {0x3805, 0x8f}, 253 {0x3806, 0x04}, 254 {0x3807, 0x47}, 255 {0x3808, 0x07}, 256 {0x3809, 0x8c}, 257 {0x380a, 0x04}, 258 {0x380b, 0x44}, 259 {0x3810, 0x00}, 260 {0x3811, 0x00}, 261 {0x3812, 0x00}, 262 {0x3813, 0x01}, 263 }; 264 265 static const char * const ov2740_test_pattern_menu[] = { 266 "Disabled", 267 "Color Bar", 268 "Top-Bottom Darker Color Bar", 269 "Right-Left Darker Color Bar", 270 "Bottom-Top Darker Color Bar", 271 }; 272 273 static const s64 link_freq_menu_items[] = { 274 OV2740_LINK_FREQ_360MHZ, 275 }; 276 277 static const struct ov2740_link_freq_config link_freq_configs[] = { 278 [OV2740_LINK_FREQ_360MHZ_INDEX] = { 279 .reg_list = { 280 .num_of_regs = ARRAY_SIZE(mipi_data_rate_720mbps), 281 .regs = mipi_data_rate_720mbps, 282 } 283 }, 284 }; 285 286 static const struct ov2740_mode supported_modes[] = { 287 { 288 .width = 1932, 289 .height = 1092, 290 .hts = 1080, 291 .vts_def = OV2740_VTS_DEF, 292 .vts_min = OV2740_VTS_MIN, 293 .reg_list = { 294 .num_of_regs = ARRAY_SIZE(mode_1932x1092_regs), 295 .regs = mode_1932x1092_regs, 296 }, 297 .link_freq_index = OV2740_LINK_FREQ_360MHZ_INDEX, 298 }, 299 }; 300 301 struct ov2740 { 302 struct v4l2_subdev sd; 303 struct media_pad pad; 304 struct v4l2_ctrl_handler ctrl_handler; 305 306 /* V4L2 Controls */ 307 struct v4l2_ctrl *link_freq; 308 struct v4l2_ctrl *pixel_rate; 309 struct v4l2_ctrl *vblank; 310 struct v4l2_ctrl *hblank; 311 struct v4l2_ctrl *exposure; 312 313 /* Current mode */ 314 const struct ov2740_mode *cur_mode; 315 316 /* To serialize asynchronus callbacks */ 317 struct mutex mutex; 318 319 /* Streaming on/off */ 320 bool streaming; 321 }; 322 323 static inline struct ov2740 *to_ov2740(struct v4l2_subdev *subdev) 324 { 325 return container_of(subdev, struct ov2740, sd); 326 } 327 328 static u64 to_pixel_rate(u32 f_index) 329 { 330 u64 pixel_rate = link_freq_menu_items[f_index] * 2 * OV2740_DATA_LANES; 331 332 do_div(pixel_rate, OV2740_RGB_DEPTH); 333 334 return pixel_rate; 335 } 336 337 static u64 to_pixels_per_line(u32 hts, u32 f_index) 338 { 339 u64 ppl = hts * to_pixel_rate(f_index); 340 341 do_div(ppl, OV2740_SCLK); 342 343 return ppl; 344 } 345 346 static int ov2740_read_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 *val) 347 { 348 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 349 struct i2c_msg msgs[2]; 350 u8 addr_buf[2]; 351 u8 data_buf[4] = {0}; 352 int ret = 0; 353 354 if (len > sizeof(data_buf)) 355 return -EINVAL; 356 357 put_unaligned_be16(reg, addr_buf); 358 msgs[0].addr = client->addr; 359 msgs[0].flags = 0; 360 msgs[0].len = sizeof(addr_buf); 361 msgs[0].buf = addr_buf; 362 msgs[1].addr = client->addr; 363 msgs[1].flags = I2C_M_RD; 364 msgs[1].len = len; 365 msgs[1].buf = &data_buf[sizeof(data_buf) - len]; 366 367 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); 368 if (ret != ARRAY_SIZE(msgs)) 369 return ret < 0 ? ret : -EIO; 370 371 *val = get_unaligned_be32(data_buf); 372 373 return 0; 374 } 375 376 static int ov2740_write_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 val) 377 { 378 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 379 u8 buf[6]; 380 int ret = 0; 381 382 if (len > 4) 383 return -EINVAL; 384 385 put_unaligned_be16(reg, buf); 386 put_unaligned_be32(val << 8 * (4 - len), buf + 2); 387 388 ret = i2c_master_send(client, buf, len + 2); 389 if (ret != len + 2) 390 return ret < 0 ? ret : -EIO; 391 392 return 0; 393 } 394 395 static int ov2740_write_reg_list(struct ov2740 *ov2740, 396 const struct ov2740_reg_list *r_list) 397 { 398 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 399 unsigned int i; 400 int ret = 0; 401 402 for (i = 0; i < r_list->num_of_regs; i++) { 403 ret = ov2740_write_reg(ov2740, r_list->regs[i].address, 1, 404 r_list->regs[i].val); 405 if (ret) { 406 dev_err_ratelimited(&client->dev, 407 "write reg 0x%4.4x return err = %d", 408 r_list->regs[i].address, ret); 409 return ret; 410 } 411 } 412 413 return 0; 414 } 415 416 static int ov2740_update_digital_gain(struct ov2740 *ov2740, u32 d_gain) 417 { 418 int ret = 0; 419 420 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_R_GAIN, 2, d_gain); 421 if (ret) 422 return ret; 423 424 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_G_GAIN, 2, d_gain); 425 if (ret) 426 return ret; 427 428 return ov2740_write_reg(ov2740, OV2740_REG_MWB_B_GAIN, 2, d_gain); 429 } 430 431 static int ov2740_test_pattern(struct ov2740 *ov2740, u32 pattern) 432 { 433 if (pattern) 434 pattern = (pattern - 1) << OV2740_TEST_PATTERN_BAR_SHIFT | 435 OV2740_TEST_PATTERN_ENABLE; 436 437 return ov2740_write_reg(ov2740, OV2740_REG_TEST_PATTERN, 1, pattern); 438 } 439 440 static int ov2740_set_ctrl(struct v4l2_ctrl *ctrl) 441 { 442 struct ov2740 *ov2740 = container_of(ctrl->handler, 443 struct ov2740, ctrl_handler); 444 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 445 s64 exposure_max; 446 int ret = 0; 447 448 /* Propagate change of current control to all related controls */ 449 if (ctrl->id == V4L2_CID_VBLANK) { 450 /* Update max exposure while meeting expected vblanking */ 451 exposure_max = ov2740->cur_mode->height + ctrl->val - 452 OV2740_EXPOSURE_MAX_MARGIN; 453 __v4l2_ctrl_modify_range(ov2740->exposure, 454 ov2740->exposure->minimum, 455 exposure_max, ov2740->exposure->step, 456 exposure_max); 457 } 458 459 /* V4L2 controls values will be applied only when power is already up */ 460 if (!pm_runtime_get_if_in_use(&client->dev)) 461 return 0; 462 463 switch (ctrl->id) { 464 case V4L2_CID_ANALOGUE_GAIN: 465 ret = ov2740_write_reg(ov2740, OV2740_REG_ANALOG_GAIN, 2, 466 ctrl->val); 467 break; 468 469 case V4L2_CID_DIGITAL_GAIN: 470 ret = ov2740_update_digital_gain(ov2740, ctrl->val); 471 break; 472 473 case V4L2_CID_EXPOSURE: 474 /* 4 least significant bits of expsoure are fractional part */ 475 ret = ov2740_write_reg(ov2740, OV2740_REG_EXPOSURE, 3, 476 ctrl->val << 4); 477 break; 478 479 case V4L2_CID_VBLANK: 480 ret = ov2740_write_reg(ov2740, OV2740_REG_VTS, 2, 481 ov2740->cur_mode->height + ctrl->val); 482 break; 483 484 case V4L2_CID_TEST_PATTERN: 485 ret = ov2740_test_pattern(ov2740, ctrl->val); 486 break; 487 488 default: 489 ret = -EINVAL; 490 break; 491 } 492 493 pm_runtime_put(&client->dev); 494 495 return ret; 496 } 497 498 static const struct v4l2_ctrl_ops ov2740_ctrl_ops = { 499 .s_ctrl = ov2740_set_ctrl, 500 }; 501 502 static int ov2740_init_controls(struct ov2740 *ov2740) 503 { 504 struct v4l2_ctrl_handler *ctrl_hdlr; 505 const struct ov2740_mode *cur_mode; 506 s64 exposure_max, h_blank, pixel_rate; 507 u32 vblank_min, vblank_max, vblank_default; 508 int size; 509 int ret = 0; 510 511 ctrl_hdlr = &ov2740->ctrl_handler; 512 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8); 513 if (ret) 514 return ret; 515 516 ctrl_hdlr->lock = &ov2740->mutex; 517 cur_mode = ov2740->cur_mode; 518 size = ARRAY_SIZE(link_freq_menu_items); 519 520 ov2740->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &ov2740_ctrl_ops, 521 V4L2_CID_LINK_FREQ, 522 size - 1, 0, 523 link_freq_menu_items); 524 if (ov2740->link_freq) 525 ov2740->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 526 527 pixel_rate = to_pixel_rate(OV2740_LINK_FREQ_360MHZ_INDEX); 528 ov2740->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, 529 V4L2_CID_PIXEL_RATE, 0, 530 pixel_rate, 1, pixel_rate); 531 532 vblank_min = cur_mode->vts_min - cur_mode->height; 533 vblank_max = OV2740_VTS_MAX - cur_mode->height; 534 vblank_default = cur_mode->vts_def - cur_mode->height; 535 ov2740->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, 536 V4L2_CID_VBLANK, vblank_min, 537 vblank_max, 1, vblank_default); 538 539 h_blank = to_pixels_per_line(cur_mode->hts, cur_mode->link_freq_index); 540 h_blank -= cur_mode->width; 541 ov2740->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, 542 V4L2_CID_HBLANK, h_blank, h_blank, 1, 543 h_blank); 544 if (ov2740->hblank) 545 ov2740->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 546 547 v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, 548 OV2740_ANAL_GAIN_MIN, OV2740_ANAL_GAIN_MAX, 549 OV2740_ANAL_GAIN_STEP, OV2740_ANAL_GAIN_MIN); 550 v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_DIGITAL_GAIN, 551 OV2740_DGTL_GAIN_MIN, OV2740_DGTL_GAIN_MAX, 552 OV2740_DGTL_GAIN_STEP, OV2740_DGTL_GAIN_DEFAULT); 553 exposure_max = cur_mode->vts_def - OV2740_EXPOSURE_MAX_MARGIN; 554 ov2740->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, 555 V4L2_CID_EXPOSURE, 556 OV2740_EXPOSURE_MIN, exposure_max, 557 OV2740_EXPOSURE_STEP, 558 exposure_max); 559 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov2740_ctrl_ops, 560 V4L2_CID_TEST_PATTERN, 561 ARRAY_SIZE(ov2740_test_pattern_menu) - 1, 562 0, 0, ov2740_test_pattern_menu); 563 if (ctrl_hdlr->error) 564 return ctrl_hdlr->error; 565 566 ov2740->sd.ctrl_handler = ctrl_hdlr; 567 568 return 0; 569 } 570 571 static void ov2740_update_pad_format(const struct ov2740_mode *mode, 572 struct v4l2_mbus_framefmt *fmt) 573 { 574 fmt->width = mode->width; 575 fmt->height = mode->height; 576 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; 577 fmt->field = V4L2_FIELD_NONE; 578 } 579 580 static int ov2740_start_streaming(struct ov2740 *ov2740) 581 { 582 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 583 const struct ov2740_reg_list *reg_list; 584 int link_freq_index; 585 int ret = 0; 586 587 link_freq_index = ov2740->cur_mode->link_freq_index; 588 reg_list = &link_freq_configs[link_freq_index].reg_list; 589 ret = ov2740_write_reg_list(ov2740, reg_list); 590 if (ret) { 591 dev_err(&client->dev, "failed to set plls"); 592 return ret; 593 } 594 595 reg_list = &ov2740->cur_mode->reg_list; 596 ret = ov2740_write_reg_list(ov2740, reg_list); 597 if (ret) { 598 dev_err(&client->dev, "failed to set mode"); 599 return ret; 600 } 601 602 ret = __v4l2_ctrl_handler_setup(ov2740->sd.ctrl_handler); 603 if (ret) 604 return ret; 605 606 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1, 607 OV2740_MODE_STREAMING); 608 if (ret) 609 dev_err(&client->dev, "failed to start streaming"); 610 611 return ret; 612 } 613 614 static void ov2740_stop_streaming(struct ov2740 *ov2740) 615 { 616 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 617 618 if (ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1, 619 OV2740_MODE_STANDBY)) 620 dev_err(&client->dev, "failed to stop streaming"); 621 } 622 623 static int ov2740_set_stream(struct v4l2_subdev *sd, int enable) 624 { 625 struct ov2740 *ov2740 = to_ov2740(sd); 626 struct i2c_client *client = v4l2_get_subdevdata(sd); 627 int ret = 0; 628 629 if (ov2740->streaming == enable) 630 return 0; 631 632 mutex_lock(&ov2740->mutex); 633 if (enable) { 634 ret = pm_runtime_get_sync(&client->dev); 635 if (ret < 0) { 636 pm_runtime_put_noidle(&client->dev); 637 mutex_unlock(&ov2740->mutex); 638 return ret; 639 } 640 641 ret = ov2740_start_streaming(ov2740); 642 if (ret) { 643 enable = 0; 644 ov2740_stop_streaming(ov2740); 645 pm_runtime_put(&client->dev); 646 } 647 } else { 648 ov2740_stop_streaming(ov2740); 649 pm_runtime_put(&client->dev); 650 } 651 652 ov2740->streaming = enable; 653 mutex_unlock(&ov2740->mutex); 654 655 return ret; 656 } 657 658 static int __maybe_unused ov2740_suspend(struct device *dev) 659 { 660 struct i2c_client *client = to_i2c_client(dev); 661 struct v4l2_subdev *sd = i2c_get_clientdata(client); 662 struct ov2740 *ov2740 = to_ov2740(sd); 663 664 mutex_lock(&ov2740->mutex); 665 if (ov2740->streaming) 666 ov2740_stop_streaming(ov2740); 667 668 mutex_unlock(&ov2740->mutex); 669 670 return 0; 671 } 672 673 static int __maybe_unused ov2740_resume(struct device *dev) 674 { 675 struct i2c_client *client = to_i2c_client(dev); 676 struct v4l2_subdev *sd = i2c_get_clientdata(client); 677 struct ov2740 *ov2740 = to_ov2740(sd); 678 int ret = 0; 679 680 mutex_lock(&ov2740->mutex); 681 if (!ov2740->streaming) 682 goto exit; 683 684 ret = ov2740_start_streaming(ov2740); 685 if (ret) { 686 ov2740->streaming = false; 687 ov2740_stop_streaming(ov2740); 688 } 689 690 exit: 691 mutex_unlock(&ov2740->mutex); 692 return ret; 693 } 694 695 static int ov2740_set_format(struct v4l2_subdev *sd, 696 struct v4l2_subdev_pad_config *cfg, 697 struct v4l2_subdev_format *fmt) 698 { 699 struct ov2740 *ov2740 = to_ov2740(sd); 700 const struct ov2740_mode *mode; 701 s32 vblank_def, h_blank; 702 703 mode = v4l2_find_nearest_size(supported_modes, 704 ARRAY_SIZE(supported_modes), width, 705 height, fmt->format.width, 706 fmt->format.height); 707 708 mutex_lock(&ov2740->mutex); 709 ov2740_update_pad_format(mode, &fmt->format); 710 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 711 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format; 712 } else { 713 ov2740->cur_mode = mode; 714 __v4l2_ctrl_s_ctrl(ov2740->link_freq, mode->link_freq_index); 715 __v4l2_ctrl_s_ctrl_int64(ov2740->pixel_rate, 716 to_pixel_rate(mode->link_freq_index)); 717 718 /* Update limits and set FPS to default */ 719 vblank_def = mode->vts_def - mode->height; 720 __v4l2_ctrl_modify_range(ov2740->vblank, 721 mode->vts_min - mode->height, 722 OV2740_VTS_MAX - mode->height, 1, 723 vblank_def); 724 __v4l2_ctrl_s_ctrl(ov2740->vblank, vblank_def); 725 h_blank = to_pixels_per_line(mode->hts, mode->link_freq_index) - 726 mode->width; 727 __v4l2_ctrl_modify_range(ov2740->hblank, h_blank, h_blank, 1, 728 h_blank); 729 } 730 mutex_unlock(&ov2740->mutex); 731 732 return 0; 733 } 734 735 static int ov2740_get_format(struct v4l2_subdev *sd, 736 struct v4l2_subdev_pad_config *cfg, 737 struct v4l2_subdev_format *fmt) 738 { 739 struct ov2740 *ov2740 = to_ov2740(sd); 740 741 mutex_lock(&ov2740->mutex); 742 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) 743 fmt->format = *v4l2_subdev_get_try_format(&ov2740->sd, cfg, 744 fmt->pad); 745 else 746 ov2740_update_pad_format(ov2740->cur_mode, &fmt->format); 747 748 mutex_unlock(&ov2740->mutex); 749 750 return 0; 751 } 752 753 static int ov2740_enum_mbus_code(struct v4l2_subdev *sd, 754 struct v4l2_subdev_pad_config *cfg, 755 struct v4l2_subdev_mbus_code_enum *code) 756 { 757 if (code->index > 0) 758 return -EINVAL; 759 760 code->code = MEDIA_BUS_FMT_SGRBG10_1X10; 761 762 return 0; 763 } 764 765 static int ov2740_enum_frame_size(struct v4l2_subdev *sd, 766 struct v4l2_subdev_pad_config *cfg, 767 struct v4l2_subdev_frame_size_enum *fse) 768 { 769 if (fse->index >= ARRAY_SIZE(supported_modes)) 770 return -EINVAL; 771 772 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10) 773 return -EINVAL; 774 775 fse->min_width = supported_modes[fse->index].width; 776 fse->max_width = fse->min_width; 777 fse->min_height = supported_modes[fse->index].height; 778 fse->max_height = fse->min_height; 779 780 return 0; 781 } 782 783 static int ov2740_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) 784 { 785 struct ov2740 *ov2740 = to_ov2740(sd); 786 787 mutex_lock(&ov2740->mutex); 788 ov2740_update_pad_format(&supported_modes[0], 789 v4l2_subdev_get_try_format(sd, fh->pad, 0)); 790 mutex_unlock(&ov2740->mutex); 791 792 return 0; 793 } 794 795 static const struct v4l2_subdev_video_ops ov2740_video_ops = { 796 .s_stream = ov2740_set_stream, 797 }; 798 799 static const struct v4l2_subdev_pad_ops ov2740_pad_ops = { 800 .set_fmt = ov2740_set_format, 801 .get_fmt = ov2740_get_format, 802 .enum_mbus_code = ov2740_enum_mbus_code, 803 .enum_frame_size = ov2740_enum_frame_size, 804 }; 805 806 static const struct v4l2_subdev_ops ov2740_subdev_ops = { 807 .video = &ov2740_video_ops, 808 .pad = &ov2740_pad_ops, 809 }; 810 811 static const struct media_entity_operations ov2740_subdev_entity_ops = { 812 .link_validate = v4l2_subdev_link_validate, 813 }; 814 815 static const struct v4l2_subdev_internal_ops ov2740_internal_ops = { 816 .open = ov2740_open, 817 }; 818 819 static int ov2740_identify_module(struct ov2740 *ov2740) 820 { 821 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 822 int ret; 823 u32 val; 824 825 ret = ov2740_read_reg(ov2740, OV2740_REG_CHIP_ID, 3, &val); 826 if (ret) 827 return ret; 828 829 if (val != OV2740_CHIP_ID) { 830 dev_err(&client->dev, "chip id mismatch: %x!=%x", 831 OV2740_CHIP_ID, val); 832 return -ENXIO; 833 } 834 835 return 0; 836 } 837 838 static int ov2740_check_hwcfg(struct device *dev) 839 { 840 struct fwnode_handle *ep; 841 struct fwnode_handle *fwnode = dev_fwnode(dev); 842 struct v4l2_fwnode_endpoint bus_cfg = { 843 .bus_type = V4L2_MBUS_CSI2_DPHY 844 }; 845 u32 mclk; 846 int ret; 847 unsigned int i, j; 848 849 if (!fwnode) 850 return -ENXIO; 851 852 ret = fwnode_property_read_u32(fwnode, "clock-frequency", &mclk); 853 if (ret) 854 return ret; 855 856 if (mclk != OV2740_MCLK) { 857 dev_err(dev, "external clock %d is not supported", mclk); 858 return -EINVAL; 859 } 860 861 ep = fwnode_graph_get_next_endpoint(fwnode, NULL); 862 if (!ep) 863 return -ENXIO; 864 865 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); 866 fwnode_handle_put(ep); 867 if (ret) 868 return ret; 869 870 if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV2740_DATA_LANES) { 871 dev_err(dev, "number of CSI2 data lanes %d is not supported", 872 bus_cfg.bus.mipi_csi2.num_data_lanes); 873 ret = -EINVAL; 874 goto check_hwcfg_error; 875 } 876 877 if (!bus_cfg.nr_of_link_frequencies) { 878 dev_err(dev, "no link frequencies defined"); 879 ret = -EINVAL; 880 goto check_hwcfg_error; 881 } 882 883 for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) { 884 for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) { 885 if (link_freq_menu_items[i] == 886 bus_cfg.link_frequencies[j]) 887 break; 888 } 889 890 if (j == bus_cfg.nr_of_link_frequencies) { 891 dev_err(dev, "no link frequency %lld supported", 892 link_freq_menu_items[i]); 893 ret = -EINVAL; 894 goto check_hwcfg_error; 895 } 896 } 897 898 check_hwcfg_error: 899 v4l2_fwnode_endpoint_free(&bus_cfg); 900 901 return ret; 902 } 903 904 static int ov2740_remove(struct i2c_client *client) 905 { 906 struct v4l2_subdev *sd = i2c_get_clientdata(client); 907 struct ov2740 *ov2740 = to_ov2740(sd); 908 909 v4l2_async_unregister_subdev(sd); 910 media_entity_cleanup(&sd->entity); 911 v4l2_ctrl_handler_free(sd->ctrl_handler); 912 pm_runtime_disable(&client->dev); 913 mutex_destroy(&ov2740->mutex); 914 915 return 0; 916 } 917 918 static int ov2740_probe(struct i2c_client *client) 919 { 920 struct ov2740 *ov2740; 921 int ret = 0; 922 923 ret = ov2740_check_hwcfg(&client->dev); 924 if (ret) { 925 dev_err(&client->dev, "failed to check HW configuration: %d", 926 ret); 927 return ret; 928 } 929 930 ov2740 = devm_kzalloc(&client->dev, sizeof(*ov2740), GFP_KERNEL); 931 if (!ov2740) 932 return -ENOMEM; 933 934 v4l2_i2c_subdev_init(&ov2740->sd, client, &ov2740_subdev_ops); 935 ret = ov2740_identify_module(ov2740); 936 if (ret) { 937 dev_err(&client->dev, "failed to find sensor: %d", ret); 938 return ret; 939 } 940 941 mutex_init(&ov2740->mutex); 942 ov2740->cur_mode = &supported_modes[0]; 943 ret = ov2740_init_controls(ov2740); 944 if (ret) { 945 dev_err(&client->dev, "failed to init controls: %d", ret); 946 goto probe_error_v4l2_ctrl_handler_free; 947 } 948 949 ov2740->sd.internal_ops = &ov2740_internal_ops; 950 ov2740->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 951 ov2740->sd.entity.ops = &ov2740_subdev_entity_ops; 952 ov2740->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 953 ov2740->pad.flags = MEDIA_PAD_FL_SOURCE; 954 ret = media_entity_pads_init(&ov2740->sd.entity, 1, &ov2740->pad); 955 if (ret) { 956 dev_err(&client->dev, "failed to init entity pads: %d", ret); 957 goto probe_error_v4l2_ctrl_handler_free; 958 } 959 960 ret = v4l2_async_register_subdev_sensor_common(&ov2740->sd); 961 if (ret < 0) { 962 dev_err(&client->dev, "failed to register V4L2 subdev: %d", 963 ret); 964 goto probe_error_media_entity_cleanup; 965 } 966 967 /* 968 * Device is already turned on by i2c-core with ACPI domain PM. 969 * Enable runtime PM and turn off the device. 970 */ 971 pm_runtime_set_active(&client->dev); 972 pm_runtime_enable(&client->dev); 973 pm_runtime_idle(&client->dev); 974 975 return 0; 976 977 probe_error_media_entity_cleanup: 978 media_entity_cleanup(&ov2740->sd.entity); 979 980 probe_error_v4l2_ctrl_handler_free: 981 v4l2_ctrl_handler_free(ov2740->sd.ctrl_handler); 982 mutex_destroy(&ov2740->mutex); 983 984 return ret; 985 } 986 987 static const struct dev_pm_ops ov2740_pm_ops = { 988 SET_SYSTEM_SLEEP_PM_OPS(ov2740_suspend, ov2740_resume) 989 }; 990 991 #ifdef CONFIG_ACPI 992 static const struct acpi_device_id ov2740_acpi_ids[] = { 993 {"INT3474"}, 994 {} 995 }; 996 997 MODULE_DEVICE_TABLE(acpi, ov2740_acpi_ids); 998 #endif 999 1000 static struct i2c_driver ov2740_i2c_driver = { 1001 .driver = { 1002 .name = "ov2740", 1003 .pm = &ov2740_pm_ops, 1004 .acpi_match_table = ACPI_PTR(ov2740_acpi_ids), 1005 }, 1006 .probe_new = ov2740_probe, 1007 .remove = ov2740_remove, 1008 }; 1009 1010 module_i2c_driver(ov2740_i2c_driver); 1011 1012 MODULE_AUTHOR("Qiu, Tianshu <tian.shu.qiu@intel.com>"); 1013 MODULE_AUTHOR("Shawn Tu <shawnx.tu@intel.com>"); 1014 MODULE_AUTHOR("Bingbu Cao <bingbu.cao@intel.com>"); 1015 MODULE_DESCRIPTION("OmniVision OV2740 sensor driver"); 1016 MODULE_LICENSE("GPL v2"); 1017