1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2020 Intel Corporation. 3 4 #include <asm/unaligned.h> 5 #include <linux/acpi.h> 6 #include <linux/delay.h> 7 #include <linux/i2c.h> 8 #include <linux/module.h> 9 #include <linux/pm_runtime.h> 10 #include <linux/nvmem-provider.h> 11 #include <linux/regmap.h> 12 #include <media/v4l2-ctrls.h> 13 #include <media/v4l2-device.h> 14 #include <media/v4l2-fwnode.h> 15 16 #define OV2740_LINK_FREQ_360MHZ 360000000ULL 17 #define OV2740_SCLK 72000000LL 18 #define OV2740_MCLK 19200000 19 #define OV2740_DATA_LANES 2 20 #define OV2740_RGB_DEPTH 10 21 22 #define OV2740_REG_CHIP_ID 0x300a 23 #define OV2740_CHIP_ID 0x2740 24 25 #define OV2740_REG_MODE_SELECT 0x0100 26 #define OV2740_MODE_STANDBY 0x00 27 #define OV2740_MODE_STREAMING 0x01 28 29 /* vertical-timings from sensor */ 30 #define OV2740_REG_VTS 0x380e 31 #define OV2740_VTS_DEF 0x088a 32 #define OV2740_VTS_MIN 0x0460 33 #define OV2740_VTS_MAX 0x7fff 34 35 /* horizontal-timings from sensor */ 36 #define OV2740_REG_HTS 0x380c 37 38 /* Exposure controls from sensor */ 39 #define OV2740_REG_EXPOSURE 0x3500 40 #define OV2740_EXPOSURE_MIN 4 41 #define OV2740_EXPOSURE_MAX_MARGIN 8 42 #define OV2740_EXPOSURE_STEP 1 43 44 /* Analog gain controls from sensor */ 45 #define OV2740_REG_ANALOG_GAIN 0x3508 46 #define OV2740_ANAL_GAIN_MIN 128 47 #define OV2740_ANAL_GAIN_MAX 1983 48 #define OV2740_ANAL_GAIN_STEP 1 49 50 /* Digital gain controls from sensor */ 51 #define OV2740_REG_MWB_R_GAIN 0x500a 52 #define OV2740_REG_MWB_G_GAIN 0x500c 53 #define OV2740_REG_MWB_B_GAIN 0x500e 54 #define OV2740_DGTL_GAIN_MIN 1024 55 #define OV2740_DGTL_GAIN_MAX 4095 56 #define OV2740_DGTL_GAIN_STEP 1 57 #define OV2740_DGTL_GAIN_DEFAULT 1024 58 59 /* Test Pattern Control */ 60 #define OV2740_REG_TEST_PATTERN 0x5040 61 #define OV2740_TEST_PATTERN_ENABLE BIT(7) 62 #define OV2740_TEST_PATTERN_BAR_SHIFT 2 63 64 /* Group Access */ 65 #define OV2740_REG_GROUP_ACCESS 0x3208 66 #define OV2740_GROUP_HOLD_START 0x0 67 #define OV2740_GROUP_HOLD_END 0x10 68 #define OV2740_GROUP_HOLD_LAUNCH 0xa0 69 70 /* ISP CTRL00 */ 71 #define OV2740_REG_ISP_CTRL00 0x5000 72 /* ISP CTRL01 */ 73 #define OV2740_REG_ISP_CTRL01 0x5001 74 /* Customer Addresses: 0x7010 - 0x710F */ 75 #define CUSTOMER_USE_OTP_SIZE 0x100 76 /* OTP registers from sensor */ 77 #define OV2740_REG_OTP_CUSTOMER 0x7010 78 79 struct nvm_data { 80 struct i2c_client *client; 81 struct nvmem_device *nvmem; 82 struct regmap *regmap; 83 char *nvm_buffer; 84 }; 85 86 enum { 87 OV2740_LINK_FREQ_360MHZ_INDEX, 88 }; 89 90 struct ov2740_reg { 91 u16 address; 92 u8 val; 93 }; 94 95 struct ov2740_reg_list { 96 u32 num_of_regs; 97 const struct ov2740_reg *regs; 98 }; 99 100 struct ov2740_link_freq_config { 101 const struct ov2740_reg_list reg_list; 102 }; 103 104 struct ov2740_mode { 105 /* Frame width in pixels */ 106 u32 width; 107 108 /* Frame height in pixels */ 109 u32 height; 110 111 /* Horizontal timining size */ 112 u32 hts; 113 114 /* Default vertical timining size */ 115 u32 vts_def; 116 117 /* Min vertical timining size */ 118 u32 vts_min; 119 120 /* Link frequency needed for this resolution */ 121 u32 link_freq_index; 122 123 /* Sensor register settings for this resolution */ 124 const struct ov2740_reg_list reg_list; 125 }; 126 127 static const struct ov2740_reg mipi_data_rate_720mbps[] = { 128 {0x0103, 0x01}, 129 {0x0302, 0x4b}, 130 {0x030d, 0x4b}, 131 {0x030e, 0x02}, 132 {0x030a, 0x01}, 133 {0x0312, 0x11}, 134 }; 135 136 static const struct ov2740_reg mode_1932x1092_regs[] = { 137 {0x3000, 0x00}, 138 {0x3018, 0x32}, 139 {0x3031, 0x0a}, 140 {0x3080, 0x08}, 141 {0x3083, 0xB4}, 142 {0x3103, 0x00}, 143 {0x3104, 0x01}, 144 {0x3106, 0x01}, 145 {0x3500, 0x00}, 146 {0x3501, 0x44}, 147 {0x3502, 0x40}, 148 {0x3503, 0x88}, 149 {0x3507, 0x00}, 150 {0x3508, 0x00}, 151 {0x3509, 0x80}, 152 {0x350c, 0x00}, 153 {0x350d, 0x80}, 154 {0x3510, 0x00}, 155 {0x3511, 0x00}, 156 {0x3512, 0x20}, 157 {0x3632, 0x00}, 158 {0x3633, 0x10}, 159 {0x3634, 0x10}, 160 {0x3635, 0x10}, 161 {0x3645, 0x13}, 162 {0x3646, 0x81}, 163 {0x3636, 0x10}, 164 {0x3651, 0x0a}, 165 {0x3656, 0x02}, 166 {0x3659, 0x04}, 167 {0x365a, 0xda}, 168 {0x365b, 0xa2}, 169 {0x365c, 0x04}, 170 {0x365d, 0x1d}, 171 {0x365e, 0x1a}, 172 {0x3662, 0xd7}, 173 {0x3667, 0x78}, 174 {0x3669, 0x0a}, 175 {0x366a, 0x92}, 176 {0x3700, 0x54}, 177 {0x3702, 0x10}, 178 {0x3706, 0x42}, 179 {0x3709, 0x30}, 180 {0x370b, 0xc2}, 181 {0x3714, 0x63}, 182 {0x3715, 0x01}, 183 {0x3716, 0x00}, 184 {0x371a, 0x3e}, 185 {0x3732, 0x0e}, 186 {0x3733, 0x10}, 187 {0x375f, 0x0e}, 188 {0x3768, 0x30}, 189 {0x3769, 0x44}, 190 {0x376a, 0x22}, 191 {0x377b, 0x20}, 192 {0x377c, 0x00}, 193 {0x377d, 0x0c}, 194 {0x3798, 0x00}, 195 {0x37a1, 0x55}, 196 {0x37a8, 0x6d}, 197 {0x37c2, 0x04}, 198 {0x37c5, 0x00}, 199 {0x37c8, 0x00}, 200 {0x3800, 0x00}, 201 {0x3801, 0x00}, 202 {0x3802, 0x00}, 203 {0x3803, 0x00}, 204 {0x3804, 0x07}, 205 {0x3805, 0x8f}, 206 {0x3806, 0x04}, 207 {0x3807, 0x47}, 208 {0x3808, 0x07}, 209 {0x3809, 0x88}, 210 {0x380a, 0x04}, 211 {0x380b, 0x40}, 212 {0x380c, 0x04}, 213 {0x380d, 0x38}, 214 {0x380e, 0x04}, 215 {0x380f, 0x60}, 216 {0x3810, 0x00}, 217 {0x3811, 0x04}, 218 {0x3812, 0x00}, 219 {0x3813, 0x04}, 220 {0x3814, 0x01}, 221 {0x3815, 0x01}, 222 {0x3820, 0x80}, 223 {0x3821, 0x46}, 224 {0x3822, 0x84}, 225 {0x3829, 0x00}, 226 {0x382a, 0x01}, 227 {0x382b, 0x01}, 228 {0x3830, 0x04}, 229 {0x3836, 0x01}, 230 {0x3837, 0x08}, 231 {0x3839, 0x01}, 232 {0x383a, 0x00}, 233 {0x383b, 0x08}, 234 {0x383c, 0x00}, 235 {0x3f0b, 0x00}, 236 {0x4001, 0x20}, 237 {0x4009, 0x07}, 238 {0x4003, 0x10}, 239 {0x4010, 0xe0}, 240 {0x4016, 0x00}, 241 {0x4017, 0x10}, 242 {0x4044, 0x02}, 243 {0x4304, 0x08}, 244 {0x4307, 0x30}, 245 {0x4320, 0x80}, 246 {0x4322, 0x00}, 247 {0x4323, 0x00}, 248 {0x4324, 0x00}, 249 {0x4325, 0x00}, 250 {0x4326, 0x00}, 251 {0x4327, 0x00}, 252 {0x4328, 0x00}, 253 {0x4329, 0x00}, 254 {0x432c, 0x03}, 255 {0x432d, 0x81}, 256 {0x4501, 0x84}, 257 {0x4502, 0x40}, 258 {0x4503, 0x18}, 259 {0x4504, 0x04}, 260 {0x4508, 0x02}, 261 {0x4601, 0x10}, 262 {0x4800, 0x00}, 263 {0x4816, 0x52}, 264 {0x4837, 0x16}, 265 {0x5000, 0x7f}, 266 {0x5001, 0x00}, 267 {0x5005, 0x38}, 268 {0x501e, 0x0d}, 269 {0x5040, 0x00}, 270 {0x5901, 0x00}, 271 {0x3800, 0x00}, 272 {0x3801, 0x00}, 273 {0x3802, 0x00}, 274 {0x3803, 0x00}, 275 {0x3804, 0x07}, 276 {0x3805, 0x8f}, 277 {0x3806, 0x04}, 278 {0x3807, 0x47}, 279 {0x3808, 0x07}, 280 {0x3809, 0x8c}, 281 {0x380a, 0x04}, 282 {0x380b, 0x44}, 283 {0x3810, 0x00}, 284 {0x3811, 0x00}, 285 {0x3812, 0x00}, 286 {0x3813, 0x01}, 287 }; 288 289 static const char * const ov2740_test_pattern_menu[] = { 290 "Disabled", 291 "Color Bar", 292 "Top-Bottom Darker Color Bar", 293 "Right-Left Darker Color Bar", 294 "Bottom-Top Darker Color Bar", 295 }; 296 297 static const s64 link_freq_menu_items[] = { 298 OV2740_LINK_FREQ_360MHZ, 299 }; 300 301 static const struct ov2740_link_freq_config link_freq_configs[] = { 302 [OV2740_LINK_FREQ_360MHZ_INDEX] = { 303 .reg_list = { 304 .num_of_regs = ARRAY_SIZE(mipi_data_rate_720mbps), 305 .regs = mipi_data_rate_720mbps, 306 } 307 }, 308 }; 309 310 static const struct ov2740_mode supported_modes[] = { 311 { 312 .width = 1932, 313 .height = 1092, 314 .hts = 1080, 315 .vts_def = OV2740_VTS_DEF, 316 .vts_min = OV2740_VTS_MIN, 317 .reg_list = { 318 .num_of_regs = ARRAY_SIZE(mode_1932x1092_regs), 319 .regs = mode_1932x1092_regs, 320 }, 321 .link_freq_index = OV2740_LINK_FREQ_360MHZ_INDEX, 322 }, 323 }; 324 325 struct ov2740 { 326 struct v4l2_subdev sd; 327 struct media_pad pad; 328 struct v4l2_ctrl_handler ctrl_handler; 329 330 /* V4L2 Controls */ 331 struct v4l2_ctrl *link_freq; 332 struct v4l2_ctrl *pixel_rate; 333 struct v4l2_ctrl *vblank; 334 struct v4l2_ctrl *hblank; 335 struct v4l2_ctrl *exposure; 336 337 /* Current mode */ 338 const struct ov2740_mode *cur_mode; 339 340 /* To serialize asynchronus callbacks */ 341 struct mutex mutex; 342 343 /* Streaming on/off */ 344 bool streaming; 345 346 /* NVM data inforamtion */ 347 struct nvm_data *nvm; 348 }; 349 350 static inline struct ov2740 *to_ov2740(struct v4l2_subdev *subdev) 351 { 352 return container_of(subdev, struct ov2740, sd); 353 } 354 355 static u64 to_pixel_rate(u32 f_index) 356 { 357 u64 pixel_rate = link_freq_menu_items[f_index] * 2 * OV2740_DATA_LANES; 358 359 do_div(pixel_rate, OV2740_RGB_DEPTH); 360 361 return pixel_rate; 362 } 363 364 static u64 to_pixels_per_line(u32 hts, u32 f_index) 365 { 366 u64 ppl = hts * to_pixel_rate(f_index); 367 368 do_div(ppl, OV2740_SCLK); 369 370 return ppl; 371 } 372 373 static int ov2740_read_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 *val) 374 { 375 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 376 struct i2c_msg msgs[2]; 377 u8 addr_buf[2]; 378 u8 data_buf[4] = {0}; 379 int ret = 0; 380 381 if (len > sizeof(data_buf)) 382 return -EINVAL; 383 384 put_unaligned_be16(reg, addr_buf); 385 msgs[0].addr = client->addr; 386 msgs[0].flags = 0; 387 msgs[0].len = sizeof(addr_buf); 388 msgs[0].buf = addr_buf; 389 msgs[1].addr = client->addr; 390 msgs[1].flags = I2C_M_RD; 391 msgs[1].len = len; 392 msgs[1].buf = &data_buf[sizeof(data_buf) - len]; 393 394 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); 395 if (ret != ARRAY_SIZE(msgs)) 396 return ret < 0 ? ret : -EIO; 397 398 *val = get_unaligned_be32(data_buf); 399 400 return 0; 401 } 402 403 static int ov2740_write_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 val) 404 { 405 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 406 u8 buf[6]; 407 int ret = 0; 408 409 if (len > 4) 410 return -EINVAL; 411 412 put_unaligned_be16(reg, buf); 413 put_unaligned_be32(val << 8 * (4 - len), buf + 2); 414 415 ret = i2c_master_send(client, buf, len + 2); 416 if (ret != len + 2) 417 return ret < 0 ? ret : -EIO; 418 419 return 0; 420 } 421 422 static int ov2740_write_reg_list(struct ov2740 *ov2740, 423 const struct ov2740_reg_list *r_list) 424 { 425 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 426 unsigned int i; 427 int ret = 0; 428 429 for (i = 0; i < r_list->num_of_regs; i++) { 430 ret = ov2740_write_reg(ov2740, r_list->regs[i].address, 1, 431 r_list->regs[i].val); 432 if (ret) { 433 dev_err_ratelimited(&client->dev, 434 "write reg 0x%4.4x return err = %d", 435 r_list->regs[i].address, ret); 436 return ret; 437 } 438 } 439 440 return 0; 441 } 442 443 static int ov2740_update_digital_gain(struct ov2740 *ov2740, u32 d_gain) 444 { 445 int ret = 0; 446 447 ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1, 448 OV2740_GROUP_HOLD_START); 449 if (ret) 450 return ret; 451 452 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_R_GAIN, 2, d_gain); 453 if (ret) 454 return ret; 455 456 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_G_GAIN, 2, d_gain); 457 if (ret) 458 return ret; 459 460 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_B_GAIN, 2, d_gain); 461 if (ret) 462 return ret; 463 464 ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1, 465 OV2740_GROUP_HOLD_END); 466 if (ret) 467 return ret; 468 469 ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1, 470 OV2740_GROUP_HOLD_LAUNCH); 471 return ret; 472 } 473 474 static int ov2740_test_pattern(struct ov2740 *ov2740, u32 pattern) 475 { 476 if (pattern) 477 pattern = (pattern - 1) << OV2740_TEST_PATTERN_BAR_SHIFT | 478 OV2740_TEST_PATTERN_ENABLE; 479 480 return ov2740_write_reg(ov2740, OV2740_REG_TEST_PATTERN, 1, pattern); 481 } 482 483 static int ov2740_set_ctrl(struct v4l2_ctrl *ctrl) 484 { 485 struct ov2740 *ov2740 = container_of(ctrl->handler, 486 struct ov2740, ctrl_handler); 487 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 488 s64 exposure_max; 489 int ret = 0; 490 491 /* Propagate change of current control to all related controls */ 492 if (ctrl->id == V4L2_CID_VBLANK) { 493 /* Update max exposure while meeting expected vblanking */ 494 exposure_max = ov2740->cur_mode->height + ctrl->val - 495 OV2740_EXPOSURE_MAX_MARGIN; 496 __v4l2_ctrl_modify_range(ov2740->exposure, 497 ov2740->exposure->minimum, 498 exposure_max, ov2740->exposure->step, 499 exposure_max); 500 } 501 502 /* V4L2 controls values will be applied only when power is already up */ 503 if (!pm_runtime_get_if_in_use(&client->dev)) 504 return 0; 505 506 switch (ctrl->id) { 507 case V4L2_CID_ANALOGUE_GAIN: 508 ret = ov2740_write_reg(ov2740, OV2740_REG_ANALOG_GAIN, 2, 509 ctrl->val); 510 break; 511 512 case V4L2_CID_DIGITAL_GAIN: 513 ret = ov2740_update_digital_gain(ov2740, ctrl->val); 514 break; 515 516 case V4L2_CID_EXPOSURE: 517 /* 4 least significant bits of expsoure are fractional part */ 518 ret = ov2740_write_reg(ov2740, OV2740_REG_EXPOSURE, 3, 519 ctrl->val << 4); 520 break; 521 522 case V4L2_CID_VBLANK: 523 ret = ov2740_write_reg(ov2740, OV2740_REG_VTS, 2, 524 ov2740->cur_mode->height + ctrl->val); 525 break; 526 527 case V4L2_CID_TEST_PATTERN: 528 ret = ov2740_test_pattern(ov2740, ctrl->val); 529 break; 530 531 default: 532 ret = -EINVAL; 533 break; 534 } 535 536 pm_runtime_put(&client->dev); 537 538 return ret; 539 } 540 541 static const struct v4l2_ctrl_ops ov2740_ctrl_ops = { 542 .s_ctrl = ov2740_set_ctrl, 543 }; 544 545 static int ov2740_init_controls(struct ov2740 *ov2740) 546 { 547 struct v4l2_ctrl_handler *ctrl_hdlr; 548 const struct ov2740_mode *cur_mode; 549 s64 exposure_max, h_blank, pixel_rate; 550 u32 vblank_min, vblank_max, vblank_default; 551 int size; 552 int ret = 0; 553 554 ctrl_hdlr = &ov2740->ctrl_handler; 555 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8); 556 if (ret) 557 return ret; 558 559 ctrl_hdlr->lock = &ov2740->mutex; 560 cur_mode = ov2740->cur_mode; 561 size = ARRAY_SIZE(link_freq_menu_items); 562 563 ov2740->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &ov2740_ctrl_ops, 564 V4L2_CID_LINK_FREQ, 565 size - 1, 0, 566 link_freq_menu_items); 567 if (ov2740->link_freq) 568 ov2740->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 569 570 pixel_rate = to_pixel_rate(OV2740_LINK_FREQ_360MHZ_INDEX); 571 ov2740->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, 572 V4L2_CID_PIXEL_RATE, 0, 573 pixel_rate, 1, pixel_rate); 574 575 vblank_min = cur_mode->vts_min - cur_mode->height; 576 vblank_max = OV2740_VTS_MAX - cur_mode->height; 577 vblank_default = cur_mode->vts_def - cur_mode->height; 578 ov2740->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, 579 V4L2_CID_VBLANK, vblank_min, 580 vblank_max, 1, vblank_default); 581 582 h_blank = to_pixels_per_line(cur_mode->hts, cur_mode->link_freq_index); 583 h_blank -= cur_mode->width; 584 ov2740->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, 585 V4L2_CID_HBLANK, h_blank, h_blank, 1, 586 h_blank); 587 if (ov2740->hblank) 588 ov2740->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 589 590 v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, 591 OV2740_ANAL_GAIN_MIN, OV2740_ANAL_GAIN_MAX, 592 OV2740_ANAL_GAIN_STEP, OV2740_ANAL_GAIN_MIN); 593 v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_DIGITAL_GAIN, 594 OV2740_DGTL_GAIN_MIN, OV2740_DGTL_GAIN_MAX, 595 OV2740_DGTL_GAIN_STEP, OV2740_DGTL_GAIN_DEFAULT); 596 exposure_max = cur_mode->vts_def - OV2740_EXPOSURE_MAX_MARGIN; 597 ov2740->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, 598 V4L2_CID_EXPOSURE, 599 OV2740_EXPOSURE_MIN, exposure_max, 600 OV2740_EXPOSURE_STEP, 601 exposure_max); 602 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov2740_ctrl_ops, 603 V4L2_CID_TEST_PATTERN, 604 ARRAY_SIZE(ov2740_test_pattern_menu) - 1, 605 0, 0, ov2740_test_pattern_menu); 606 if (ctrl_hdlr->error) 607 return ctrl_hdlr->error; 608 609 ov2740->sd.ctrl_handler = ctrl_hdlr; 610 611 return 0; 612 } 613 614 static void ov2740_update_pad_format(const struct ov2740_mode *mode, 615 struct v4l2_mbus_framefmt *fmt) 616 { 617 fmt->width = mode->width; 618 fmt->height = mode->height; 619 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; 620 fmt->field = V4L2_FIELD_NONE; 621 } 622 623 static int ov2740_load_otp_data(struct nvm_data *nvm) 624 { 625 struct i2c_client *client; 626 struct ov2740 *ov2740; 627 u32 isp_ctrl00 = 0; 628 u32 isp_ctrl01 = 0; 629 int ret; 630 631 if (!nvm) 632 return -EINVAL; 633 634 if (nvm->nvm_buffer) 635 return 0; 636 637 client = nvm->client; 638 ov2740 = to_ov2740(i2c_get_clientdata(client)); 639 640 nvm->nvm_buffer = kzalloc(CUSTOMER_USE_OTP_SIZE, GFP_KERNEL); 641 if (!nvm->nvm_buffer) 642 return -ENOMEM; 643 644 ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, &isp_ctrl00); 645 if (ret) { 646 dev_err(&client->dev, "failed to read ISP CTRL00\n"); 647 goto err; 648 } 649 650 ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, &isp_ctrl01); 651 if (ret) { 652 dev_err(&client->dev, "failed to read ISP CTRL01\n"); 653 goto err; 654 } 655 656 /* Clear bit 5 of ISP CTRL00 */ 657 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, 658 isp_ctrl00 & ~BIT(5)); 659 if (ret) { 660 dev_err(&client->dev, "failed to set ISP CTRL00\n"); 661 goto err; 662 } 663 664 /* Clear bit 7 of ISP CTRL01 */ 665 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, 666 isp_ctrl01 & ~BIT(7)); 667 if (ret) { 668 dev_err(&client->dev, "failed to set ISP CTRL01\n"); 669 goto err; 670 } 671 672 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1, 673 OV2740_MODE_STREAMING); 674 if (ret) { 675 dev_err(&client->dev, "failed to set streaming mode\n"); 676 goto err; 677 } 678 679 /* 680 * Users are not allowed to access OTP-related registers and memory 681 * during the 20 ms period after streaming starts (0x100 = 0x01). 682 */ 683 msleep(20); 684 685 ret = regmap_bulk_read(nvm->regmap, OV2740_REG_OTP_CUSTOMER, 686 nvm->nvm_buffer, CUSTOMER_USE_OTP_SIZE); 687 if (ret) { 688 dev_err(&client->dev, "failed to read OTP data, ret %d\n", ret); 689 goto err; 690 } 691 692 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1, 693 OV2740_MODE_STANDBY); 694 if (ret) { 695 dev_err(&client->dev, "failed to set streaming mode\n"); 696 goto err; 697 } 698 699 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, isp_ctrl01); 700 if (ret) { 701 dev_err(&client->dev, "failed to set ISP CTRL01\n"); 702 goto err; 703 } 704 705 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, isp_ctrl00); 706 if (ret) { 707 dev_err(&client->dev, "failed to set ISP CTRL00\n"); 708 goto err; 709 } 710 711 return 0; 712 err: 713 kfree(nvm->nvm_buffer); 714 nvm->nvm_buffer = NULL; 715 716 return ret; 717 } 718 719 static int ov2740_start_streaming(struct ov2740 *ov2740) 720 { 721 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 722 struct nvm_data *nvm = ov2740->nvm; 723 const struct ov2740_reg_list *reg_list; 724 int link_freq_index; 725 int ret = 0; 726 727 ov2740_load_otp_data(nvm); 728 729 link_freq_index = ov2740->cur_mode->link_freq_index; 730 reg_list = &link_freq_configs[link_freq_index].reg_list; 731 ret = ov2740_write_reg_list(ov2740, reg_list); 732 if (ret) { 733 dev_err(&client->dev, "failed to set plls"); 734 return ret; 735 } 736 737 reg_list = &ov2740->cur_mode->reg_list; 738 ret = ov2740_write_reg_list(ov2740, reg_list); 739 if (ret) { 740 dev_err(&client->dev, "failed to set mode"); 741 return ret; 742 } 743 744 ret = __v4l2_ctrl_handler_setup(ov2740->sd.ctrl_handler); 745 if (ret) 746 return ret; 747 748 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1, 749 OV2740_MODE_STREAMING); 750 if (ret) 751 dev_err(&client->dev, "failed to start streaming"); 752 753 return ret; 754 } 755 756 static void ov2740_stop_streaming(struct ov2740 *ov2740) 757 { 758 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 759 760 if (ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1, 761 OV2740_MODE_STANDBY)) 762 dev_err(&client->dev, "failed to stop streaming"); 763 } 764 765 static int ov2740_set_stream(struct v4l2_subdev *sd, int enable) 766 { 767 struct ov2740 *ov2740 = to_ov2740(sd); 768 struct i2c_client *client = v4l2_get_subdevdata(sd); 769 int ret = 0; 770 771 if (ov2740->streaming == enable) 772 return 0; 773 774 mutex_lock(&ov2740->mutex); 775 if (enable) { 776 ret = pm_runtime_resume_and_get(&client->dev); 777 if (ret < 0) { 778 mutex_unlock(&ov2740->mutex); 779 return ret; 780 } 781 782 ret = ov2740_start_streaming(ov2740); 783 if (ret) { 784 enable = 0; 785 ov2740_stop_streaming(ov2740); 786 pm_runtime_put(&client->dev); 787 } 788 } else { 789 ov2740_stop_streaming(ov2740); 790 pm_runtime_put(&client->dev); 791 } 792 793 ov2740->streaming = enable; 794 mutex_unlock(&ov2740->mutex); 795 796 return ret; 797 } 798 799 static int __maybe_unused ov2740_suspend(struct device *dev) 800 { 801 struct v4l2_subdev *sd = dev_get_drvdata(dev); 802 struct ov2740 *ov2740 = to_ov2740(sd); 803 804 mutex_lock(&ov2740->mutex); 805 if (ov2740->streaming) 806 ov2740_stop_streaming(ov2740); 807 808 mutex_unlock(&ov2740->mutex); 809 810 return 0; 811 } 812 813 static int __maybe_unused ov2740_resume(struct device *dev) 814 { 815 struct v4l2_subdev *sd = dev_get_drvdata(dev); 816 struct ov2740 *ov2740 = to_ov2740(sd); 817 int ret = 0; 818 819 mutex_lock(&ov2740->mutex); 820 if (!ov2740->streaming) 821 goto exit; 822 823 ret = ov2740_start_streaming(ov2740); 824 if (ret) { 825 ov2740->streaming = false; 826 ov2740_stop_streaming(ov2740); 827 } 828 829 exit: 830 mutex_unlock(&ov2740->mutex); 831 return ret; 832 } 833 834 static int ov2740_set_format(struct v4l2_subdev *sd, 835 struct v4l2_subdev_state *sd_state, 836 struct v4l2_subdev_format *fmt) 837 { 838 struct ov2740 *ov2740 = to_ov2740(sd); 839 const struct ov2740_mode *mode; 840 s32 vblank_def, h_blank; 841 842 mode = v4l2_find_nearest_size(supported_modes, 843 ARRAY_SIZE(supported_modes), width, 844 height, fmt->format.width, 845 fmt->format.height); 846 847 mutex_lock(&ov2740->mutex); 848 ov2740_update_pad_format(mode, &fmt->format); 849 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 850 *v4l2_subdev_get_try_format(sd, sd_state, fmt->pad) = fmt->format; 851 } else { 852 ov2740->cur_mode = mode; 853 __v4l2_ctrl_s_ctrl(ov2740->link_freq, mode->link_freq_index); 854 __v4l2_ctrl_s_ctrl_int64(ov2740->pixel_rate, 855 to_pixel_rate(mode->link_freq_index)); 856 857 /* Update limits and set FPS to default */ 858 vblank_def = mode->vts_def - mode->height; 859 __v4l2_ctrl_modify_range(ov2740->vblank, 860 mode->vts_min - mode->height, 861 OV2740_VTS_MAX - mode->height, 1, 862 vblank_def); 863 __v4l2_ctrl_s_ctrl(ov2740->vblank, vblank_def); 864 h_blank = to_pixels_per_line(mode->hts, mode->link_freq_index) - 865 mode->width; 866 __v4l2_ctrl_modify_range(ov2740->hblank, h_blank, h_blank, 1, 867 h_blank); 868 } 869 mutex_unlock(&ov2740->mutex); 870 871 return 0; 872 } 873 874 static int ov2740_get_format(struct v4l2_subdev *sd, 875 struct v4l2_subdev_state *sd_state, 876 struct v4l2_subdev_format *fmt) 877 { 878 struct ov2740 *ov2740 = to_ov2740(sd); 879 880 mutex_lock(&ov2740->mutex); 881 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) 882 fmt->format = *v4l2_subdev_get_try_format(&ov2740->sd, 883 sd_state, 884 fmt->pad); 885 else 886 ov2740_update_pad_format(ov2740->cur_mode, &fmt->format); 887 888 mutex_unlock(&ov2740->mutex); 889 890 return 0; 891 } 892 893 static int ov2740_enum_mbus_code(struct v4l2_subdev *sd, 894 struct v4l2_subdev_state *sd_state, 895 struct v4l2_subdev_mbus_code_enum *code) 896 { 897 if (code->index > 0) 898 return -EINVAL; 899 900 code->code = MEDIA_BUS_FMT_SGRBG10_1X10; 901 902 return 0; 903 } 904 905 static int ov2740_enum_frame_size(struct v4l2_subdev *sd, 906 struct v4l2_subdev_state *sd_state, 907 struct v4l2_subdev_frame_size_enum *fse) 908 { 909 if (fse->index >= ARRAY_SIZE(supported_modes)) 910 return -EINVAL; 911 912 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10) 913 return -EINVAL; 914 915 fse->min_width = supported_modes[fse->index].width; 916 fse->max_width = fse->min_width; 917 fse->min_height = supported_modes[fse->index].height; 918 fse->max_height = fse->min_height; 919 920 return 0; 921 } 922 923 static int ov2740_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) 924 { 925 struct ov2740 *ov2740 = to_ov2740(sd); 926 927 mutex_lock(&ov2740->mutex); 928 ov2740_update_pad_format(&supported_modes[0], 929 v4l2_subdev_get_try_format(sd, fh->state, 0)); 930 mutex_unlock(&ov2740->mutex); 931 932 return 0; 933 } 934 935 static const struct v4l2_subdev_video_ops ov2740_video_ops = { 936 .s_stream = ov2740_set_stream, 937 }; 938 939 static const struct v4l2_subdev_pad_ops ov2740_pad_ops = { 940 .set_fmt = ov2740_set_format, 941 .get_fmt = ov2740_get_format, 942 .enum_mbus_code = ov2740_enum_mbus_code, 943 .enum_frame_size = ov2740_enum_frame_size, 944 }; 945 946 static const struct v4l2_subdev_ops ov2740_subdev_ops = { 947 .video = &ov2740_video_ops, 948 .pad = &ov2740_pad_ops, 949 }; 950 951 static const struct media_entity_operations ov2740_subdev_entity_ops = { 952 .link_validate = v4l2_subdev_link_validate, 953 }; 954 955 static const struct v4l2_subdev_internal_ops ov2740_internal_ops = { 956 .open = ov2740_open, 957 }; 958 959 static int ov2740_identify_module(struct ov2740 *ov2740) 960 { 961 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 962 int ret; 963 u32 val; 964 965 ret = ov2740_read_reg(ov2740, OV2740_REG_CHIP_ID, 3, &val); 966 if (ret) 967 return ret; 968 969 if (val != OV2740_CHIP_ID) { 970 dev_err(&client->dev, "chip id mismatch: %x!=%x", 971 OV2740_CHIP_ID, val); 972 return -ENXIO; 973 } 974 975 return 0; 976 } 977 978 static int ov2740_check_hwcfg(struct device *dev) 979 { 980 struct fwnode_handle *ep; 981 struct fwnode_handle *fwnode = dev_fwnode(dev); 982 struct v4l2_fwnode_endpoint bus_cfg = { 983 .bus_type = V4L2_MBUS_CSI2_DPHY 984 }; 985 u32 mclk; 986 int ret; 987 unsigned int i, j; 988 989 if (!fwnode) 990 return -ENXIO; 991 992 ret = fwnode_property_read_u32(fwnode, "clock-frequency", &mclk); 993 if (ret) 994 return ret; 995 996 if (mclk != OV2740_MCLK) { 997 dev_err(dev, "external clock %d is not supported", mclk); 998 return -EINVAL; 999 } 1000 1001 ep = fwnode_graph_get_next_endpoint(fwnode, NULL); 1002 if (!ep) 1003 return -ENXIO; 1004 1005 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); 1006 fwnode_handle_put(ep); 1007 if (ret) 1008 return ret; 1009 1010 if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV2740_DATA_LANES) { 1011 dev_err(dev, "number of CSI2 data lanes %d is not supported", 1012 bus_cfg.bus.mipi_csi2.num_data_lanes); 1013 ret = -EINVAL; 1014 goto check_hwcfg_error; 1015 } 1016 1017 if (!bus_cfg.nr_of_link_frequencies) { 1018 dev_err(dev, "no link frequencies defined"); 1019 ret = -EINVAL; 1020 goto check_hwcfg_error; 1021 } 1022 1023 for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) { 1024 for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) { 1025 if (link_freq_menu_items[i] == 1026 bus_cfg.link_frequencies[j]) 1027 break; 1028 } 1029 1030 if (j == bus_cfg.nr_of_link_frequencies) { 1031 dev_err(dev, "no link frequency %lld supported", 1032 link_freq_menu_items[i]); 1033 ret = -EINVAL; 1034 goto check_hwcfg_error; 1035 } 1036 } 1037 1038 check_hwcfg_error: 1039 v4l2_fwnode_endpoint_free(&bus_cfg); 1040 1041 return ret; 1042 } 1043 1044 static int ov2740_remove(struct i2c_client *client) 1045 { 1046 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1047 struct ov2740 *ov2740 = to_ov2740(sd); 1048 1049 v4l2_async_unregister_subdev(sd); 1050 media_entity_cleanup(&sd->entity); 1051 v4l2_ctrl_handler_free(sd->ctrl_handler); 1052 pm_runtime_disable(&client->dev); 1053 mutex_destroy(&ov2740->mutex); 1054 1055 return 0; 1056 } 1057 1058 static int ov2740_nvmem_read(void *priv, unsigned int off, void *val, 1059 size_t count) 1060 { 1061 struct nvm_data *nvm = priv; 1062 struct v4l2_subdev *sd = i2c_get_clientdata(nvm->client); 1063 struct device *dev = &nvm->client->dev; 1064 struct ov2740 *ov2740 = to_ov2740(sd); 1065 int ret = 0; 1066 1067 mutex_lock(&ov2740->mutex); 1068 1069 if (nvm->nvm_buffer) { 1070 memcpy(val, nvm->nvm_buffer + off, count); 1071 goto exit; 1072 } 1073 1074 ret = pm_runtime_resume_and_get(dev); 1075 if (ret < 0) { 1076 goto exit; 1077 } 1078 1079 ret = ov2740_load_otp_data(nvm); 1080 if (!ret) 1081 memcpy(val, nvm->nvm_buffer + off, count); 1082 1083 pm_runtime_put(dev); 1084 exit: 1085 mutex_unlock(&ov2740->mutex); 1086 return ret; 1087 } 1088 1089 static int ov2740_register_nvmem(struct i2c_client *client, 1090 struct ov2740 *ov2740) 1091 { 1092 struct nvm_data *nvm; 1093 struct regmap_config regmap_config = { }; 1094 struct nvmem_config nvmem_config = { }; 1095 struct regmap *regmap; 1096 struct device *dev = &client->dev; 1097 int ret; 1098 1099 nvm = devm_kzalloc(dev, sizeof(*nvm), GFP_KERNEL); 1100 if (!nvm) 1101 return -ENOMEM; 1102 1103 regmap_config.val_bits = 8; 1104 regmap_config.reg_bits = 16; 1105 regmap_config.disable_locking = true; 1106 regmap = devm_regmap_init_i2c(client, ®map_config); 1107 if (IS_ERR(regmap)) 1108 return PTR_ERR(regmap); 1109 1110 nvm->regmap = regmap; 1111 nvm->client = client; 1112 1113 nvmem_config.name = dev_name(dev); 1114 nvmem_config.dev = dev; 1115 nvmem_config.read_only = true; 1116 nvmem_config.root_only = true; 1117 nvmem_config.owner = THIS_MODULE; 1118 nvmem_config.compat = true; 1119 nvmem_config.base_dev = dev; 1120 nvmem_config.reg_read = ov2740_nvmem_read; 1121 nvmem_config.reg_write = NULL; 1122 nvmem_config.priv = nvm; 1123 nvmem_config.stride = 1; 1124 nvmem_config.word_size = 1; 1125 nvmem_config.size = CUSTOMER_USE_OTP_SIZE; 1126 1127 nvm->nvmem = devm_nvmem_register(dev, &nvmem_config); 1128 1129 ret = PTR_ERR_OR_ZERO(nvm->nvmem); 1130 if (!ret) 1131 ov2740->nvm = nvm; 1132 1133 return ret; 1134 } 1135 1136 static int ov2740_probe(struct i2c_client *client) 1137 { 1138 struct ov2740 *ov2740; 1139 int ret = 0; 1140 1141 ret = ov2740_check_hwcfg(&client->dev); 1142 if (ret) { 1143 dev_err(&client->dev, "failed to check HW configuration: %d", 1144 ret); 1145 return ret; 1146 } 1147 1148 ov2740 = devm_kzalloc(&client->dev, sizeof(*ov2740), GFP_KERNEL); 1149 if (!ov2740) 1150 return -ENOMEM; 1151 1152 v4l2_i2c_subdev_init(&ov2740->sd, client, &ov2740_subdev_ops); 1153 ret = ov2740_identify_module(ov2740); 1154 if (ret) { 1155 dev_err(&client->dev, "failed to find sensor: %d", ret); 1156 return ret; 1157 } 1158 1159 mutex_init(&ov2740->mutex); 1160 ov2740->cur_mode = &supported_modes[0]; 1161 ret = ov2740_init_controls(ov2740); 1162 if (ret) { 1163 dev_err(&client->dev, "failed to init controls: %d", ret); 1164 goto probe_error_v4l2_ctrl_handler_free; 1165 } 1166 1167 ov2740->sd.internal_ops = &ov2740_internal_ops; 1168 ov2740->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1169 ov2740->sd.entity.ops = &ov2740_subdev_entity_ops; 1170 ov2740->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1171 ov2740->pad.flags = MEDIA_PAD_FL_SOURCE; 1172 ret = media_entity_pads_init(&ov2740->sd.entity, 1, &ov2740->pad); 1173 if (ret) { 1174 dev_err(&client->dev, "failed to init entity pads: %d", ret); 1175 goto probe_error_v4l2_ctrl_handler_free; 1176 } 1177 1178 ret = v4l2_async_register_subdev_sensor(&ov2740->sd); 1179 if (ret < 0) { 1180 dev_err(&client->dev, "failed to register V4L2 subdev: %d", 1181 ret); 1182 goto probe_error_media_entity_cleanup; 1183 } 1184 1185 ret = ov2740_register_nvmem(client, ov2740); 1186 if (ret) 1187 dev_warn(&client->dev, "register nvmem failed, ret %d\n", ret); 1188 1189 /* 1190 * Device is already turned on by i2c-core with ACPI domain PM. 1191 * Enable runtime PM and turn off the device. 1192 */ 1193 pm_runtime_set_active(&client->dev); 1194 pm_runtime_enable(&client->dev); 1195 pm_runtime_idle(&client->dev); 1196 1197 return 0; 1198 1199 probe_error_media_entity_cleanup: 1200 media_entity_cleanup(&ov2740->sd.entity); 1201 1202 probe_error_v4l2_ctrl_handler_free: 1203 v4l2_ctrl_handler_free(ov2740->sd.ctrl_handler); 1204 mutex_destroy(&ov2740->mutex); 1205 1206 return ret; 1207 } 1208 1209 static const struct dev_pm_ops ov2740_pm_ops = { 1210 SET_SYSTEM_SLEEP_PM_OPS(ov2740_suspend, ov2740_resume) 1211 }; 1212 1213 static const struct acpi_device_id ov2740_acpi_ids[] = { 1214 {"INT3474"}, 1215 {} 1216 }; 1217 1218 MODULE_DEVICE_TABLE(acpi, ov2740_acpi_ids); 1219 1220 static struct i2c_driver ov2740_i2c_driver = { 1221 .driver = { 1222 .name = "ov2740", 1223 .pm = &ov2740_pm_ops, 1224 .acpi_match_table = ov2740_acpi_ids, 1225 }, 1226 .probe_new = ov2740_probe, 1227 .remove = ov2740_remove, 1228 }; 1229 1230 module_i2c_driver(ov2740_i2c_driver); 1231 1232 MODULE_AUTHOR("Qiu, Tianshu <tian.shu.qiu@intel.com>"); 1233 MODULE_AUTHOR("Shawn Tu <shawnx.tu@intel.com>"); 1234 MODULE_AUTHOR("Bingbu Cao <bingbu.cao@intel.com>"); 1235 MODULE_DESCRIPTION("OmniVision OV2740 sensor driver"); 1236 MODULE_LICENSE("GPL v2"); 1237