1866edc89SBingbu Cao // SPDX-License-Identifier: GPL-2.0 2866edc89SBingbu Cao // Copyright (c) 2020 Intel Corporation. 3866edc89SBingbu Cao 4866edc89SBingbu Cao #include <asm/unaligned.h> 5866edc89SBingbu Cao #include <linux/acpi.h> 6866edc89SBingbu Cao #include <linux/delay.h> 7866edc89SBingbu Cao #include <linux/i2c.h> 8866edc89SBingbu Cao #include <linux/module.h> 9866edc89SBingbu Cao #include <linux/pm_runtime.h> 107b981288SQingwu Zhang #include <linux/nvmem-provider.h> 117b981288SQingwu Zhang #include <linux/regmap.h> 12866edc89SBingbu Cao #include <media/v4l2-ctrls.h> 13866edc89SBingbu Cao #include <media/v4l2-device.h> 14866edc89SBingbu Cao #include <media/v4l2-fwnode.h> 15866edc89SBingbu Cao 16866edc89SBingbu Cao #define OV2740_LINK_FREQ_360MHZ 360000000ULL 17866edc89SBingbu Cao #define OV2740_SCLK 72000000LL 18866edc89SBingbu Cao #define OV2740_MCLK 19200000 19866edc89SBingbu Cao #define OV2740_DATA_LANES 2 20866edc89SBingbu Cao #define OV2740_RGB_DEPTH 10 21866edc89SBingbu Cao 22866edc89SBingbu Cao #define OV2740_REG_CHIP_ID 0x300a 23866edc89SBingbu Cao #define OV2740_CHIP_ID 0x2740 24866edc89SBingbu Cao 25866edc89SBingbu Cao #define OV2740_REG_MODE_SELECT 0x0100 26866edc89SBingbu Cao #define OV2740_MODE_STANDBY 0x00 27866edc89SBingbu Cao #define OV2740_MODE_STREAMING 0x01 28866edc89SBingbu Cao 29866edc89SBingbu Cao /* vertical-timings from sensor */ 30866edc89SBingbu Cao #define OV2740_REG_VTS 0x380e 31866edc89SBingbu Cao #define OV2740_VTS_DEF 0x088a 32866edc89SBingbu Cao #define OV2740_VTS_MIN 0x0460 33866edc89SBingbu Cao #define OV2740_VTS_MAX 0x7fff 34866edc89SBingbu Cao 35866edc89SBingbu Cao /* horizontal-timings from sensor */ 36866edc89SBingbu Cao #define OV2740_REG_HTS 0x380c 37866edc89SBingbu Cao 38866edc89SBingbu Cao /* Exposure controls from sensor */ 39866edc89SBingbu Cao #define OV2740_REG_EXPOSURE 0x3500 40866edc89SBingbu Cao #define OV2740_EXPOSURE_MIN 8 41866edc89SBingbu Cao #define OV2740_EXPOSURE_MAX_MARGIN 8 42866edc89SBingbu Cao #define OV2740_EXPOSURE_STEP 1 43866edc89SBingbu Cao 44866edc89SBingbu Cao /* Analog gain controls from sensor */ 45866edc89SBingbu Cao #define OV2740_REG_ANALOG_GAIN 0x3508 46866edc89SBingbu Cao #define OV2740_ANAL_GAIN_MIN 128 47866edc89SBingbu Cao #define OV2740_ANAL_GAIN_MAX 1983 48866edc89SBingbu Cao #define OV2740_ANAL_GAIN_STEP 1 49866edc89SBingbu Cao 50866edc89SBingbu Cao /* Digital gain controls from sensor */ 51866edc89SBingbu Cao #define OV2740_REG_MWB_R_GAIN 0x500a 52866edc89SBingbu Cao #define OV2740_REG_MWB_G_GAIN 0x500c 53866edc89SBingbu Cao #define OV2740_REG_MWB_B_GAIN 0x500e 54866edc89SBingbu Cao #define OV2740_DGTL_GAIN_MIN 0 55866edc89SBingbu Cao #define OV2740_DGTL_GAIN_MAX 4095 56866edc89SBingbu Cao #define OV2740_DGTL_GAIN_STEP 1 57866edc89SBingbu Cao #define OV2740_DGTL_GAIN_DEFAULT 1024 58866edc89SBingbu Cao 59866edc89SBingbu Cao /* Test Pattern Control */ 60866edc89SBingbu Cao #define OV2740_REG_TEST_PATTERN 0x5040 61866edc89SBingbu Cao #define OV2740_TEST_PATTERN_ENABLE BIT(7) 62866edc89SBingbu Cao #define OV2740_TEST_PATTERN_BAR_SHIFT 2 63866edc89SBingbu Cao 647b981288SQingwu Zhang /* ISP CTRL00 */ 657b981288SQingwu Zhang #define OV2740_REG_ISP_CTRL00 0x5000 667b981288SQingwu Zhang /* ISP CTRL01 */ 677b981288SQingwu Zhang #define OV2740_REG_ISP_CTRL01 0x5001 687b981288SQingwu Zhang /* Customer Addresses: 0x7010 - 0x710F */ 697b981288SQingwu Zhang #define CUSTOMER_USE_OTP_SIZE 0x100 707b981288SQingwu Zhang /* OTP registers from sensor */ 717b981288SQingwu Zhang #define OV2740_REG_OTP_CUSTOMER 0x7010 727b981288SQingwu Zhang 737b981288SQingwu Zhang struct nvm_data { 747b981288SQingwu Zhang char *nvm_buffer; 757b981288SQingwu Zhang struct nvmem_device *nvmem; 767b981288SQingwu Zhang struct regmap *regmap; 777b981288SQingwu Zhang }; 787b981288SQingwu Zhang 79866edc89SBingbu Cao enum { 80866edc89SBingbu Cao OV2740_LINK_FREQ_360MHZ_INDEX, 81866edc89SBingbu Cao }; 82866edc89SBingbu Cao 83866edc89SBingbu Cao struct ov2740_reg { 84866edc89SBingbu Cao u16 address; 85866edc89SBingbu Cao u8 val; 86866edc89SBingbu Cao }; 87866edc89SBingbu Cao 88866edc89SBingbu Cao struct ov2740_reg_list { 89866edc89SBingbu Cao u32 num_of_regs; 90866edc89SBingbu Cao const struct ov2740_reg *regs; 91866edc89SBingbu Cao }; 92866edc89SBingbu Cao 93866edc89SBingbu Cao struct ov2740_link_freq_config { 94866edc89SBingbu Cao const struct ov2740_reg_list reg_list; 95866edc89SBingbu Cao }; 96866edc89SBingbu Cao 97866edc89SBingbu Cao struct ov2740_mode { 98866edc89SBingbu Cao /* Frame width in pixels */ 99866edc89SBingbu Cao u32 width; 100866edc89SBingbu Cao 101866edc89SBingbu Cao /* Frame height in pixels */ 102866edc89SBingbu Cao u32 height; 103866edc89SBingbu Cao 104866edc89SBingbu Cao /* Horizontal timining size */ 105866edc89SBingbu Cao u32 hts; 106866edc89SBingbu Cao 107866edc89SBingbu Cao /* Default vertical timining size */ 108866edc89SBingbu Cao u32 vts_def; 109866edc89SBingbu Cao 110866edc89SBingbu Cao /* Min vertical timining size */ 111866edc89SBingbu Cao u32 vts_min; 112866edc89SBingbu Cao 113866edc89SBingbu Cao /* Link frequency needed for this resolution */ 114866edc89SBingbu Cao u32 link_freq_index; 115866edc89SBingbu Cao 116866edc89SBingbu Cao /* Sensor register settings for this resolution */ 117866edc89SBingbu Cao const struct ov2740_reg_list reg_list; 118866edc89SBingbu Cao }; 119866edc89SBingbu Cao 120866edc89SBingbu Cao static const struct ov2740_reg mipi_data_rate_720mbps[] = { 121866edc89SBingbu Cao {0x0103, 0x01}, 122866edc89SBingbu Cao {0x0302, 0x4b}, 123866edc89SBingbu Cao {0x030d, 0x4b}, 124866edc89SBingbu Cao {0x030e, 0x02}, 125866edc89SBingbu Cao {0x030a, 0x01}, 126866edc89SBingbu Cao {0x0312, 0x11}, 127866edc89SBingbu Cao }; 128866edc89SBingbu Cao 129866edc89SBingbu Cao static const struct ov2740_reg mode_1932x1092_regs[] = { 130866edc89SBingbu Cao {0x3000, 0x00}, 131866edc89SBingbu Cao {0x3018, 0x32}, 132866edc89SBingbu Cao {0x3031, 0x0a}, 133866edc89SBingbu Cao {0x3080, 0x08}, 134866edc89SBingbu Cao {0x3083, 0xB4}, 135866edc89SBingbu Cao {0x3103, 0x00}, 136866edc89SBingbu Cao {0x3104, 0x01}, 137866edc89SBingbu Cao {0x3106, 0x01}, 138866edc89SBingbu Cao {0x3500, 0x00}, 139866edc89SBingbu Cao {0x3501, 0x44}, 140866edc89SBingbu Cao {0x3502, 0x40}, 141866edc89SBingbu Cao {0x3503, 0x88}, 142866edc89SBingbu Cao {0x3507, 0x00}, 143866edc89SBingbu Cao {0x3508, 0x00}, 144866edc89SBingbu Cao {0x3509, 0x80}, 145866edc89SBingbu Cao {0x350c, 0x00}, 146866edc89SBingbu Cao {0x350d, 0x80}, 147866edc89SBingbu Cao {0x3510, 0x00}, 148866edc89SBingbu Cao {0x3511, 0x00}, 149866edc89SBingbu Cao {0x3512, 0x20}, 150866edc89SBingbu Cao {0x3632, 0x00}, 151866edc89SBingbu Cao {0x3633, 0x10}, 152866edc89SBingbu Cao {0x3634, 0x10}, 153866edc89SBingbu Cao {0x3635, 0x10}, 154866edc89SBingbu Cao {0x3645, 0x13}, 155866edc89SBingbu Cao {0x3646, 0x81}, 156866edc89SBingbu Cao {0x3636, 0x10}, 157866edc89SBingbu Cao {0x3651, 0x0a}, 158866edc89SBingbu Cao {0x3656, 0x02}, 159866edc89SBingbu Cao {0x3659, 0x04}, 160866edc89SBingbu Cao {0x365a, 0xda}, 161866edc89SBingbu Cao {0x365b, 0xa2}, 162866edc89SBingbu Cao {0x365c, 0x04}, 163866edc89SBingbu Cao {0x365d, 0x1d}, 164866edc89SBingbu Cao {0x365e, 0x1a}, 165866edc89SBingbu Cao {0x3662, 0xd7}, 166866edc89SBingbu Cao {0x3667, 0x78}, 167866edc89SBingbu Cao {0x3669, 0x0a}, 168866edc89SBingbu Cao {0x366a, 0x92}, 169866edc89SBingbu Cao {0x3700, 0x54}, 170866edc89SBingbu Cao {0x3702, 0x10}, 171866edc89SBingbu Cao {0x3706, 0x42}, 172866edc89SBingbu Cao {0x3709, 0x30}, 173866edc89SBingbu Cao {0x370b, 0xc2}, 174866edc89SBingbu Cao {0x3714, 0x63}, 175866edc89SBingbu Cao {0x3715, 0x01}, 176866edc89SBingbu Cao {0x3716, 0x00}, 177866edc89SBingbu Cao {0x371a, 0x3e}, 178866edc89SBingbu Cao {0x3732, 0x0e}, 179866edc89SBingbu Cao {0x3733, 0x10}, 180866edc89SBingbu Cao {0x375f, 0x0e}, 181866edc89SBingbu Cao {0x3768, 0x30}, 182866edc89SBingbu Cao {0x3769, 0x44}, 183866edc89SBingbu Cao {0x376a, 0x22}, 184866edc89SBingbu Cao {0x377b, 0x20}, 185866edc89SBingbu Cao {0x377c, 0x00}, 186866edc89SBingbu Cao {0x377d, 0x0c}, 187866edc89SBingbu Cao {0x3798, 0x00}, 188866edc89SBingbu Cao {0x37a1, 0x55}, 189866edc89SBingbu Cao {0x37a8, 0x6d}, 190866edc89SBingbu Cao {0x37c2, 0x04}, 191866edc89SBingbu Cao {0x37c5, 0x00}, 192866edc89SBingbu Cao {0x37c8, 0x00}, 193866edc89SBingbu Cao {0x3800, 0x00}, 194866edc89SBingbu Cao {0x3801, 0x00}, 195866edc89SBingbu Cao {0x3802, 0x00}, 196866edc89SBingbu Cao {0x3803, 0x00}, 197866edc89SBingbu Cao {0x3804, 0x07}, 198866edc89SBingbu Cao {0x3805, 0x8f}, 199866edc89SBingbu Cao {0x3806, 0x04}, 200866edc89SBingbu Cao {0x3807, 0x47}, 201866edc89SBingbu Cao {0x3808, 0x07}, 202866edc89SBingbu Cao {0x3809, 0x88}, 203866edc89SBingbu Cao {0x380a, 0x04}, 204866edc89SBingbu Cao {0x380b, 0x40}, 205866edc89SBingbu Cao {0x380c, 0x04}, 206866edc89SBingbu Cao {0x380d, 0x38}, 207866edc89SBingbu Cao {0x380e, 0x04}, 208866edc89SBingbu Cao {0x380f, 0x60}, 209866edc89SBingbu Cao {0x3810, 0x00}, 210866edc89SBingbu Cao {0x3811, 0x04}, 211866edc89SBingbu Cao {0x3812, 0x00}, 212866edc89SBingbu Cao {0x3813, 0x04}, 213866edc89SBingbu Cao {0x3814, 0x01}, 214866edc89SBingbu Cao {0x3815, 0x01}, 215866edc89SBingbu Cao {0x3820, 0x80}, 216866edc89SBingbu Cao {0x3821, 0x46}, 217866edc89SBingbu Cao {0x3822, 0x84}, 218866edc89SBingbu Cao {0x3829, 0x00}, 219866edc89SBingbu Cao {0x382a, 0x01}, 220866edc89SBingbu Cao {0x382b, 0x01}, 221866edc89SBingbu Cao {0x3830, 0x04}, 222866edc89SBingbu Cao {0x3836, 0x01}, 223866edc89SBingbu Cao {0x3837, 0x08}, 224866edc89SBingbu Cao {0x3839, 0x01}, 225866edc89SBingbu Cao {0x383a, 0x00}, 226866edc89SBingbu Cao {0x383b, 0x08}, 227866edc89SBingbu Cao {0x383c, 0x00}, 228866edc89SBingbu Cao {0x3f0b, 0x00}, 229866edc89SBingbu Cao {0x4001, 0x20}, 230866edc89SBingbu Cao {0x4009, 0x07}, 231866edc89SBingbu Cao {0x4003, 0x10}, 232866edc89SBingbu Cao {0x4010, 0xe0}, 233866edc89SBingbu Cao {0x4016, 0x00}, 234866edc89SBingbu Cao {0x4017, 0x10}, 235866edc89SBingbu Cao {0x4044, 0x02}, 236866edc89SBingbu Cao {0x4304, 0x08}, 237866edc89SBingbu Cao {0x4307, 0x30}, 238866edc89SBingbu Cao {0x4320, 0x80}, 239866edc89SBingbu Cao {0x4322, 0x00}, 240866edc89SBingbu Cao {0x4323, 0x00}, 241866edc89SBingbu Cao {0x4324, 0x00}, 242866edc89SBingbu Cao {0x4325, 0x00}, 243866edc89SBingbu Cao {0x4326, 0x00}, 244866edc89SBingbu Cao {0x4327, 0x00}, 245866edc89SBingbu Cao {0x4328, 0x00}, 246866edc89SBingbu Cao {0x4329, 0x00}, 247866edc89SBingbu Cao {0x432c, 0x03}, 248866edc89SBingbu Cao {0x432d, 0x81}, 249866edc89SBingbu Cao {0x4501, 0x84}, 250866edc89SBingbu Cao {0x4502, 0x40}, 251866edc89SBingbu Cao {0x4503, 0x18}, 252866edc89SBingbu Cao {0x4504, 0x04}, 253866edc89SBingbu Cao {0x4508, 0x02}, 254866edc89SBingbu Cao {0x4601, 0x10}, 255866edc89SBingbu Cao {0x4800, 0x00}, 256866edc89SBingbu Cao {0x4816, 0x52}, 257866edc89SBingbu Cao {0x4837, 0x16}, 258866edc89SBingbu Cao {0x5000, 0x7f}, 259866edc89SBingbu Cao {0x5001, 0x00}, 260866edc89SBingbu Cao {0x5005, 0x38}, 261866edc89SBingbu Cao {0x501e, 0x0d}, 262866edc89SBingbu Cao {0x5040, 0x00}, 263866edc89SBingbu Cao {0x5901, 0x00}, 264866edc89SBingbu Cao {0x3800, 0x00}, 265866edc89SBingbu Cao {0x3801, 0x00}, 266866edc89SBingbu Cao {0x3802, 0x00}, 267866edc89SBingbu Cao {0x3803, 0x00}, 268866edc89SBingbu Cao {0x3804, 0x07}, 269866edc89SBingbu Cao {0x3805, 0x8f}, 270866edc89SBingbu Cao {0x3806, 0x04}, 271866edc89SBingbu Cao {0x3807, 0x47}, 272866edc89SBingbu Cao {0x3808, 0x07}, 273866edc89SBingbu Cao {0x3809, 0x8c}, 274866edc89SBingbu Cao {0x380a, 0x04}, 275866edc89SBingbu Cao {0x380b, 0x44}, 276866edc89SBingbu Cao {0x3810, 0x00}, 277866edc89SBingbu Cao {0x3811, 0x00}, 278866edc89SBingbu Cao {0x3812, 0x00}, 279866edc89SBingbu Cao {0x3813, 0x01}, 280866edc89SBingbu Cao }; 281866edc89SBingbu Cao 282866edc89SBingbu Cao static const char * const ov2740_test_pattern_menu[] = { 283866edc89SBingbu Cao "Disabled", 284866edc89SBingbu Cao "Color Bar", 285866edc89SBingbu Cao "Top-Bottom Darker Color Bar", 286866edc89SBingbu Cao "Right-Left Darker Color Bar", 287866edc89SBingbu Cao "Bottom-Top Darker Color Bar", 288866edc89SBingbu Cao }; 289866edc89SBingbu Cao 290866edc89SBingbu Cao static const s64 link_freq_menu_items[] = { 291866edc89SBingbu Cao OV2740_LINK_FREQ_360MHZ, 292866edc89SBingbu Cao }; 293866edc89SBingbu Cao 294866edc89SBingbu Cao static const struct ov2740_link_freq_config link_freq_configs[] = { 295866edc89SBingbu Cao [OV2740_LINK_FREQ_360MHZ_INDEX] = { 296866edc89SBingbu Cao .reg_list = { 297866edc89SBingbu Cao .num_of_regs = ARRAY_SIZE(mipi_data_rate_720mbps), 298866edc89SBingbu Cao .regs = mipi_data_rate_720mbps, 299866edc89SBingbu Cao } 300866edc89SBingbu Cao }, 301866edc89SBingbu Cao }; 302866edc89SBingbu Cao 303866edc89SBingbu Cao static const struct ov2740_mode supported_modes[] = { 304866edc89SBingbu Cao { 305866edc89SBingbu Cao .width = 1932, 306866edc89SBingbu Cao .height = 1092, 307866edc89SBingbu Cao .hts = 1080, 308866edc89SBingbu Cao .vts_def = OV2740_VTS_DEF, 309866edc89SBingbu Cao .vts_min = OV2740_VTS_MIN, 310866edc89SBingbu Cao .reg_list = { 311866edc89SBingbu Cao .num_of_regs = ARRAY_SIZE(mode_1932x1092_regs), 312866edc89SBingbu Cao .regs = mode_1932x1092_regs, 313866edc89SBingbu Cao }, 314866edc89SBingbu Cao .link_freq_index = OV2740_LINK_FREQ_360MHZ_INDEX, 315866edc89SBingbu Cao }, 316866edc89SBingbu Cao }; 317866edc89SBingbu Cao 318866edc89SBingbu Cao struct ov2740 { 319866edc89SBingbu Cao struct v4l2_subdev sd; 320866edc89SBingbu Cao struct media_pad pad; 321866edc89SBingbu Cao struct v4l2_ctrl_handler ctrl_handler; 322866edc89SBingbu Cao 323866edc89SBingbu Cao /* V4L2 Controls */ 324866edc89SBingbu Cao struct v4l2_ctrl *link_freq; 325866edc89SBingbu Cao struct v4l2_ctrl *pixel_rate; 326866edc89SBingbu Cao struct v4l2_ctrl *vblank; 327866edc89SBingbu Cao struct v4l2_ctrl *hblank; 328866edc89SBingbu Cao struct v4l2_ctrl *exposure; 329866edc89SBingbu Cao 330866edc89SBingbu Cao /* Current mode */ 331866edc89SBingbu Cao const struct ov2740_mode *cur_mode; 332866edc89SBingbu Cao 333866edc89SBingbu Cao /* To serialize asynchronus callbacks */ 334866edc89SBingbu Cao struct mutex mutex; 335866edc89SBingbu Cao 336866edc89SBingbu Cao /* Streaming on/off */ 337866edc89SBingbu Cao bool streaming; 338866edc89SBingbu Cao }; 339866edc89SBingbu Cao 340866edc89SBingbu Cao static inline struct ov2740 *to_ov2740(struct v4l2_subdev *subdev) 341866edc89SBingbu Cao { 342866edc89SBingbu Cao return container_of(subdev, struct ov2740, sd); 343866edc89SBingbu Cao } 344866edc89SBingbu Cao 345866edc89SBingbu Cao static u64 to_pixel_rate(u32 f_index) 346866edc89SBingbu Cao { 347866edc89SBingbu Cao u64 pixel_rate = link_freq_menu_items[f_index] * 2 * OV2740_DATA_LANES; 348866edc89SBingbu Cao 349866edc89SBingbu Cao do_div(pixel_rate, OV2740_RGB_DEPTH); 350866edc89SBingbu Cao 351866edc89SBingbu Cao return pixel_rate; 352866edc89SBingbu Cao } 353866edc89SBingbu Cao 354866edc89SBingbu Cao static u64 to_pixels_per_line(u32 hts, u32 f_index) 355866edc89SBingbu Cao { 356866edc89SBingbu Cao u64 ppl = hts * to_pixel_rate(f_index); 357866edc89SBingbu Cao 358866edc89SBingbu Cao do_div(ppl, OV2740_SCLK); 359866edc89SBingbu Cao 360866edc89SBingbu Cao return ppl; 361866edc89SBingbu Cao } 362866edc89SBingbu Cao 363866edc89SBingbu Cao static int ov2740_read_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 *val) 364866edc89SBingbu Cao { 365866edc89SBingbu Cao struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 366866edc89SBingbu Cao struct i2c_msg msgs[2]; 367866edc89SBingbu Cao u8 addr_buf[2]; 368866edc89SBingbu Cao u8 data_buf[4] = {0}; 369866edc89SBingbu Cao int ret = 0; 370866edc89SBingbu Cao 371866edc89SBingbu Cao if (len > sizeof(data_buf)) 372866edc89SBingbu Cao return -EINVAL; 373866edc89SBingbu Cao 374866edc89SBingbu Cao put_unaligned_be16(reg, addr_buf); 375866edc89SBingbu Cao msgs[0].addr = client->addr; 376866edc89SBingbu Cao msgs[0].flags = 0; 377866edc89SBingbu Cao msgs[0].len = sizeof(addr_buf); 378866edc89SBingbu Cao msgs[0].buf = addr_buf; 379866edc89SBingbu Cao msgs[1].addr = client->addr; 380866edc89SBingbu Cao msgs[1].flags = I2C_M_RD; 381866edc89SBingbu Cao msgs[1].len = len; 382866edc89SBingbu Cao msgs[1].buf = &data_buf[sizeof(data_buf) - len]; 383866edc89SBingbu Cao 384866edc89SBingbu Cao ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); 385866edc89SBingbu Cao if (ret != ARRAY_SIZE(msgs)) 386866edc89SBingbu Cao return ret < 0 ? ret : -EIO; 387866edc89SBingbu Cao 388866edc89SBingbu Cao *val = get_unaligned_be32(data_buf); 389866edc89SBingbu Cao 390866edc89SBingbu Cao return 0; 391866edc89SBingbu Cao } 392866edc89SBingbu Cao 393866edc89SBingbu Cao static int ov2740_write_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 val) 394866edc89SBingbu Cao { 395866edc89SBingbu Cao struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 396866edc89SBingbu Cao u8 buf[6]; 397866edc89SBingbu Cao int ret = 0; 398866edc89SBingbu Cao 399866edc89SBingbu Cao if (len > 4) 400866edc89SBingbu Cao return -EINVAL; 401866edc89SBingbu Cao 402866edc89SBingbu Cao put_unaligned_be16(reg, buf); 403866edc89SBingbu Cao put_unaligned_be32(val << 8 * (4 - len), buf + 2); 404866edc89SBingbu Cao 405866edc89SBingbu Cao ret = i2c_master_send(client, buf, len + 2); 406866edc89SBingbu Cao if (ret != len + 2) 407866edc89SBingbu Cao return ret < 0 ? ret : -EIO; 408866edc89SBingbu Cao 409866edc89SBingbu Cao return 0; 410866edc89SBingbu Cao } 411866edc89SBingbu Cao 412866edc89SBingbu Cao static int ov2740_write_reg_list(struct ov2740 *ov2740, 413866edc89SBingbu Cao const struct ov2740_reg_list *r_list) 414866edc89SBingbu Cao { 415866edc89SBingbu Cao struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 416866edc89SBingbu Cao unsigned int i; 417866edc89SBingbu Cao int ret = 0; 418866edc89SBingbu Cao 419866edc89SBingbu Cao for (i = 0; i < r_list->num_of_regs; i++) { 420866edc89SBingbu Cao ret = ov2740_write_reg(ov2740, r_list->regs[i].address, 1, 421866edc89SBingbu Cao r_list->regs[i].val); 422866edc89SBingbu Cao if (ret) { 423866edc89SBingbu Cao dev_err_ratelimited(&client->dev, 424866edc89SBingbu Cao "write reg 0x%4.4x return err = %d", 425866edc89SBingbu Cao r_list->regs[i].address, ret); 426866edc89SBingbu Cao return ret; 427866edc89SBingbu Cao } 428866edc89SBingbu Cao } 429866edc89SBingbu Cao 430866edc89SBingbu Cao return 0; 431866edc89SBingbu Cao } 432866edc89SBingbu Cao 433866edc89SBingbu Cao static int ov2740_update_digital_gain(struct ov2740 *ov2740, u32 d_gain) 434866edc89SBingbu Cao { 435866edc89SBingbu Cao int ret = 0; 436866edc89SBingbu Cao 437866edc89SBingbu Cao ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_R_GAIN, 2, d_gain); 438866edc89SBingbu Cao if (ret) 439866edc89SBingbu Cao return ret; 440866edc89SBingbu Cao 441866edc89SBingbu Cao ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_G_GAIN, 2, d_gain); 442866edc89SBingbu Cao if (ret) 443866edc89SBingbu Cao return ret; 444866edc89SBingbu Cao 445866edc89SBingbu Cao return ov2740_write_reg(ov2740, OV2740_REG_MWB_B_GAIN, 2, d_gain); 446866edc89SBingbu Cao } 447866edc89SBingbu Cao 448866edc89SBingbu Cao static int ov2740_test_pattern(struct ov2740 *ov2740, u32 pattern) 449866edc89SBingbu Cao { 450866edc89SBingbu Cao if (pattern) 451866edc89SBingbu Cao pattern = (pattern - 1) << OV2740_TEST_PATTERN_BAR_SHIFT | 452866edc89SBingbu Cao OV2740_TEST_PATTERN_ENABLE; 453866edc89SBingbu Cao 454866edc89SBingbu Cao return ov2740_write_reg(ov2740, OV2740_REG_TEST_PATTERN, 1, pattern); 455866edc89SBingbu Cao } 456866edc89SBingbu Cao 457866edc89SBingbu Cao static int ov2740_set_ctrl(struct v4l2_ctrl *ctrl) 458866edc89SBingbu Cao { 459866edc89SBingbu Cao struct ov2740 *ov2740 = container_of(ctrl->handler, 460866edc89SBingbu Cao struct ov2740, ctrl_handler); 461866edc89SBingbu Cao struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 462866edc89SBingbu Cao s64 exposure_max; 463866edc89SBingbu Cao int ret = 0; 464866edc89SBingbu Cao 465866edc89SBingbu Cao /* Propagate change of current control to all related controls */ 466866edc89SBingbu Cao if (ctrl->id == V4L2_CID_VBLANK) { 467866edc89SBingbu Cao /* Update max exposure while meeting expected vblanking */ 468866edc89SBingbu Cao exposure_max = ov2740->cur_mode->height + ctrl->val - 469866edc89SBingbu Cao OV2740_EXPOSURE_MAX_MARGIN; 470866edc89SBingbu Cao __v4l2_ctrl_modify_range(ov2740->exposure, 471866edc89SBingbu Cao ov2740->exposure->minimum, 472866edc89SBingbu Cao exposure_max, ov2740->exposure->step, 473866edc89SBingbu Cao exposure_max); 474866edc89SBingbu Cao } 475866edc89SBingbu Cao 476866edc89SBingbu Cao /* V4L2 controls values will be applied only when power is already up */ 477866edc89SBingbu Cao if (!pm_runtime_get_if_in_use(&client->dev)) 478866edc89SBingbu Cao return 0; 479866edc89SBingbu Cao 480866edc89SBingbu Cao switch (ctrl->id) { 481866edc89SBingbu Cao case V4L2_CID_ANALOGUE_GAIN: 482866edc89SBingbu Cao ret = ov2740_write_reg(ov2740, OV2740_REG_ANALOG_GAIN, 2, 483866edc89SBingbu Cao ctrl->val); 484866edc89SBingbu Cao break; 485866edc89SBingbu Cao 486866edc89SBingbu Cao case V4L2_CID_DIGITAL_GAIN: 487866edc89SBingbu Cao ret = ov2740_update_digital_gain(ov2740, ctrl->val); 488866edc89SBingbu Cao break; 489866edc89SBingbu Cao 490866edc89SBingbu Cao case V4L2_CID_EXPOSURE: 491866edc89SBingbu Cao /* 4 least significant bits of expsoure are fractional part */ 492866edc89SBingbu Cao ret = ov2740_write_reg(ov2740, OV2740_REG_EXPOSURE, 3, 493866edc89SBingbu Cao ctrl->val << 4); 494866edc89SBingbu Cao break; 495866edc89SBingbu Cao 496866edc89SBingbu Cao case V4L2_CID_VBLANK: 497866edc89SBingbu Cao ret = ov2740_write_reg(ov2740, OV2740_REG_VTS, 2, 498866edc89SBingbu Cao ov2740->cur_mode->height + ctrl->val); 499866edc89SBingbu Cao break; 500866edc89SBingbu Cao 501866edc89SBingbu Cao case V4L2_CID_TEST_PATTERN: 502866edc89SBingbu Cao ret = ov2740_test_pattern(ov2740, ctrl->val); 503866edc89SBingbu Cao break; 504866edc89SBingbu Cao 505866edc89SBingbu Cao default: 506866edc89SBingbu Cao ret = -EINVAL; 507866edc89SBingbu Cao break; 508866edc89SBingbu Cao } 509866edc89SBingbu Cao 510866edc89SBingbu Cao pm_runtime_put(&client->dev); 511866edc89SBingbu Cao 512866edc89SBingbu Cao return ret; 513866edc89SBingbu Cao } 514866edc89SBingbu Cao 515866edc89SBingbu Cao static const struct v4l2_ctrl_ops ov2740_ctrl_ops = { 516866edc89SBingbu Cao .s_ctrl = ov2740_set_ctrl, 517866edc89SBingbu Cao }; 518866edc89SBingbu Cao 519866edc89SBingbu Cao static int ov2740_init_controls(struct ov2740 *ov2740) 520866edc89SBingbu Cao { 521866edc89SBingbu Cao struct v4l2_ctrl_handler *ctrl_hdlr; 522866edc89SBingbu Cao const struct ov2740_mode *cur_mode; 523866edc89SBingbu Cao s64 exposure_max, h_blank, pixel_rate; 524866edc89SBingbu Cao u32 vblank_min, vblank_max, vblank_default; 525866edc89SBingbu Cao int size; 526866edc89SBingbu Cao int ret = 0; 527866edc89SBingbu Cao 528866edc89SBingbu Cao ctrl_hdlr = &ov2740->ctrl_handler; 529866edc89SBingbu Cao ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8); 530866edc89SBingbu Cao if (ret) 531866edc89SBingbu Cao return ret; 532866edc89SBingbu Cao 533866edc89SBingbu Cao ctrl_hdlr->lock = &ov2740->mutex; 534866edc89SBingbu Cao cur_mode = ov2740->cur_mode; 535866edc89SBingbu Cao size = ARRAY_SIZE(link_freq_menu_items); 536866edc89SBingbu Cao 537866edc89SBingbu Cao ov2740->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &ov2740_ctrl_ops, 538866edc89SBingbu Cao V4L2_CID_LINK_FREQ, 539866edc89SBingbu Cao size - 1, 0, 540866edc89SBingbu Cao link_freq_menu_items); 541866edc89SBingbu Cao if (ov2740->link_freq) 542866edc89SBingbu Cao ov2740->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 543866edc89SBingbu Cao 544866edc89SBingbu Cao pixel_rate = to_pixel_rate(OV2740_LINK_FREQ_360MHZ_INDEX); 545866edc89SBingbu Cao ov2740->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, 546866edc89SBingbu Cao V4L2_CID_PIXEL_RATE, 0, 547866edc89SBingbu Cao pixel_rate, 1, pixel_rate); 548866edc89SBingbu Cao 549866edc89SBingbu Cao vblank_min = cur_mode->vts_min - cur_mode->height; 550866edc89SBingbu Cao vblank_max = OV2740_VTS_MAX - cur_mode->height; 551866edc89SBingbu Cao vblank_default = cur_mode->vts_def - cur_mode->height; 552866edc89SBingbu Cao ov2740->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, 553866edc89SBingbu Cao V4L2_CID_VBLANK, vblank_min, 554866edc89SBingbu Cao vblank_max, 1, vblank_default); 555866edc89SBingbu Cao 556866edc89SBingbu Cao h_blank = to_pixels_per_line(cur_mode->hts, cur_mode->link_freq_index); 557866edc89SBingbu Cao h_blank -= cur_mode->width; 558866edc89SBingbu Cao ov2740->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, 559866edc89SBingbu Cao V4L2_CID_HBLANK, h_blank, h_blank, 1, 560866edc89SBingbu Cao h_blank); 561866edc89SBingbu Cao if (ov2740->hblank) 562866edc89SBingbu Cao ov2740->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 563866edc89SBingbu Cao 564866edc89SBingbu Cao v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, 565866edc89SBingbu Cao OV2740_ANAL_GAIN_MIN, OV2740_ANAL_GAIN_MAX, 566866edc89SBingbu Cao OV2740_ANAL_GAIN_STEP, OV2740_ANAL_GAIN_MIN); 567866edc89SBingbu Cao v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_DIGITAL_GAIN, 568866edc89SBingbu Cao OV2740_DGTL_GAIN_MIN, OV2740_DGTL_GAIN_MAX, 569866edc89SBingbu Cao OV2740_DGTL_GAIN_STEP, OV2740_DGTL_GAIN_DEFAULT); 570866edc89SBingbu Cao exposure_max = cur_mode->vts_def - OV2740_EXPOSURE_MAX_MARGIN; 571866edc89SBingbu Cao ov2740->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, 572866edc89SBingbu Cao V4L2_CID_EXPOSURE, 573866edc89SBingbu Cao OV2740_EXPOSURE_MIN, exposure_max, 574866edc89SBingbu Cao OV2740_EXPOSURE_STEP, 575866edc89SBingbu Cao exposure_max); 576866edc89SBingbu Cao v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov2740_ctrl_ops, 577866edc89SBingbu Cao V4L2_CID_TEST_PATTERN, 578866edc89SBingbu Cao ARRAY_SIZE(ov2740_test_pattern_menu) - 1, 579866edc89SBingbu Cao 0, 0, ov2740_test_pattern_menu); 580866edc89SBingbu Cao if (ctrl_hdlr->error) 581866edc89SBingbu Cao return ctrl_hdlr->error; 582866edc89SBingbu Cao 583866edc89SBingbu Cao ov2740->sd.ctrl_handler = ctrl_hdlr; 584866edc89SBingbu Cao 585866edc89SBingbu Cao return 0; 586866edc89SBingbu Cao } 587866edc89SBingbu Cao 588866edc89SBingbu Cao static void ov2740_update_pad_format(const struct ov2740_mode *mode, 589866edc89SBingbu Cao struct v4l2_mbus_framefmt *fmt) 590866edc89SBingbu Cao { 591866edc89SBingbu Cao fmt->width = mode->width; 592866edc89SBingbu Cao fmt->height = mode->height; 593866edc89SBingbu Cao fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; 594866edc89SBingbu Cao fmt->field = V4L2_FIELD_NONE; 595866edc89SBingbu Cao } 596866edc89SBingbu Cao 597866edc89SBingbu Cao static int ov2740_start_streaming(struct ov2740 *ov2740) 598866edc89SBingbu Cao { 599866edc89SBingbu Cao struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 600866edc89SBingbu Cao const struct ov2740_reg_list *reg_list; 601866edc89SBingbu Cao int link_freq_index; 602866edc89SBingbu Cao int ret = 0; 603866edc89SBingbu Cao 604866edc89SBingbu Cao link_freq_index = ov2740->cur_mode->link_freq_index; 605866edc89SBingbu Cao reg_list = &link_freq_configs[link_freq_index].reg_list; 606866edc89SBingbu Cao ret = ov2740_write_reg_list(ov2740, reg_list); 607866edc89SBingbu Cao if (ret) { 608866edc89SBingbu Cao dev_err(&client->dev, "failed to set plls"); 609866edc89SBingbu Cao return ret; 610866edc89SBingbu Cao } 611866edc89SBingbu Cao 612866edc89SBingbu Cao reg_list = &ov2740->cur_mode->reg_list; 613866edc89SBingbu Cao ret = ov2740_write_reg_list(ov2740, reg_list); 614866edc89SBingbu Cao if (ret) { 615866edc89SBingbu Cao dev_err(&client->dev, "failed to set mode"); 616866edc89SBingbu Cao return ret; 617866edc89SBingbu Cao } 618866edc89SBingbu Cao 619866edc89SBingbu Cao ret = __v4l2_ctrl_handler_setup(ov2740->sd.ctrl_handler); 620866edc89SBingbu Cao if (ret) 621866edc89SBingbu Cao return ret; 622866edc89SBingbu Cao 623866edc89SBingbu Cao ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1, 624866edc89SBingbu Cao OV2740_MODE_STREAMING); 625866edc89SBingbu Cao if (ret) 626866edc89SBingbu Cao dev_err(&client->dev, "failed to start streaming"); 627866edc89SBingbu Cao 628866edc89SBingbu Cao return ret; 629866edc89SBingbu Cao } 630866edc89SBingbu Cao 631866edc89SBingbu Cao static void ov2740_stop_streaming(struct ov2740 *ov2740) 632866edc89SBingbu Cao { 633866edc89SBingbu Cao struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 634866edc89SBingbu Cao 635866edc89SBingbu Cao if (ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1, 636866edc89SBingbu Cao OV2740_MODE_STANDBY)) 637866edc89SBingbu Cao dev_err(&client->dev, "failed to stop streaming"); 638866edc89SBingbu Cao } 639866edc89SBingbu Cao 640866edc89SBingbu Cao static int ov2740_set_stream(struct v4l2_subdev *sd, int enable) 641866edc89SBingbu Cao { 642866edc89SBingbu Cao struct ov2740 *ov2740 = to_ov2740(sd); 643866edc89SBingbu Cao struct i2c_client *client = v4l2_get_subdevdata(sd); 644866edc89SBingbu Cao int ret = 0; 645866edc89SBingbu Cao 646866edc89SBingbu Cao if (ov2740->streaming == enable) 647866edc89SBingbu Cao return 0; 648866edc89SBingbu Cao 649866edc89SBingbu Cao mutex_lock(&ov2740->mutex); 650866edc89SBingbu Cao if (enable) { 651866edc89SBingbu Cao ret = pm_runtime_get_sync(&client->dev); 652866edc89SBingbu Cao if (ret < 0) { 653866edc89SBingbu Cao pm_runtime_put_noidle(&client->dev); 654866edc89SBingbu Cao mutex_unlock(&ov2740->mutex); 655866edc89SBingbu Cao return ret; 656866edc89SBingbu Cao } 657866edc89SBingbu Cao 658866edc89SBingbu Cao ret = ov2740_start_streaming(ov2740); 659866edc89SBingbu Cao if (ret) { 660866edc89SBingbu Cao enable = 0; 661866edc89SBingbu Cao ov2740_stop_streaming(ov2740); 662866edc89SBingbu Cao pm_runtime_put(&client->dev); 663866edc89SBingbu Cao } 664866edc89SBingbu Cao } else { 665866edc89SBingbu Cao ov2740_stop_streaming(ov2740); 666866edc89SBingbu Cao pm_runtime_put(&client->dev); 667866edc89SBingbu Cao } 668866edc89SBingbu Cao 669866edc89SBingbu Cao ov2740->streaming = enable; 670866edc89SBingbu Cao mutex_unlock(&ov2740->mutex); 671866edc89SBingbu Cao 672866edc89SBingbu Cao return ret; 673866edc89SBingbu Cao } 674866edc89SBingbu Cao 675866edc89SBingbu Cao static int __maybe_unused ov2740_suspend(struct device *dev) 676866edc89SBingbu Cao { 677866edc89SBingbu Cao struct i2c_client *client = to_i2c_client(dev); 678866edc89SBingbu Cao struct v4l2_subdev *sd = i2c_get_clientdata(client); 679866edc89SBingbu Cao struct ov2740 *ov2740 = to_ov2740(sd); 680866edc89SBingbu Cao 681866edc89SBingbu Cao mutex_lock(&ov2740->mutex); 682866edc89SBingbu Cao if (ov2740->streaming) 683866edc89SBingbu Cao ov2740_stop_streaming(ov2740); 684866edc89SBingbu Cao 685866edc89SBingbu Cao mutex_unlock(&ov2740->mutex); 686866edc89SBingbu Cao 687866edc89SBingbu Cao return 0; 688866edc89SBingbu Cao } 689866edc89SBingbu Cao 690866edc89SBingbu Cao static int __maybe_unused ov2740_resume(struct device *dev) 691866edc89SBingbu Cao { 692866edc89SBingbu Cao struct i2c_client *client = to_i2c_client(dev); 693866edc89SBingbu Cao struct v4l2_subdev *sd = i2c_get_clientdata(client); 694866edc89SBingbu Cao struct ov2740 *ov2740 = to_ov2740(sd); 695866edc89SBingbu Cao int ret = 0; 696866edc89SBingbu Cao 697866edc89SBingbu Cao mutex_lock(&ov2740->mutex); 698866edc89SBingbu Cao if (!ov2740->streaming) 699866edc89SBingbu Cao goto exit; 700866edc89SBingbu Cao 701866edc89SBingbu Cao ret = ov2740_start_streaming(ov2740); 702866edc89SBingbu Cao if (ret) { 703866edc89SBingbu Cao ov2740->streaming = false; 704866edc89SBingbu Cao ov2740_stop_streaming(ov2740); 705866edc89SBingbu Cao } 706866edc89SBingbu Cao 707866edc89SBingbu Cao exit: 708866edc89SBingbu Cao mutex_unlock(&ov2740->mutex); 709866edc89SBingbu Cao return ret; 710866edc89SBingbu Cao } 711866edc89SBingbu Cao 712866edc89SBingbu Cao static int ov2740_set_format(struct v4l2_subdev *sd, 713866edc89SBingbu Cao struct v4l2_subdev_pad_config *cfg, 714866edc89SBingbu Cao struct v4l2_subdev_format *fmt) 715866edc89SBingbu Cao { 716866edc89SBingbu Cao struct ov2740 *ov2740 = to_ov2740(sd); 717866edc89SBingbu Cao const struct ov2740_mode *mode; 718866edc89SBingbu Cao s32 vblank_def, h_blank; 719866edc89SBingbu Cao 720866edc89SBingbu Cao mode = v4l2_find_nearest_size(supported_modes, 721866edc89SBingbu Cao ARRAY_SIZE(supported_modes), width, 722866edc89SBingbu Cao height, fmt->format.width, 723866edc89SBingbu Cao fmt->format.height); 724866edc89SBingbu Cao 725866edc89SBingbu Cao mutex_lock(&ov2740->mutex); 726866edc89SBingbu Cao ov2740_update_pad_format(mode, &fmt->format); 727866edc89SBingbu Cao if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 728866edc89SBingbu Cao *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format; 729866edc89SBingbu Cao } else { 730866edc89SBingbu Cao ov2740->cur_mode = mode; 731866edc89SBingbu Cao __v4l2_ctrl_s_ctrl(ov2740->link_freq, mode->link_freq_index); 732866edc89SBingbu Cao __v4l2_ctrl_s_ctrl_int64(ov2740->pixel_rate, 733866edc89SBingbu Cao to_pixel_rate(mode->link_freq_index)); 734866edc89SBingbu Cao 735866edc89SBingbu Cao /* Update limits and set FPS to default */ 736866edc89SBingbu Cao vblank_def = mode->vts_def - mode->height; 737866edc89SBingbu Cao __v4l2_ctrl_modify_range(ov2740->vblank, 738866edc89SBingbu Cao mode->vts_min - mode->height, 739866edc89SBingbu Cao OV2740_VTS_MAX - mode->height, 1, 740866edc89SBingbu Cao vblank_def); 741866edc89SBingbu Cao __v4l2_ctrl_s_ctrl(ov2740->vblank, vblank_def); 742866edc89SBingbu Cao h_blank = to_pixels_per_line(mode->hts, mode->link_freq_index) - 743866edc89SBingbu Cao mode->width; 744866edc89SBingbu Cao __v4l2_ctrl_modify_range(ov2740->hblank, h_blank, h_blank, 1, 745866edc89SBingbu Cao h_blank); 746866edc89SBingbu Cao } 747866edc89SBingbu Cao mutex_unlock(&ov2740->mutex); 748866edc89SBingbu Cao 749866edc89SBingbu Cao return 0; 750866edc89SBingbu Cao } 751866edc89SBingbu Cao 752866edc89SBingbu Cao static int ov2740_get_format(struct v4l2_subdev *sd, 753866edc89SBingbu Cao struct v4l2_subdev_pad_config *cfg, 754866edc89SBingbu Cao struct v4l2_subdev_format *fmt) 755866edc89SBingbu Cao { 756866edc89SBingbu Cao struct ov2740 *ov2740 = to_ov2740(sd); 757866edc89SBingbu Cao 758866edc89SBingbu Cao mutex_lock(&ov2740->mutex); 759866edc89SBingbu Cao if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) 760866edc89SBingbu Cao fmt->format = *v4l2_subdev_get_try_format(&ov2740->sd, cfg, 761866edc89SBingbu Cao fmt->pad); 762866edc89SBingbu Cao else 763866edc89SBingbu Cao ov2740_update_pad_format(ov2740->cur_mode, &fmt->format); 764866edc89SBingbu Cao 765866edc89SBingbu Cao mutex_unlock(&ov2740->mutex); 766866edc89SBingbu Cao 767866edc89SBingbu Cao return 0; 768866edc89SBingbu Cao } 769866edc89SBingbu Cao 770866edc89SBingbu Cao static int ov2740_enum_mbus_code(struct v4l2_subdev *sd, 771866edc89SBingbu Cao struct v4l2_subdev_pad_config *cfg, 772866edc89SBingbu Cao struct v4l2_subdev_mbus_code_enum *code) 773866edc89SBingbu Cao { 774866edc89SBingbu Cao if (code->index > 0) 775866edc89SBingbu Cao return -EINVAL; 776866edc89SBingbu Cao 777866edc89SBingbu Cao code->code = MEDIA_BUS_FMT_SGRBG10_1X10; 778866edc89SBingbu Cao 779866edc89SBingbu Cao return 0; 780866edc89SBingbu Cao } 781866edc89SBingbu Cao 782866edc89SBingbu Cao static int ov2740_enum_frame_size(struct v4l2_subdev *sd, 783866edc89SBingbu Cao struct v4l2_subdev_pad_config *cfg, 784866edc89SBingbu Cao struct v4l2_subdev_frame_size_enum *fse) 785866edc89SBingbu Cao { 786866edc89SBingbu Cao if (fse->index >= ARRAY_SIZE(supported_modes)) 787866edc89SBingbu Cao return -EINVAL; 788866edc89SBingbu Cao 789866edc89SBingbu Cao if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10) 790866edc89SBingbu Cao return -EINVAL; 791866edc89SBingbu Cao 792866edc89SBingbu Cao fse->min_width = supported_modes[fse->index].width; 793866edc89SBingbu Cao fse->max_width = fse->min_width; 794866edc89SBingbu Cao fse->min_height = supported_modes[fse->index].height; 795866edc89SBingbu Cao fse->max_height = fse->min_height; 796866edc89SBingbu Cao 797866edc89SBingbu Cao return 0; 798866edc89SBingbu Cao } 799866edc89SBingbu Cao 800866edc89SBingbu Cao static int ov2740_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) 801866edc89SBingbu Cao { 802866edc89SBingbu Cao struct ov2740 *ov2740 = to_ov2740(sd); 803866edc89SBingbu Cao 804866edc89SBingbu Cao mutex_lock(&ov2740->mutex); 805866edc89SBingbu Cao ov2740_update_pad_format(&supported_modes[0], 806866edc89SBingbu Cao v4l2_subdev_get_try_format(sd, fh->pad, 0)); 807866edc89SBingbu Cao mutex_unlock(&ov2740->mutex); 808866edc89SBingbu Cao 809866edc89SBingbu Cao return 0; 810866edc89SBingbu Cao } 811866edc89SBingbu Cao 812866edc89SBingbu Cao static const struct v4l2_subdev_video_ops ov2740_video_ops = { 813866edc89SBingbu Cao .s_stream = ov2740_set_stream, 814866edc89SBingbu Cao }; 815866edc89SBingbu Cao 816866edc89SBingbu Cao static const struct v4l2_subdev_pad_ops ov2740_pad_ops = { 817866edc89SBingbu Cao .set_fmt = ov2740_set_format, 818866edc89SBingbu Cao .get_fmt = ov2740_get_format, 819866edc89SBingbu Cao .enum_mbus_code = ov2740_enum_mbus_code, 820866edc89SBingbu Cao .enum_frame_size = ov2740_enum_frame_size, 821866edc89SBingbu Cao }; 822866edc89SBingbu Cao 823866edc89SBingbu Cao static const struct v4l2_subdev_ops ov2740_subdev_ops = { 824866edc89SBingbu Cao .video = &ov2740_video_ops, 825866edc89SBingbu Cao .pad = &ov2740_pad_ops, 826866edc89SBingbu Cao }; 827866edc89SBingbu Cao 828866edc89SBingbu Cao static const struct media_entity_operations ov2740_subdev_entity_ops = { 829866edc89SBingbu Cao .link_validate = v4l2_subdev_link_validate, 830866edc89SBingbu Cao }; 831866edc89SBingbu Cao 832866edc89SBingbu Cao static const struct v4l2_subdev_internal_ops ov2740_internal_ops = { 833866edc89SBingbu Cao .open = ov2740_open, 834866edc89SBingbu Cao }; 835866edc89SBingbu Cao 836866edc89SBingbu Cao static int ov2740_identify_module(struct ov2740 *ov2740) 837866edc89SBingbu Cao { 838866edc89SBingbu Cao struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 839866edc89SBingbu Cao int ret; 840866edc89SBingbu Cao u32 val; 841866edc89SBingbu Cao 842866edc89SBingbu Cao ret = ov2740_read_reg(ov2740, OV2740_REG_CHIP_ID, 3, &val); 843866edc89SBingbu Cao if (ret) 844866edc89SBingbu Cao return ret; 845866edc89SBingbu Cao 846866edc89SBingbu Cao if (val != OV2740_CHIP_ID) { 847866edc89SBingbu Cao dev_err(&client->dev, "chip id mismatch: %x!=%x", 848866edc89SBingbu Cao OV2740_CHIP_ID, val); 849866edc89SBingbu Cao return -ENXIO; 850866edc89SBingbu Cao } 851866edc89SBingbu Cao 852866edc89SBingbu Cao return 0; 853866edc89SBingbu Cao } 854866edc89SBingbu Cao 855866edc89SBingbu Cao static int ov2740_check_hwcfg(struct device *dev) 856866edc89SBingbu Cao { 857866edc89SBingbu Cao struct fwnode_handle *ep; 858866edc89SBingbu Cao struct fwnode_handle *fwnode = dev_fwnode(dev); 859866edc89SBingbu Cao struct v4l2_fwnode_endpoint bus_cfg = { 860866edc89SBingbu Cao .bus_type = V4L2_MBUS_CSI2_DPHY 861866edc89SBingbu Cao }; 862866edc89SBingbu Cao u32 mclk; 863866edc89SBingbu Cao int ret; 864866edc89SBingbu Cao unsigned int i, j; 865866edc89SBingbu Cao 866866edc89SBingbu Cao if (!fwnode) 867866edc89SBingbu Cao return -ENXIO; 868866edc89SBingbu Cao 869866edc89SBingbu Cao ret = fwnode_property_read_u32(fwnode, "clock-frequency", &mclk); 870866edc89SBingbu Cao if (ret) 871866edc89SBingbu Cao return ret; 872866edc89SBingbu Cao 873866edc89SBingbu Cao if (mclk != OV2740_MCLK) { 874866edc89SBingbu Cao dev_err(dev, "external clock %d is not supported", mclk); 875866edc89SBingbu Cao return -EINVAL; 876866edc89SBingbu Cao } 877866edc89SBingbu Cao 878866edc89SBingbu Cao ep = fwnode_graph_get_next_endpoint(fwnode, NULL); 879866edc89SBingbu Cao if (!ep) 880866edc89SBingbu Cao return -ENXIO; 881866edc89SBingbu Cao 882866edc89SBingbu Cao ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); 883866edc89SBingbu Cao fwnode_handle_put(ep); 884866edc89SBingbu Cao if (ret) 885866edc89SBingbu Cao return ret; 886866edc89SBingbu Cao 887866edc89SBingbu Cao if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV2740_DATA_LANES) { 888866edc89SBingbu Cao dev_err(dev, "number of CSI2 data lanes %d is not supported", 889866edc89SBingbu Cao bus_cfg.bus.mipi_csi2.num_data_lanes); 890866edc89SBingbu Cao ret = -EINVAL; 891866edc89SBingbu Cao goto check_hwcfg_error; 892866edc89SBingbu Cao } 893866edc89SBingbu Cao 894866edc89SBingbu Cao if (!bus_cfg.nr_of_link_frequencies) { 895866edc89SBingbu Cao dev_err(dev, "no link frequencies defined"); 896866edc89SBingbu Cao ret = -EINVAL; 897866edc89SBingbu Cao goto check_hwcfg_error; 898866edc89SBingbu Cao } 899866edc89SBingbu Cao 900866edc89SBingbu Cao for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) { 901866edc89SBingbu Cao for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) { 902866edc89SBingbu Cao if (link_freq_menu_items[i] == 903866edc89SBingbu Cao bus_cfg.link_frequencies[j]) 904866edc89SBingbu Cao break; 905866edc89SBingbu Cao } 906866edc89SBingbu Cao 907866edc89SBingbu Cao if (j == bus_cfg.nr_of_link_frequencies) { 908866edc89SBingbu Cao dev_err(dev, "no link frequency %lld supported", 909866edc89SBingbu Cao link_freq_menu_items[i]); 910866edc89SBingbu Cao ret = -EINVAL; 911866edc89SBingbu Cao goto check_hwcfg_error; 912866edc89SBingbu Cao } 913866edc89SBingbu Cao } 914866edc89SBingbu Cao 915866edc89SBingbu Cao check_hwcfg_error: 916866edc89SBingbu Cao v4l2_fwnode_endpoint_free(&bus_cfg); 917866edc89SBingbu Cao 918866edc89SBingbu Cao return ret; 919866edc89SBingbu Cao } 920866edc89SBingbu Cao 921866edc89SBingbu Cao static int ov2740_remove(struct i2c_client *client) 922866edc89SBingbu Cao { 923866edc89SBingbu Cao struct v4l2_subdev *sd = i2c_get_clientdata(client); 924866edc89SBingbu Cao struct ov2740 *ov2740 = to_ov2740(sd); 925866edc89SBingbu Cao 926866edc89SBingbu Cao v4l2_async_unregister_subdev(sd); 927866edc89SBingbu Cao media_entity_cleanup(&sd->entity); 928866edc89SBingbu Cao v4l2_ctrl_handler_free(sd->ctrl_handler); 929866edc89SBingbu Cao pm_runtime_disable(&client->dev); 930866edc89SBingbu Cao mutex_destroy(&ov2740->mutex); 931866edc89SBingbu Cao 932866edc89SBingbu Cao return 0; 933866edc89SBingbu Cao } 934866edc89SBingbu Cao 9357b981288SQingwu Zhang static int ov2740_load_otp_data(struct i2c_client *client, struct nvm_data *nvm) 9367b981288SQingwu Zhang { 9377b981288SQingwu Zhang struct ov2740 *ov2740 = to_ov2740(i2c_get_clientdata(client)); 9387b981288SQingwu Zhang u32 isp_ctrl00 = 0; 9397b981288SQingwu Zhang u32 isp_ctrl01 = 0; 9407b981288SQingwu Zhang int ret; 9417b981288SQingwu Zhang 9427b981288SQingwu Zhang ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, &isp_ctrl00); 9437b981288SQingwu Zhang if (ret) { 9447b981288SQingwu Zhang dev_err(&client->dev, "failed to read ISP CTRL00\n"); 9457b981288SQingwu Zhang goto exit; 9467b981288SQingwu Zhang } 9477b981288SQingwu Zhang ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, &isp_ctrl01); 9487b981288SQingwu Zhang if (ret) { 9497b981288SQingwu Zhang dev_err(&client->dev, "failed to read ISP CTRL01\n"); 9507b981288SQingwu Zhang goto exit; 9517b981288SQingwu Zhang } 9527b981288SQingwu Zhang 9537b981288SQingwu Zhang /* Clear bit 5 of ISP CTRL00 */ 9547b981288SQingwu Zhang ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, 9557b981288SQingwu Zhang isp_ctrl00 & ~BIT(5)); 9567b981288SQingwu Zhang if (ret) { 9577b981288SQingwu Zhang dev_err(&client->dev, "failed to write ISP CTRL00\n"); 9587b981288SQingwu Zhang goto exit; 9597b981288SQingwu Zhang } 9607b981288SQingwu Zhang 9617b981288SQingwu Zhang /* Clear bit 7 of ISP CTRL01 */ 9627b981288SQingwu Zhang ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, 9637b981288SQingwu Zhang isp_ctrl01 & ~BIT(7)); 9647b981288SQingwu Zhang if (ret) { 9657b981288SQingwu Zhang dev_err(&client->dev, "failed to write ISP CTRL01\n"); 9667b981288SQingwu Zhang goto exit; 9677b981288SQingwu Zhang } 9687b981288SQingwu Zhang 9697b981288SQingwu Zhang ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1, 9707b981288SQingwu Zhang OV2740_MODE_STREAMING); 9717b981288SQingwu Zhang if (ret) { 9727b981288SQingwu Zhang dev_err(&client->dev, "failed to start streaming\n"); 9737b981288SQingwu Zhang goto exit; 9747b981288SQingwu Zhang } 9757b981288SQingwu Zhang 9767b981288SQingwu Zhang /* 9777b981288SQingwu Zhang * Users are not allowed to access OTP-related registers and memory 9787b981288SQingwu Zhang * during the 20 ms period after streaming starts (0x100 = 0x01). 9797b981288SQingwu Zhang */ 9807b981288SQingwu Zhang msleep(20); 9817b981288SQingwu Zhang 9827b981288SQingwu Zhang ret = regmap_bulk_read(nvm->regmap, OV2740_REG_OTP_CUSTOMER, 9837b981288SQingwu Zhang nvm->nvm_buffer, CUSTOMER_USE_OTP_SIZE); 9847b981288SQingwu Zhang if (ret) { 9857b981288SQingwu Zhang dev_err(&client->dev, "failed to read OTP data, ret %d\n", ret); 9867b981288SQingwu Zhang goto exit; 9877b981288SQingwu Zhang } 9887b981288SQingwu Zhang 9897b981288SQingwu Zhang ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1, 9907b981288SQingwu Zhang OV2740_MODE_STANDBY); 9917b981288SQingwu Zhang ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, isp_ctrl01); 9927b981288SQingwu Zhang ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, isp_ctrl00); 9937b981288SQingwu Zhang 9947b981288SQingwu Zhang exit: 9957b981288SQingwu Zhang return ret; 9967b981288SQingwu Zhang } 9977b981288SQingwu Zhang 9987b981288SQingwu Zhang static int ov2740_nvmem_read(void *priv, unsigned int off, void *val, 9997b981288SQingwu Zhang size_t count) 10007b981288SQingwu Zhang { 10017b981288SQingwu Zhang struct nvm_data *nvm = priv; 10027b981288SQingwu Zhang 10037b981288SQingwu Zhang memcpy(val, nvm->nvm_buffer + off, count); 10047b981288SQingwu Zhang 10057b981288SQingwu Zhang return 0; 10067b981288SQingwu Zhang } 10077b981288SQingwu Zhang 10087b981288SQingwu Zhang static int ov2740_register_nvmem(struct i2c_client *client) 10097b981288SQingwu Zhang { 10107b981288SQingwu Zhang struct nvm_data *nvm; 10117b981288SQingwu Zhang struct regmap_config regmap_config = { }; 10127b981288SQingwu Zhang struct nvmem_config nvmem_config = { }; 10137b981288SQingwu Zhang struct regmap *regmap; 10147b981288SQingwu Zhang struct device *dev = &client->dev; 10157b981288SQingwu Zhang int ret = 0; 10167b981288SQingwu Zhang 10177b981288SQingwu Zhang nvm = devm_kzalloc(dev, sizeof(*nvm), GFP_KERNEL); 10187b981288SQingwu Zhang if (!nvm) 10197b981288SQingwu Zhang return -ENOMEM; 10207b981288SQingwu Zhang 10213cb14256SBingbu Cao nvm->nvm_buffer = devm_kzalloc(dev, CUSTOMER_USE_OTP_SIZE, GFP_KERNEL); 10223cb14256SBingbu Cao if (!nvm->nvm_buffer) 10233cb14256SBingbu Cao return -ENOMEM; 10243cb14256SBingbu Cao 10257b981288SQingwu Zhang regmap_config.val_bits = 8; 10267b981288SQingwu Zhang regmap_config.reg_bits = 16; 10277b981288SQingwu Zhang regmap_config.disable_locking = true; 10287b981288SQingwu Zhang regmap = devm_regmap_init_i2c(client, ®map_config); 10297b981288SQingwu Zhang if (IS_ERR(regmap)) 10307b981288SQingwu Zhang return PTR_ERR(regmap); 10317b981288SQingwu Zhang 10327b981288SQingwu Zhang nvm->regmap = regmap; 10337b981288SQingwu Zhang 10343cb14256SBingbu Cao ret = ov2740_load_otp_data(client, nvm); 10353cb14256SBingbu Cao if (ret) { 10363cb14256SBingbu Cao dev_err(dev, "failed to load OTP data, ret %d\n", ret); 10373cb14256SBingbu Cao return ret; 10383cb14256SBingbu Cao } 10393cb14256SBingbu Cao 10407b981288SQingwu Zhang nvmem_config.name = dev_name(dev); 10417b981288SQingwu Zhang nvmem_config.dev = dev; 10427b981288SQingwu Zhang nvmem_config.read_only = true; 10437b981288SQingwu Zhang nvmem_config.root_only = true; 10447b981288SQingwu Zhang nvmem_config.owner = THIS_MODULE; 10457b981288SQingwu Zhang nvmem_config.compat = true; 10467b981288SQingwu Zhang nvmem_config.base_dev = dev; 10477b981288SQingwu Zhang nvmem_config.reg_read = ov2740_nvmem_read; 10487b981288SQingwu Zhang nvmem_config.reg_write = NULL; 10497b981288SQingwu Zhang nvmem_config.priv = nvm; 10507b981288SQingwu Zhang nvmem_config.stride = 1; 10517b981288SQingwu Zhang nvmem_config.word_size = 1; 10527b981288SQingwu Zhang nvmem_config.size = CUSTOMER_USE_OTP_SIZE; 10537b981288SQingwu Zhang 10547b981288SQingwu Zhang nvm->nvmem = devm_nvmem_register(dev, &nvmem_config); 10557b981288SQingwu Zhang 10563cb14256SBingbu Cao return PTR_ERR_OR_ZERO(nvm->nvmem); 10577b981288SQingwu Zhang } 10587b981288SQingwu Zhang 1059866edc89SBingbu Cao static int ov2740_probe(struct i2c_client *client) 1060866edc89SBingbu Cao { 1061866edc89SBingbu Cao struct ov2740 *ov2740; 1062866edc89SBingbu Cao int ret = 0; 1063866edc89SBingbu Cao 1064866edc89SBingbu Cao ret = ov2740_check_hwcfg(&client->dev); 1065866edc89SBingbu Cao if (ret) { 1066866edc89SBingbu Cao dev_err(&client->dev, "failed to check HW configuration: %d", 1067866edc89SBingbu Cao ret); 1068866edc89SBingbu Cao return ret; 1069866edc89SBingbu Cao } 1070866edc89SBingbu Cao 1071866edc89SBingbu Cao ov2740 = devm_kzalloc(&client->dev, sizeof(*ov2740), GFP_KERNEL); 1072866edc89SBingbu Cao if (!ov2740) 1073866edc89SBingbu Cao return -ENOMEM; 1074866edc89SBingbu Cao 1075866edc89SBingbu Cao v4l2_i2c_subdev_init(&ov2740->sd, client, &ov2740_subdev_ops); 1076866edc89SBingbu Cao ret = ov2740_identify_module(ov2740); 1077866edc89SBingbu Cao if (ret) { 1078866edc89SBingbu Cao dev_err(&client->dev, "failed to find sensor: %d", ret); 1079866edc89SBingbu Cao return ret; 1080866edc89SBingbu Cao } 1081866edc89SBingbu Cao 1082866edc89SBingbu Cao mutex_init(&ov2740->mutex); 1083866edc89SBingbu Cao ov2740->cur_mode = &supported_modes[0]; 1084866edc89SBingbu Cao ret = ov2740_init_controls(ov2740); 1085866edc89SBingbu Cao if (ret) { 1086866edc89SBingbu Cao dev_err(&client->dev, "failed to init controls: %d", ret); 1087866edc89SBingbu Cao goto probe_error_v4l2_ctrl_handler_free; 1088866edc89SBingbu Cao } 1089866edc89SBingbu Cao 1090866edc89SBingbu Cao ov2740->sd.internal_ops = &ov2740_internal_ops; 1091866edc89SBingbu Cao ov2740->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1092866edc89SBingbu Cao ov2740->sd.entity.ops = &ov2740_subdev_entity_ops; 1093866edc89SBingbu Cao ov2740->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1094866edc89SBingbu Cao ov2740->pad.flags = MEDIA_PAD_FL_SOURCE; 1095866edc89SBingbu Cao ret = media_entity_pads_init(&ov2740->sd.entity, 1, &ov2740->pad); 1096866edc89SBingbu Cao if (ret) { 1097866edc89SBingbu Cao dev_err(&client->dev, "failed to init entity pads: %d", ret); 1098866edc89SBingbu Cao goto probe_error_v4l2_ctrl_handler_free; 1099866edc89SBingbu Cao } 1100866edc89SBingbu Cao 1101866edc89SBingbu Cao ret = v4l2_async_register_subdev_sensor_common(&ov2740->sd); 1102866edc89SBingbu Cao if (ret < 0) { 1103866edc89SBingbu Cao dev_err(&client->dev, "failed to register V4L2 subdev: %d", 1104866edc89SBingbu Cao ret); 1105866edc89SBingbu Cao goto probe_error_media_entity_cleanup; 1106866edc89SBingbu Cao } 1107866edc89SBingbu Cao 11087b981288SQingwu Zhang ret = ov2740_register_nvmem(client); 11097b981288SQingwu Zhang if (ret) 11103cb14256SBingbu Cao dev_warn(&client->dev, "register nvmem failed, ret %d\n", ret); 11117b981288SQingwu Zhang 1112866edc89SBingbu Cao /* 1113866edc89SBingbu Cao * Device is already turned on by i2c-core with ACPI domain PM. 1114866edc89SBingbu Cao * Enable runtime PM and turn off the device. 1115866edc89SBingbu Cao */ 1116866edc89SBingbu Cao pm_runtime_set_active(&client->dev); 1117866edc89SBingbu Cao pm_runtime_enable(&client->dev); 1118866edc89SBingbu Cao pm_runtime_idle(&client->dev); 1119866edc89SBingbu Cao 1120866edc89SBingbu Cao return 0; 1121866edc89SBingbu Cao 1122866edc89SBingbu Cao probe_error_media_entity_cleanup: 1123866edc89SBingbu Cao media_entity_cleanup(&ov2740->sd.entity); 1124866edc89SBingbu Cao 1125866edc89SBingbu Cao probe_error_v4l2_ctrl_handler_free: 1126866edc89SBingbu Cao v4l2_ctrl_handler_free(ov2740->sd.ctrl_handler); 1127866edc89SBingbu Cao mutex_destroy(&ov2740->mutex); 1128866edc89SBingbu Cao 1129866edc89SBingbu Cao return ret; 1130866edc89SBingbu Cao } 1131866edc89SBingbu Cao 1132866edc89SBingbu Cao static const struct dev_pm_ops ov2740_pm_ops = { 1133866edc89SBingbu Cao SET_SYSTEM_SLEEP_PM_OPS(ov2740_suspend, ov2740_resume) 1134866edc89SBingbu Cao }; 1135866edc89SBingbu Cao 1136866edc89SBingbu Cao static const struct acpi_device_id ov2740_acpi_ids[] = { 1137866edc89SBingbu Cao {"INT3474"}, 1138866edc89SBingbu Cao {} 1139866edc89SBingbu Cao }; 1140866edc89SBingbu Cao 1141866edc89SBingbu Cao MODULE_DEVICE_TABLE(acpi, ov2740_acpi_ids); 1142866edc89SBingbu Cao 1143866edc89SBingbu Cao static struct i2c_driver ov2740_i2c_driver = { 1144866edc89SBingbu Cao .driver = { 1145866edc89SBingbu Cao .name = "ov2740", 1146866edc89SBingbu Cao .pm = &ov2740_pm_ops, 11471e8d3bbcSBingbu Cao .acpi_match_table = ov2740_acpi_ids, 1148866edc89SBingbu Cao }, 1149866edc89SBingbu Cao .probe_new = ov2740_probe, 1150866edc89SBingbu Cao .remove = ov2740_remove, 1151866edc89SBingbu Cao }; 1152866edc89SBingbu Cao 1153866edc89SBingbu Cao module_i2c_driver(ov2740_i2c_driver); 1154866edc89SBingbu Cao 1155866edc89SBingbu Cao MODULE_AUTHOR("Qiu, Tianshu <tian.shu.qiu@intel.com>"); 1156866edc89SBingbu Cao MODULE_AUTHOR("Shawn Tu <shawnx.tu@intel.com>"); 1157866edc89SBingbu Cao MODULE_AUTHOR("Bingbu Cao <bingbu.cao@intel.com>"); 1158866edc89SBingbu Cao MODULE_DESCRIPTION("OmniVision OV2740 sensor driver"); 1159866edc89SBingbu Cao MODULE_LICENSE("GPL v2"); 1160