1866edc89SBingbu Cao // SPDX-License-Identifier: GPL-2.0 2866edc89SBingbu Cao // Copyright (c) 2020 Intel Corporation. 3866edc89SBingbu Cao 4866edc89SBingbu Cao #include <asm/unaligned.h> 5866edc89SBingbu Cao #include <linux/acpi.h> 6866edc89SBingbu Cao #include <linux/delay.h> 7866edc89SBingbu Cao #include <linux/i2c.h> 8866edc89SBingbu Cao #include <linux/module.h> 9866edc89SBingbu Cao #include <linux/pm_runtime.h> 107b981288SQingwu Zhang #include <linux/nvmem-provider.h> 117b981288SQingwu Zhang #include <linux/regmap.h> 12866edc89SBingbu Cao #include <media/v4l2-ctrls.h> 13866edc89SBingbu Cao #include <media/v4l2-device.h> 14866edc89SBingbu Cao #include <media/v4l2-fwnode.h> 15866edc89SBingbu Cao 16866edc89SBingbu Cao #define OV2740_LINK_FREQ_360MHZ 360000000ULL 17866edc89SBingbu Cao #define OV2740_SCLK 72000000LL 18866edc89SBingbu Cao #define OV2740_MCLK 19200000 19866edc89SBingbu Cao #define OV2740_DATA_LANES 2 20866edc89SBingbu Cao #define OV2740_RGB_DEPTH 10 21866edc89SBingbu Cao 22866edc89SBingbu Cao #define OV2740_REG_CHIP_ID 0x300a 23866edc89SBingbu Cao #define OV2740_CHIP_ID 0x2740 24866edc89SBingbu Cao 25866edc89SBingbu Cao #define OV2740_REG_MODE_SELECT 0x0100 26866edc89SBingbu Cao #define OV2740_MODE_STANDBY 0x00 27866edc89SBingbu Cao #define OV2740_MODE_STREAMING 0x01 28866edc89SBingbu Cao 29866edc89SBingbu Cao /* vertical-timings from sensor */ 30866edc89SBingbu Cao #define OV2740_REG_VTS 0x380e 31866edc89SBingbu Cao #define OV2740_VTS_DEF 0x088a 32866edc89SBingbu Cao #define OV2740_VTS_MIN 0x0460 33866edc89SBingbu Cao #define OV2740_VTS_MAX 0x7fff 34866edc89SBingbu Cao 35866edc89SBingbu Cao /* horizontal-timings from sensor */ 36866edc89SBingbu Cao #define OV2740_REG_HTS 0x380c 37866edc89SBingbu Cao 38866edc89SBingbu Cao /* Exposure controls from sensor */ 39866edc89SBingbu Cao #define OV2740_REG_EXPOSURE 0x3500 401d7b18a9SBingbu Cao #define OV2740_EXPOSURE_MIN 4 41866edc89SBingbu Cao #define OV2740_EXPOSURE_MAX_MARGIN 8 42866edc89SBingbu Cao #define OV2740_EXPOSURE_STEP 1 43866edc89SBingbu Cao 44866edc89SBingbu Cao /* Analog gain controls from sensor */ 45866edc89SBingbu Cao #define OV2740_REG_ANALOG_GAIN 0x3508 46866edc89SBingbu Cao #define OV2740_ANAL_GAIN_MIN 128 47866edc89SBingbu Cao #define OV2740_ANAL_GAIN_MAX 1983 48866edc89SBingbu Cao #define OV2740_ANAL_GAIN_STEP 1 49866edc89SBingbu Cao 50866edc89SBingbu Cao /* Digital gain controls from sensor */ 51866edc89SBingbu Cao #define OV2740_REG_MWB_R_GAIN 0x500a 52866edc89SBingbu Cao #define OV2740_REG_MWB_G_GAIN 0x500c 53866edc89SBingbu Cao #define OV2740_REG_MWB_B_GAIN 0x500e 5484363509SBingbu Cao #define OV2740_DGTL_GAIN_MIN 1024 55866edc89SBingbu Cao #define OV2740_DGTL_GAIN_MAX 4095 56866edc89SBingbu Cao #define OV2740_DGTL_GAIN_STEP 1 57866edc89SBingbu Cao #define OV2740_DGTL_GAIN_DEFAULT 1024 58866edc89SBingbu Cao 59866edc89SBingbu Cao /* Test Pattern Control */ 60866edc89SBingbu Cao #define OV2740_REG_TEST_PATTERN 0x5040 61866edc89SBingbu Cao #define OV2740_TEST_PATTERN_ENABLE BIT(7) 62866edc89SBingbu Cao #define OV2740_TEST_PATTERN_BAR_SHIFT 2 63866edc89SBingbu Cao 6484363509SBingbu Cao /* Group Access */ 6584363509SBingbu Cao #define OV2740_REG_GROUP_ACCESS 0x3208 6684363509SBingbu Cao #define OV2740_GROUP_HOLD_START 0x0 6784363509SBingbu Cao #define OV2740_GROUP_HOLD_END 0x10 6884363509SBingbu Cao #define OV2740_GROUP_HOLD_LAUNCH 0xa0 6984363509SBingbu Cao 707b981288SQingwu Zhang /* ISP CTRL00 */ 717b981288SQingwu Zhang #define OV2740_REG_ISP_CTRL00 0x5000 727b981288SQingwu Zhang /* ISP CTRL01 */ 737b981288SQingwu Zhang #define OV2740_REG_ISP_CTRL01 0x5001 747b981288SQingwu Zhang /* Customer Addresses: 0x7010 - 0x710F */ 757b981288SQingwu Zhang #define CUSTOMER_USE_OTP_SIZE 0x100 767b981288SQingwu Zhang /* OTP registers from sensor */ 777b981288SQingwu Zhang #define OV2740_REG_OTP_CUSTOMER 0x7010 787b981288SQingwu Zhang 797b981288SQingwu Zhang struct nvm_data { 807b981288SQingwu Zhang struct nvmem_device *nvmem; 817b981288SQingwu Zhang struct regmap *regmap; 82798f1a6bSBingbu Cao char *nvm_buffer; 837b981288SQingwu Zhang }; 847b981288SQingwu Zhang 85866edc89SBingbu Cao enum { 86866edc89SBingbu Cao OV2740_LINK_FREQ_360MHZ_INDEX, 87866edc89SBingbu Cao }; 88866edc89SBingbu Cao 89866edc89SBingbu Cao struct ov2740_reg { 90866edc89SBingbu Cao u16 address; 91866edc89SBingbu Cao u8 val; 92866edc89SBingbu Cao }; 93866edc89SBingbu Cao 94866edc89SBingbu Cao struct ov2740_reg_list { 95866edc89SBingbu Cao u32 num_of_regs; 96866edc89SBingbu Cao const struct ov2740_reg *regs; 97866edc89SBingbu Cao }; 98866edc89SBingbu Cao 99866edc89SBingbu Cao struct ov2740_link_freq_config { 100866edc89SBingbu Cao const struct ov2740_reg_list reg_list; 101866edc89SBingbu Cao }; 102866edc89SBingbu Cao 103866edc89SBingbu Cao struct ov2740_mode { 104866edc89SBingbu Cao /* Frame width in pixels */ 105866edc89SBingbu Cao u32 width; 106866edc89SBingbu Cao 107866edc89SBingbu Cao /* Frame height in pixels */ 108866edc89SBingbu Cao u32 height; 109866edc89SBingbu Cao 110866edc89SBingbu Cao /* Horizontal timining size */ 111866edc89SBingbu Cao u32 hts; 112866edc89SBingbu Cao 113866edc89SBingbu Cao /* Default vertical timining size */ 114866edc89SBingbu Cao u32 vts_def; 115866edc89SBingbu Cao 116866edc89SBingbu Cao /* Min vertical timining size */ 117866edc89SBingbu Cao u32 vts_min; 118866edc89SBingbu Cao 119866edc89SBingbu Cao /* Link frequency needed for this resolution */ 120866edc89SBingbu Cao u32 link_freq_index; 121866edc89SBingbu Cao 122866edc89SBingbu Cao /* Sensor register settings for this resolution */ 123866edc89SBingbu Cao const struct ov2740_reg_list reg_list; 124866edc89SBingbu Cao }; 125866edc89SBingbu Cao 126866edc89SBingbu Cao static const struct ov2740_reg mipi_data_rate_720mbps[] = { 127866edc89SBingbu Cao {0x0103, 0x01}, 128866edc89SBingbu Cao {0x0302, 0x4b}, 129866edc89SBingbu Cao {0x030d, 0x4b}, 130866edc89SBingbu Cao {0x030e, 0x02}, 131866edc89SBingbu Cao {0x030a, 0x01}, 132866edc89SBingbu Cao {0x0312, 0x11}, 133866edc89SBingbu Cao }; 134866edc89SBingbu Cao 135866edc89SBingbu Cao static const struct ov2740_reg mode_1932x1092_regs[] = { 136866edc89SBingbu Cao {0x3000, 0x00}, 137866edc89SBingbu Cao {0x3018, 0x32}, 138866edc89SBingbu Cao {0x3031, 0x0a}, 139866edc89SBingbu Cao {0x3080, 0x08}, 140866edc89SBingbu Cao {0x3083, 0xB4}, 141866edc89SBingbu Cao {0x3103, 0x00}, 142866edc89SBingbu Cao {0x3104, 0x01}, 143866edc89SBingbu Cao {0x3106, 0x01}, 144866edc89SBingbu Cao {0x3500, 0x00}, 145866edc89SBingbu Cao {0x3501, 0x44}, 146866edc89SBingbu Cao {0x3502, 0x40}, 147866edc89SBingbu Cao {0x3503, 0x88}, 148866edc89SBingbu Cao {0x3507, 0x00}, 149866edc89SBingbu Cao {0x3508, 0x00}, 150866edc89SBingbu Cao {0x3509, 0x80}, 151866edc89SBingbu Cao {0x350c, 0x00}, 152866edc89SBingbu Cao {0x350d, 0x80}, 153866edc89SBingbu Cao {0x3510, 0x00}, 154866edc89SBingbu Cao {0x3511, 0x00}, 155866edc89SBingbu Cao {0x3512, 0x20}, 156866edc89SBingbu Cao {0x3632, 0x00}, 157866edc89SBingbu Cao {0x3633, 0x10}, 158866edc89SBingbu Cao {0x3634, 0x10}, 159866edc89SBingbu Cao {0x3635, 0x10}, 160866edc89SBingbu Cao {0x3645, 0x13}, 161866edc89SBingbu Cao {0x3646, 0x81}, 162866edc89SBingbu Cao {0x3636, 0x10}, 163866edc89SBingbu Cao {0x3651, 0x0a}, 164866edc89SBingbu Cao {0x3656, 0x02}, 165866edc89SBingbu Cao {0x3659, 0x04}, 166866edc89SBingbu Cao {0x365a, 0xda}, 167866edc89SBingbu Cao {0x365b, 0xa2}, 168866edc89SBingbu Cao {0x365c, 0x04}, 169866edc89SBingbu Cao {0x365d, 0x1d}, 170866edc89SBingbu Cao {0x365e, 0x1a}, 171866edc89SBingbu Cao {0x3662, 0xd7}, 172866edc89SBingbu Cao {0x3667, 0x78}, 173866edc89SBingbu Cao {0x3669, 0x0a}, 174866edc89SBingbu Cao {0x366a, 0x92}, 175866edc89SBingbu Cao {0x3700, 0x54}, 176866edc89SBingbu Cao {0x3702, 0x10}, 177866edc89SBingbu Cao {0x3706, 0x42}, 178866edc89SBingbu Cao {0x3709, 0x30}, 179866edc89SBingbu Cao {0x370b, 0xc2}, 180866edc89SBingbu Cao {0x3714, 0x63}, 181866edc89SBingbu Cao {0x3715, 0x01}, 182866edc89SBingbu Cao {0x3716, 0x00}, 183866edc89SBingbu Cao {0x371a, 0x3e}, 184866edc89SBingbu Cao {0x3732, 0x0e}, 185866edc89SBingbu Cao {0x3733, 0x10}, 186866edc89SBingbu Cao {0x375f, 0x0e}, 187866edc89SBingbu Cao {0x3768, 0x30}, 188866edc89SBingbu Cao {0x3769, 0x44}, 189866edc89SBingbu Cao {0x376a, 0x22}, 190866edc89SBingbu Cao {0x377b, 0x20}, 191866edc89SBingbu Cao {0x377c, 0x00}, 192866edc89SBingbu Cao {0x377d, 0x0c}, 193866edc89SBingbu Cao {0x3798, 0x00}, 194866edc89SBingbu Cao {0x37a1, 0x55}, 195866edc89SBingbu Cao {0x37a8, 0x6d}, 196866edc89SBingbu Cao {0x37c2, 0x04}, 197866edc89SBingbu Cao {0x37c5, 0x00}, 198866edc89SBingbu Cao {0x37c8, 0x00}, 199866edc89SBingbu Cao {0x3800, 0x00}, 200866edc89SBingbu Cao {0x3801, 0x00}, 201866edc89SBingbu Cao {0x3802, 0x00}, 202866edc89SBingbu Cao {0x3803, 0x00}, 203866edc89SBingbu Cao {0x3804, 0x07}, 204866edc89SBingbu Cao {0x3805, 0x8f}, 205866edc89SBingbu Cao {0x3806, 0x04}, 206866edc89SBingbu Cao {0x3807, 0x47}, 207866edc89SBingbu Cao {0x3808, 0x07}, 208866edc89SBingbu Cao {0x3809, 0x88}, 209866edc89SBingbu Cao {0x380a, 0x04}, 210866edc89SBingbu Cao {0x380b, 0x40}, 211866edc89SBingbu Cao {0x380c, 0x04}, 212866edc89SBingbu Cao {0x380d, 0x38}, 213866edc89SBingbu Cao {0x380e, 0x04}, 214866edc89SBingbu Cao {0x380f, 0x60}, 215866edc89SBingbu Cao {0x3810, 0x00}, 216866edc89SBingbu Cao {0x3811, 0x04}, 217866edc89SBingbu Cao {0x3812, 0x00}, 218866edc89SBingbu Cao {0x3813, 0x04}, 219866edc89SBingbu Cao {0x3814, 0x01}, 220866edc89SBingbu Cao {0x3815, 0x01}, 221866edc89SBingbu Cao {0x3820, 0x80}, 222866edc89SBingbu Cao {0x3821, 0x46}, 223866edc89SBingbu Cao {0x3822, 0x84}, 224866edc89SBingbu Cao {0x3829, 0x00}, 225866edc89SBingbu Cao {0x382a, 0x01}, 226866edc89SBingbu Cao {0x382b, 0x01}, 227866edc89SBingbu Cao {0x3830, 0x04}, 228866edc89SBingbu Cao {0x3836, 0x01}, 229866edc89SBingbu Cao {0x3837, 0x08}, 230866edc89SBingbu Cao {0x3839, 0x01}, 231866edc89SBingbu Cao {0x383a, 0x00}, 232866edc89SBingbu Cao {0x383b, 0x08}, 233866edc89SBingbu Cao {0x383c, 0x00}, 234866edc89SBingbu Cao {0x3f0b, 0x00}, 235866edc89SBingbu Cao {0x4001, 0x20}, 236866edc89SBingbu Cao {0x4009, 0x07}, 237866edc89SBingbu Cao {0x4003, 0x10}, 238866edc89SBingbu Cao {0x4010, 0xe0}, 239866edc89SBingbu Cao {0x4016, 0x00}, 240866edc89SBingbu Cao {0x4017, 0x10}, 241866edc89SBingbu Cao {0x4044, 0x02}, 242866edc89SBingbu Cao {0x4304, 0x08}, 243866edc89SBingbu Cao {0x4307, 0x30}, 244866edc89SBingbu Cao {0x4320, 0x80}, 245866edc89SBingbu Cao {0x4322, 0x00}, 246866edc89SBingbu Cao {0x4323, 0x00}, 247866edc89SBingbu Cao {0x4324, 0x00}, 248866edc89SBingbu Cao {0x4325, 0x00}, 249866edc89SBingbu Cao {0x4326, 0x00}, 250866edc89SBingbu Cao {0x4327, 0x00}, 251866edc89SBingbu Cao {0x4328, 0x00}, 252866edc89SBingbu Cao {0x4329, 0x00}, 253866edc89SBingbu Cao {0x432c, 0x03}, 254866edc89SBingbu Cao {0x432d, 0x81}, 255866edc89SBingbu Cao {0x4501, 0x84}, 256866edc89SBingbu Cao {0x4502, 0x40}, 257866edc89SBingbu Cao {0x4503, 0x18}, 258866edc89SBingbu Cao {0x4504, 0x04}, 259866edc89SBingbu Cao {0x4508, 0x02}, 260866edc89SBingbu Cao {0x4601, 0x10}, 261866edc89SBingbu Cao {0x4800, 0x00}, 262866edc89SBingbu Cao {0x4816, 0x52}, 263866edc89SBingbu Cao {0x4837, 0x16}, 264866edc89SBingbu Cao {0x5000, 0x7f}, 265866edc89SBingbu Cao {0x5001, 0x00}, 266866edc89SBingbu Cao {0x5005, 0x38}, 267866edc89SBingbu Cao {0x501e, 0x0d}, 268866edc89SBingbu Cao {0x5040, 0x00}, 269866edc89SBingbu Cao {0x5901, 0x00}, 270866edc89SBingbu Cao {0x3800, 0x00}, 271866edc89SBingbu Cao {0x3801, 0x00}, 272866edc89SBingbu Cao {0x3802, 0x00}, 273866edc89SBingbu Cao {0x3803, 0x00}, 274866edc89SBingbu Cao {0x3804, 0x07}, 275866edc89SBingbu Cao {0x3805, 0x8f}, 276866edc89SBingbu Cao {0x3806, 0x04}, 277866edc89SBingbu Cao {0x3807, 0x47}, 278866edc89SBingbu Cao {0x3808, 0x07}, 279866edc89SBingbu Cao {0x3809, 0x8c}, 280866edc89SBingbu Cao {0x380a, 0x04}, 281866edc89SBingbu Cao {0x380b, 0x44}, 282866edc89SBingbu Cao {0x3810, 0x00}, 283866edc89SBingbu Cao {0x3811, 0x00}, 284866edc89SBingbu Cao {0x3812, 0x00}, 285866edc89SBingbu Cao {0x3813, 0x01}, 286866edc89SBingbu Cao }; 287866edc89SBingbu Cao 288866edc89SBingbu Cao static const char * const ov2740_test_pattern_menu[] = { 289866edc89SBingbu Cao "Disabled", 290866edc89SBingbu Cao "Color Bar", 291866edc89SBingbu Cao "Top-Bottom Darker Color Bar", 292866edc89SBingbu Cao "Right-Left Darker Color Bar", 293866edc89SBingbu Cao "Bottom-Top Darker Color Bar", 294866edc89SBingbu Cao }; 295866edc89SBingbu Cao 296866edc89SBingbu Cao static const s64 link_freq_menu_items[] = { 297866edc89SBingbu Cao OV2740_LINK_FREQ_360MHZ, 298866edc89SBingbu Cao }; 299866edc89SBingbu Cao 300866edc89SBingbu Cao static const struct ov2740_link_freq_config link_freq_configs[] = { 301866edc89SBingbu Cao [OV2740_LINK_FREQ_360MHZ_INDEX] = { 302866edc89SBingbu Cao .reg_list = { 303866edc89SBingbu Cao .num_of_regs = ARRAY_SIZE(mipi_data_rate_720mbps), 304866edc89SBingbu Cao .regs = mipi_data_rate_720mbps, 305866edc89SBingbu Cao } 306866edc89SBingbu Cao }, 307866edc89SBingbu Cao }; 308866edc89SBingbu Cao 309866edc89SBingbu Cao static const struct ov2740_mode supported_modes[] = { 310866edc89SBingbu Cao { 311866edc89SBingbu Cao .width = 1932, 312866edc89SBingbu Cao .height = 1092, 313866edc89SBingbu Cao .hts = 1080, 314866edc89SBingbu Cao .vts_def = OV2740_VTS_DEF, 315866edc89SBingbu Cao .vts_min = OV2740_VTS_MIN, 316866edc89SBingbu Cao .reg_list = { 317866edc89SBingbu Cao .num_of_regs = ARRAY_SIZE(mode_1932x1092_regs), 318866edc89SBingbu Cao .regs = mode_1932x1092_regs, 319866edc89SBingbu Cao }, 320866edc89SBingbu Cao .link_freq_index = OV2740_LINK_FREQ_360MHZ_INDEX, 321866edc89SBingbu Cao }, 322866edc89SBingbu Cao }; 323866edc89SBingbu Cao 324866edc89SBingbu Cao struct ov2740 { 325866edc89SBingbu Cao struct v4l2_subdev sd; 326866edc89SBingbu Cao struct media_pad pad; 327866edc89SBingbu Cao struct v4l2_ctrl_handler ctrl_handler; 328866edc89SBingbu Cao 329866edc89SBingbu Cao /* V4L2 Controls */ 330866edc89SBingbu Cao struct v4l2_ctrl *link_freq; 331866edc89SBingbu Cao struct v4l2_ctrl *pixel_rate; 332866edc89SBingbu Cao struct v4l2_ctrl *vblank; 333866edc89SBingbu Cao struct v4l2_ctrl *hblank; 334866edc89SBingbu Cao struct v4l2_ctrl *exposure; 335866edc89SBingbu Cao 336866edc89SBingbu Cao /* Current mode */ 337866edc89SBingbu Cao const struct ov2740_mode *cur_mode; 338866edc89SBingbu Cao 339866edc89SBingbu Cao /* To serialize asynchronus callbacks */ 340866edc89SBingbu Cao struct mutex mutex; 341866edc89SBingbu Cao 342866edc89SBingbu Cao /* Streaming on/off */ 343866edc89SBingbu Cao bool streaming; 344798f1a6bSBingbu Cao 345798f1a6bSBingbu Cao /* NVM data inforamtion */ 346798f1a6bSBingbu Cao struct nvm_data *nvm; 347ada2c4f5SBingbu Cao 348ada2c4f5SBingbu Cao /* True if the device has been identified */ 349ada2c4f5SBingbu Cao bool identified; 350866edc89SBingbu Cao }; 351866edc89SBingbu Cao 352866edc89SBingbu Cao static inline struct ov2740 *to_ov2740(struct v4l2_subdev *subdev) 353866edc89SBingbu Cao { 354866edc89SBingbu Cao return container_of(subdev, struct ov2740, sd); 355866edc89SBingbu Cao } 356866edc89SBingbu Cao 357866edc89SBingbu Cao static u64 to_pixel_rate(u32 f_index) 358866edc89SBingbu Cao { 359866edc89SBingbu Cao u64 pixel_rate = link_freq_menu_items[f_index] * 2 * OV2740_DATA_LANES; 360866edc89SBingbu Cao 361866edc89SBingbu Cao do_div(pixel_rate, OV2740_RGB_DEPTH); 362866edc89SBingbu Cao 363866edc89SBingbu Cao return pixel_rate; 364866edc89SBingbu Cao } 365866edc89SBingbu Cao 366866edc89SBingbu Cao static u64 to_pixels_per_line(u32 hts, u32 f_index) 367866edc89SBingbu Cao { 368866edc89SBingbu Cao u64 ppl = hts * to_pixel_rate(f_index); 369866edc89SBingbu Cao 370866edc89SBingbu Cao do_div(ppl, OV2740_SCLK); 371866edc89SBingbu Cao 372866edc89SBingbu Cao return ppl; 373866edc89SBingbu Cao } 374866edc89SBingbu Cao 375866edc89SBingbu Cao static int ov2740_read_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 *val) 376866edc89SBingbu Cao { 377866edc89SBingbu Cao struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 378866edc89SBingbu Cao struct i2c_msg msgs[2]; 379866edc89SBingbu Cao u8 addr_buf[2]; 380866edc89SBingbu Cao u8 data_buf[4] = {0}; 381*3b0d0f33SAndy Shevchenko int ret; 382866edc89SBingbu Cao 383866edc89SBingbu Cao if (len > sizeof(data_buf)) 384866edc89SBingbu Cao return -EINVAL; 385866edc89SBingbu Cao 386866edc89SBingbu Cao put_unaligned_be16(reg, addr_buf); 387866edc89SBingbu Cao msgs[0].addr = client->addr; 388866edc89SBingbu Cao msgs[0].flags = 0; 389866edc89SBingbu Cao msgs[0].len = sizeof(addr_buf); 390866edc89SBingbu Cao msgs[0].buf = addr_buf; 391866edc89SBingbu Cao msgs[1].addr = client->addr; 392866edc89SBingbu Cao msgs[1].flags = I2C_M_RD; 393866edc89SBingbu Cao msgs[1].len = len; 394866edc89SBingbu Cao msgs[1].buf = &data_buf[sizeof(data_buf) - len]; 395866edc89SBingbu Cao 396866edc89SBingbu Cao ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); 397866edc89SBingbu Cao if (ret != ARRAY_SIZE(msgs)) 398866edc89SBingbu Cao return ret < 0 ? ret : -EIO; 399866edc89SBingbu Cao 400866edc89SBingbu Cao *val = get_unaligned_be32(data_buf); 401866edc89SBingbu Cao 402866edc89SBingbu Cao return 0; 403866edc89SBingbu Cao } 404866edc89SBingbu Cao 405866edc89SBingbu Cao static int ov2740_write_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 val) 406866edc89SBingbu Cao { 407866edc89SBingbu Cao struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 408866edc89SBingbu Cao u8 buf[6]; 409*3b0d0f33SAndy Shevchenko int ret; 410866edc89SBingbu Cao 411866edc89SBingbu Cao if (len > 4) 412866edc89SBingbu Cao return -EINVAL; 413866edc89SBingbu Cao 414866edc89SBingbu Cao put_unaligned_be16(reg, buf); 415866edc89SBingbu Cao put_unaligned_be32(val << 8 * (4 - len), buf + 2); 416866edc89SBingbu Cao 417866edc89SBingbu Cao ret = i2c_master_send(client, buf, len + 2); 418866edc89SBingbu Cao if (ret != len + 2) 419866edc89SBingbu Cao return ret < 0 ? ret : -EIO; 420866edc89SBingbu Cao 421866edc89SBingbu Cao return 0; 422866edc89SBingbu Cao } 423866edc89SBingbu Cao 424866edc89SBingbu Cao static int ov2740_write_reg_list(struct ov2740 *ov2740, 425866edc89SBingbu Cao const struct ov2740_reg_list *r_list) 426866edc89SBingbu Cao { 427866edc89SBingbu Cao struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 428866edc89SBingbu Cao unsigned int i; 429*3b0d0f33SAndy Shevchenko int ret; 430866edc89SBingbu Cao 431866edc89SBingbu Cao for (i = 0; i < r_list->num_of_regs; i++) { 432866edc89SBingbu Cao ret = ov2740_write_reg(ov2740, r_list->regs[i].address, 1, 433866edc89SBingbu Cao r_list->regs[i].val); 434866edc89SBingbu Cao if (ret) { 435866edc89SBingbu Cao dev_err_ratelimited(&client->dev, 436866edc89SBingbu Cao "write reg 0x%4.4x return err = %d", 437866edc89SBingbu Cao r_list->regs[i].address, ret); 438866edc89SBingbu Cao return ret; 439866edc89SBingbu Cao } 440866edc89SBingbu Cao } 441866edc89SBingbu Cao 442866edc89SBingbu Cao return 0; 443866edc89SBingbu Cao } 444866edc89SBingbu Cao 445ada2c4f5SBingbu Cao static int ov2740_identify_module(struct ov2740 *ov2740) 446ada2c4f5SBingbu Cao { 447ada2c4f5SBingbu Cao struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 448ada2c4f5SBingbu Cao int ret; 449ada2c4f5SBingbu Cao u32 val; 450ada2c4f5SBingbu Cao 451ada2c4f5SBingbu Cao if (ov2740->identified) 452ada2c4f5SBingbu Cao return 0; 453ada2c4f5SBingbu Cao 454ada2c4f5SBingbu Cao ret = ov2740_read_reg(ov2740, OV2740_REG_CHIP_ID, 3, &val); 455ada2c4f5SBingbu Cao if (ret) 456ada2c4f5SBingbu Cao return ret; 457ada2c4f5SBingbu Cao 458ada2c4f5SBingbu Cao if (val != OV2740_CHIP_ID) { 459ada2c4f5SBingbu Cao dev_err(&client->dev, "chip id mismatch: %x!=%x", 460ada2c4f5SBingbu Cao OV2740_CHIP_ID, val); 461ada2c4f5SBingbu Cao return -ENXIO; 462ada2c4f5SBingbu Cao } 463ada2c4f5SBingbu Cao 464ada2c4f5SBingbu Cao ov2740->identified = true; 465ada2c4f5SBingbu Cao 466ada2c4f5SBingbu Cao return 0; 467ada2c4f5SBingbu Cao } 468ada2c4f5SBingbu Cao 469866edc89SBingbu Cao static int ov2740_update_digital_gain(struct ov2740 *ov2740, u32 d_gain) 470866edc89SBingbu Cao { 471*3b0d0f33SAndy Shevchenko int ret; 472866edc89SBingbu Cao 47384363509SBingbu Cao ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1, 47484363509SBingbu Cao OV2740_GROUP_HOLD_START); 47584363509SBingbu Cao if (ret) 47684363509SBingbu Cao return ret; 47784363509SBingbu Cao 478866edc89SBingbu Cao ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_R_GAIN, 2, d_gain); 479866edc89SBingbu Cao if (ret) 480866edc89SBingbu Cao return ret; 481866edc89SBingbu Cao 482866edc89SBingbu Cao ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_G_GAIN, 2, d_gain); 483866edc89SBingbu Cao if (ret) 484866edc89SBingbu Cao return ret; 485866edc89SBingbu Cao 48684363509SBingbu Cao ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_B_GAIN, 2, d_gain); 48784363509SBingbu Cao if (ret) 48884363509SBingbu Cao return ret; 48984363509SBingbu Cao 49084363509SBingbu Cao ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1, 49184363509SBingbu Cao OV2740_GROUP_HOLD_END); 49284363509SBingbu Cao if (ret) 49384363509SBingbu Cao return ret; 49484363509SBingbu Cao 49584363509SBingbu Cao ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1, 49684363509SBingbu Cao OV2740_GROUP_HOLD_LAUNCH); 49784363509SBingbu Cao return ret; 498866edc89SBingbu Cao } 499866edc89SBingbu Cao 500866edc89SBingbu Cao static int ov2740_test_pattern(struct ov2740 *ov2740, u32 pattern) 501866edc89SBingbu Cao { 502866edc89SBingbu Cao if (pattern) 503866edc89SBingbu Cao pattern = (pattern - 1) << OV2740_TEST_PATTERN_BAR_SHIFT | 504866edc89SBingbu Cao OV2740_TEST_PATTERN_ENABLE; 505866edc89SBingbu Cao 506866edc89SBingbu Cao return ov2740_write_reg(ov2740, OV2740_REG_TEST_PATTERN, 1, pattern); 507866edc89SBingbu Cao } 508866edc89SBingbu Cao 509866edc89SBingbu Cao static int ov2740_set_ctrl(struct v4l2_ctrl *ctrl) 510866edc89SBingbu Cao { 511866edc89SBingbu Cao struct ov2740 *ov2740 = container_of(ctrl->handler, 512866edc89SBingbu Cao struct ov2740, ctrl_handler); 513866edc89SBingbu Cao struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 514866edc89SBingbu Cao s64 exposure_max; 515*3b0d0f33SAndy Shevchenko int ret; 516866edc89SBingbu Cao 517866edc89SBingbu Cao /* Propagate change of current control to all related controls */ 518866edc89SBingbu Cao if (ctrl->id == V4L2_CID_VBLANK) { 519866edc89SBingbu Cao /* Update max exposure while meeting expected vblanking */ 520866edc89SBingbu Cao exposure_max = ov2740->cur_mode->height + ctrl->val - 521866edc89SBingbu Cao OV2740_EXPOSURE_MAX_MARGIN; 522866edc89SBingbu Cao __v4l2_ctrl_modify_range(ov2740->exposure, 523866edc89SBingbu Cao ov2740->exposure->minimum, 524866edc89SBingbu Cao exposure_max, ov2740->exposure->step, 525866edc89SBingbu Cao exposure_max); 526866edc89SBingbu Cao } 527866edc89SBingbu Cao 528866edc89SBingbu Cao /* V4L2 controls values will be applied only when power is already up */ 529866edc89SBingbu Cao if (!pm_runtime_get_if_in_use(&client->dev)) 530866edc89SBingbu Cao return 0; 531866edc89SBingbu Cao 532866edc89SBingbu Cao switch (ctrl->id) { 533866edc89SBingbu Cao case V4L2_CID_ANALOGUE_GAIN: 534866edc89SBingbu Cao ret = ov2740_write_reg(ov2740, OV2740_REG_ANALOG_GAIN, 2, 535866edc89SBingbu Cao ctrl->val); 536866edc89SBingbu Cao break; 537866edc89SBingbu Cao 538866edc89SBingbu Cao case V4L2_CID_DIGITAL_GAIN: 539866edc89SBingbu Cao ret = ov2740_update_digital_gain(ov2740, ctrl->val); 540866edc89SBingbu Cao break; 541866edc89SBingbu Cao 542866edc89SBingbu Cao case V4L2_CID_EXPOSURE: 543866edc89SBingbu Cao /* 4 least significant bits of expsoure are fractional part */ 544866edc89SBingbu Cao ret = ov2740_write_reg(ov2740, OV2740_REG_EXPOSURE, 3, 545866edc89SBingbu Cao ctrl->val << 4); 546866edc89SBingbu Cao break; 547866edc89SBingbu Cao 548866edc89SBingbu Cao case V4L2_CID_VBLANK: 549866edc89SBingbu Cao ret = ov2740_write_reg(ov2740, OV2740_REG_VTS, 2, 550866edc89SBingbu Cao ov2740->cur_mode->height + ctrl->val); 551866edc89SBingbu Cao break; 552866edc89SBingbu Cao 553866edc89SBingbu Cao case V4L2_CID_TEST_PATTERN: 554866edc89SBingbu Cao ret = ov2740_test_pattern(ov2740, ctrl->val); 555866edc89SBingbu Cao break; 556866edc89SBingbu Cao 557866edc89SBingbu Cao default: 558866edc89SBingbu Cao ret = -EINVAL; 559866edc89SBingbu Cao break; 560866edc89SBingbu Cao } 561866edc89SBingbu Cao 562866edc89SBingbu Cao pm_runtime_put(&client->dev); 563866edc89SBingbu Cao 564866edc89SBingbu Cao return ret; 565866edc89SBingbu Cao } 566866edc89SBingbu Cao 567866edc89SBingbu Cao static const struct v4l2_ctrl_ops ov2740_ctrl_ops = { 568866edc89SBingbu Cao .s_ctrl = ov2740_set_ctrl, 569866edc89SBingbu Cao }; 570866edc89SBingbu Cao 571866edc89SBingbu Cao static int ov2740_init_controls(struct ov2740 *ov2740) 572866edc89SBingbu Cao { 573866edc89SBingbu Cao struct v4l2_ctrl_handler *ctrl_hdlr; 574866edc89SBingbu Cao const struct ov2740_mode *cur_mode; 575866edc89SBingbu Cao s64 exposure_max, h_blank, pixel_rate; 576866edc89SBingbu Cao u32 vblank_min, vblank_max, vblank_default; 577866edc89SBingbu Cao int size; 578*3b0d0f33SAndy Shevchenko int ret; 579866edc89SBingbu Cao 580866edc89SBingbu Cao ctrl_hdlr = &ov2740->ctrl_handler; 581866edc89SBingbu Cao ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8); 582866edc89SBingbu Cao if (ret) 583866edc89SBingbu Cao return ret; 584866edc89SBingbu Cao 585866edc89SBingbu Cao ctrl_hdlr->lock = &ov2740->mutex; 586866edc89SBingbu Cao cur_mode = ov2740->cur_mode; 587866edc89SBingbu Cao size = ARRAY_SIZE(link_freq_menu_items); 588866edc89SBingbu Cao 589866edc89SBingbu Cao ov2740->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &ov2740_ctrl_ops, 590866edc89SBingbu Cao V4L2_CID_LINK_FREQ, 591866edc89SBingbu Cao size - 1, 0, 592866edc89SBingbu Cao link_freq_menu_items); 593866edc89SBingbu Cao if (ov2740->link_freq) 594866edc89SBingbu Cao ov2740->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 595866edc89SBingbu Cao 596866edc89SBingbu Cao pixel_rate = to_pixel_rate(OV2740_LINK_FREQ_360MHZ_INDEX); 597866edc89SBingbu Cao ov2740->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, 598866edc89SBingbu Cao V4L2_CID_PIXEL_RATE, 0, 599866edc89SBingbu Cao pixel_rate, 1, pixel_rate); 600866edc89SBingbu Cao 601866edc89SBingbu Cao vblank_min = cur_mode->vts_min - cur_mode->height; 602866edc89SBingbu Cao vblank_max = OV2740_VTS_MAX - cur_mode->height; 603866edc89SBingbu Cao vblank_default = cur_mode->vts_def - cur_mode->height; 604866edc89SBingbu Cao ov2740->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, 605866edc89SBingbu Cao V4L2_CID_VBLANK, vblank_min, 606866edc89SBingbu Cao vblank_max, 1, vblank_default); 607866edc89SBingbu Cao 608866edc89SBingbu Cao h_blank = to_pixels_per_line(cur_mode->hts, cur_mode->link_freq_index); 609866edc89SBingbu Cao h_blank -= cur_mode->width; 610866edc89SBingbu Cao ov2740->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, 611866edc89SBingbu Cao V4L2_CID_HBLANK, h_blank, h_blank, 1, 612866edc89SBingbu Cao h_blank); 613866edc89SBingbu Cao if (ov2740->hblank) 614866edc89SBingbu Cao ov2740->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 615866edc89SBingbu Cao 616866edc89SBingbu Cao v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, 617866edc89SBingbu Cao OV2740_ANAL_GAIN_MIN, OV2740_ANAL_GAIN_MAX, 618866edc89SBingbu Cao OV2740_ANAL_GAIN_STEP, OV2740_ANAL_GAIN_MIN); 619866edc89SBingbu Cao v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_DIGITAL_GAIN, 620866edc89SBingbu Cao OV2740_DGTL_GAIN_MIN, OV2740_DGTL_GAIN_MAX, 621866edc89SBingbu Cao OV2740_DGTL_GAIN_STEP, OV2740_DGTL_GAIN_DEFAULT); 622866edc89SBingbu Cao exposure_max = cur_mode->vts_def - OV2740_EXPOSURE_MAX_MARGIN; 623866edc89SBingbu Cao ov2740->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, 624866edc89SBingbu Cao V4L2_CID_EXPOSURE, 625866edc89SBingbu Cao OV2740_EXPOSURE_MIN, exposure_max, 626866edc89SBingbu Cao OV2740_EXPOSURE_STEP, 627866edc89SBingbu Cao exposure_max); 628866edc89SBingbu Cao v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov2740_ctrl_ops, 629866edc89SBingbu Cao V4L2_CID_TEST_PATTERN, 630866edc89SBingbu Cao ARRAY_SIZE(ov2740_test_pattern_menu) - 1, 631866edc89SBingbu Cao 0, 0, ov2740_test_pattern_menu); 632866edc89SBingbu Cao if (ctrl_hdlr->error) 633866edc89SBingbu Cao return ctrl_hdlr->error; 634866edc89SBingbu Cao 635866edc89SBingbu Cao ov2740->sd.ctrl_handler = ctrl_hdlr; 636866edc89SBingbu Cao 637866edc89SBingbu Cao return 0; 638866edc89SBingbu Cao } 639866edc89SBingbu Cao 640866edc89SBingbu Cao static void ov2740_update_pad_format(const struct ov2740_mode *mode, 641866edc89SBingbu Cao struct v4l2_mbus_framefmt *fmt) 642866edc89SBingbu Cao { 643866edc89SBingbu Cao fmt->width = mode->width; 644866edc89SBingbu Cao fmt->height = mode->height; 645866edc89SBingbu Cao fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; 646866edc89SBingbu Cao fmt->field = V4L2_FIELD_NONE; 647866edc89SBingbu Cao } 648866edc89SBingbu Cao 6495e6fd339SBingbu Cao static int ov2740_load_otp_data(struct nvm_data *nvm) 6505e6fd339SBingbu Cao { 65139cc0f20SAndy Shevchenko struct device *dev = regmap_get_device(nvm->regmap); 65239cc0f20SAndy Shevchenko struct ov2740 *ov2740 = to_ov2740(dev_get_drvdata(dev)); 6535e6fd339SBingbu Cao u32 isp_ctrl00 = 0; 6545e6fd339SBingbu Cao u32 isp_ctrl01 = 0; 6555e6fd339SBingbu Cao int ret; 6565e6fd339SBingbu Cao 6575e6fd339SBingbu Cao if (nvm->nvm_buffer) 6585e6fd339SBingbu Cao return 0; 6595e6fd339SBingbu Cao 6605e6fd339SBingbu Cao nvm->nvm_buffer = kzalloc(CUSTOMER_USE_OTP_SIZE, GFP_KERNEL); 6615e6fd339SBingbu Cao if (!nvm->nvm_buffer) 6625e6fd339SBingbu Cao return -ENOMEM; 6635e6fd339SBingbu Cao 6645e6fd339SBingbu Cao ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, &isp_ctrl00); 6655e6fd339SBingbu Cao if (ret) { 66639cc0f20SAndy Shevchenko dev_err(dev, "failed to read ISP CTRL00\n"); 6675e6fd339SBingbu Cao goto err; 6685e6fd339SBingbu Cao } 6695e6fd339SBingbu Cao 6705e6fd339SBingbu Cao ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, &isp_ctrl01); 6715e6fd339SBingbu Cao if (ret) { 67239cc0f20SAndy Shevchenko dev_err(dev, "failed to read ISP CTRL01\n"); 6735e6fd339SBingbu Cao goto err; 6745e6fd339SBingbu Cao } 6755e6fd339SBingbu Cao 6765e6fd339SBingbu Cao /* Clear bit 5 of ISP CTRL00 */ 6775e6fd339SBingbu Cao ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, 6785e6fd339SBingbu Cao isp_ctrl00 & ~BIT(5)); 6795e6fd339SBingbu Cao if (ret) { 68039cc0f20SAndy Shevchenko dev_err(dev, "failed to set ISP CTRL00\n"); 6815e6fd339SBingbu Cao goto err; 6825e6fd339SBingbu Cao } 6835e6fd339SBingbu Cao 6845e6fd339SBingbu Cao /* Clear bit 7 of ISP CTRL01 */ 6855e6fd339SBingbu Cao ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, 6865e6fd339SBingbu Cao isp_ctrl01 & ~BIT(7)); 6875e6fd339SBingbu Cao if (ret) { 68839cc0f20SAndy Shevchenko dev_err(dev, "failed to set ISP CTRL01\n"); 6895e6fd339SBingbu Cao goto err; 6905e6fd339SBingbu Cao } 6915e6fd339SBingbu Cao 6925e6fd339SBingbu Cao ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1, 6935e6fd339SBingbu Cao OV2740_MODE_STREAMING); 6945e6fd339SBingbu Cao if (ret) { 69539cc0f20SAndy Shevchenko dev_err(dev, "failed to set streaming mode\n"); 6965e6fd339SBingbu Cao goto err; 6975e6fd339SBingbu Cao } 6985e6fd339SBingbu Cao 6995e6fd339SBingbu Cao /* 7005e6fd339SBingbu Cao * Users are not allowed to access OTP-related registers and memory 7015e6fd339SBingbu Cao * during the 20 ms period after streaming starts (0x100 = 0x01). 7025e6fd339SBingbu Cao */ 7035e6fd339SBingbu Cao msleep(20); 7045e6fd339SBingbu Cao 7055e6fd339SBingbu Cao ret = regmap_bulk_read(nvm->regmap, OV2740_REG_OTP_CUSTOMER, 7065e6fd339SBingbu Cao nvm->nvm_buffer, CUSTOMER_USE_OTP_SIZE); 7075e6fd339SBingbu Cao if (ret) { 70839cc0f20SAndy Shevchenko dev_err(dev, "failed to read OTP data, ret %d\n", ret); 7095e6fd339SBingbu Cao goto err; 7105e6fd339SBingbu Cao } 7115e6fd339SBingbu Cao 7125e6fd339SBingbu Cao ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1, 7135e6fd339SBingbu Cao OV2740_MODE_STANDBY); 7145e6fd339SBingbu Cao if (ret) { 71539cc0f20SAndy Shevchenko dev_err(dev, "failed to set streaming mode\n"); 7165e6fd339SBingbu Cao goto err; 7175e6fd339SBingbu Cao } 7185e6fd339SBingbu Cao 7195e6fd339SBingbu Cao ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, isp_ctrl01); 7205e6fd339SBingbu Cao if (ret) { 72139cc0f20SAndy Shevchenko dev_err(dev, "failed to set ISP CTRL01\n"); 7225e6fd339SBingbu Cao goto err; 7235e6fd339SBingbu Cao } 7245e6fd339SBingbu Cao 7255e6fd339SBingbu Cao ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, isp_ctrl00); 7265e6fd339SBingbu Cao if (ret) { 72739cc0f20SAndy Shevchenko dev_err(dev, "failed to set ISP CTRL00\n"); 7285e6fd339SBingbu Cao goto err; 7295e6fd339SBingbu Cao } 7305e6fd339SBingbu Cao 7315e6fd339SBingbu Cao return 0; 7325e6fd339SBingbu Cao err: 7335e6fd339SBingbu Cao kfree(nvm->nvm_buffer); 7345e6fd339SBingbu Cao nvm->nvm_buffer = NULL; 7355e6fd339SBingbu Cao 7365e6fd339SBingbu Cao return ret; 7375e6fd339SBingbu Cao } 7385e6fd339SBingbu Cao 739866edc89SBingbu Cao static int ov2740_start_streaming(struct ov2740 *ov2740) 740866edc89SBingbu Cao { 741866edc89SBingbu Cao struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 742866edc89SBingbu Cao const struct ov2740_reg_list *reg_list; 743866edc89SBingbu Cao int link_freq_index; 744*3b0d0f33SAndy Shevchenko int ret; 745866edc89SBingbu Cao 746ada2c4f5SBingbu Cao ret = ov2740_identify_module(ov2740); 747ada2c4f5SBingbu Cao if (ret) 748ada2c4f5SBingbu Cao return ret; 749ada2c4f5SBingbu Cao 75039cc0f20SAndy Shevchenko if (ov2740->nvm) 75139cc0f20SAndy Shevchenko ov2740_load_otp_data(ov2740->nvm); 7525e6fd339SBingbu Cao 753866edc89SBingbu Cao link_freq_index = ov2740->cur_mode->link_freq_index; 754866edc89SBingbu Cao reg_list = &link_freq_configs[link_freq_index].reg_list; 755866edc89SBingbu Cao ret = ov2740_write_reg_list(ov2740, reg_list); 756866edc89SBingbu Cao if (ret) { 757866edc89SBingbu Cao dev_err(&client->dev, "failed to set plls"); 758866edc89SBingbu Cao return ret; 759866edc89SBingbu Cao } 760866edc89SBingbu Cao 761866edc89SBingbu Cao reg_list = &ov2740->cur_mode->reg_list; 762866edc89SBingbu Cao ret = ov2740_write_reg_list(ov2740, reg_list); 763866edc89SBingbu Cao if (ret) { 764866edc89SBingbu Cao dev_err(&client->dev, "failed to set mode"); 765866edc89SBingbu Cao return ret; 766866edc89SBingbu Cao } 767866edc89SBingbu Cao 768866edc89SBingbu Cao ret = __v4l2_ctrl_handler_setup(ov2740->sd.ctrl_handler); 769866edc89SBingbu Cao if (ret) 770866edc89SBingbu Cao return ret; 771866edc89SBingbu Cao 772866edc89SBingbu Cao ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1, 773866edc89SBingbu Cao OV2740_MODE_STREAMING); 774866edc89SBingbu Cao if (ret) 775866edc89SBingbu Cao dev_err(&client->dev, "failed to start streaming"); 776866edc89SBingbu Cao 777866edc89SBingbu Cao return ret; 778866edc89SBingbu Cao } 779866edc89SBingbu Cao 780866edc89SBingbu Cao static void ov2740_stop_streaming(struct ov2740 *ov2740) 781866edc89SBingbu Cao { 782866edc89SBingbu Cao struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 783866edc89SBingbu Cao 784866edc89SBingbu Cao if (ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1, 785866edc89SBingbu Cao OV2740_MODE_STANDBY)) 786866edc89SBingbu Cao dev_err(&client->dev, "failed to stop streaming"); 787866edc89SBingbu Cao } 788866edc89SBingbu Cao 789866edc89SBingbu Cao static int ov2740_set_stream(struct v4l2_subdev *sd, int enable) 790866edc89SBingbu Cao { 791866edc89SBingbu Cao struct ov2740 *ov2740 = to_ov2740(sd); 792866edc89SBingbu Cao struct i2c_client *client = v4l2_get_subdevdata(sd); 793866edc89SBingbu Cao int ret = 0; 794866edc89SBingbu Cao 795866edc89SBingbu Cao if (ov2740->streaming == enable) 796866edc89SBingbu Cao return 0; 797866edc89SBingbu Cao 798866edc89SBingbu Cao mutex_lock(&ov2740->mutex); 799866edc89SBingbu Cao if (enable) { 800b9be93aaSMauro Carvalho Chehab ret = pm_runtime_resume_and_get(&client->dev); 801866edc89SBingbu Cao if (ret < 0) { 802866edc89SBingbu Cao mutex_unlock(&ov2740->mutex); 803866edc89SBingbu Cao return ret; 804866edc89SBingbu Cao } 805866edc89SBingbu Cao 806866edc89SBingbu Cao ret = ov2740_start_streaming(ov2740); 807866edc89SBingbu Cao if (ret) { 808866edc89SBingbu Cao enable = 0; 809866edc89SBingbu Cao ov2740_stop_streaming(ov2740); 810866edc89SBingbu Cao pm_runtime_put(&client->dev); 811866edc89SBingbu Cao } 812866edc89SBingbu Cao } else { 813866edc89SBingbu Cao ov2740_stop_streaming(ov2740); 814866edc89SBingbu Cao pm_runtime_put(&client->dev); 815866edc89SBingbu Cao } 816866edc89SBingbu Cao 817866edc89SBingbu Cao ov2740->streaming = enable; 818866edc89SBingbu Cao mutex_unlock(&ov2740->mutex); 819866edc89SBingbu Cao 820866edc89SBingbu Cao return ret; 821866edc89SBingbu Cao } 822866edc89SBingbu Cao 8231ba4b745SAndy Shevchenko static int ov2740_suspend(struct device *dev) 824866edc89SBingbu Cao { 8255fa6f1fcSKrzysztof Kozlowski struct v4l2_subdev *sd = dev_get_drvdata(dev); 826866edc89SBingbu Cao struct ov2740 *ov2740 = to_ov2740(sd); 827866edc89SBingbu Cao 828866edc89SBingbu Cao mutex_lock(&ov2740->mutex); 829866edc89SBingbu Cao if (ov2740->streaming) 830866edc89SBingbu Cao ov2740_stop_streaming(ov2740); 831866edc89SBingbu Cao 832866edc89SBingbu Cao mutex_unlock(&ov2740->mutex); 833866edc89SBingbu Cao 834866edc89SBingbu Cao return 0; 835866edc89SBingbu Cao } 836866edc89SBingbu Cao 8371ba4b745SAndy Shevchenko static int ov2740_resume(struct device *dev) 838866edc89SBingbu Cao { 8395fa6f1fcSKrzysztof Kozlowski struct v4l2_subdev *sd = dev_get_drvdata(dev); 840866edc89SBingbu Cao struct ov2740 *ov2740 = to_ov2740(sd); 841866edc89SBingbu Cao int ret = 0; 842866edc89SBingbu Cao 843866edc89SBingbu Cao mutex_lock(&ov2740->mutex); 844866edc89SBingbu Cao if (!ov2740->streaming) 845866edc89SBingbu Cao goto exit; 846866edc89SBingbu Cao 847866edc89SBingbu Cao ret = ov2740_start_streaming(ov2740); 848866edc89SBingbu Cao if (ret) { 849866edc89SBingbu Cao ov2740->streaming = false; 850866edc89SBingbu Cao ov2740_stop_streaming(ov2740); 851866edc89SBingbu Cao } 852866edc89SBingbu Cao 853866edc89SBingbu Cao exit: 854866edc89SBingbu Cao mutex_unlock(&ov2740->mutex); 855866edc89SBingbu Cao return ret; 856866edc89SBingbu Cao } 857866edc89SBingbu Cao 858866edc89SBingbu Cao static int ov2740_set_format(struct v4l2_subdev *sd, 8590d346d2aSTomi Valkeinen struct v4l2_subdev_state *sd_state, 860866edc89SBingbu Cao struct v4l2_subdev_format *fmt) 861866edc89SBingbu Cao { 862866edc89SBingbu Cao struct ov2740 *ov2740 = to_ov2740(sd); 863866edc89SBingbu Cao const struct ov2740_mode *mode; 864866edc89SBingbu Cao s32 vblank_def, h_blank; 865866edc89SBingbu Cao 866866edc89SBingbu Cao mode = v4l2_find_nearest_size(supported_modes, 867866edc89SBingbu Cao ARRAY_SIZE(supported_modes), width, 868866edc89SBingbu Cao height, fmt->format.width, 869866edc89SBingbu Cao fmt->format.height); 870866edc89SBingbu Cao 871866edc89SBingbu Cao mutex_lock(&ov2740->mutex); 872866edc89SBingbu Cao ov2740_update_pad_format(mode, &fmt->format); 873866edc89SBingbu Cao if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 8740d346d2aSTomi Valkeinen *v4l2_subdev_get_try_format(sd, sd_state, fmt->pad) = fmt->format; 875866edc89SBingbu Cao } else { 876866edc89SBingbu Cao ov2740->cur_mode = mode; 877866edc89SBingbu Cao __v4l2_ctrl_s_ctrl(ov2740->link_freq, mode->link_freq_index); 878866edc89SBingbu Cao __v4l2_ctrl_s_ctrl_int64(ov2740->pixel_rate, 879866edc89SBingbu Cao to_pixel_rate(mode->link_freq_index)); 880866edc89SBingbu Cao 881866edc89SBingbu Cao /* Update limits and set FPS to default */ 882866edc89SBingbu Cao vblank_def = mode->vts_def - mode->height; 883866edc89SBingbu Cao __v4l2_ctrl_modify_range(ov2740->vblank, 884866edc89SBingbu Cao mode->vts_min - mode->height, 885866edc89SBingbu Cao OV2740_VTS_MAX - mode->height, 1, 886866edc89SBingbu Cao vblank_def); 887866edc89SBingbu Cao __v4l2_ctrl_s_ctrl(ov2740->vblank, vblank_def); 888866edc89SBingbu Cao h_blank = to_pixels_per_line(mode->hts, mode->link_freq_index) - 889866edc89SBingbu Cao mode->width; 890866edc89SBingbu Cao __v4l2_ctrl_modify_range(ov2740->hblank, h_blank, h_blank, 1, 891866edc89SBingbu Cao h_blank); 892866edc89SBingbu Cao } 893866edc89SBingbu Cao mutex_unlock(&ov2740->mutex); 894866edc89SBingbu Cao 895866edc89SBingbu Cao return 0; 896866edc89SBingbu Cao } 897866edc89SBingbu Cao 898866edc89SBingbu Cao static int ov2740_get_format(struct v4l2_subdev *sd, 8990d346d2aSTomi Valkeinen struct v4l2_subdev_state *sd_state, 900866edc89SBingbu Cao struct v4l2_subdev_format *fmt) 901866edc89SBingbu Cao { 902866edc89SBingbu Cao struct ov2740 *ov2740 = to_ov2740(sd); 903866edc89SBingbu Cao 904866edc89SBingbu Cao mutex_lock(&ov2740->mutex); 905866edc89SBingbu Cao if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) 9060d346d2aSTomi Valkeinen fmt->format = *v4l2_subdev_get_try_format(&ov2740->sd, 9070d346d2aSTomi Valkeinen sd_state, 908866edc89SBingbu Cao fmt->pad); 909866edc89SBingbu Cao else 910866edc89SBingbu Cao ov2740_update_pad_format(ov2740->cur_mode, &fmt->format); 911866edc89SBingbu Cao 912866edc89SBingbu Cao mutex_unlock(&ov2740->mutex); 913866edc89SBingbu Cao 914866edc89SBingbu Cao return 0; 915866edc89SBingbu Cao } 916866edc89SBingbu Cao 917866edc89SBingbu Cao static int ov2740_enum_mbus_code(struct v4l2_subdev *sd, 9180d346d2aSTomi Valkeinen struct v4l2_subdev_state *sd_state, 919866edc89SBingbu Cao struct v4l2_subdev_mbus_code_enum *code) 920866edc89SBingbu Cao { 921866edc89SBingbu Cao if (code->index > 0) 922866edc89SBingbu Cao return -EINVAL; 923866edc89SBingbu Cao 924866edc89SBingbu Cao code->code = MEDIA_BUS_FMT_SGRBG10_1X10; 925866edc89SBingbu Cao 926866edc89SBingbu Cao return 0; 927866edc89SBingbu Cao } 928866edc89SBingbu Cao 929866edc89SBingbu Cao static int ov2740_enum_frame_size(struct v4l2_subdev *sd, 9300d346d2aSTomi Valkeinen struct v4l2_subdev_state *sd_state, 931866edc89SBingbu Cao struct v4l2_subdev_frame_size_enum *fse) 932866edc89SBingbu Cao { 933866edc89SBingbu Cao if (fse->index >= ARRAY_SIZE(supported_modes)) 934866edc89SBingbu Cao return -EINVAL; 935866edc89SBingbu Cao 936866edc89SBingbu Cao if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10) 937866edc89SBingbu Cao return -EINVAL; 938866edc89SBingbu Cao 939866edc89SBingbu Cao fse->min_width = supported_modes[fse->index].width; 940866edc89SBingbu Cao fse->max_width = fse->min_width; 941866edc89SBingbu Cao fse->min_height = supported_modes[fse->index].height; 942866edc89SBingbu Cao fse->max_height = fse->min_height; 943866edc89SBingbu Cao 944866edc89SBingbu Cao return 0; 945866edc89SBingbu Cao } 946866edc89SBingbu Cao 947866edc89SBingbu Cao static int ov2740_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) 948866edc89SBingbu Cao { 949866edc89SBingbu Cao struct ov2740 *ov2740 = to_ov2740(sd); 950866edc89SBingbu Cao 951866edc89SBingbu Cao mutex_lock(&ov2740->mutex); 952866edc89SBingbu Cao ov2740_update_pad_format(&supported_modes[0], 9530d346d2aSTomi Valkeinen v4l2_subdev_get_try_format(sd, fh->state, 0)); 954866edc89SBingbu Cao mutex_unlock(&ov2740->mutex); 955866edc89SBingbu Cao 956866edc89SBingbu Cao return 0; 957866edc89SBingbu Cao } 958866edc89SBingbu Cao 959866edc89SBingbu Cao static const struct v4l2_subdev_video_ops ov2740_video_ops = { 960866edc89SBingbu Cao .s_stream = ov2740_set_stream, 961866edc89SBingbu Cao }; 962866edc89SBingbu Cao 963866edc89SBingbu Cao static const struct v4l2_subdev_pad_ops ov2740_pad_ops = { 964866edc89SBingbu Cao .set_fmt = ov2740_set_format, 965866edc89SBingbu Cao .get_fmt = ov2740_get_format, 966866edc89SBingbu Cao .enum_mbus_code = ov2740_enum_mbus_code, 967866edc89SBingbu Cao .enum_frame_size = ov2740_enum_frame_size, 968866edc89SBingbu Cao }; 969866edc89SBingbu Cao 970866edc89SBingbu Cao static const struct v4l2_subdev_ops ov2740_subdev_ops = { 971866edc89SBingbu Cao .video = &ov2740_video_ops, 972866edc89SBingbu Cao .pad = &ov2740_pad_ops, 973866edc89SBingbu Cao }; 974866edc89SBingbu Cao 975866edc89SBingbu Cao static const struct media_entity_operations ov2740_subdev_entity_ops = { 976866edc89SBingbu Cao .link_validate = v4l2_subdev_link_validate, 977866edc89SBingbu Cao }; 978866edc89SBingbu Cao 979866edc89SBingbu Cao static const struct v4l2_subdev_internal_ops ov2740_internal_ops = { 980866edc89SBingbu Cao .open = ov2740_open, 981866edc89SBingbu Cao }; 982866edc89SBingbu Cao 983866edc89SBingbu Cao static int ov2740_check_hwcfg(struct device *dev) 984866edc89SBingbu Cao { 985866edc89SBingbu Cao struct fwnode_handle *ep; 986866edc89SBingbu Cao struct fwnode_handle *fwnode = dev_fwnode(dev); 987866edc89SBingbu Cao struct v4l2_fwnode_endpoint bus_cfg = { 988866edc89SBingbu Cao .bus_type = V4L2_MBUS_CSI2_DPHY 989866edc89SBingbu Cao }; 990866edc89SBingbu Cao u32 mclk; 991866edc89SBingbu Cao int ret; 992866edc89SBingbu Cao unsigned int i, j; 993866edc89SBingbu Cao 994866edc89SBingbu Cao ret = fwnode_property_read_u32(fwnode, "clock-frequency", &mclk); 995866edc89SBingbu Cao if (ret) 996866edc89SBingbu Cao return ret; 997866edc89SBingbu Cao 998866edc89SBingbu Cao if (mclk != OV2740_MCLK) { 999866edc89SBingbu Cao dev_err(dev, "external clock %d is not supported", mclk); 1000866edc89SBingbu Cao return -EINVAL; 1001866edc89SBingbu Cao } 1002866edc89SBingbu Cao 1003866edc89SBingbu Cao ep = fwnode_graph_get_next_endpoint(fwnode, NULL); 1004866edc89SBingbu Cao if (!ep) 1005866edc89SBingbu Cao return -ENXIO; 1006866edc89SBingbu Cao 1007866edc89SBingbu Cao ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); 1008866edc89SBingbu Cao fwnode_handle_put(ep); 1009866edc89SBingbu Cao if (ret) 1010866edc89SBingbu Cao return ret; 1011866edc89SBingbu Cao 1012866edc89SBingbu Cao if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV2740_DATA_LANES) { 1013866edc89SBingbu Cao dev_err(dev, "number of CSI2 data lanes %d is not supported", 1014866edc89SBingbu Cao bus_cfg.bus.mipi_csi2.num_data_lanes); 1015866edc89SBingbu Cao ret = -EINVAL; 1016866edc89SBingbu Cao goto check_hwcfg_error; 1017866edc89SBingbu Cao } 1018866edc89SBingbu Cao 1019866edc89SBingbu Cao if (!bus_cfg.nr_of_link_frequencies) { 1020866edc89SBingbu Cao dev_err(dev, "no link frequencies defined"); 1021866edc89SBingbu Cao ret = -EINVAL; 1022866edc89SBingbu Cao goto check_hwcfg_error; 1023866edc89SBingbu Cao } 1024866edc89SBingbu Cao 1025866edc89SBingbu Cao for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) { 1026866edc89SBingbu Cao for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) { 1027866edc89SBingbu Cao if (link_freq_menu_items[i] == 1028866edc89SBingbu Cao bus_cfg.link_frequencies[j]) 1029866edc89SBingbu Cao break; 1030866edc89SBingbu Cao } 1031866edc89SBingbu Cao 1032866edc89SBingbu Cao if (j == bus_cfg.nr_of_link_frequencies) { 1033866edc89SBingbu Cao dev_err(dev, "no link frequency %lld supported", 1034866edc89SBingbu Cao link_freq_menu_items[i]); 1035866edc89SBingbu Cao ret = -EINVAL; 1036866edc89SBingbu Cao goto check_hwcfg_error; 1037866edc89SBingbu Cao } 1038866edc89SBingbu Cao } 1039866edc89SBingbu Cao 1040866edc89SBingbu Cao check_hwcfg_error: 1041866edc89SBingbu Cao v4l2_fwnode_endpoint_free(&bus_cfg); 1042866edc89SBingbu Cao 1043866edc89SBingbu Cao return ret; 1044866edc89SBingbu Cao } 1045866edc89SBingbu Cao 1046ed5c2f5fSUwe Kleine-König static void ov2740_remove(struct i2c_client *client) 1047866edc89SBingbu Cao { 1048866edc89SBingbu Cao struct v4l2_subdev *sd = i2c_get_clientdata(client); 1049866edc89SBingbu Cao struct ov2740 *ov2740 = to_ov2740(sd); 1050866edc89SBingbu Cao 1051866edc89SBingbu Cao v4l2_async_unregister_subdev(sd); 1052866edc89SBingbu Cao media_entity_cleanup(&sd->entity); 1053866edc89SBingbu Cao v4l2_ctrl_handler_free(sd->ctrl_handler); 1054866edc89SBingbu Cao pm_runtime_disable(&client->dev); 1055866edc89SBingbu Cao mutex_destroy(&ov2740->mutex); 1056866edc89SBingbu Cao } 1057866edc89SBingbu Cao 10587b981288SQingwu Zhang static int ov2740_nvmem_read(void *priv, unsigned int off, void *val, 10597b981288SQingwu Zhang size_t count) 10607b981288SQingwu Zhang { 10617b981288SQingwu Zhang struct nvm_data *nvm = priv; 106239cc0f20SAndy Shevchenko struct device *dev = regmap_get_device(nvm->regmap); 106339cc0f20SAndy Shevchenko struct ov2740 *ov2740 = to_ov2740(dev_get_drvdata(dev)); 1064798f1a6bSBingbu Cao int ret = 0; 10657b981288SQingwu Zhang 1066798f1a6bSBingbu Cao mutex_lock(&ov2740->mutex); 1067798f1a6bSBingbu Cao 1068798f1a6bSBingbu Cao if (nvm->nvm_buffer) { 10697b981288SQingwu Zhang memcpy(val, nvm->nvm_buffer + off, count); 1070798f1a6bSBingbu Cao goto exit; 10717b981288SQingwu Zhang } 10727b981288SQingwu Zhang 1073b9be93aaSMauro Carvalho Chehab ret = pm_runtime_resume_and_get(dev); 1074798f1a6bSBingbu Cao if (ret < 0) { 1075798f1a6bSBingbu Cao goto exit; 1076798f1a6bSBingbu Cao } 1077798f1a6bSBingbu Cao 1078798f1a6bSBingbu Cao ret = ov2740_load_otp_data(nvm); 1079798f1a6bSBingbu Cao if (!ret) 1080798f1a6bSBingbu Cao memcpy(val, nvm->nvm_buffer + off, count); 1081798f1a6bSBingbu Cao 1082798f1a6bSBingbu Cao pm_runtime_put(dev); 1083798f1a6bSBingbu Cao exit: 1084798f1a6bSBingbu Cao mutex_unlock(&ov2740->mutex); 1085798f1a6bSBingbu Cao return ret; 1086798f1a6bSBingbu Cao } 1087798f1a6bSBingbu Cao 1088798f1a6bSBingbu Cao static int ov2740_register_nvmem(struct i2c_client *client, 1089798f1a6bSBingbu Cao struct ov2740 *ov2740) 10907b981288SQingwu Zhang { 10917b981288SQingwu Zhang struct nvm_data *nvm; 10927b981288SQingwu Zhang struct regmap_config regmap_config = { }; 10937b981288SQingwu Zhang struct nvmem_config nvmem_config = { }; 10947b981288SQingwu Zhang struct regmap *regmap; 10957b981288SQingwu Zhang struct device *dev = &client->dev; 1096798f1a6bSBingbu Cao int ret; 10977b981288SQingwu Zhang 10987b981288SQingwu Zhang nvm = devm_kzalloc(dev, sizeof(*nvm), GFP_KERNEL); 10997b981288SQingwu Zhang if (!nvm) 11007b981288SQingwu Zhang return -ENOMEM; 11017b981288SQingwu Zhang 11027b981288SQingwu Zhang regmap_config.val_bits = 8; 11037b981288SQingwu Zhang regmap_config.reg_bits = 16; 11047b981288SQingwu Zhang regmap_config.disable_locking = true; 11057b981288SQingwu Zhang regmap = devm_regmap_init_i2c(client, ®map_config); 11067b981288SQingwu Zhang if (IS_ERR(regmap)) 11077b981288SQingwu Zhang return PTR_ERR(regmap); 11087b981288SQingwu Zhang 11097b981288SQingwu Zhang nvm->regmap = regmap; 11103cb14256SBingbu Cao 11117b981288SQingwu Zhang nvmem_config.name = dev_name(dev); 11127b981288SQingwu Zhang nvmem_config.dev = dev; 11137b981288SQingwu Zhang nvmem_config.read_only = true; 11147b981288SQingwu Zhang nvmem_config.root_only = true; 11157b981288SQingwu Zhang nvmem_config.owner = THIS_MODULE; 11167b981288SQingwu Zhang nvmem_config.compat = true; 11177b981288SQingwu Zhang nvmem_config.base_dev = dev; 11187b981288SQingwu Zhang nvmem_config.reg_read = ov2740_nvmem_read; 11197b981288SQingwu Zhang nvmem_config.reg_write = NULL; 11207b981288SQingwu Zhang nvmem_config.priv = nvm; 11217b981288SQingwu Zhang nvmem_config.stride = 1; 11227b981288SQingwu Zhang nvmem_config.word_size = 1; 11237b981288SQingwu Zhang nvmem_config.size = CUSTOMER_USE_OTP_SIZE; 11247b981288SQingwu Zhang 11257b981288SQingwu Zhang nvm->nvmem = devm_nvmem_register(dev, &nvmem_config); 11267b981288SQingwu Zhang 1127798f1a6bSBingbu Cao ret = PTR_ERR_OR_ZERO(nvm->nvmem); 1128798f1a6bSBingbu Cao if (!ret) 1129798f1a6bSBingbu Cao ov2740->nvm = nvm; 1130798f1a6bSBingbu Cao 1131798f1a6bSBingbu Cao return ret; 11327b981288SQingwu Zhang } 11337b981288SQingwu Zhang 1134866edc89SBingbu Cao static int ov2740_probe(struct i2c_client *client) 1135866edc89SBingbu Cao { 1136866edc89SBingbu Cao struct ov2740 *ov2740; 1137ada2c4f5SBingbu Cao bool full_power; 1138*3b0d0f33SAndy Shevchenko int ret; 1139866edc89SBingbu Cao 1140866edc89SBingbu Cao ret = ov2740_check_hwcfg(&client->dev); 1141866edc89SBingbu Cao if (ret) { 1142866edc89SBingbu Cao dev_err(&client->dev, "failed to check HW configuration: %d", 1143866edc89SBingbu Cao ret); 1144866edc89SBingbu Cao return ret; 1145866edc89SBingbu Cao } 1146866edc89SBingbu Cao 1147866edc89SBingbu Cao ov2740 = devm_kzalloc(&client->dev, sizeof(*ov2740), GFP_KERNEL); 1148866edc89SBingbu Cao if (!ov2740) 1149866edc89SBingbu Cao return -ENOMEM; 1150866edc89SBingbu Cao 115154ade663SBingbu Cao v4l2_i2c_subdev_init(&ov2740->sd, client, &ov2740_subdev_ops); 1152ada2c4f5SBingbu Cao full_power = acpi_dev_state_d0(&client->dev); 1153ada2c4f5SBingbu Cao if (full_power) { 1154ada2c4f5SBingbu Cao ret = ov2740_identify_module(ov2740); 1155ada2c4f5SBingbu Cao if (ret) { 1156ada2c4f5SBingbu Cao dev_err(&client->dev, "failed to find sensor: %d", ret); 1157ada2c4f5SBingbu Cao return ret; 1158ada2c4f5SBingbu Cao } 1159ada2c4f5SBingbu Cao } 1160ada2c4f5SBingbu Cao 1161866edc89SBingbu Cao mutex_init(&ov2740->mutex); 1162866edc89SBingbu Cao ov2740->cur_mode = &supported_modes[0]; 1163866edc89SBingbu Cao ret = ov2740_init_controls(ov2740); 1164866edc89SBingbu Cao if (ret) { 1165866edc89SBingbu Cao dev_err(&client->dev, "failed to init controls: %d", ret); 1166866edc89SBingbu Cao goto probe_error_v4l2_ctrl_handler_free; 1167866edc89SBingbu Cao } 1168866edc89SBingbu Cao 1169866edc89SBingbu Cao ov2740->sd.internal_ops = &ov2740_internal_ops; 1170866edc89SBingbu Cao ov2740->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1171866edc89SBingbu Cao ov2740->sd.entity.ops = &ov2740_subdev_entity_ops; 1172866edc89SBingbu Cao ov2740->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1173866edc89SBingbu Cao ov2740->pad.flags = MEDIA_PAD_FL_SOURCE; 1174866edc89SBingbu Cao ret = media_entity_pads_init(&ov2740->sd.entity, 1, &ov2740->pad); 1175866edc89SBingbu Cao if (ret) { 1176866edc89SBingbu Cao dev_err(&client->dev, "failed to init entity pads: %d", ret); 1177866edc89SBingbu Cao goto probe_error_v4l2_ctrl_handler_free; 1178866edc89SBingbu Cao } 1179866edc89SBingbu Cao 118015786f7bSSakari Ailus ret = v4l2_async_register_subdev_sensor(&ov2740->sd); 1181866edc89SBingbu Cao if (ret < 0) { 1182866edc89SBingbu Cao dev_err(&client->dev, "failed to register V4L2 subdev: %d", 1183866edc89SBingbu Cao ret); 1184866edc89SBingbu Cao goto probe_error_media_entity_cleanup; 1185866edc89SBingbu Cao } 1186866edc89SBingbu Cao 1187798f1a6bSBingbu Cao ret = ov2740_register_nvmem(client, ov2740); 11887b981288SQingwu Zhang if (ret) 11893cb14256SBingbu Cao dev_warn(&client->dev, "register nvmem failed, ret %d\n", ret); 11907b981288SQingwu Zhang 1191ada2c4f5SBingbu Cao /* Set the device's state to active if it's in D0 state. */ 1192ada2c4f5SBingbu Cao if (full_power) 1193866edc89SBingbu Cao pm_runtime_set_active(&client->dev); 1194866edc89SBingbu Cao pm_runtime_enable(&client->dev); 1195866edc89SBingbu Cao pm_runtime_idle(&client->dev); 1196866edc89SBingbu Cao 1197866edc89SBingbu Cao return 0; 1198866edc89SBingbu Cao 1199866edc89SBingbu Cao probe_error_media_entity_cleanup: 1200866edc89SBingbu Cao media_entity_cleanup(&ov2740->sd.entity); 1201866edc89SBingbu Cao 1202866edc89SBingbu Cao probe_error_v4l2_ctrl_handler_free: 1203866edc89SBingbu Cao v4l2_ctrl_handler_free(ov2740->sd.ctrl_handler); 1204866edc89SBingbu Cao mutex_destroy(&ov2740->mutex); 1205866edc89SBingbu Cao 1206866edc89SBingbu Cao return ret; 1207866edc89SBingbu Cao } 1208866edc89SBingbu Cao 12091ba4b745SAndy Shevchenko static DEFINE_SIMPLE_DEV_PM_OPS(ov2740_pm_ops, ov2740_suspend, ov2740_resume); 1210866edc89SBingbu Cao 1211866edc89SBingbu Cao static const struct acpi_device_id ov2740_acpi_ids[] = { 1212866edc89SBingbu Cao {"INT3474"}, 1213866edc89SBingbu Cao {} 1214866edc89SBingbu Cao }; 1215866edc89SBingbu Cao 1216866edc89SBingbu Cao MODULE_DEVICE_TABLE(acpi, ov2740_acpi_ids); 1217866edc89SBingbu Cao 1218866edc89SBingbu Cao static struct i2c_driver ov2740_i2c_driver = { 1219866edc89SBingbu Cao .driver = { 1220866edc89SBingbu Cao .name = "ov2740", 12211ba4b745SAndy Shevchenko .pm = pm_sleep_ptr(&ov2740_pm_ops), 12221e8d3bbcSBingbu Cao .acpi_match_table = ov2740_acpi_ids, 1223866edc89SBingbu Cao }, 1224866edc89SBingbu Cao .probe_new = ov2740_probe, 1225866edc89SBingbu Cao .remove = ov2740_remove, 1226ada2c4f5SBingbu Cao .flags = I2C_DRV_ACPI_WAIVE_D0_PROBE, 1227866edc89SBingbu Cao }; 1228866edc89SBingbu Cao 1229866edc89SBingbu Cao module_i2c_driver(ov2740_i2c_driver); 1230866edc89SBingbu Cao 1231866edc89SBingbu Cao MODULE_AUTHOR("Qiu, Tianshu <tian.shu.qiu@intel.com>"); 1232866edc89SBingbu Cao MODULE_AUTHOR("Shawn Tu <shawnx.tu@intel.com>"); 1233866edc89SBingbu Cao MODULE_AUTHOR("Bingbu Cao <bingbu.cao@intel.com>"); 1234866edc89SBingbu Cao MODULE_DESCRIPTION("OmniVision OV2740 sensor driver"); 1235866edc89SBingbu Cao MODULE_LICENSE("GPL v2"); 1236