xref: /openbmc/linux/drivers/media/i2c/ov2685.c (revision aaeb31c0)
1e3861d91SShunqian Zheng // SPDX-License-Identifier: GPL-2.0
2e3861d91SShunqian Zheng /*
3e3861d91SShunqian Zheng  * ov2685 driver
4e3861d91SShunqian Zheng  *
5e3861d91SShunqian Zheng  * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
6e3861d91SShunqian Zheng  */
7e3861d91SShunqian Zheng 
8e3861d91SShunqian Zheng #include <linux/clk.h>
9e3861d91SShunqian Zheng #include <linux/device.h>
10e3861d91SShunqian Zheng #include <linux/delay.h>
11e3861d91SShunqian Zheng #include <linux/gpio/consumer.h>
12e3861d91SShunqian Zheng #include <linux/i2c.h>
13e3861d91SShunqian Zheng #include <linux/module.h>
14e3861d91SShunqian Zheng #include <linux/pm_runtime.h>
15e3861d91SShunqian Zheng #include <linux/regulator/consumer.h>
16e3861d91SShunqian Zheng #include <linux/sysfs.h>
17e3861d91SShunqian Zheng #include <media/media-entity.h>
18e3861d91SShunqian Zheng #include <media/v4l2-async.h>
19e3861d91SShunqian Zheng #include <media/v4l2-ctrls.h>
2036cc66b0SLuca Weiss #include <media/v4l2-fwnode.h>
21e3861d91SShunqian Zheng #include <media/v4l2-subdev.h>
22e3861d91SShunqian Zheng 
23e3861d91SShunqian Zheng #define CHIP_ID				0x2685
24e3861d91SShunqian Zheng #define OV2685_REG_CHIP_ID		0x300a
25e3861d91SShunqian Zheng 
26e3861d91SShunqian Zheng #define OV2685_XVCLK_FREQ		24000000
27e3861d91SShunqian Zheng 
28e3861d91SShunqian Zheng #define REG_SC_CTRL_MODE		0x0100
29e3861d91SShunqian Zheng #define     SC_CTRL_MODE_STANDBY	0x0
30e3861d91SShunqian Zheng #define     SC_CTRL_MODE_STREAMING	BIT(0)
31e3861d91SShunqian Zheng 
32e3861d91SShunqian Zheng #define OV2685_REG_EXPOSURE		0x3500
33e3861d91SShunqian Zheng #define	OV2685_EXPOSURE_MIN		4
34e3861d91SShunqian Zheng #define	OV2685_EXPOSURE_STEP		1
35e3861d91SShunqian Zheng 
36e3861d91SShunqian Zheng #define OV2685_REG_VTS			0x380e
37e3861d91SShunqian Zheng #define OV2685_VTS_MAX			0x7fff
38e3861d91SShunqian Zheng 
39e3861d91SShunqian Zheng #define OV2685_REG_GAIN			0x350a
40e3861d91SShunqian Zheng #define OV2685_GAIN_MIN			0
41e3861d91SShunqian Zheng #define OV2685_GAIN_MAX			0x07ff
42e3861d91SShunqian Zheng #define OV2685_GAIN_STEP		0x1
43e3861d91SShunqian Zheng #define OV2685_GAIN_DEFAULT		0x0036
44e3861d91SShunqian Zheng 
45e3861d91SShunqian Zheng #define OV2685_REG_TEST_PATTERN		0x5080
46e3861d91SShunqian Zheng #define OV2685_TEST_PATTERN_DISABLED		0x00
47e3861d91SShunqian Zheng #define OV2685_TEST_PATTERN_COLOR_BAR		0x80
48e3861d91SShunqian Zheng #define OV2685_TEST_PATTERN_RANDOM		0x81
49e3861d91SShunqian Zheng #define OV2685_TEST_PATTERN_COLOR_BAR_FADE	0x88
50e3861d91SShunqian Zheng #define OV2685_TEST_PATTERN_BW_SQUARE		0x92
51e3861d91SShunqian Zheng #define OV2685_TEST_PATTERN_COLOR_SQUARE	0x82
52e3861d91SShunqian Zheng 
53e3861d91SShunqian Zheng #define REG_NULL			0xFFFF
54e3861d91SShunqian Zheng 
55e3861d91SShunqian Zheng #define OV2685_REG_VALUE_08BIT		1
56e3861d91SShunqian Zheng #define OV2685_REG_VALUE_16BIT		2
57e3861d91SShunqian Zheng #define OV2685_REG_VALUE_24BIT		3
58e3861d91SShunqian Zheng 
59859128abSLuca Weiss #define OV2685_NATIVE_WIDTH		1616
60859128abSLuca Weiss #define OV2685_NATIVE_HEIGHT		1216
61859128abSLuca Weiss 
62e3861d91SShunqian Zheng #define OV2685_LANES			1
63e3861d91SShunqian Zheng #define OV2685_BITS_PER_SAMPLE		10
64e3861d91SShunqian Zheng 
65e3861d91SShunqian Zheng static const char * const ov2685_supply_names[] = {
66e3861d91SShunqian Zheng 	"avdd",		/* Analog power */
67e3861d91SShunqian Zheng 	"dovdd",	/* Digital I/O power */
68e3861d91SShunqian Zheng 	"dvdd",		/* Digital core power */
69e3861d91SShunqian Zheng };
70e3861d91SShunqian Zheng 
71e3861d91SShunqian Zheng #define OV2685_NUM_SUPPLIES ARRAY_SIZE(ov2685_supply_names)
72e3861d91SShunqian Zheng 
73e3861d91SShunqian Zheng struct regval {
74e3861d91SShunqian Zheng 	u16 addr;
75e3861d91SShunqian Zheng 	u8 val;
76e3861d91SShunqian Zheng };
77e3861d91SShunqian Zheng 
78e3861d91SShunqian Zheng struct ov2685_mode {
79e3861d91SShunqian Zheng 	u32 width;
80e3861d91SShunqian Zheng 	u32 height;
81e3861d91SShunqian Zheng 	u32 exp_def;
82e3861d91SShunqian Zheng 	u32 hts_def;
83e3861d91SShunqian Zheng 	u32 vts_def;
84859128abSLuca Weiss 	const struct v4l2_rect *analog_crop;
85e3861d91SShunqian Zheng 	const struct regval *reg_list;
86e3861d91SShunqian Zheng };
87e3861d91SShunqian Zheng 
88e3861d91SShunqian Zheng struct ov2685 {
89e3861d91SShunqian Zheng 	struct i2c_client	*client;
90e3861d91SShunqian Zheng 	struct clk		*xvclk;
91e3861d91SShunqian Zheng 	struct gpio_desc	*reset_gpio;
92e3861d91SShunqian Zheng 	struct regulator_bulk_data supplies[OV2685_NUM_SUPPLIES];
93e3861d91SShunqian Zheng 
94e3861d91SShunqian Zheng 	bool			streaming;
95e3861d91SShunqian Zheng 	struct mutex		mutex;
96e3861d91SShunqian Zheng 	struct v4l2_subdev	subdev;
97e3861d91SShunqian Zheng 	struct media_pad	pad;
98e3861d91SShunqian Zheng 	struct v4l2_ctrl	*anal_gain;
99e3861d91SShunqian Zheng 	struct v4l2_ctrl	*exposure;
100e3861d91SShunqian Zheng 	struct v4l2_ctrl	*hblank;
101e3861d91SShunqian Zheng 	struct v4l2_ctrl	*vblank;
102e3861d91SShunqian Zheng 	struct v4l2_ctrl	*test_pattern;
103e3861d91SShunqian Zheng 	struct v4l2_ctrl_handler ctrl_handler;
104e3861d91SShunqian Zheng 
105e3861d91SShunqian Zheng 	const struct ov2685_mode *cur_mode;
106e3861d91SShunqian Zheng };
107e3861d91SShunqian Zheng 
108e3861d91SShunqian Zheng #define to_ov2685(sd) container_of(sd, struct ov2685, subdev)
109e3861d91SShunqian Zheng 
110e3861d91SShunqian Zheng /* PLL settings bases on 24M xvclk */
111e3861d91SShunqian Zheng static struct regval ov2685_1600x1200_regs[] = {
112e3861d91SShunqian Zheng 	{0x0103, 0x01},
113e3861d91SShunqian Zheng 	{0x0100, 0x00},
114e3861d91SShunqian Zheng 	{0x3002, 0x00},
115e3861d91SShunqian Zheng 	{0x3016, 0x1c},
116e3861d91SShunqian Zheng 	{0x3018, 0x44},
117e3861d91SShunqian Zheng 	{0x301d, 0xf0},
118e3861d91SShunqian Zheng 	{0x3020, 0x00},
119e3861d91SShunqian Zheng 	{0x3082, 0x37},
120e3861d91SShunqian Zheng 	{0x3083, 0x03},
121e3861d91SShunqian Zheng 	{0x3084, 0x09},
122e3861d91SShunqian Zheng 	{0x3085, 0x04},
123e3861d91SShunqian Zheng 	{0x3086, 0x00},
124e3861d91SShunqian Zheng 	{0x3087, 0x00},
125e3861d91SShunqian Zheng 	{0x3501, 0x4e},
126e3861d91SShunqian Zheng 	{0x3502, 0xe0},
12767f2219cSShunqian Zheng 	{0x3503, 0x27},
128e3861d91SShunqian Zheng 	{0x350b, 0x36},
129e3861d91SShunqian Zheng 	{0x3600, 0xb4},
130e3861d91SShunqian Zheng 	{0x3603, 0x35},
131e3861d91SShunqian Zheng 	{0x3604, 0x24},
132e3861d91SShunqian Zheng 	{0x3605, 0x00},
133e3861d91SShunqian Zheng 	{0x3620, 0x24},
134e3861d91SShunqian Zheng 	{0x3621, 0x34},
135e3861d91SShunqian Zheng 	{0x3622, 0x03},
136e3861d91SShunqian Zheng 	{0x3628, 0x10},
137e3861d91SShunqian Zheng 	{0x3705, 0x3c},
138e3861d91SShunqian Zheng 	{0x370a, 0x21},
139e3861d91SShunqian Zheng 	{0x370c, 0x50},
140e3861d91SShunqian Zheng 	{0x370d, 0xc0},
141e3861d91SShunqian Zheng 	{0x3717, 0x58},
142e3861d91SShunqian Zheng 	{0x3718, 0x80},
143e3861d91SShunqian Zheng 	{0x3720, 0x00},
144e3861d91SShunqian Zheng 	{0x3721, 0x09},
145e3861d91SShunqian Zheng 	{0x3722, 0x06},
146e3861d91SShunqian Zheng 	{0x3723, 0x59},
147e3861d91SShunqian Zheng 	{0x3738, 0x99},
148e3861d91SShunqian Zheng 	{0x3781, 0x80},
149e3861d91SShunqian Zheng 	{0x3784, 0x0c},
150e3861d91SShunqian Zheng 	{0x3789, 0x60},
151e3861d91SShunqian Zheng 	{0x3800, 0x00},
152e3861d91SShunqian Zheng 	{0x3801, 0x00},
153e3861d91SShunqian Zheng 	{0x3802, 0x00},
154e3861d91SShunqian Zheng 	{0x3803, 0x00},
155e3861d91SShunqian Zheng 	{0x3804, 0x06},
156e3861d91SShunqian Zheng 	{0x3805, 0x4f},
157e3861d91SShunqian Zheng 	{0x3806, 0x04},
158e3861d91SShunqian Zheng 	{0x3807, 0xbf},
159e3861d91SShunqian Zheng 	{0x3808, 0x06},
160e3861d91SShunqian Zheng 	{0x3809, 0x40},
161e3861d91SShunqian Zheng 	{0x380a, 0x04},
162e3861d91SShunqian Zheng 	{0x380b, 0xb0},
163e3861d91SShunqian Zheng 	{0x380c, 0x06},
164e3861d91SShunqian Zheng 	{0x380d, 0xa4},
165e3861d91SShunqian Zheng 	{0x380e, 0x05},
166e3861d91SShunqian Zheng 	{0x380f, 0x0e},
167e3861d91SShunqian Zheng 	{0x3810, 0x00},
168e3861d91SShunqian Zheng 	{0x3811, 0x08},
169e3861d91SShunqian Zheng 	{0x3812, 0x00},
170e3861d91SShunqian Zheng 	{0x3813, 0x08},
171e3861d91SShunqian Zheng 	{0x3814, 0x11},
172e3861d91SShunqian Zheng 	{0x3815, 0x11},
173e3861d91SShunqian Zheng 	{0x3819, 0x04},
174e3861d91SShunqian Zheng 	{0x3820, 0xc0},
175e3861d91SShunqian Zheng 	{0x3821, 0x00},
176e3861d91SShunqian Zheng 	{0x3a06, 0x01},
177e3861d91SShunqian Zheng 	{0x3a07, 0x84},
178e3861d91SShunqian Zheng 	{0x3a08, 0x01},
179e3861d91SShunqian Zheng 	{0x3a09, 0x43},
180e3861d91SShunqian Zheng 	{0x3a0a, 0x24},
181e3861d91SShunqian Zheng 	{0x3a0b, 0x60},
182e3861d91SShunqian Zheng 	{0x3a0c, 0x28},
183e3861d91SShunqian Zheng 	{0x3a0d, 0x60},
184e3861d91SShunqian Zheng 	{0x3a0e, 0x04},
185e3861d91SShunqian Zheng 	{0x3a0f, 0x8c},
186e3861d91SShunqian Zheng 	{0x3a10, 0x05},
187e3861d91SShunqian Zheng 	{0x3a11, 0x0c},
188e3861d91SShunqian Zheng 	{0x4000, 0x81},
189e3861d91SShunqian Zheng 	{0x4001, 0x40},
190e3861d91SShunqian Zheng 	{0x4008, 0x02},
191e3861d91SShunqian Zheng 	{0x4009, 0x09},
192e3861d91SShunqian Zheng 	{0x4300, 0x00},
193e3861d91SShunqian Zheng 	{0x430e, 0x00},
194e3861d91SShunqian Zheng 	{0x4602, 0x02},
195e3861d91SShunqian Zheng 	{0x481b, 0x40},
196e3861d91SShunqian Zheng 	{0x481f, 0x40},
197e3861d91SShunqian Zheng 	{0x4837, 0x18},
198e3861d91SShunqian Zheng 	{0x5000, 0x1f},
199e3861d91SShunqian Zheng 	{0x5001, 0x05},
200e3861d91SShunqian Zheng 	{0x5002, 0x30},
201e3861d91SShunqian Zheng 	{0x5003, 0x04},
202e3861d91SShunqian Zheng 	{0x5004, 0x00},
203e3861d91SShunqian Zheng 	{0x5005, 0x0c},
204e3861d91SShunqian Zheng 	{0x5280, 0x15},
205e3861d91SShunqian Zheng 	{0x5281, 0x06},
206e3861d91SShunqian Zheng 	{0x5282, 0x06},
207e3861d91SShunqian Zheng 	{0x5283, 0x08},
208e3861d91SShunqian Zheng 	{0x5284, 0x1c},
209e3861d91SShunqian Zheng 	{0x5285, 0x1c},
210e3861d91SShunqian Zheng 	{0x5286, 0x20},
211e3861d91SShunqian Zheng 	{0x5287, 0x10},
212e3861d91SShunqian Zheng 	{REG_NULL, 0x00}
213e3861d91SShunqian Zheng };
214e3861d91SShunqian Zheng 
215e3861d91SShunqian Zheng #define OV2685_LINK_FREQ_330MHZ		330000000
216e3861d91SShunqian Zheng static const s64 link_freq_menu_items[] = {
217e3861d91SShunqian Zheng 	OV2685_LINK_FREQ_330MHZ
218e3861d91SShunqian Zheng };
219e3861d91SShunqian Zheng 
220e3861d91SShunqian Zheng static const char * const ov2685_test_pattern_menu[] = {
221e3861d91SShunqian Zheng 	"Disabled",
222e3861d91SShunqian Zheng 	"Color Bar",
223e3861d91SShunqian Zheng 	"Color Bar FADE",
224e3861d91SShunqian Zheng 	"Random Data",
225e3861d91SShunqian Zheng 	"Black White Square",
226e3861d91SShunqian Zheng 	"Color Square"
227e3861d91SShunqian Zheng };
228e3861d91SShunqian Zheng 
229e3861d91SShunqian Zheng static const int ov2685_test_pattern_val[] = {
230e3861d91SShunqian Zheng 	OV2685_TEST_PATTERN_DISABLED,
231e3861d91SShunqian Zheng 	OV2685_TEST_PATTERN_COLOR_BAR,
232e3861d91SShunqian Zheng 	OV2685_TEST_PATTERN_COLOR_BAR_FADE,
233e3861d91SShunqian Zheng 	OV2685_TEST_PATTERN_RANDOM,
234e3861d91SShunqian Zheng 	OV2685_TEST_PATTERN_BW_SQUARE,
235e3861d91SShunqian Zheng 	OV2685_TEST_PATTERN_COLOR_SQUARE,
236e3861d91SShunqian Zheng };
237e3861d91SShunqian Zheng 
238859128abSLuca Weiss static const struct v4l2_rect ov2685_analog_crop = {
239859128abSLuca Weiss 	.left	= 8,
240859128abSLuca Weiss 	.top	= 8,
241859128abSLuca Weiss 	.width	= 1600,
242859128abSLuca Weiss 	.height	= 1200,
243859128abSLuca Weiss };
244859128abSLuca Weiss 
245e3861d91SShunqian Zheng static const struct ov2685_mode supported_modes[] = {
246e3861d91SShunqian Zheng 	{
247e3861d91SShunqian Zheng 		.width = 1600,
248e3861d91SShunqian Zheng 		.height = 1200,
249e3861d91SShunqian Zheng 		.exp_def = 0x04ee,
250e3861d91SShunqian Zheng 		.hts_def = 0x06a4,
251e3861d91SShunqian Zheng 		.vts_def = 0x050e,
252859128abSLuca Weiss 		.analog_crop = &ov2685_analog_crop,
253e3861d91SShunqian Zheng 		.reg_list = ov2685_1600x1200_regs,
254e3861d91SShunqian Zheng 	},
255e3861d91SShunqian Zheng };
256e3861d91SShunqian Zheng 
257e3861d91SShunqian Zheng /* Write registers up to 4 at a time */
ov2685_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)258e3861d91SShunqian Zheng static int ov2685_write_reg(struct i2c_client *client, u16 reg,
259e3861d91SShunqian Zheng 			    u32 len, u32 val)
260e3861d91SShunqian Zheng {
261e3861d91SShunqian Zheng 	u32 val_i, buf_i;
262e3861d91SShunqian Zheng 	u8 buf[6];
263e3861d91SShunqian Zheng 	u8 *val_p;
264e3861d91SShunqian Zheng 	__be32 val_be;
265e3861d91SShunqian Zheng 
266e3861d91SShunqian Zheng 	if (len > 4)
267e3861d91SShunqian Zheng 		return -EINVAL;
268e3861d91SShunqian Zheng 
269e3861d91SShunqian Zheng 	buf[0] = reg >> 8;
270e3861d91SShunqian Zheng 	buf[1] = reg & 0xff;
271e3861d91SShunqian Zheng 
272e3861d91SShunqian Zheng 	val_be = cpu_to_be32(val);
273e3861d91SShunqian Zheng 	val_p = (u8 *)&val_be;
274e3861d91SShunqian Zheng 	buf_i = 2;
275e3861d91SShunqian Zheng 	val_i = 4 - len;
276e3861d91SShunqian Zheng 
277e3861d91SShunqian Zheng 	while (val_i < 4)
278e3861d91SShunqian Zheng 		buf[buf_i++] = val_p[val_i++];
279e3861d91SShunqian Zheng 
280e3861d91SShunqian Zheng 	if (i2c_master_send(client, buf, len + 2) != len + 2)
281e3861d91SShunqian Zheng 		return -EIO;
282e3861d91SShunqian Zheng 
283e3861d91SShunqian Zheng 	return 0;
284e3861d91SShunqian Zheng }
285e3861d91SShunqian Zheng 
ov2685_write_array(struct i2c_client * client,const struct regval * regs)286e3861d91SShunqian Zheng static int ov2685_write_array(struct i2c_client *client,
287e3861d91SShunqian Zheng 			      const struct regval *regs)
288e3861d91SShunqian Zheng {
289e3861d91SShunqian Zheng 	int ret = 0;
290e3861d91SShunqian Zheng 	u32 i;
291e3861d91SShunqian Zheng 
292e3861d91SShunqian Zheng 	for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
293e3861d91SShunqian Zheng 		ret = ov2685_write_reg(client, regs[i].addr,
294e3861d91SShunqian Zheng 				       OV2685_REG_VALUE_08BIT, regs[i].val);
295e3861d91SShunqian Zheng 
296e3861d91SShunqian Zheng 	return ret;
297e3861d91SShunqian Zheng }
298e3861d91SShunqian Zheng 
299e3861d91SShunqian Zheng /* Read registers up to 4 at a time */
ov2685_read_reg(struct i2c_client * client,u16 reg,u32 len,u32 * val)300e3861d91SShunqian Zheng static int ov2685_read_reg(struct i2c_client *client, u16 reg,
301e3861d91SShunqian Zheng 			   u32 len, u32 *val)
302e3861d91SShunqian Zheng {
303e3861d91SShunqian Zheng 	struct i2c_msg msgs[2];
304e3861d91SShunqian Zheng 	u8 *data_be_p;
305e3861d91SShunqian Zheng 	__be32 data_be = 0;
306e3861d91SShunqian Zheng 	__be16 reg_addr_be = cpu_to_be16(reg);
307e3861d91SShunqian Zheng 	int ret;
308e3861d91SShunqian Zheng 
309e3861d91SShunqian Zheng 	if (len > 4)
310e3861d91SShunqian Zheng 		return -EINVAL;
311e3861d91SShunqian Zheng 
312e3861d91SShunqian Zheng 	data_be_p = (u8 *)&data_be;
313e3861d91SShunqian Zheng 	/* Write register address */
314e3861d91SShunqian Zheng 	msgs[0].addr = client->addr;
315e3861d91SShunqian Zheng 	msgs[0].flags = 0;
316e3861d91SShunqian Zheng 	msgs[0].len = 2;
317e3861d91SShunqian Zheng 	msgs[0].buf = (u8 *)&reg_addr_be;
318e3861d91SShunqian Zheng 
319e3861d91SShunqian Zheng 	/* Read data from register */
320e3861d91SShunqian Zheng 	msgs[1].addr = client->addr;
321e3861d91SShunqian Zheng 	msgs[1].flags = I2C_M_RD;
322e3861d91SShunqian Zheng 	msgs[1].len = len;
323e3861d91SShunqian Zheng 	msgs[1].buf = &data_be_p[4 - len];
324e3861d91SShunqian Zheng 
325e3861d91SShunqian Zheng 	ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
326e3861d91SShunqian Zheng 	if (ret != ARRAY_SIZE(msgs))
327e3861d91SShunqian Zheng 		return -EIO;
328e3861d91SShunqian Zheng 
329e3861d91SShunqian Zheng 	*val = be32_to_cpu(data_be);
330e3861d91SShunqian Zheng 
331e3861d91SShunqian Zheng 	return 0;
332e3861d91SShunqian Zheng }
333e3861d91SShunqian Zheng 
ov2685_fill_fmt(const struct ov2685_mode * mode,struct v4l2_mbus_framefmt * fmt)334e3861d91SShunqian Zheng static void ov2685_fill_fmt(const struct ov2685_mode *mode,
335e3861d91SShunqian Zheng 			    struct v4l2_mbus_framefmt *fmt)
336e3861d91SShunqian Zheng {
337e3861d91SShunqian Zheng 	fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10;
338e3861d91SShunqian Zheng 	fmt->width = mode->width;
339e3861d91SShunqian Zheng 	fmt->height = mode->height;
340e3861d91SShunqian Zheng 	fmt->field = V4L2_FIELD_NONE;
341e3861d91SShunqian Zheng }
342e3861d91SShunqian Zheng 
ov2685_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)343e3861d91SShunqian Zheng static int ov2685_set_fmt(struct v4l2_subdev *sd,
3440d346d2aSTomi Valkeinen 			  struct v4l2_subdev_state *sd_state,
345e3861d91SShunqian Zheng 			  struct v4l2_subdev_format *fmt)
346e3861d91SShunqian Zheng {
347e3861d91SShunqian Zheng 	struct ov2685 *ov2685 = to_ov2685(sd);
348e3861d91SShunqian Zheng 	struct v4l2_mbus_framefmt *mbus_fmt = &fmt->format;
349e3861d91SShunqian Zheng 
350e3861d91SShunqian Zheng 	/* only one mode supported for now */
351e3861d91SShunqian Zheng 	ov2685_fill_fmt(ov2685->cur_mode, mbus_fmt);
352e3861d91SShunqian Zheng 
353e3861d91SShunqian Zheng 	return 0;
354e3861d91SShunqian Zheng }
355e3861d91SShunqian Zheng 
ov2685_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)356e3861d91SShunqian Zheng static int ov2685_get_fmt(struct v4l2_subdev *sd,
3570d346d2aSTomi Valkeinen 			  struct v4l2_subdev_state *sd_state,
358e3861d91SShunqian Zheng 			  struct v4l2_subdev_format *fmt)
359e3861d91SShunqian Zheng {
360e3861d91SShunqian Zheng 	struct ov2685 *ov2685 = to_ov2685(sd);
361e3861d91SShunqian Zheng 	struct v4l2_mbus_framefmt *mbus_fmt = &fmt->format;
362e3861d91SShunqian Zheng 
363e3861d91SShunqian Zheng 	ov2685_fill_fmt(ov2685->cur_mode, mbus_fmt);
364e3861d91SShunqian Zheng 
365e3861d91SShunqian Zheng 	return 0;
366e3861d91SShunqian Zheng }
367e3861d91SShunqian Zheng 
ov2685_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)368e3861d91SShunqian Zheng static int ov2685_enum_mbus_code(struct v4l2_subdev *sd,
3690d346d2aSTomi Valkeinen 				 struct v4l2_subdev_state *sd_state,
370e3861d91SShunqian Zheng 				 struct v4l2_subdev_mbus_code_enum *code)
371e3861d91SShunqian Zheng {
372e3861d91SShunqian Zheng 	if (code->index >= ARRAY_SIZE(supported_modes))
373e3861d91SShunqian Zheng 		return -EINVAL;
374e3861d91SShunqian Zheng 
375e3861d91SShunqian Zheng 	code->code = MEDIA_BUS_FMT_SBGGR10_1X10;
376e3861d91SShunqian Zheng 
377e3861d91SShunqian Zheng 	return 0;
378e3861d91SShunqian Zheng }
379e3861d91SShunqian Zheng 
ov2685_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_size_enum * fse)380e3861d91SShunqian Zheng static int ov2685_enum_frame_sizes(struct v4l2_subdev *sd,
3810d346d2aSTomi Valkeinen 				   struct v4l2_subdev_state *sd_state,
382e3861d91SShunqian Zheng 				   struct v4l2_subdev_frame_size_enum *fse)
383e3861d91SShunqian Zheng {
384e3861d91SShunqian Zheng 	int index = fse->index;
385e3861d91SShunqian Zheng 
386e3861d91SShunqian Zheng 	if (index >= ARRAY_SIZE(supported_modes))
387e3861d91SShunqian Zheng 		return -EINVAL;
388e3861d91SShunqian Zheng 
389e3861d91SShunqian Zheng 	fse->code = MEDIA_BUS_FMT_SBGGR10_1X10;
390e3861d91SShunqian Zheng 
391e3861d91SShunqian Zheng 	fse->min_width  = supported_modes[index].width;
392e3861d91SShunqian Zheng 	fse->max_width  = supported_modes[index].width;
393e3861d91SShunqian Zheng 	fse->max_height = supported_modes[index].height;
394e3861d91SShunqian Zheng 	fse->min_height = supported_modes[index].height;
395e3861d91SShunqian Zheng 
396e3861d91SShunqian Zheng 	return 0;
397e3861d91SShunqian Zheng }
398e3861d91SShunqian Zheng 
399859128abSLuca Weiss static const struct v4l2_rect *
__ov2685_get_pad_crop(struct ov2685 * ov2685,struct v4l2_subdev_state * state,unsigned int pad,enum v4l2_subdev_format_whence which)400859128abSLuca Weiss __ov2685_get_pad_crop(struct ov2685 *ov2685,
401859128abSLuca Weiss 		      struct v4l2_subdev_state *state, unsigned int pad,
402859128abSLuca Weiss 		      enum v4l2_subdev_format_whence which)
403859128abSLuca Weiss {
404859128abSLuca Weiss 	const struct ov2685_mode *mode = ov2685->cur_mode;
405859128abSLuca Weiss 
406859128abSLuca Weiss 	switch (which) {
407859128abSLuca Weiss 	case V4L2_SUBDEV_FORMAT_TRY:
408859128abSLuca Weiss 		return v4l2_subdev_get_try_crop(&ov2685->subdev, state, pad);
409859128abSLuca Weiss 	case V4L2_SUBDEV_FORMAT_ACTIVE:
410859128abSLuca Weiss 		return mode->analog_crop;
411859128abSLuca Weiss 	}
412859128abSLuca Weiss 
413859128abSLuca Weiss 	return NULL;
414859128abSLuca Weiss }
415859128abSLuca Weiss 
ov2685_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_selection * sel)416859128abSLuca Weiss static int ov2685_get_selection(struct v4l2_subdev *sd,
417859128abSLuca Weiss 				struct v4l2_subdev_state *sd_state,
418859128abSLuca Weiss 				struct v4l2_subdev_selection *sel)
419859128abSLuca Weiss {
420859128abSLuca Weiss 	struct ov2685 *ov2685 = to_ov2685(sd);
421859128abSLuca Weiss 
422859128abSLuca Weiss 	switch (sel->target) {
423859128abSLuca Weiss 	case V4L2_SEL_TGT_CROP:
424859128abSLuca Weiss 		mutex_lock(&ov2685->mutex);
425859128abSLuca Weiss 		sel->r = *__ov2685_get_pad_crop(ov2685, sd_state, sel->pad,
426859128abSLuca Weiss 				sel->which);
427859128abSLuca Weiss 		mutex_unlock(&ov2685->mutex);
428859128abSLuca Weiss 		break;
429859128abSLuca Weiss 	case V4L2_SEL_TGT_NATIVE_SIZE:
430859128abSLuca Weiss 	case V4L2_SEL_TGT_CROP_BOUNDS:
431859128abSLuca Weiss 		sel->r.top = 0;
432859128abSLuca Weiss 		sel->r.left = 0;
433859128abSLuca Weiss 		sel->r.width = OV2685_NATIVE_WIDTH;
434859128abSLuca Weiss 		sel->r.height = OV2685_NATIVE_HEIGHT;
435859128abSLuca Weiss 		break;
436859128abSLuca Weiss 	case V4L2_SEL_TGT_CROP_DEFAULT:
437859128abSLuca Weiss 		sel->r = ov2685_analog_crop;
438859128abSLuca Weiss 		break;
439859128abSLuca Weiss 	default:
440859128abSLuca Weiss 		return -EINVAL;
441859128abSLuca Weiss 	}
442859128abSLuca Weiss 
443859128abSLuca Weiss 	return 0;
444859128abSLuca Weiss }
445859128abSLuca Weiss 
446e3861d91SShunqian Zheng /* Calculate the delay in us by clock rate and clock cycles */
ov2685_cal_delay(u32 cycles)447e3861d91SShunqian Zheng static inline u32 ov2685_cal_delay(u32 cycles)
448e3861d91SShunqian Zheng {
449e3861d91SShunqian Zheng 	return DIV_ROUND_UP(cycles, OV2685_XVCLK_FREQ / 1000 / 1000);
450e3861d91SShunqian Zheng }
451e3861d91SShunqian Zheng 
__ov2685_power_on(struct ov2685 * ov2685)452e3861d91SShunqian Zheng static int __ov2685_power_on(struct ov2685 *ov2685)
453e3861d91SShunqian Zheng {
454e3861d91SShunqian Zheng 	int ret;
455e3861d91SShunqian Zheng 	u32 delay_us;
456e3861d91SShunqian Zheng 	struct device *dev = &ov2685->client->dev;
457e3861d91SShunqian Zheng 
458e3861d91SShunqian Zheng 	ret = clk_prepare_enable(ov2685->xvclk);
459e3861d91SShunqian Zheng 	if (ret < 0) {
460e3861d91SShunqian Zheng 		dev_err(dev, "Failed to enable xvclk\n");
461e3861d91SShunqian Zheng 		return ret;
462e3861d91SShunqian Zheng 	}
463e3861d91SShunqian Zheng 
464e3861d91SShunqian Zheng 	gpiod_set_value_cansleep(ov2685->reset_gpio, 1);
465e3861d91SShunqian Zheng 
466e3861d91SShunqian Zheng 	ret = regulator_bulk_enable(OV2685_NUM_SUPPLIES, ov2685->supplies);
467e3861d91SShunqian Zheng 	if (ret < 0) {
468e3861d91SShunqian Zheng 		dev_err(dev, "Failed to enable regulators\n");
469e3861d91SShunqian Zheng 		goto disable_clk;
470e3861d91SShunqian Zheng 	}
471e3861d91SShunqian Zheng 
472e3861d91SShunqian Zheng 	/* The minimum delay between power supplies and reset rising can be 0 */
473e3861d91SShunqian Zheng 	gpiod_set_value_cansleep(ov2685->reset_gpio, 0);
474e3861d91SShunqian Zheng 	/* 8192 xvclk cycles prior to the first SCCB transaction */
475e3861d91SShunqian Zheng 	delay_us = ov2685_cal_delay(8192);
476e3861d91SShunqian Zheng 	usleep_range(delay_us, delay_us * 2);
477e3861d91SShunqian Zheng 
478e3861d91SShunqian Zheng 	/* HACK: ov2685 would output messy data after reset(R0103),
479e3861d91SShunqian Zheng 	 * writing register before .s_stream() as a workaround
480e3861d91SShunqian Zheng 	 */
481e3861d91SShunqian Zheng 	ret = ov2685_write_array(ov2685->client, ov2685->cur_mode->reg_list);
48274b506cbSLuca Weiss 	if (ret) {
48374b506cbSLuca Weiss 		dev_err(dev, "Failed to set regs for power on\n");
484e3861d91SShunqian Zheng 		goto disable_supplies;
48574b506cbSLuca Weiss 	}
486e3861d91SShunqian Zheng 
487e3861d91SShunqian Zheng 	return 0;
488e3861d91SShunqian Zheng 
489e3861d91SShunqian Zheng disable_supplies:
490e3861d91SShunqian Zheng 	regulator_bulk_disable(OV2685_NUM_SUPPLIES, ov2685->supplies);
491e3861d91SShunqian Zheng disable_clk:
492e3861d91SShunqian Zheng 	clk_disable_unprepare(ov2685->xvclk);
493e3861d91SShunqian Zheng 
494e3861d91SShunqian Zheng 	return ret;
495e3861d91SShunqian Zheng }
496e3861d91SShunqian Zheng 
__ov2685_power_off(struct ov2685 * ov2685)497e3861d91SShunqian Zheng static void __ov2685_power_off(struct ov2685 *ov2685)
498e3861d91SShunqian Zheng {
499e3861d91SShunqian Zheng 	/* 512 xvclk cycles after the last SCCB transaction or MIPI frame end */
500e3861d91SShunqian Zheng 	u32 delay_us = ov2685_cal_delay(512);
501e3861d91SShunqian Zheng 
502e3861d91SShunqian Zheng 	usleep_range(delay_us, delay_us * 2);
503e3861d91SShunqian Zheng 	clk_disable_unprepare(ov2685->xvclk);
504e3861d91SShunqian Zheng 	gpiod_set_value_cansleep(ov2685->reset_gpio, 1);
505e3861d91SShunqian Zheng 	regulator_bulk_disable(OV2685_NUM_SUPPLIES, ov2685->supplies);
506e3861d91SShunqian Zheng }
507e3861d91SShunqian Zheng 
ov2685_s_stream(struct v4l2_subdev * sd,int on)508e3861d91SShunqian Zheng static int ov2685_s_stream(struct v4l2_subdev *sd, int on)
509e3861d91SShunqian Zheng {
510e3861d91SShunqian Zheng 	struct ov2685 *ov2685 = to_ov2685(sd);
511e3861d91SShunqian Zheng 	struct i2c_client *client = ov2685->client;
512e3861d91SShunqian Zheng 	int ret = 0;
513e3861d91SShunqian Zheng 
514e3861d91SShunqian Zheng 	mutex_lock(&ov2685->mutex);
515e3861d91SShunqian Zheng 
516e3861d91SShunqian Zheng 	on = !!on;
517e3861d91SShunqian Zheng 	if (on == ov2685->streaming)
518e3861d91SShunqian Zheng 		goto unlock_and_return;
519e3861d91SShunqian Zheng 
520e3861d91SShunqian Zheng 	if (on) {
521c679b236SMauro Carvalho Chehab 		ret = pm_runtime_resume_and_get(&ov2685->client->dev);
522c679b236SMauro Carvalho Chehab 		if (ret < 0)
523e3861d91SShunqian Zheng 			goto unlock_and_return;
524c679b236SMauro Carvalho Chehab 
525e3861d91SShunqian Zheng 		ret = __v4l2_ctrl_handler_setup(&ov2685->ctrl_handler);
526e3861d91SShunqian Zheng 		if (ret) {
527e3861d91SShunqian Zheng 			pm_runtime_put(&client->dev);
528e3861d91SShunqian Zheng 			goto unlock_and_return;
529e3861d91SShunqian Zheng 		}
530e3861d91SShunqian Zheng 		ret = ov2685_write_reg(client, REG_SC_CTRL_MODE,
531e3861d91SShunqian Zheng 				OV2685_REG_VALUE_08BIT, SC_CTRL_MODE_STREAMING);
532e3861d91SShunqian Zheng 		if (ret) {
533e3861d91SShunqian Zheng 			pm_runtime_put(&client->dev);
534e3861d91SShunqian Zheng 			goto unlock_and_return;
535e3861d91SShunqian Zheng 		}
536e3861d91SShunqian Zheng 	} else {
537e3861d91SShunqian Zheng 		ov2685_write_reg(client, REG_SC_CTRL_MODE,
538e3861d91SShunqian Zheng 				OV2685_REG_VALUE_08BIT, SC_CTRL_MODE_STANDBY);
539e3861d91SShunqian Zheng 		pm_runtime_put(&ov2685->client->dev);
540e3861d91SShunqian Zheng 	}
541e3861d91SShunqian Zheng 
542e3861d91SShunqian Zheng 	ov2685->streaming = on;
543e3861d91SShunqian Zheng 
544e3861d91SShunqian Zheng unlock_and_return:
545e3861d91SShunqian Zheng 	mutex_unlock(&ov2685->mutex);
546e3861d91SShunqian Zheng 
547e3861d91SShunqian Zheng 	return ret;
548e3861d91SShunqian Zheng }
549e3861d91SShunqian Zheng 
550e3861d91SShunqian Zheng #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
ov2685_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)551e3861d91SShunqian Zheng static int ov2685_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
552e3861d91SShunqian Zheng {
553e3861d91SShunqian Zheng 	struct ov2685 *ov2685 = to_ov2685(sd);
554e3861d91SShunqian Zheng 	struct v4l2_mbus_framefmt *try_fmt;
555e3861d91SShunqian Zheng 
556e3861d91SShunqian Zheng 	mutex_lock(&ov2685->mutex);
557e3861d91SShunqian Zheng 
5580d346d2aSTomi Valkeinen 	try_fmt = v4l2_subdev_get_try_format(sd, fh->state, 0);
559e3861d91SShunqian Zheng 	/* Initialize try_fmt */
560e3861d91SShunqian Zheng 	ov2685_fill_fmt(&supported_modes[0], try_fmt);
561e3861d91SShunqian Zheng 
562e3861d91SShunqian Zheng 	mutex_unlock(&ov2685->mutex);
563e3861d91SShunqian Zheng 
564e3861d91SShunqian Zheng 	return 0;
565e3861d91SShunqian Zheng }
566e3861d91SShunqian Zheng #endif
567e3861d91SShunqian Zheng 
ov2685_runtime_resume(struct device * dev)56815ea2df9SArnd Bergmann static int __maybe_unused ov2685_runtime_resume(struct device *dev)
569e3861d91SShunqian Zheng {
570dab24a22SKrzysztof Kozlowski 	struct v4l2_subdev *sd = dev_get_drvdata(dev);
571e3861d91SShunqian Zheng 	struct ov2685 *ov2685 = to_ov2685(sd);
572e3861d91SShunqian Zheng 
573e3861d91SShunqian Zheng 	return __ov2685_power_on(ov2685);
574e3861d91SShunqian Zheng }
575e3861d91SShunqian Zheng 
ov2685_runtime_suspend(struct device * dev)57615ea2df9SArnd Bergmann static int __maybe_unused ov2685_runtime_suspend(struct device *dev)
577e3861d91SShunqian Zheng {
578dab24a22SKrzysztof Kozlowski 	struct v4l2_subdev *sd = dev_get_drvdata(dev);
579e3861d91SShunqian Zheng 	struct ov2685 *ov2685 = to_ov2685(sd);
580e3861d91SShunqian Zheng 
581e3861d91SShunqian Zheng 	__ov2685_power_off(ov2685);
582e3861d91SShunqian Zheng 
583e3861d91SShunqian Zheng 	return 0;
584e3861d91SShunqian Zheng }
585e3861d91SShunqian Zheng 
586e3861d91SShunqian Zheng static const struct dev_pm_ops ov2685_pm_ops = {
587e3861d91SShunqian Zheng 	SET_RUNTIME_PM_OPS(ov2685_runtime_suspend,
588e3861d91SShunqian Zheng 			   ov2685_runtime_resume, NULL)
589e3861d91SShunqian Zheng };
590e3861d91SShunqian Zheng 
ov2685_set_ctrl(struct v4l2_ctrl * ctrl)591e3861d91SShunqian Zheng static int ov2685_set_ctrl(struct v4l2_ctrl *ctrl)
592e3861d91SShunqian Zheng {
593e3861d91SShunqian Zheng 	struct ov2685 *ov2685 = container_of(ctrl->handler,
594e3861d91SShunqian Zheng 					     struct ov2685, ctrl_handler);
595e3861d91SShunqian Zheng 	struct i2c_client *client = ov2685->client;
596e3861d91SShunqian Zheng 	s64 max_expo;
597e3861d91SShunqian Zheng 	int ret;
598e3861d91SShunqian Zheng 
599e3861d91SShunqian Zheng 	/* Propagate change of current control to all related controls */
600e3861d91SShunqian Zheng 	switch (ctrl->id) {
601e3861d91SShunqian Zheng 	case V4L2_CID_VBLANK:
602e3861d91SShunqian Zheng 		/* Update max exposure while meeting expected vblanking */
603e3861d91SShunqian Zheng 		max_expo = ov2685->cur_mode->height + ctrl->val - 4;
604e3861d91SShunqian Zheng 		__v4l2_ctrl_modify_range(ov2685->exposure,
605e3861d91SShunqian Zheng 					 ov2685->exposure->minimum, max_expo,
606e3861d91SShunqian Zheng 					 ov2685->exposure->step,
607e3861d91SShunqian Zheng 					 ov2685->exposure->default_value);
608e3861d91SShunqian Zheng 		break;
609e3861d91SShunqian Zheng 	}
610e3861d91SShunqian Zheng 
6114d471563SSakari Ailus 	if (!pm_runtime_get_if_in_use(&client->dev))
612e3861d91SShunqian Zheng 		return 0;
613e3861d91SShunqian Zheng 
614e3861d91SShunqian Zheng 	switch (ctrl->id) {
615e3861d91SShunqian Zheng 	case V4L2_CID_EXPOSURE:
616e3861d91SShunqian Zheng 		ret = ov2685_write_reg(ov2685->client, OV2685_REG_EXPOSURE,
617e3861d91SShunqian Zheng 				       OV2685_REG_VALUE_24BIT, ctrl->val << 4);
618e3861d91SShunqian Zheng 		break;
619e3861d91SShunqian Zheng 	case V4L2_CID_ANALOGUE_GAIN:
620e3861d91SShunqian Zheng 		ret = ov2685_write_reg(ov2685->client, OV2685_REG_GAIN,
621e3861d91SShunqian Zheng 				       OV2685_REG_VALUE_16BIT, ctrl->val);
622e3861d91SShunqian Zheng 		break;
623e3861d91SShunqian Zheng 	case V4L2_CID_VBLANK:
624e3861d91SShunqian Zheng 		ret = ov2685_write_reg(ov2685->client, OV2685_REG_VTS,
625e3861d91SShunqian Zheng 				       OV2685_REG_VALUE_16BIT,
626e3861d91SShunqian Zheng 				       ctrl->val + ov2685->cur_mode->height);
627e3861d91SShunqian Zheng 		break;
628e3861d91SShunqian Zheng 	case V4L2_CID_TEST_PATTERN:
629e3861d91SShunqian Zheng 		ret = ov2685_write_reg(ov2685->client, OV2685_REG_TEST_PATTERN,
630e3861d91SShunqian Zheng 				       OV2685_REG_VALUE_08BIT,
631e3861d91SShunqian Zheng 				       ov2685_test_pattern_val[ctrl->val]);
632e3861d91SShunqian Zheng 		break;
633e3861d91SShunqian Zheng 	default:
634e3861d91SShunqian Zheng 		dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
635e3861d91SShunqian Zheng 			 __func__, ctrl->id, ctrl->val);
636c723001fSSakari Ailus 		ret = -EINVAL;
637e3861d91SShunqian Zheng 		break;
63826092e7eSShobhit Kukreti 	}
639e3861d91SShunqian Zheng 
640e3861d91SShunqian Zheng 	pm_runtime_put(&client->dev);
641e3861d91SShunqian Zheng 
642e3861d91SShunqian Zheng 	return ret;
643e3861d91SShunqian Zheng }
644e3861d91SShunqian Zheng 
645e3861d91SShunqian Zheng static const struct v4l2_subdev_video_ops ov2685_video_ops = {
646e3861d91SShunqian Zheng 	.s_stream = ov2685_s_stream,
647e3861d91SShunqian Zheng };
648e3861d91SShunqian Zheng 
649e3861d91SShunqian Zheng static const struct v4l2_subdev_pad_ops ov2685_pad_ops = {
650e3861d91SShunqian Zheng 	.enum_mbus_code = ov2685_enum_mbus_code,
651e3861d91SShunqian Zheng 	.enum_frame_size = ov2685_enum_frame_sizes,
652e3861d91SShunqian Zheng 	.get_fmt = ov2685_get_fmt,
653e3861d91SShunqian Zheng 	.set_fmt = ov2685_set_fmt,
654859128abSLuca Weiss 	.get_selection = ov2685_get_selection,
655859128abSLuca Weiss 	.set_selection = ov2685_get_selection,
656e3861d91SShunqian Zheng };
657e3861d91SShunqian Zheng 
658e3861d91SShunqian Zheng static const struct v4l2_subdev_ops ov2685_subdev_ops = {
659e3861d91SShunqian Zheng 	.video	= &ov2685_video_ops,
660e3861d91SShunqian Zheng 	.pad	= &ov2685_pad_ops,
661e3861d91SShunqian Zheng };
662e3861d91SShunqian Zheng 
663e3861d91SShunqian Zheng #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
664e3861d91SShunqian Zheng static const struct v4l2_subdev_internal_ops ov2685_internal_ops = {
665e3861d91SShunqian Zheng 	.open = ov2685_open,
666e3861d91SShunqian Zheng };
667e3861d91SShunqian Zheng #endif
668e3861d91SShunqian Zheng 
669e3861d91SShunqian Zheng static const struct v4l2_ctrl_ops ov2685_ctrl_ops = {
670e3861d91SShunqian Zheng 	.s_ctrl = ov2685_set_ctrl,
671e3861d91SShunqian Zheng };
672e3861d91SShunqian Zheng 
ov2685_initialize_controls(struct ov2685 * ov2685)673e3861d91SShunqian Zheng static int ov2685_initialize_controls(struct ov2685 *ov2685)
674e3861d91SShunqian Zheng {
675e3861d91SShunqian Zheng 	const struct ov2685_mode *mode;
676e3861d91SShunqian Zheng 	struct v4l2_ctrl_handler *handler;
677e3861d91SShunqian Zheng 	struct v4l2_ctrl *ctrl;
67836cc66b0SLuca Weiss 	struct v4l2_fwnode_device_properties props;
679e3861d91SShunqian Zheng 	u64 exposure_max;
680e3861d91SShunqian Zheng 	u32 pixel_rate, h_blank;
681e3861d91SShunqian Zheng 	int ret;
682e3861d91SShunqian Zheng 
683e3861d91SShunqian Zheng 	handler = &ov2685->ctrl_handler;
684e3861d91SShunqian Zheng 	mode = ov2685->cur_mode;
68536cc66b0SLuca Weiss 	ret = v4l2_ctrl_handler_init(handler, 10);
686e3861d91SShunqian Zheng 	if (ret)
687e3861d91SShunqian Zheng 		return ret;
688e3861d91SShunqian Zheng 	handler->lock = &ov2685->mutex;
689e3861d91SShunqian Zheng 
690e3861d91SShunqian Zheng 	ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
691e3861d91SShunqian Zheng 				      0, 0, link_freq_menu_items);
692e3861d91SShunqian Zheng 	if (ctrl)
693e3861d91SShunqian Zheng 		ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
694e3861d91SShunqian Zheng 
695e3861d91SShunqian Zheng 	pixel_rate = (link_freq_menu_items[0] * 2 * OV2685_LANES) /
696e3861d91SShunqian Zheng 		     OV2685_BITS_PER_SAMPLE;
697e3861d91SShunqian Zheng 	v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
698e3861d91SShunqian Zheng 			  0, pixel_rate, 1, pixel_rate);
699e3861d91SShunqian Zheng 
700e3861d91SShunqian Zheng 	h_blank = mode->hts_def - mode->width;
701e3861d91SShunqian Zheng 	ov2685->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
702e3861d91SShunqian Zheng 				h_blank, h_blank, 1, h_blank);
703e3861d91SShunqian Zheng 	if (ov2685->hblank)
704e3861d91SShunqian Zheng 		ov2685->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
705e3861d91SShunqian Zheng 
706e3861d91SShunqian Zheng 	ov2685->vblank = v4l2_ctrl_new_std(handler, &ov2685_ctrl_ops,
707e3861d91SShunqian Zheng 				V4L2_CID_VBLANK, mode->vts_def - mode->height,
708e3861d91SShunqian Zheng 				OV2685_VTS_MAX - mode->height, 1,
709e3861d91SShunqian Zheng 				mode->vts_def - mode->height);
710e3861d91SShunqian Zheng 
711e3861d91SShunqian Zheng 	exposure_max = mode->vts_def - 4;
712e3861d91SShunqian Zheng 	ov2685->exposure = v4l2_ctrl_new_std(handler, &ov2685_ctrl_ops,
713e3861d91SShunqian Zheng 				V4L2_CID_EXPOSURE, OV2685_EXPOSURE_MIN,
714e3861d91SShunqian Zheng 				exposure_max, OV2685_EXPOSURE_STEP,
715e3861d91SShunqian Zheng 				mode->exp_def);
716e3861d91SShunqian Zheng 
717e3861d91SShunqian Zheng 	ov2685->anal_gain = v4l2_ctrl_new_std(handler, &ov2685_ctrl_ops,
718e3861d91SShunqian Zheng 				V4L2_CID_ANALOGUE_GAIN, OV2685_GAIN_MIN,
719e3861d91SShunqian Zheng 				OV2685_GAIN_MAX, OV2685_GAIN_STEP,
720e3861d91SShunqian Zheng 				OV2685_GAIN_DEFAULT);
721e3861d91SShunqian Zheng 
722e3861d91SShunqian Zheng 	ov2685->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
723e3861d91SShunqian Zheng 				&ov2685_ctrl_ops, V4L2_CID_TEST_PATTERN,
724e3861d91SShunqian Zheng 				ARRAY_SIZE(ov2685_test_pattern_menu) - 1,
725e3861d91SShunqian Zheng 				0, 0, ov2685_test_pattern_menu);
726e3861d91SShunqian Zheng 
72736cc66b0SLuca Weiss 	/* set properties from fwnode (e.g. rotation, orientation) */
72836cc66b0SLuca Weiss 	ret = v4l2_fwnode_device_parse(&ov2685->client->dev, &props);
72936cc66b0SLuca Weiss 	if (ret)
73036cc66b0SLuca Weiss 		goto err_free_handler;
73136cc66b0SLuca Weiss 
73236cc66b0SLuca Weiss 	ret = v4l2_ctrl_new_fwnode_properties(handler, &ov2685_ctrl_ops, &props);
73336cc66b0SLuca Weiss 	if (ret)
73436cc66b0SLuca Weiss 		goto err_free_handler;
73536cc66b0SLuca Weiss 
736e3861d91SShunqian Zheng 	if (handler->error) {
737e3861d91SShunqian Zheng 		ret = handler->error;
738e3861d91SShunqian Zheng 		dev_err(&ov2685->client->dev,
739e3861d91SShunqian Zheng 			"Failed to init controls(%d)\n", ret);
740e3861d91SShunqian Zheng 		goto err_free_handler;
741e3861d91SShunqian Zheng 	}
742e3861d91SShunqian Zheng 
743e3861d91SShunqian Zheng 	ov2685->subdev.ctrl_handler = handler;
744e3861d91SShunqian Zheng 
745e3861d91SShunqian Zheng 	return 0;
746e3861d91SShunqian Zheng 
747e3861d91SShunqian Zheng err_free_handler:
748e3861d91SShunqian Zheng 	v4l2_ctrl_handler_free(handler);
749e3861d91SShunqian Zheng 
750e3861d91SShunqian Zheng 	return ret;
751e3861d91SShunqian Zheng }
752e3861d91SShunqian Zheng 
ov2685_check_sensor_id(struct ov2685 * ov2685,struct i2c_client * client)753e3861d91SShunqian Zheng static int ov2685_check_sensor_id(struct ov2685 *ov2685,
754e3861d91SShunqian Zheng 				  struct i2c_client *client)
755e3861d91SShunqian Zheng {
756e3861d91SShunqian Zheng 	struct device *dev = &ov2685->client->dev;
757e3861d91SShunqian Zheng 	int ret;
758e3861d91SShunqian Zheng 	u32 id = 0;
759e3861d91SShunqian Zheng 
760e3861d91SShunqian Zheng 	ret = ov2685_read_reg(client, OV2685_REG_CHIP_ID,
761e3861d91SShunqian Zheng 			      OV2685_REG_VALUE_16BIT, &id);
762e3861d91SShunqian Zheng 	if (id != CHIP_ID) {
763e3861d91SShunqian Zheng 		dev_err(dev, "Unexpected sensor id(%04x), ret(%d)\n", id, ret);
764e3861d91SShunqian Zheng 		return ret;
765e3861d91SShunqian Zheng 	}
766e3861d91SShunqian Zheng 
767e3861d91SShunqian Zheng 	dev_info(dev, "Detected OV%04x sensor\n", CHIP_ID);
768e3861d91SShunqian Zheng 
769e3861d91SShunqian Zheng 	return 0;
770e3861d91SShunqian Zheng }
771e3861d91SShunqian Zheng 
ov2685_configure_regulators(struct ov2685 * ov2685)772e3861d91SShunqian Zheng static int ov2685_configure_regulators(struct ov2685 *ov2685)
773e3861d91SShunqian Zheng {
774e3861d91SShunqian Zheng 	int i;
775e3861d91SShunqian Zheng 
776e3861d91SShunqian Zheng 	for (i = 0; i < OV2685_NUM_SUPPLIES; i++)
777e3861d91SShunqian Zheng 		ov2685->supplies[i].supply = ov2685_supply_names[i];
778e3861d91SShunqian Zheng 
779e3861d91SShunqian Zheng 	return devm_regulator_bulk_get(&ov2685->client->dev,
780e3861d91SShunqian Zheng 				       OV2685_NUM_SUPPLIES,
781e3861d91SShunqian Zheng 				       ov2685->supplies);
782e3861d91SShunqian Zheng }
783e3861d91SShunqian Zheng 
ov2685_probe(struct i2c_client * client)7847eafbd40SUwe Kleine-König static int ov2685_probe(struct i2c_client *client)
785e3861d91SShunqian Zheng {
786e3861d91SShunqian Zheng 	struct device *dev = &client->dev;
787e3861d91SShunqian Zheng 	struct ov2685 *ov2685;
788e3861d91SShunqian Zheng 	int ret;
789e3861d91SShunqian Zheng 
790e3861d91SShunqian Zheng 	ov2685 = devm_kzalloc(dev, sizeof(*ov2685), GFP_KERNEL);
791e3861d91SShunqian Zheng 	if (!ov2685)
792e3861d91SShunqian Zheng 		return -ENOMEM;
793e3861d91SShunqian Zheng 
794e3861d91SShunqian Zheng 	ov2685->client = client;
795e3861d91SShunqian Zheng 	ov2685->cur_mode = &supported_modes[0];
796e3861d91SShunqian Zheng 
797e3861d91SShunqian Zheng 	ov2685->xvclk = devm_clk_get(dev, "xvclk");
798e3861d91SShunqian Zheng 	if (IS_ERR(ov2685->xvclk)) {
799e3861d91SShunqian Zheng 		dev_err(dev, "Failed to get xvclk\n");
800e3861d91SShunqian Zheng 		return -EINVAL;
801e3861d91SShunqian Zheng 	}
802e3861d91SShunqian Zheng 	ret = clk_set_rate(ov2685->xvclk, OV2685_XVCLK_FREQ);
803e3861d91SShunqian Zheng 	if (ret < 0) {
804e3861d91SShunqian Zheng 		dev_err(dev, "Failed to set xvclk rate (24MHz)\n");
805e3861d91SShunqian Zheng 		return ret;
806e3861d91SShunqian Zheng 	}
807e3861d91SShunqian Zheng 	if (clk_get_rate(ov2685->xvclk) != OV2685_XVCLK_FREQ)
808e3861d91SShunqian Zheng 		dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
809e3861d91SShunqian Zheng 
8100482fbb1SLuca Weiss 	ov2685->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
811e3861d91SShunqian Zheng 	if (IS_ERR(ov2685->reset_gpio)) {
812e3861d91SShunqian Zheng 		dev_err(dev, "Failed to get reset-gpios\n");
813e3861d91SShunqian Zheng 		return -EINVAL;
814e3861d91SShunqian Zheng 	}
815e3861d91SShunqian Zheng 
816e3861d91SShunqian Zheng 	ret = ov2685_configure_regulators(ov2685);
817e3861d91SShunqian Zheng 	if (ret) {
818e3861d91SShunqian Zheng 		dev_err(dev, "Failed to get power regulators\n");
819e3861d91SShunqian Zheng 		return ret;
820e3861d91SShunqian Zheng 	}
821e3861d91SShunqian Zheng 
822e3861d91SShunqian Zheng 	mutex_init(&ov2685->mutex);
823e3861d91SShunqian Zheng 	v4l2_i2c_subdev_init(&ov2685->subdev, client, &ov2685_subdev_ops);
824e3861d91SShunqian Zheng 	ret = ov2685_initialize_controls(ov2685);
825e3861d91SShunqian Zheng 	if (ret)
826e3861d91SShunqian Zheng 		goto err_destroy_mutex;
827e3861d91SShunqian Zheng 
828e3861d91SShunqian Zheng 	ret = __ov2685_power_on(ov2685);
829e3861d91SShunqian Zheng 	if (ret)
830e3861d91SShunqian Zheng 		goto err_free_handler;
831e3861d91SShunqian Zheng 
832e3861d91SShunqian Zheng 	ret = ov2685_check_sensor_id(ov2685, client);
833e3861d91SShunqian Zheng 	if (ret)
834e3861d91SShunqian Zheng 		goto err_power_off;
835e3861d91SShunqian Zheng 
836e3861d91SShunqian Zheng #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
837e3861d91SShunqian Zheng 	ov2685->subdev.internal_ops = &ov2685_internal_ops;
838e3861d91SShunqian Zheng 	ov2685->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
839e3861d91SShunqian Zheng #endif
840e3861d91SShunqian Zheng #if defined(CONFIG_MEDIA_CONTROLLER)
841e3861d91SShunqian Zheng 	ov2685->pad.flags = MEDIA_PAD_FL_SOURCE;
842e3861d91SShunqian Zheng 	ov2685->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR;
843e3861d91SShunqian Zheng 	ret = media_entity_pads_init(&ov2685->subdev.entity, 1, &ov2685->pad);
844e3861d91SShunqian Zheng 	if (ret < 0)
845e3861d91SShunqian Zheng 		goto err_power_off;
846e3861d91SShunqian Zheng #endif
847e3861d91SShunqian Zheng 
848e3861d91SShunqian Zheng 	ret = v4l2_async_register_subdev(&ov2685->subdev);
849e3861d91SShunqian Zheng 	if (ret) {
850e3861d91SShunqian Zheng 		dev_err(dev, "v4l2 async register subdev failed\n");
851e3861d91SShunqian Zheng 		goto err_clean_entity;
852e3861d91SShunqian Zheng 	}
853e3861d91SShunqian Zheng 
854e3861d91SShunqian Zheng 	pm_runtime_set_active(dev);
855e3861d91SShunqian Zheng 	pm_runtime_enable(dev);
856e3861d91SShunqian Zheng 	pm_runtime_idle(dev);
857e3861d91SShunqian Zheng 
858e3861d91SShunqian Zheng 	return 0;
859e3861d91SShunqian Zheng 
860e3861d91SShunqian Zheng err_clean_entity:
861e3861d91SShunqian Zheng #if defined(CONFIG_MEDIA_CONTROLLER)
862e3861d91SShunqian Zheng 	media_entity_cleanup(&ov2685->subdev.entity);
863e3861d91SShunqian Zheng #endif
864e3861d91SShunqian Zheng err_power_off:
865e3861d91SShunqian Zheng 	__ov2685_power_off(ov2685);
866e3861d91SShunqian Zheng err_free_handler:
867e3861d91SShunqian Zheng 	v4l2_ctrl_handler_free(&ov2685->ctrl_handler);
868e3861d91SShunqian Zheng err_destroy_mutex:
869e3861d91SShunqian Zheng 	mutex_destroy(&ov2685->mutex);
870e3861d91SShunqian Zheng 
871e3861d91SShunqian Zheng 	return ret;
872e3861d91SShunqian Zheng }
873e3861d91SShunqian Zheng 
ov2685_remove(struct i2c_client * client)874ed5c2f5fSUwe Kleine-König static void ov2685_remove(struct i2c_client *client)
875e3861d91SShunqian Zheng {
876e3861d91SShunqian Zheng 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
877e3861d91SShunqian Zheng 	struct ov2685 *ov2685 = to_ov2685(sd);
878e3861d91SShunqian Zheng 
879e3861d91SShunqian Zheng 	v4l2_async_unregister_subdev(sd);
880e3861d91SShunqian Zheng #if defined(CONFIG_MEDIA_CONTROLLER)
881e3861d91SShunqian Zheng 	media_entity_cleanup(&sd->entity);
882e3861d91SShunqian Zheng #endif
883e3861d91SShunqian Zheng 	v4l2_ctrl_handler_free(&ov2685->ctrl_handler);
884e3861d91SShunqian Zheng 	mutex_destroy(&ov2685->mutex);
885e3861d91SShunqian Zheng 
886e3861d91SShunqian Zheng 	pm_runtime_disable(&client->dev);
887e3861d91SShunqian Zheng 	if (!pm_runtime_status_suspended(&client->dev))
888e3861d91SShunqian Zheng 		__ov2685_power_off(ov2685);
889e3861d91SShunqian Zheng 	pm_runtime_set_suspended(&client->dev);
890e3861d91SShunqian Zheng }
891e3861d91SShunqian Zheng 
892e3861d91SShunqian Zheng #if IS_ENABLED(CONFIG_OF)
893e3861d91SShunqian Zheng static const struct of_device_id ov2685_of_match[] = {
894e3861d91SShunqian Zheng 	{ .compatible = "ovti,ov2685" },
895e3861d91SShunqian Zheng 	{},
896e3861d91SShunqian Zheng };
897e3861d91SShunqian Zheng MODULE_DEVICE_TABLE(of, ov2685_of_match);
898e3861d91SShunqian Zheng #endif
899e3861d91SShunqian Zheng 
900e3861d91SShunqian Zheng static struct i2c_driver ov2685_i2c_driver = {
901e3861d91SShunqian Zheng 	.driver = {
902e3861d91SShunqian Zheng 		.name = "ov2685",
903e3861d91SShunqian Zheng 		.pm = &ov2685_pm_ops,
904e3861d91SShunqian Zheng 		.of_match_table = of_match_ptr(ov2685_of_match),
905e3861d91SShunqian Zheng 	},
906*aaeb31c0SUwe Kleine-König 	.probe		= ov2685_probe,
907*aaeb31c0SUwe Kleine-König 	.remove		= ov2685_remove,
908e3861d91SShunqian Zheng };
909e3861d91SShunqian Zheng 
910e3861d91SShunqian Zheng module_i2c_driver(ov2685_i2c_driver);
911e3861d91SShunqian Zheng 
912e3861d91SShunqian Zheng MODULE_DESCRIPTION("OmniVision ov2685 sensor driver");
913e3861d91SShunqian Zheng MODULE_LICENSE("GPL v2");
914