1 /* 2 * Omnivision OV2659 CMOS Image Sensor driver 3 * 4 * Copyright (C) 2015 Texas Instruments, Inc. 5 * 6 * Benoit Parrot <bparrot@ti.com> 7 * Lad, Prabhakar <prabhakar.csengg@gmail.com> 8 * 9 * This program is free software; you may redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; version 2 of the License. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 15 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 16 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 17 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 18 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 * SOFTWARE. 21 */ 22 23 #include <linux/clk.h> 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/i2c.h> 27 #include <linux/module.h> 28 #include <linux/of_graph.h> 29 #include <linux/pm_runtime.h> 30 31 #include <media/i2c/ov2659.h> 32 #include <media/v4l2-ctrls.h> 33 #include <media/v4l2-event.h> 34 #include <media/v4l2-fwnode.h> 35 #include <media/v4l2-image-sizes.h> 36 #include <media/v4l2-subdev.h> 37 38 #define DRIVER_NAME "ov2659" 39 40 /* 41 * OV2659 register definitions 42 */ 43 #define REG_SOFTWARE_STANDBY 0x0100 44 #define REG_SOFTWARE_RESET 0x0103 45 #define REG_IO_CTRL00 0x3000 46 #define REG_IO_CTRL01 0x3001 47 #define REG_IO_CTRL02 0x3002 48 #define REG_OUTPUT_VALUE00 0x3008 49 #define REG_OUTPUT_VALUE01 0x3009 50 #define REG_OUTPUT_VALUE02 0x300d 51 #define REG_OUTPUT_SELECT00 0x300e 52 #define REG_OUTPUT_SELECT01 0x300f 53 #define REG_OUTPUT_SELECT02 0x3010 54 #define REG_OUTPUT_DRIVE 0x3011 55 #define REG_INPUT_READOUT00 0x302d 56 #define REG_INPUT_READOUT01 0x302e 57 #define REG_INPUT_READOUT02 0x302f 58 59 #define REG_SC_PLL_CTRL0 0x3003 60 #define REG_SC_PLL_CTRL1 0x3004 61 #define REG_SC_PLL_CTRL2 0x3005 62 #define REG_SC_PLL_CTRL3 0x3006 63 #define REG_SC_CHIP_ID_H 0x300a 64 #define REG_SC_CHIP_ID_L 0x300b 65 #define REG_SC_PWC 0x3014 66 #define REG_SC_CLKRST0 0x301a 67 #define REG_SC_CLKRST1 0x301b 68 #define REG_SC_CLKRST2 0x301c 69 #define REG_SC_CLKRST3 0x301d 70 #define REG_SC_SUB_ID 0x302a 71 #define REG_SC_SCCB_ID 0x302b 72 73 #define REG_GROUP_ADDRESS_00 0x3200 74 #define REG_GROUP_ADDRESS_01 0x3201 75 #define REG_GROUP_ADDRESS_02 0x3202 76 #define REG_GROUP_ADDRESS_03 0x3203 77 #define REG_GROUP_ACCESS 0x3208 78 79 #define REG_AWB_R_GAIN_H 0x3400 80 #define REG_AWB_R_GAIN_L 0x3401 81 #define REG_AWB_G_GAIN_H 0x3402 82 #define REG_AWB_G_GAIN_L 0x3403 83 #define REG_AWB_B_GAIN_H 0x3404 84 #define REG_AWB_B_GAIN_L 0x3405 85 #define REG_AWB_MANUAL_CONTROL 0x3406 86 87 #define REG_TIMING_HS_H 0x3800 88 #define REG_TIMING_HS_L 0x3801 89 #define REG_TIMING_VS_H 0x3802 90 #define REG_TIMING_VS_L 0x3803 91 #define REG_TIMING_HW_H 0x3804 92 #define REG_TIMING_HW_L 0x3805 93 #define REG_TIMING_VH_H 0x3806 94 #define REG_TIMING_VH_L 0x3807 95 #define REG_TIMING_DVPHO_H 0x3808 96 #define REG_TIMING_DVPHO_L 0x3809 97 #define REG_TIMING_DVPVO_H 0x380a 98 #define REG_TIMING_DVPVO_L 0x380b 99 #define REG_TIMING_HTS_H 0x380c 100 #define REG_TIMING_HTS_L 0x380d 101 #define REG_TIMING_VTS_H 0x380e 102 #define REG_TIMING_VTS_L 0x380f 103 #define REG_TIMING_HOFFS_H 0x3810 104 #define REG_TIMING_HOFFS_L 0x3811 105 #define REG_TIMING_VOFFS_H 0x3812 106 #define REG_TIMING_VOFFS_L 0x3813 107 #define REG_TIMING_XINC 0x3814 108 #define REG_TIMING_YINC 0x3815 109 #define REG_TIMING_VERT_FORMAT 0x3820 110 #define REG_TIMING_HORIZ_FORMAT 0x3821 111 112 #define REG_FORMAT_CTRL00 0x4300 113 114 #define REG_VFIFO_READ_START_H 0x4608 115 #define REG_VFIFO_READ_START_L 0x4609 116 117 #define REG_DVP_CTRL02 0x4708 118 119 #define REG_ISP_CTRL00 0x5000 120 #define REG_ISP_CTRL01 0x5001 121 #define REG_ISP_CTRL02 0x5002 122 123 #define REG_LENC_RED_X0_H 0x500c 124 #define REG_LENC_RED_X0_L 0x500d 125 #define REG_LENC_RED_Y0_H 0x500e 126 #define REG_LENC_RED_Y0_L 0x500f 127 #define REG_LENC_RED_A1 0x5010 128 #define REG_LENC_RED_B1 0x5011 129 #define REG_LENC_RED_A2_B2 0x5012 130 #define REG_LENC_GREEN_X0_H 0x5013 131 #define REG_LENC_GREEN_X0_L 0x5014 132 #define REG_LENC_GREEN_Y0_H 0x5015 133 #define REG_LENC_GREEN_Y0_L 0x5016 134 #define REG_LENC_GREEN_A1 0x5017 135 #define REG_LENC_GREEN_B1 0x5018 136 #define REG_LENC_GREEN_A2_B2 0x5019 137 #define REG_LENC_BLUE_X0_H 0x501a 138 #define REG_LENC_BLUE_X0_L 0x501b 139 #define REG_LENC_BLUE_Y0_H 0x501c 140 #define REG_LENC_BLUE_Y0_L 0x501d 141 #define REG_LENC_BLUE_A1 0x501e 142 #define REG_LENC_BLUE_B1 0x501f 143 #define REG_LENC_BLUE_A2_B2 0x5020 144 145 #define REG_AWB_CTRL00 0x5035 146 #define REG_AWB_CTRL01 0x5036 147 #define REG_AWB_CTRL02 0x5037 148 #define REG_AWB_CTRL03 0x5038 149 #define REG_AWB_CTRL04 0x5039 150 #define REG_AWB_LOCAL_LIMIT 0x503a 151 #define REG_AWB_CTRL12 0x5049 152 #define REG_AWB_CTRL13 0x504a 153 #define REG_AWB_CTRL14 0x504b 154 155 #define REG_SHARPENMT_THRESH1 0x5064 156 #define REG_SHARPENMT_THRESH2 0x5065 157 #define REG_SHARPENMT_OFFSET1 0x5066 158 #define REG_SHARPENMT_OFFSET2 0x5067 159 #define REG_DENOISE_THRESH1 0x5068 160 #define REG_DENOISE_THRESH2 0x5069 161 #define REG_DENOISE_OFFSET1 0x506a 162 #define REG_DENOISE_OFFSET2 0x506b 163 #define REG_SHARPEN_THRESH1 0x506c 164 #define REG_SHARPEN_THRESH2 0x506d 165 #define REG_CIP_CTRL00 0x506e 166 #define REG_CIP_CTRL01 0x506f 167 168 #define REG_CMX_SIGN 0x5079 169 #define REG_CMX_MISC_CTRL 0x507a 170 171 #define REG_PRE_ISP_CTRL00 0x50a0 172 #define TEST_PATTERN_ENABLE BIT(7) 173 #define VERTICAL_COLOR_BAR_MASK 0x53 174 175 #define REG_NULL 0x0000 /* Array end token */ 176 177 #define OV265X_ID(_msb, _lsb) ((_msb) << 8 | (_lsb)) 178 #define OV2659_ID 0x2656 179 180 struct sensor_register { 181 u16 addr; 182 u8 value; 183 }; 184 185 struct ov2659_framesize { 186 u16 width; 187 u16 height; 188 u16 max_exp_lines; 189 const struct sensor_register *regs; 190 }; 191 192 struct ov2659_pll_ctrl { 193 u8 ctrl1; 194 u8 ctrl2; 195 u8 ctrl3; 196 }; 197 198 struct ov2659_pixfmt { 199 u32 code; 200 /* Output format Register Value (REG_FORMAT_CTRL00) */ 201 struct sensor_register *format_ctrl_regs; 202 }; 203 204 struct pll_ctrl_reg { 205 unsigned int div; 206 unsigned char reg; 207 }; 208 209 struct ov2659 { 210 struct v4l2_subdev sd; 211 struct media_pad pad; 212 struct v4l2_mbus_framefmt format; 213 unsigned int xvclk_frequency; 214 const struct ov2659_platform_data *pdata; 215 struct mutex lock; 216 struct i2c_client *client; 217 struct v4l2_ctrl_handler ctrls; 218 struct v4l2_ctrl *link_frequency; 219 const struct ov2659_framesize *frame_size; 220 struct sensor_register *format_ctrl_regs; 221 struct ov2659_pll_ctrl pll; 222 int streaming; 223 /* used to control the sensor PWDN pin */ 224 struct gpio_desc *pwdn_gpio; 225 /* used to control the sensor RESETB pin */ 226 struct gpio_desc *resetb_gpio; 227 }; 228 229 static const struct sensor_register ov2659_init_regs[] = { 230 { REG_IO_CTRL00, 0x03 }, 231 { REG_IO_CTRL01, 0xff }, 232 { REG_IO_CTRL02, 0xe0 }, 233 { 0x3633, 0x3d }, 234 { 0x3620, 0x02 }, 235 { 0x3631, 0x11 }, 236 { 0x3612, 0x04 }, 237 { 0x3630, 0x20 }, 238 { 0x4702, 0x02 }, 239 { 0x370c, 0x34 }, 240 { REG_TIMING_HS_H, 0x00 }, 241 { REG_TIMING_HS_L, 0x00 }, 242 { REG_TIMING_VS_H, 0x00 }, 243 { REG_TIMING_VS_L, 0x00 }, 244 { REG_TIMING_HW_H, 0x06 }, 245 { REG_TIMING_HW_L, 0x5f }, 246 { REG_TIMING_VH_H, 0x04 }, 247 { REG_TIMING_VH_L, 0xb7 }, 248 { REG_TIMING_DVPHO_H, 0x03 }, 249 { REG_TIMING_DVPHO_L, 0x20 }, 250 { REG_TIMING_DVPVO_H, 0x02 }, 251 { REG_TIMING_DVPVO_L, 0x58 }, 252 { REG_TIMING_HTS_H, 0x05 }, 253 { REG_TIMING_HTS_L, 0x14 }, 254 { REG_TIMING_VTS_H, 0x02 }, 255 { REG_TIMING_VTS_L, 0x68 }, 256 { REG_TIMING_HOFFS_L, 0x08 }, 257 { REG_TIMING_VOFFS_L, 0x02 }, 258 { REG_TIMING_XINC, 0x31 }, 259 { REG_TIMING_YINC, 0x31 }, 260 { 0x3a02, 0x02 }, 261 { 0x3a03, 0x68 }, 262 { 0x3a08, 0x00 }, 263 { 0x3a09, 0x5c }, 264 { 0x3a0a, 0x00 }, 265 { 0x3a0b, 0x4d }, 266 { 0x3a0d, 0x08 }, 267 { 0x3a0e, 0x06 }, 268 { 0x3a14, 0x02 }, 269 { 0x3a15, 0x28 }, 270 { REG_DVP_CTRL02, 0x01 }, 271 { 0x3623, 0x00 }, 272 { 0x3634, 0x76 }, 273 { 0x3701, 0x44 }, 274 { 0x3702, 0x18 }, 275 { 0x3703, 0x24 }, 276 { 0x3704, 0x24 }, 277 { 0x3705, 0x0c }, 278 { REG_TIMING_VERT_FORMAT, 0x81 }, 279 { REG_TIMING_HORIZ_FORMAT, 0x01 }, 280 { 0x370a, 0x52 }, 281 { REG_VFIFO_READ_START_H, 0x00 }, 282 { REG_VFIFO_READ_START_L, 0x80 }, 283 { REG_FORMAT_CTRL00, 0x30 }, 284 { 0x5086, 0x02 }, 285 { REG_ISP_CTRL00, 0xfb }, 286 { REG_ISP_CTRL01, 0x1f }, 287 { REG_ISP_CTRL02, 0x00 }, 288 { 0x5025, 0x0e }, 289 { 0x5026, 0x18 }, 290 { 0x5027, 0x34 }, 291 { 0x5028, 0x4c }, 292 { 0x5029, 0x62 }, 293 { 0x502a, 0x74 }, 294 { 0x502b, 0x85 }, 295 { 0x502c, 0x92 }, 296 { 0x502d, 0x9e }, 297 { 0x502e, 0xb2 }, 298 { 0x502f, 0xc0 }, 299 { 0x5030, 0xcc }, 300 { 0x5031, 0xe0 }, 301 { 0x5032, 0xee }, 302 { 0x5033, 0xf6 }, 303 { 0x5034, 0x11 }, 304 { 0x5070, 0x1c }, 305 { 0x5071, 0x5b }, 306 { 0x5072, 0x05 }, 307 { 0x5073, 0x20 }, 308 { 0x5074, 0x94 }, 309 { 0x5075, 0xb4 }, 310 { 0x5076, 0xb4 }, 311 { 0x5077, 0xaf }, 312 { 0x5078, 0x05 }, 313 { REG_CMX_SIGN, 0x98 }, 314 { REG_CMX_MISC_CTRL, 0x21 }, 315 { REG_AWB_CTRL00, 0x6a }, 316 { REG_AWB_CTRL01, 0x11 }, 317 { REG_AWB_CTRL02, 0x92 }, 318 { REG_AWB_CTRL03, 0x21 }, 319 { REG_AWB_CTRL04, 0xe1 }, 320 { REG_AWB_LOCAL_LIMIT, 0x01 }, 321 { 0x503c, 0x05 }, 322 { 0x503d, 0x08 }, 323 { 0x503e, 0x08 }, 324 { 0x503f, 0x64 }, 325 { 0x5040, 0x58 }, 326 { 0x5041, 0x2a }, 327 { 0x5042, 0xc5 }, 328 { 0x5043, 0x2e }, 329 { 0x5044, 0x3a }, 330 { 0x5045, 0x3c }, 331 { 0x5046, 0x44 }, 332 { 0x5047, 0xf8 }, 333 { 0x5048, 0x08 }, 334 { REG_AWB_CTRL12, 0x70 }, 335 { REG_AWB_CTRL13, 0xf0 }, 336 { REG_AWB_CTRL14, 0xf0 }, 337 { REG_LENC_RED_X0_H, 0x03 }, 338 { REG_LENC_RED_X0_L, 0x20 }, 339 { REG_LENC_RED_Y0_H, 0x02 }, 340 { REG_LENC_RED_Y0_L, 0x5c }, 341 { REG_LENC_RED_A1, 0x48 }, 342 { REG_LENC_RED_B1, 0x00 }, 343 { REG_LENC_RED_A2_B2, 0x66 }, 344 { REG_LENC_GREEN_X0_H, 0x03 }, 345 { REG_LENC_GREEN_X0_L, 0x30 }, 346 { REG_LENC_GREEN_Y0_H, 0x02 }, 347 { REG_LENC_GREEN_Y0_L, 0x7c }, 348 { REG_LENC_GREEN_A1, 0x40 }, 349 { REG_LENC_GREEN_B1, 0x00 }, 350 { REG_LENC_GREEN_A2_B2, 0x66 }, 351 { REG_LENC_BLUE_X0_H, 0x03 }, 352 { REG_LENC_BLUE_X0_L, 0x10 }, 353 { REG_LENC_BLUE_Y0_H, 0x02 }, 354 { REG_LENC_BLUE_Y0_L, 0x7c }, 355 { REG_LENC_BLUE_A1, 0x3a }, 356 { REG_LENC_BLUE_B1, 0x00 }, 357 { REG_LENC_BLUE_A2_B2, 0x66 }, 358 { REG_CIP_CTRL00, 0x44 }, 359 { REG_SHARPENMT_THRESH1, 0x08 }, 360 { REG_SHARPENMT_THRESH2, 0x10 }, 361 { REG_SHARPENMT_OFFSET1, 0x12 }, 362 { REG_SHARPENMT_OFFSET2, 0x02 }, 363 { REG_SHARPEN_THRESH1, 0x08 }, 364 { REG_SHARPEN_THRESH2, 0x10 }, 365 { REG_CIP_CTRL01, 0xa6 }, 366 { REG_DENOISE_THRESH1, 0x08 }, 367 { REG_DENOISE_THRESH2, 0x10 }, 368 { REG_DENOISE_OFFSET1, 0x04 }, 369 { REG_DENOISE_OFFSET2, 0x12 }, 370 { 0x507e, 0x40 }, 371 { 0x507f, 0x20 }, 372 { 0x507b, 0x02 }, 373 { REG_CMX_MISC_CTRL, 0x01 }, 374 { 0x5084, 0x0c }, 375 { 0x5085, 0x3e }, 376 { 0x5005, 0x80 }, 377 { 0x3a0f, 0x30 }, 378 { 0x3a10, 0x28 }, 379 { 0x3a1b, 0x32 }, 380 { 0x3a1e, 0x26 }, 381 { 0x3a11, 0x60 }, 382 { 0x3a1f, 0x14 }, 383 { 0x5060, 0x69 }, 384 { 0x5061, 0x7d }, 385 { 0x5062, 0x7d }, 386 { 0x5063, 0x69 }, 387 { REG_NULL, 0x00 }, 388 }; 389 390 /* 1280X720 720p */ 391 static struct sensor_register ov2659_720p[] = { 392 { REG_TIMING_HS_H, 0x00 }, 393 { REG_TIMING_HS_L, 0xa0 }, 394 { REG_TIMING_VS_H, 0x00 }, 395 { REG_TIMING_VS_L, 0xf0 }, 396 { REG_TIMING_HW_H, 0x05 }, 397 { REG_TIMING_HW_L, 0xbf }, 398 { REG_TIMING_VH_H, 0x03 }, 399 { REG_TIMING_VH_L, 0xcb }, 400 { REG_TIMING_DVPHO_H, 0x05 }, 401 { REG_TIMING_DVPHO_L, 0x00 }, 402 { REG_TIMING_DVPVO_H, 0x02 }, 403 { REG_TIMING_DVPVO_L, 0xd0 }, 404 { REG_TIMING_HTS_H, 0x06 }, 405 { REG_TIMING_HTS_L, 0x4c }, 406 { REG_TIMING_VTS_H, 0x02 }, 407 { REG_TIMING_VTS_L, 0xe8 }, 408 { REG_TIMING_HOFFS_L, 0x10 }, 409 { REG_TIMING_VOFFS_L, 0x06 }, 410 { REG_TIMING_XINC, 0x11 }, 411 { REG_TIMING_YINC, 0x11 }, 412 { REG_TIMING_VERT_FORMAT, 0x80 }, 413 { REG_TIMING_HORIZ_FORMAT, 0x00 }, 414 { 0x370a, 0x12 }, 415 { 0x3a03, 0xe8 }, 416 { 0x3a09, 0x6f }, 417 { 0x3a0b, 0x5d }, 418 { 0x3a15, 0x9a }, 419 { REG_VFIFO_READ_START_H, 0x00 }, 420 { REG_VFIFO_READ_START_L, 0x80 }, 421 { REG_ISP_CTRL02, 0x00 }, 422 { REG_NULL, 0x00 }, 423 }; 424 425 /* 1600X1200 UXGA */ 426 static struct sensor_register ov2659_uxga[] = { 427 { REG_TIMING_HS_H, 0x00 }, 428 { REG_TIMING_HS_L, 0x00 }, 429 { REG_TIMING_VS_H, 0x00 }, 430 { REG_TIMING_VS_L, 0x00 }, 431 { REG_TIMING_HW_H, 0x06 }, 432 { REG_TIMING_HW_L, 0x5f }, 433 { REG_TIMING_VH_H, 0x04 }, 434 { REG_TIMING_VH_L, 0xbb }, 435 { REG_TIMING_DVPHO_H, 0x06 }, 436 { REG_TIMING_DVPHO_L, 0x40 }, 437 { REG_TIMING_DVPVO_H, 0x04 }, 438 { REG_TIMING_DVPVO_L, 0xb0 }, 439 { REG_TIMING_HTS_H, 0x07 }, 440 { REG_TIMING_HTS_L, 0x9f }, 441 { REG_TIMING_VTS_H, 0x04 }, 442 { REG_TIMING_VTS_L, 0xd0 }, 443 { REG_TIMING_HOFFS_L, 0x10 }, 444 { REG_TIMING_VOFFS_L, 0x06 }, 445 { REG_TIMING_XINC, 0x11 }, 446 { REG_TIMING_YINC, 0x11 }, 447 { 0x3a02, 0x04 }, 448 { 0x3a03, 0xd0 }, 449 { 0x3a08, 0x00 }, 450 { 0x3a09, 0xb8 }, 451 { 0x3a0a, 0x00 }, 452 { 0x3a0b, 0x9a }, 453 { 0x3a0d, 0x08 }, 454 { 0x3a0e, 0x06 }, 455 { 0x3a14, 0x04 }, 456 { 0x3a15, 0x50 }, 457 { 0x3623, 0x00 }, 458 { 0x3634, 0x44 }, 459 { 0x3701, 0x44 }, 460 { 0x3702, 0x30 }, 461 { 0x3703, 0x48 }, 462 { 0x3704, 0x48 }, 463 { 0x3705, 0x18 }, 464 { REG_TIMING_VERT_FORMAT, 0x80 }, 465 { REG_TIMING_HORIZ_FORMAT, 0x00 }, 466 { 0x370a, 0x12 }, 467 { REG_VFIFO_READ_START_H, 0x00 }, 468 { REG_VFIFO_READ_START_L, 0x80 }, 469 { REG_ISP_CTRL02, 0x00 }, 470 { REG_NULL, 0x00 }, 471 }; 472 473 /* 1280X1024 SXGA */ 474 static struct sensor_register ov2659_sxga[] = { 475 { REG_TIMING_HS_H, 0x00 }, 476 { REG_TIMING_HS_L, 0x00 }, 477 { REG_TIMING_VS_H, 0x00 }, 478 { REG_TIMING_VS_L, 0x00 }, 479 { REG_TIMING_HW_H, 0x06 }, 480 { REG_TIMING_HW_L, 0x5f }, 481 { REG_TIMING_VH_H, 0x04 }, 482 { REG_TIMING_VH_L, 0xb7 }, 483 { REG_TIMING_DVPHO_H, 0x05 }, 484 { REG_TIMING_DVPHO_L, 0x00 }, 485 { REG_TIMING_DVPVO_H, 0x04 }, 486 { REG_TIMING_DVPVO_L, 0x00 }, 487 { REG_TIMING_HTS_H, 0x07 }, 488 { REG_TIMING_HTS_L, 0x9c }, 489 { REG_TIMING_VTS_H, 0x04 }, 490 { REG_TIMING_VTS_L, 0xd0 }, 491 { REG_TIMING_HOFFS_L, 0x10 }, 492 { REG_TIMING_VOFFS_L, 0x06 }, 493 { REG_TIMING_XINC, 0x11 }, 494 { REG_TIMING_YINC, 0x11 }, 495 { 0x3a02, 0x02 }, 496 { 0x3a03, 0x68 }, 497 { 0x3a08, 0x00 }, 498 { 0x3a09, 0x5c }, 499 { 0x3a0a, 0x00 }, 500 { 0x3a0b, 0x4d }, 501 { 0x3a0d, 0x08 }, 502 { 0x3a0e, 0x06 }, 503 { 0x3a14, 0x02 }, 504 { 0x3a15, 0x28 }, 505 { 0x3623, 0x00 }, 506 { 0x3634, 0x76 }, 507 { 0x3701, 0x44 }, 508 { 0x3702, 0x18 }, 509 { 0x3703, 0x24 }, 510 { 0x3704, 0x24 }, 511 { 0x3705, 0x0c }, 512 { REG_TIMING_VERT_FORMAT, 0x80 }, 513 { REG_TIMING_HORIZ_FORMAT, 0x00 }, 514 { 0x370a, 0x52 }, 515 { REG_VFIFO_READ_START_H, 0x00 }, 516 { REG_VFIFO_READ_START_L, 0x80 }, 517 { REG_ISP_CTRL02, 0x00 }, 518 { REG_NULL, 0x00 }, 519 }; 520 521 /* 1024X768 SXGA */ 522 static struct sensor_register ov2659_xga[] = { 523 { REG_TIMING_HS_H, 0x00 }, 524 { REG_TIMING_HS_L, 0x00 }, 525 { REG_TIMING_VS_H, 0x00 }, 526 { REG_TIMING_VS_L, 0x00 }, 527 { REG_TIMING_HW_H, 0x06 }, 528 { REG_TIMING_HW_L, 0x5f }, 529 { REG_TIMING_VH_H, 0x04 }, 530 { REG_TIMING_VH_L, 0xb7 }, 531 { REG_TIMING_DVPHO_H, 0x04 }, 532 { REG_TIMING_DVPHO_L, 0x00 }, 533 { REG_TIMING_DVPVO_H, 0x03 }, 534 { REG_TIMING_DVPVO_L, 0x00 }, 535 { REG_TIMING_HTS_H, 0x07 }, 536 { REG_TIMING_HTS_L, 0x9c }, 537 { REG_TIMING_VTS_H, 0x04 }, 538 { REG_TIMING_VTS_L, 0xd0 }, 539 { REG_TIMING_HOFFS_L, 0x10 }, 540 { REG_TIMING_VOFFS_L, 0x06 }, 541 { REG_TIMING_XINC, 0x11 }, 542 { REG_TIMING_YINC, 0x11 }, 543 { 0x3a02, 0x02 }, 544 { 0x3a03, 0x68 }, 545 { 0x3a08, 0x00 }, 546 { 0x3a09, 0x5c }, 547 { 0x3a0a, 0x00 }, 548 { 0x3a0b, 0x4d }, 549 { 0x3a0d, 0x08 }, 550 { 0x3a0e, 0x06 }, 551 { 0x3a14, 0x02 }, 552 { 0x3a15, 0x28 }, 553 { 0x3623, 0x00 }, 554 { 0x3634, 0x76 }, 555 { 0x3701, 0x44 }, 556 { 0x3702, 0x18 }, 557 { 0x3703, 0x24 }, 558 { 0x3704, 0x24 }, 559 { 0x3705, 0x0c }, 560 { REG_TIMING_VERT_FORMAT, 0x80 }, 561 { REG_TIMING_HORIZ_FORMAT, 0x00 }, 562 { 0x370a, 0x52 }, 563 { REG_VFIFO_READ_START_H, 0x00 }, 564 { REG_VFIFO_READ_START_L, 0x80 }, 565 { REG_ISP_CTRL02, 0x00 }, 566 { REG_NULL, 0x00 }, 567 }; 568 569 /* 800X600 SVGA */ 570 static struct sensor_register ov2659_svga[] = { 571 { REG_TIMING_HS_H, 0x00 }, 572 { REG_TIMING_HS_L, 0x00 }, 573 { REG_TIMING_VS_H, 0x00 }, 574 { REG_TIMING_VS_L, 0x00 }, 575 { REG_TIMING_HW_H, 0x06 }, 576 { REG_TIMING_HW_L, 0x5f }, 577 { REG_TIMING_VH_H, 0x04 }, 578 { REG_TIMING_VH_L, 0xb7 }, 579 { REG_TIMING_DVPHO_H, 0x03 }, 580 { REG_TIMING_DVPHO_L, 0x20 }, 581 { REG_TIMING_DVPVO_H, 0x02 }, 582 { REG_TIMING_DVPVO_L, 0x58 }, 583 { REG_TIMING_HTS_H, 0x05 }, 584 { REG_TIMING_HTS_L, 0x14 }, 585 { REG_TIMING_VTS_H, 0x02 }, 586 { REG_TIMING_VTS_L, 0x68 }, 587 { REG_TIMING_HOFFS_L, 0x08 }, 588 { REG_TIMING_VOFFS_L, 0x02 }, 589 { REG_TIMING_XINC, 0x31 }, 590 { REG_TIMING_YINC, 0x31 }, 591 { 0x3a02, 0x02 }, 592 { 0x3a03, 0x68 }, 593 { 0x3a08, 0x00 }, 594 { 0x3a09, 0x5c }, 595 { 0x3a0a, 0x00 }, 596 { 0x3a0b, 0x4d }, 597 { 0x3a0d, 0x08 }, 598 { 0x3a0e, 0x06 }, 599 { 0x3a14, 0x02 }, 600 { 0x3a15, 0x28 }, 601 { 0x3623, 0x00 }, 602 { 0x3634, 0x76 }, 603 { 0x3701, 0x44 }, 604 { 0x3702, 0x18 }, 605 { 0x3703, 0x24 }, 606 { 0x3704, 0x24 }, 607 { 0x3705, 0x0c }, 608 { REG_TIMING_VERT_FORMAT, 0x81 }, 609 { REG_TIMING_HORIZ_FORMAT, 0x01 }, 610 { 0x370a, 0x52 }, 611 { REG_VFIFO_READ_START_H, 0x00 }, 612 { REG_VFIFO_READ_START_L, 0x80 }, 613 { REG_ISP_CTRL02, 0x00 }, 614 { REG_NULL, 0x00 }, 615 }; 616 617 /* 640X480 VGA */ 618 static struct sensor_register ov2659_vga[] = { 619 { REG_TIMING_HS_H, 0x00 }, 620 { REG_TIMING_HS_L, 0x00 }, 621 { REG_TIMING_VS_H, 0x00 }, 622 { REG_TIMING_VS_L, 0x00 }, 623 { REG_TIMING_HW_H, 0x06 }, 624 { REG_TIMING_HW_L, 0x5f }, 625 { REG_TIMING_VH_H, 0x04 }, 626 { REG_TIMING_VH_L, 0xb7 }, 627 { REG_TIMING_DVPHO_H, 0x02 }, 628 { REG_TIMING_DVPHO_L, 0x80 }, 629 { REG_TIMING_DVPVO_H, 0x01 }, 630 { REG_TIMING_DVPVO_L, 0xe0 }, 631 { REG_TIMING_HTS_H, 0x05 }, 632 { REG_TIMING_HTS_L, 0x14 }, 633 { REG_TIMING_VTS_H, 0x02 }, 634 { REG_TIMING_VTS_L, 0x68 }, 635 { REG_TIMING_HOFFS_L, 0x08 }, 636 { REG_TIMING_VOFFS_L, 0x02 }, 637 { REG_TIMING_XINC, 0x31 }, 638 { REG_TIMING_YINC, 0x31 }, 639 { 0x3a02, 0x02 }, 640 { 0x3a03, 0x68 }, 641 { 0x3a08, 0x00 }, 642 { 0x3a09, 0x5c }, 643 { 0x3a0a, 0x00 }, 644 { 0x3a0b, 0x4d }, 645 { 0x3a0d, 0x08 }, 646 { 0x3a0e, 0x06 }, 647 { 0x3a14, 0x02 }, 648 { 0x3a15, 0x28 }, 649 { 0x3623, 0x00 }, 650 { 0x3634, 0x76 }, 651 { 0x3701, 0x44 }, 652 { 0x3702, 0x18 }, 653 { 0x3703, 0x24 }, 654 { 0x3704, 0x24 }, 655 { 0x3705, 0x0c }, 656 { REG_TIMING_VERT_FORMAT, 0x81 }, 657 { REG_TIMING_HORIZ_FORMAT, 0x01 }, 658 { 0x370a, 0x52 }, 659 { REG_VFIFO_READ_START_H, 0x00 }, 660 { REG_VFIFO_READ_START_L, 0xa0 }, 661 { REG_ISP_CTRL02, 0x10 }, 662 { REG_NULL, 0x00 }, 663 }; 664 665 /* 320X240 QVGA */ 666 static struct sensor_register ov2659_qvga[] = { 667 { REG_TIMING_HS_H, 0x00 }, 668 { REG_TIMING_HS_L, 0x00 }, 669 { REG_TIMING_VS_H, 0x00 }, 670 { REG_TIMING_VS_L, 0x00 }, 671 { REG_TIMING_HW_H, 0x06 }, 672 { REG_TIMING_HW_L, 0x5f }, 673 { REG_TIMING_VH_H, 0x04 }, 674 { REG_TIMING_VH_L, 0xb7 }, 675 { REG_TIMING_DVPHO_H, 0x01 }, 676 { REG_TIMING_DVPHO_L, 0x40 }, 677 { REG_TIMING_DVPVO_H, 0x00 }, 678 { REG_TIMING_DVPVO_L, 0xf0 }, 679 { REG_TIMING_HTS_H, 0x05 }, 680 { REG_TIMING_HTS_L, 0x14 }, 681 { REG_TIMING_VTS_H, 0x02 }, 682 { REG_TIMING_VTS_L, 0x68 }, 683 { REG_TIMING_HOFFS_L, 0x08 }, 684 { REG_TIMING_VOFFS_L, 0x02 }, 685 { REG_TIMING_XINC, 0x31 }, 686 { REG_TIMING_YINC, 0x31 }, 687 { 0x3a02, 0x02 }, 688 { 0x3a03, 0x68 }, 689 { 0x3a08, 0x00 }, 690 { 0x3a09, 0x5c }, 691 { 0x3a0a, 0x00 }, 692 { 0x3a0b, 0x4d }, 693 { 0x3a0d, 0x08 }, 694 { 0x3a0e, 0x06 }, 695 { 0x3a14, 0x02 }, 696 { 0x3a15, 0x28 }, 697 { 0x3623, 0x00 }, 698 { 0x3634, 0x76 }, 699 { 0x3701, 0x44 }, 700 { 0x3702, 0x18 }, 701 { 0x3703, 0x24 }, 702 { 0x3704, 0x24 }, 703 { 0x3705, 0x0c }, 704 { REG_TIMING_VERT_FORMAT, 0x81 }, 705 { REG_TIMING_HORIZ_FORMAT, 0x01 }, 706 { 0x370a, 0x52 }, 707 { REG_VFIFO_READ_START_H, 0x00 }, 708 { REG_VFIFO_READ_START_L, 0xa0 }, 709 { REG_ISP_CTRL02, 0x10 }, 710 { REG_NULL, 0x00 }, 711 }; 712 713 static const struct pll_ctrl_reg ctrl3[] = { 714 { 1, 0x00 }, 715 { 2, 0x02 }, 716 { 3, 0x03 }, 717 { 4, 0x06 }, 718 { 6, 0x0d }, 719 { 8, 0x0e }, 720 { 12, 0x0f }, 721 { 16, 0x12 }, 722 { 24, 0x13 }, 723 { 32, 0x16 }, 724 { 48, 0x1b }, 725 { 64, 0x1e }, 726 { 96, 0x1f }, 727 { 0, 0x00 }, 728 }; 729 730 static const struct pll_ctrl_reg ctrl1[] = { 731 { 2, 0x10 }, 732 { 4, 0x20 }, 733 { 6, 0x30 }, 734 { 8, 0x40 }, 735 { 10, 0x50 }, 736 { 12, 0x60 }, 737 { 14, 0x70 }, 738 { 16, 0x80 }, 739 { 18, 0x90 }, 740 { 20, 0xa0 }, 741 { 22, 0xb0 }, 742 { 24, 0xc0 }, 743 { 26, 0xd0 }, 744 { 28, 0xe0 }, 745 { 30, 0xf0 }, 746 { 0, 0x00 }, 747 }; 748 749 static const struct ov2659_framesize ov2659_framesizes[] = { 750 { /* QVGA */ 751 .width = 320, 752 .height = 240, 753 .regs = ov2659_qvga, 754 .max_exp_lines = 248, 755 }, { /* VGA */ 756 .width = 640, 757 .height = 480, 758 .regs = ov2659_vga, 759 .max_exp_lines = 498, 760 }, { /* SVGA */ 761 .width = 800, 762 .height = 600, 763 .regs = ov2659_svga, 764 .max_exp_lines = 498, 765 }, { /* XGA */ 766 .width = 1024, 767 .height = 768, 768 .regs = ov2659_xga, 769 .max_exp_lines = 498, 770 }, { /* 720P */ 771 .width = 1280, 772 .height = 720, 773 .regs = ov2659_720p, 774 .max_exp_lines = 498, 775 }, { /* SXGA */ 776 .width = 1280, 777 .height = 1024, 778 .regs = ov2659_sxga, 779 .max_exp_lines = 1048, 780 }, { /* UXGA */ 781 .width = 1600, 782 .height = 1200, 783 .regs = ov2659_uxga, 784 .max_exp_lines = 498, 785 }, 786 }; 787 788 /* YUV422 YUYV*/ 789 static struct sensor_register ov2659_format_yuyv[] = { 790 { REG_FORMAT_CTRL00, 0x30 }, 791 { REG_NULL, 0x0 }, 792 }; 793 794 /* YUV422 UYVY */ 795 static struct sensor_register ov2659_format_uyvy[] = { 796 { REG_FORMAT_CTRL00, 0x32 }, 797 { REG_NULL, 0x0 }, 798 }; 799 800 /* Raw Bayer BGGR */ 801 static struct sensor_register ov2659_format_bggr[] = { 802 { REG_FORMAT_CTRL00, 0x00 }, 803 { REG_NULL, 0x0 }, 804 }; 805 806 /* RGB565 */ 807 static struct sensor_register ov2659_format_rgb565[] = { 808 { REG_FORMAT_CTRL00, 0x60 }, 809 { REG_NULL, 0x0 }, 810 }; 811 812 static const struct ov2659_pixfmt ov2659_formats[] = { 813 { 814 .code = MEDIA_BUS_FMT_YUYV8_2X8, 815 .format_ctrl_regs = ov2659_format_yuyv, 816 }, { 817 .code = MEDIA_BUS_FMT_UYVY8_2X8, 818 .format_ctrl_regs = ov2659_format_uyvy, 819 }, { 820 .code = MEDIA_BUS_FMT_RGB565_2X8_BE, 821 .format_ctrl_regs = ov2659_format_rgb565, 822 }, { 823 .code = MEDIA_BUS_FMT_SBGGR8_1X8, 824 .format_ctrl_regs = ov2659_format_bggr, 825 }, 826 }; 827 828 static inline struct ov2659 *to_ov2659(struct v4l2_subdev *sd) 829 { 830 return container_of(sd, struct ov2659, sd); 831 } 832 833 /* sensor register write */ 834 static int ov2659_write(struct i2c_client *client, u16 reg, u8 val) 835 { 836 struct i2c_msg msg; 837 u8 buf[3]; 838 int ret; 839 840 buf[0] = reg >> 8; 841 buf[1] = reg & 0xFF; 842 buf[2] = val; 843 844 msg.addr = client->addr; 845 msg.flags = client->flags; 846 msg.buf = buf; 847 msg.len = sizeof(buf); 848 849 ret = i2c_transfer(client->adapter, &msg, 1); 850 if (ret >= 0) 851 return 0; 852 853 dev_dbg(&client->dev, 854 "ov2659 write reg(0x%x val:0x%x) failed !\n", reg, val); 855 856 return ret; 857 } 858 859 /* sensor register read */ 860 static int ov2659_read(struct i2c_client *client, u16 reg, u8 *val) 861 { 862 struct i2c_msg msg[2]; 863 u8 buf[2]; 864 int ret; 865 866 buf[0] = reg >> 8; 867 buf[1] = reg & 0xFF; 868 869 msg[0].addr = client->addr; 870 msg[0].flags = client->flags; 871 msg[0].buf = buf; 872 msg[0].len = sizeof(buf); 873 874 msg[1].addr = client->addr; 875 msg[1].flags = client->flags | I2C_M_RD; 876 msg[1].buf = buf; 877 msg[1].len = 1; 878 879 ret = i2c_transfer(client->adapter, msg, 2); 880 if (ret >= 0) { 881 *val = buf[0]; 882 return 0; 883 } 884 885 dev_dbg(&client->dev, 886 "ov2659 read reg(0x%x val:0x%x) failed !\n", reg, *val); 887 888 return ret; 889 } 890 891 static int ov2659_write_array(struct i2c_client *client, 892 const struct sensor_register *regs) 893 { 894 int i, ret = 0; 895 896 for (i = 0; ret == 0 && regs[i].addr; i++) 897 ret = ov2659_write(client, regs[i].addr, regs[i].value); 898 899 return ret; 900 } 901 902 static void ov2659_pll_calc_params(struct ov2659 *ov2659) 903 { 904 const struct ov2659_platform_data *pdata = ov2659->pdata; 905 u8 ctrl1_reg = 0, ctrl2_reg = 0, ctrl3_reg = 0; 906 struct i2c_client *client = ov2659->client; 907 unsigned int desired = pdata->link_frequency; 908 u32 prediv, postdiv, mult; 909 u32 bestdelta = -1; 910 u32 delta, actual; 911 int i, j; 912 913 for (i = 0; ctrl1[i].div != 0; i++) { 914 postdiv = ctrl1[i].div; 915 for (j = 0; ctrl3[j].div != 0; j++) { 916 prediv = ctrl3[j].div; 917 for (mult = 1; mult <= 63; mult++) { 918 actual = ov2659->xvclk_frequency; 919 actual *= mult; 920 actual /= prediv; 921 actual /= postdiv; 922 delta = actual - desired; 923 delta = abs(delta); 924 925 if ((delta < bestdelta) || (bestdelta == -1)) { 926 bestdelta = delta; 927 ctrl1_reg = ctrl1[i].reg; 928 ctrl2_reg = mult; 929 ctrl3_reg = ctrl3[j].reg; 930 } 931 } 932 } 933 } 934 935 ov2659->pll.ctrl1 = ctrl1_reg; 936 ov2659->pll.ctrl2 = ctrl2_reg; 937 ov2659->pll.ctrl3 = ctrl3_reg; 938 939 dev_dbg(&client->dev, 940 "Actual reg config: ctrl1_reg: %02x ctrl2_reg: %02x ctrl3_reg: %02x\n", 941 ctrl1_reg, ctrl2_reg, ctrl3_reg); 942 } 943 944 static int ov2659_set_pixel_clock(struct ov2659 *ov2659) 945 { 946 struct i2c_client *client = ov2659->client; 947 struct sensor_register pll_regs[] = { 948 {REG_SC_PLL_CTRL1, ov2659->pll.ctrl1}, 949 {REG_SC_PLL_CTRL2, ov2659->pll.ctrl2}, 950 {REG_SC_PLL_CTRL3, ov2659->pll.ctrl3}, 951 {REG_NULL, 0x00}, 952 }; 953 954 dev_dbg(&client->dev, "%s\n", __func__); 955 956 return ov2659_write_array(client, pll_regs); 957 }; 958 959 static void ov2659_get_default_format(struct v4l2_mbus_framefmt *format) 960 { 961 format->width = ov2659_framesizes[2].width; 962 format->height = ov2659_framesizes[2].height; 963 format->colorspace = V4L2_COLORSPACE_SRGB; 964 format->code = ov2659_formats[0].code; 965 format->field = V4L2_FIELD_NONE; 966 } 967 968 static void ov2659_set_streaming(struct ov2659 *ov2659, int on) 969 { 970 struct i2c_client *client = ov2659->client; 971 int ret; 972 973 on = !!on; 974 975 dev_dbg(&client->dev, "%s: on: %d\n", __func__, on); 976 977 ret = ov2659_write(client, REG_SOFTWARE_STANDBY, on); 978 if (ret) 979 dev_err(&client->dev, "ov2659 soft standby failed\n"); 980 } 981 982 static int ov2659_init(struct v4l2_subdev *sd, u32 val) 983 { 984 struct i2c_client *client = v4l2_get_subdevdata(sd); 985 986 return ov2659_write_array(client, ov2659_init_regs); 987 } 988 989 /* 990 * V4L2 subdev video and pad level operations 991 */ 992 993 static int ov2659_enum_mbus_code(struct v4l2_subdev *sd, 994 struct v4l2_subdev_pad_config *cfg, 995 struct v4l2_subdev_mbus_code_enum *code) 996 { 997 struct i2c_client *client = v4l2_get_subdevdata(sd); 998 999 dev_dbg(&client->dev, "%s:\n", __func__); 1000 1001 if (code->index >= ARRAY_SIZE(ov2659_formats)) 1002 return -EINVAL; 1003 1004 code->code = ov2659_formats[code->index].code; 1005 1006 return 0; 1007 } 1008 1009 static int ov2659_enum_frame_sizes(struct v4l2_subdev *sd, 1010 struct v4l2_subdev_pad_config *cfg, 1011 struct v4l2_subdev_frame_size_enum *fse) 1012 { 1013 struct i2c_client *client = v4l2_get_subdevdata(sd); 1014 int i = ARRAY_SIZE(ov2659_formats); 1015 1016 dev_dbg(&client->dev, "%s:\n", __func__); 1017 1018 if (fse->index >= ARRAY_SIZE(ov2659_framesizes)) 1019 return -EINVAL; 1020 1021 while (--i) 1022 if (fse->code == ov2659_formats[i].code) 1023 break; 1024 1025 fse->code = ov2659_formats[i].code; 1026 1027 fse->min_width = ov2659_framesizes[fse->index].width; 1028 fse->max_width = fse->min_width; 1029 fse->max_height = ov2659_framesizes[fse->index].height; 1030 fse->min_height = fse->max_height; 1031 1032 return 0; 1033 } 1034 1035 static int ov2659_get_fmt(struct v4l2_subdev *sd, 1036 struct v4l2_subdev_pad_config *cfg, 1037 struct v4l2_subdev_format *fmt) 1038 { 1039 struct i2c_client *client = v4l2_get_subdevdata(sd); 1040 struct ov2659 *ov2659 = to_ov2659(sd); 1041 1042 dev_dbg(&client->dev, "ov2659_get_fmt\n"); 1043 1044 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 1045 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1046 struct v4l2_mbus_framefmt *mf; 1047 1048 mf = v4l2_subdev_get_try_format(sd, cfg, 0); 1049 mutex_lock(&ov2659->lock); 1050 fmt->format = *mf; 1051 mutex_unlock(&ov2659->lock); 1052 return 0; 1053 #else 1054 return -EINVAL; 1055 #endif 1056 } 1057 1058 mutex_lock(&ov2659->lock); 1059 fmt->format = ov2659->format; 1060 mutex_unlock(&ov2659->lock); 1061 1062 dev_dbg(&client->dev, "ov2659_get_fmt: %x %dx%d\n", 1063 ov2659->format.code, ov2659->format.width, 1064 ov2659->format.height); 1065 1066 return 0; 1067 } 1068 1069 static void __ov2659_try_frame_size(struct v4l2_mbus_framefmt *mf, 1070 const struct ov2659_framesize **size) 1071 { 1072 const struct ov2659_framesize *fsize = &ov2659_framesizes[0]; 1073 const struct ov2659_framesize *match = NULL; 1074 int i = ARRAY_SIZE(ov2659_framesizes); 1075 unsigned int min_err = UINT_MAX; 1076 1077 while (i--) { 1078 int err = abs(fsize->width - mf->width) 1079 + abs(fsize->height - mf->height); 1080 if ((err < min_err) && (fsize->regs[0].addr)) { 1081 min_err = err; 1082 match = fsize; 1083 } 1084 fsize++; 1085 } 1086 1087 if (!match) 1088 match = &ov2659_framesizes[2]; 1089 1090 mf->width = match->width; 1091 mf->height = match->height; 1092 1093 if (size) 1094 *size = match; 1095 } 1096 1097 static int ov2659_set_fmt(struct v4l2_subdev *sd, 1098 struct v4l2_subdev_pad_config *cfg, 1099 struct v4l2_subdev_format *fmt) 1100 { 1101 struct i2c_client *client = v4l2_get_subdevdata(sd); 1102 int index = ARRAY_SIZE(ov2659_formats); 1103 struct v4l2_mbus_framefmt *mf = &fmt->format; 1104 const struct ov2659_framesize *size = NULL; 1105 struct ov2659 *ov2659 = to_ov2659(sd); 1106 int ret = 0; 1107 1108 dev_dbg(&client->dev, "ov2659_set_fmt\n"); 1109 1110 __ov2659_try_frame_size(mf, &size); 1111 1112 while (--index >= 0) 1113 if (ov2659_formats[index].code == mf->code) 1114 break; 1115 1116 if (index < 0) { 1117 index = 0; 1118 mf->code = ov2659_formats[index].code; 1119 } 1120 1121 mf->colorspace = V4L2_COLORSPACE_SRGB; 1122 mf->field = V4L2_FIELD_NONE; 1123 1124 mutex_lock(&ov2659->lock); 1125 1126 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 1127 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1128 mf = v4l2_subdev_get_try_format(sd, cfg, fmt->pad); 1129 *mf = fmt->format; 1130 #endif 1131 } else { 1132 s64 val; 1133 1134 if (ov2659->streaming) { 1135 mutex_unlock(&ov2659->lock); 1136 return -EBUSY; 1137 } 1138 1139 ov2659->frame_size = size; 1140 ov2659->format = fmt->format; 1141 ov2659->format_ctrl_regs = 1142 ov2659_formats[index].format_ctrl_regs; 1143 1144 if (ov2659->format.code != MEDIA_BUS_FMT_SBGGR8_1X8) 1145 val = ov2659->pdata->link_frequency / 2; 1146 else 1147 val = ov2659->pdata->link_frequency; 1148 1149 ret = v4l2_ctrl_s_ctrl_int64(ov2659->link_frequency, val); 1150 if (ret < 0) 1151 dev_warn(&client->dev, 1152 "failed to set link_frequency rate (%d)\n", 1153 ret); 1154 } 1155 1156 mutex_unlock(&ov2659->lock); 1157 return ret; 1158 } 1159 1160 static int ov2659_set_frame_size(struct ov2659 *ov2659) 1161 { 1162 struct i2c_client *client = ov2659->client; 1163 1164 dev_dbg(&client->dev, "%s\n", __func__); 1165 1166 return ov2659_write_array(ov2659->client, ov2659->frame_size->regs); 1167 } 1168 1169 static int ov2659_set_format(struct ov2659 *ov2659) 1170 { 1171 struct i2c_client *client = ov2659->client; 1172 1173 dev_dbg(&client->dev, "%s\n", __func__); 1174 1175 return ov2659_write_array(ov2659->client, ov2659->format_ctrl_regs); 1176 } 1177 1178 static int ov2659_s_stream(struct v4l2_subdev *sd, int on) 1179 { 1180 struct i2c_client *client = v4l2_get_subdevdata(sd); 1181 struct ov2659 *ov2659 = to_ov2659(sd); 1182 int ret = 0; 1183 1184 dev_dbg(&client->dev, "%s: on: %d\n", __func__, on); 1185 1186 mutex_lock(&ov2659->lock); 1187 1188 on = !!on; 1189 1190 if (ov2659->streaming == on) 1191 goto unlock; 1192 1193 if (!on) { 1194 /* Stop Streaming Sequence */ 1195 ov2659_set_streaming(ov2659, 0); 1196 ov2659->streaming = on; 1197 pm_runtime_put(&client->dev); 1198 goto unlock; 1199 } 1200 1201 ret = pm_runtime_get_sync(&client->dev); 1202 if (ret < 0) { 1203 pm_runtime_put_noidle(&client->dev); 1204 goto unlock; 1205 } 1206 1207 ret = ov2659_init(sd, 0); 1208 if (!ret) 1209 ret = ov2659_set_pixel_clock(ov2659); 1210 if (!ret) 1211 ret = ov2659_set_frame_size(ov2659); 1212 if (!ret) 1213 ret = ov2659_set_format(ov2659); 1214 if (!ret) { 1215 ov2659_set_streaming(ov2659, 1); 1216 ov2659->streaming = on; 1217 } 1218 1219 unlock: 1220 mutex_unlock(&ov2659->lock); 1221 return ret; 1222 } 1223 1224 static int ov2659_set_test_pattern(struct ov2659 *ov2659, int value) 1225 { 1226 struct i2c_client *client = v4l2_get_subdevdata(&ov2659->sd); 1227 int ret; 1228 u8 val; 1229 1230 ret = ov2659_read(client, REG_PRE_ISP_CTRL00, &val); 1231 if (ret < 0) 1232 return ret; 1233 1234 switch (value) { 1235 case 0: 1236 val &= ~TEST_PATTERN_ENABLE; 1237 break; 1238 case 1: 1239 val &= VERTICAL_COLOR_BAR_MASK; 1240 val |= TEST_PATTERN_ENABLE; 1241 break; 1242 } 1243 1244 return ov2659_write(client, REG_PRE_ISP_CTRL00, val); 1245 } 1246 1247 static int ov2659_s_ctrl(struct v4l2_ctrl *ctrl) 1248 { 1249 struct ov2659 *ov2659 = 1250 container_of(ctrl->handler, struct ov2659, ctrls); 1251 struct i2c_client *client = ov2659->client; 1252 1253 /* V4L2 controls values will be applied only when power is already up */ 1254 if (!pm_runtime_get_if_in_use(&client->dev)) 1255 return 0; 1256 1257 switch (ctrl->id) { 1258 case V4L2_CID_TEST_PATTERN: 1259 return ov2659_set_test_pattern(ov2659, ctrl->val); 1260 } 1261 1262 pm_runtime_put(&client->dev); 1263 return 0; 1264 } 1265 1266 static const struct v4l2_ctrl_ops ov2659_ctrl_ops = { 1267 .s_ctrl = ov2659_s_ctrl, 1268 }; 1269 1270 static const char * const ov2659_test_pattern_menu[] = { 1271 "Disabled", 1272 "Vertical Color Bars", 1273 }; 1274 1275 static int ov2659_power_off(struct device *dev) 1276 { 1277 struct i2c_client *client = to_i2c_client(dev); 1278 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1279 struct ov2659 *ov2659 = to_ov2659(sd); 1280 1281 dev_dbg(&client->dev, "%s:\n", __func__); 1282 1283 gpiod_set_value(ov2659->pwdn_gpio, 1); 1284 1285 return 0; 1286 } 1287 1288 static int ov2659_power_on(struct device *dev) 1289 { 1290 struct i2c_client *client = to_i2c_client(dev); 1291 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1292 struct ov2659 *ov2659 = to_ov2659(sd); 1293 1294 dev_dbg(&client->dev, "%s:\n", __func__); 1295 1296 gpiod_set_value(ov2659->pwdn_gpio, 0); 1297 1298 if (ov2659->resetb_gpio) { 1299 gpiod_set_value(ov2659->resetb_gpio, 1); 1300 usleep_range(500, 1000); 1301 gpiod_set_value(ov2659->resetb_gpio, 0); 1302 usleep_range(3000, 5000); 1303 } 1304 1305 return 0; 1306 } 1307 1308 /* ----------------------------------------------------------------------------- 1309 * V4L2 subdev internal operations 1310 */ 1311 1312 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1313 static int ov2659_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) 1314 { 1315 struct i2c_client *client = v4l2_get_subdevdata(sd); 1316 struct v4l2_mbus_framefmt *format = 1317 v4l2_subdev_get_try_format(sd, fh->pad, 0); 1318 1319 dev_dbg(&client->dev, "%s:\n", __func__); 1320 1321 ov2659_get_default_format(format); 1322 1323 return 0; 1324 } 1325 #endif 1326 1327 static const struct v4l2_subdev_core_ops ov2659_subdev_core_ops = { 1328 .log_status = v4l2_ctrl_subdev_log_status, 1329 .subscribe_event = v4l2_ctrl_subdev_subscribe_event, 1330 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 1331 }; 1332 1333 static const struct v4l2_subdev_video_ops ov2659_subdev_video_ops = { 1334 .s_stream = ov2659_s_stream, 1335 }; 1336 1337 static const struct v4l2_subdev_pad_ops ov2659_subdev_pad_ops = { 1338 .enum_mbus_code = ov2659_enum_mbus_code, 1339 .enum_frame_size = ov2659_enum_frame_sizes, 1340 .get_fmt = ov2659_get_fmt, 1341 .set_fmt = ov2659_set_fmt, 1342 }; 1343 1344 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1345 static const struct v4l2_subdev_ops ov2659_subdev_ops = { 1346 .core = &ov2659_subdev_core_ops, 1347 .video = &ov2659_subdev_video_ops, 1348 .pad = &ov2659_subdev_pad_ops, 1349 }; 1350 1351 static const struct v4l2_subdev_internal_ops ov2659_subdev_internal_ops = { 1352 .open = ov2659_open, 1353 }; 1354 #endif 1355 1356 static int ov2659_detect(struct v4l2_subdev *sd) 1357 { 1358 struct i2c_client *client = v4l2_get_subdevdata(sd); 1359 u8 pid = 0; 1360 u8 ver = 0; 1361 int ret; 1362 1363 dev_dbg(&client->dev, "%s:\n", __func__); 1364 1365 ret = ov2659_write(client, REG_SOFTWARE_RESET, 0x01); 1366 if (ret != 0) { 1367 dev_err(&client->dev, "Sensor soft reset failed\n"); 1368 return -ENODEV; 1369 } 1370 usleep_range(1000, 2000); 1371 1372 /* Check sensor revision */ 1373 ret = ov2659_read(client, REG_SC_CHIP_ID_H, &pid); 1374 if (!ret) 1375 ret = ov2659_read(client, REG_SC_CHIP_ID_L, &ver); 1376 1377 if (!ret) { 1378 unsigned short id; 1379 1380 id = OV265X_ID(pid, ver); 1381 if (id != OV2659_ID) { 1382 dev_err(&client->dev, 1383 "Sensor detection failed (%04X, %d)\n", 1384 id, ret); 1385 ret = -ENODEV; 1386 } else { 1387 dev_info(&client->dev, "Found OV%04X sensor\n", id); 1388 } 1389 } 1390 1391 return ret; 1392 } 1393 1394 static struct ov2659_platform_data * 1395 ov2659_get_pdata(struct i2c_client *client) 1396 { 1397 struct ov2659_platform_data *pdata; 1398 struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 }; 1399 struct device_node *endpoint; 1400 int ret; 1401 1402 if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node) 1403 return client->dev.platform_data; 1404 1405 endpoint = of_graph_get_next_endpoint(client->dev.of_node, NULL); 1406 if (!endpoint) 1407 return NULL; 1408 1409 ret = v4l2_fwnode_endpoint_alloc_parse(of_fwnode_handle(endpoint), 1410 &bus_cfg); 1411 if (ret) { 1412 pdata = NULL; 1413 goto done; 1414 } 1415 1416 pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL); 1417 if (!pdata) 1418 goto done; 1419 1420 if (!bus_cfg.nr_of_link_frequencies) { 1421 dev_err(&client->dev, 1422 "link-frequencies property not found or too many\n"); 1423 pdata = NULL; 1424 goto done; 1425 } 1426 1427 pdata->link_frequency = bus_cfg.link_frequencies[0]; 1428 1429 done: 1430 v4l2_fwnode_endpoint_free(&bus_cfg); 1431 of_node_put(endpoint); 1432 return pdata; 1433 } 1434 1435 static int ov2659_probe(struct i2c_client *client) 1436 { 1437 const struct ov2659_platform_data *pdata = ov2659_get_pdata(client); 1438 struct v4l2_subdev *sd; 1439 struct ov2659 *ov2659; 1440 struct clk *clk; 1441 int ret; 1442 1443 if (!pdata) { 1444 dev_err(&client->dev, "platform data not specified\n"); 1445 return -EINVAL; 1446 } 1447 1448 ov2659 = devm_kzalloc(&client->dev, sizeof(*ov2659), GFP_KERNEL); 1449 if (!ov2659) 1450 return -ENOMEM; 1451 1452 ov2659->pdata = pdata; 1453 ov2659->client = client; 1454 1455 clk = devm_clk_get(&client->dev, "xvclk"); 1456 if (IS_ERR(clk)) 1457 return PTR_ERR(clk); 1458 1459 ov2659->xvclk_frequency = clk_get_rate(clk); 1460 if (ov2659->xvclk_frequency < 6000000 || 1461 ov2659->xvclk_frequency > 27000000) 1462 return -EINVAL; 1463 1464 /* Optional gpio don't fail if not present */ 1465 ov2659->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown", 1466 GPIOD_OUT_LOW); 1467 if (IS_ERR(ov2659->pwdn_gpio)) 1468 return PTR_ERR(ov2659->pwdn_gpio); 1469 1470 /* Optional gpio don't fail if not present */ 1471 ov2659->resetb_gpio = devm_gpiod_get_optional(&client->dev, "reset", 1472 GPIOD_OUT_HIGH); 1473 if (IS_ERR(ov2659->resetb_gpio)) 1474 return PTR_ERR(ov2659->resetb_gpio); 1475 1476 v4l2_ctrl_handler_init(&ov2659->ctrls, 2); 1477 ov2659->link_frequency = 1478 v4l2_ctrl_new_std(&ov2659->ctrls, &ov2659_ctrl_ops, 1479 V4L2_CID_PIXEL_RATE, 1480 pdata->link_frequency / 2, 1481 pdata->link_frequency, 1, 1482 pdata->link_frequency); 1483 v4l2_ctrl_new_std_menu_items(&ov2659->ctrls, &ov2659_ctrl_ops, 1484 V4L2_CID_TEST_PATTERN, 1485 ARRAY_SIZE(ov2659_test_pattern_menu) - 1, 1486 0, 0, ov2659_test_pattern_menu); 1487 ov2659->sd.ctrl_handler = &ov2659->ctrls; 1488 1489 if (ov2659->ctrls.error) { 1490 dev_err(&client->dev, "%s: control initialization error %d\n", 1491 __func__, ov2659->ctrls.error); 1492 return ov2659->ctrls.error; 1493 } 1494 1495 sd = &ov2659->sd; 1496 client->flags |= I2C_CLIENT_SCCB; 1497 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1498 v4l2_i2c_subdev_init(sd, client, &ov2659_subdev_ops); 1499 1500 sd->internal_ops = &ov2659_subdev_internal_ops; 1501 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | 1502 V4L2_SUBDEV_FL_HAS_EVENTS; 1503 #endif 1504 1505 #if defined(CONFIG_MEDIA_CONTROLLER) 1506 ov2659->pad.flags = MEDIA_PAD_FL_SOURCE; 1507 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR; 1508 ret = media_entity_pads_init(&sd->entity, 1, &ov2659->pad); 1509 if (ret < 0) { 1510 v4l2_ctrl_handler_free(&ov2659->ctrls); 1511 return ret; 1512 } 1513 #endif 1514 1515 mutex_init(&ov2659->lock); 1516 1517 ov2659_get_default_format(&ov2659->format); 1518 ov2659->frame_size = &ov2659_framesizes[2]; 1519 ov2659->format_ctrl_regs = ov2659_formats[0].format_ctrl_regs; 1520 1521 ov2659_power_on(&client->dev); 1522 1523 ret = ov2659_detect(sd); 1524 if (ret < 0) 1525 goto error; 1526 1527 /* Calculate the PLL register value needed */ 1528 ov2659_pll_calc_params(ov2659); 1529 1530 ret = v4l2_async_register_subdev(&ov2659->sd); 1531 if (ret) 1532 goto error; 1533 1534 dev_info(&client->dev, "%s sensor driver registered !!\n", sd->name); 1535 1536 pm_runtime_set_active(&client->dev); 1537 pm_runtime_enable(&client->dev); 1538 pm_runtime_idle(&client->dev); 1539 1540 return 0; 1541 1542 error: 1543 v4l2_ctrl_handler_free(&ov2659->ctrls); 1544 ov2659_power_off(&client->dev); 1545 media_entity_cleanup(&sd->entity); 1546 mutex_destroy(&ov2659->lock); 1547 return ret; 1548 } 1549 1550 static int ov2659_remove(struct i2c_client *client) 1551 { 1552 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1553 struct ov2659 *ov2659 = to_ov2659(sd); 1554 1555 v4l2_ctrl_handler_free(&ov2659->ctrls); 1556 v4l2_async_unregister_subdev(sd); 1557 media_entity_cleanup(&sd->entity); 1558 mutex_destroy(&ov2659->lock); 1559 1560 pm_runtime_disable(&client->dev); 1561 if (!pm_runtime_status_suspended(&client->dev)) 1562 ov2659_power_off(&client->dev); 1563 pm_runtime_set_suspended(&client->dev); 1564 1565 return 0; 1566 } 1567 1568 static const struct dev_pm_ops ov2659_pm_ops = { 1569 SET_RUNTIME_PM_OPS(ov2659_power_off, ov2659_power_on, NULL) 1570 }; 1571 1572 static const struct i2c_device_id ov2659_id[] = { 1573 { "ov2659", 0 }, 1574 { /* sentinel */ }, 1575 }; 1576 MODULE_DEVICE_TABLE(i2c, ov2659_id); 1577 1578 #if IS_ENABLED(CONFIG_OF) 1579 static const struct of_device_id ov2659_of_match[] = { 1580 { .compatible = "ovti,ov2659", }, 1581 { /* sentinel */ }, 1582 }; 1583 MODULE_DEVICE_TABLE(of, ov2659_of_match); 1584 #endif 1585 1586 static struct i2c_driver ov2659_i2c_driver = { 1587 .driver = { 1588 .name = DRIVER_NAME, 1589 .pm = &ov2659_pm_ops, 1590 .of_match_table = of_match_ptr(ov2659_of_match), 1591 }, 1592 .probe_new = ov2659_probe, 1593 .remove = ov2659_remove, 1594 .id_table = ov2659_id, 1595 }; 1596 1597 module_i2c_driver(ov2659_i2c_driver); 1598 1599 MODULE_AUTHOR("Benoit Parrot <bparrot@ti.com>"); 1600 MODULE_DESCRIPTION("OV2659 CMOS Image Sensor driver"); 1601 MODULE_LICENSE("GPL v2"); 1602