1 /* 2 * Omnivision OV2659 CMOS Image Sensor driver 3 * 4 * Copyright (C) 2015 Texas Instruments, Inc. 5 * 6 * Benoit Parrot <bparrot@ti.com> 7 * Lad, Prabhakar <prabhakar.csengg@gmail.com> 8 * 9 * This program is free software; you may redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; version 2 of the License. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 15 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 16 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 17 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 18 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 * SOFTWARE. 21 */ 22 23 #include <linux/clk.h> 24 #include <linux/delay.h> 25 #include <linux/i2c.h> 26 #include <linux/module.h> 27 #include <linux/of_graph.h> 28 29 #include <media/i2c/ov2659.h> 30 #include <media/v4l2-ctrls.h> 31 #include <media/v4l2-event.h> 32 #include <media/v4l2-fwnode.h> 33 #include <media/v4l2-image-sizes.h> 34 #include <media/v4l2-subdev.h> 35 36 #define DRIVER_NAME "ov2659" 37 38 /* 39 * OV2659 register definitions 40 */ 41 #define REG_SOFTWARE_STANDBY 0x0100 42 #define REG_SOFTWARE_RESET 0x0103 43 #define REG_IO_CTRL00 0x3000 44 #define REG_IO_CTRL01 0x3001 45 #define REG_IO_CTRL02 0x3002 46 #define REG_OUTPUT_VALUE00 0x3008 47 #define REG_OUTPUT_VALUE01 0x3009 48 #define REG_OUTPUT_VALUE02 0x300d 49 #define REG_OUTPUT_SELECT00 0x300e 50 #define REG_OUTPUT_SELECT01 0x300f 51 #define REG_OUTPUT_SELECT02 0x3010 52 #define REG_OUTPUT_DRIVE 0x3011 53 #define REG_INPUT_READOUT00 0x302d 54 #define REG_INPUT_READOUT01 0x302e 55 #define REG_INPUT_READOUT02 0x302f 56 57 #define REG_SC_PLL_CTRL0 0x3003 58 #define REG_SC_PLL_CTRL1 0x3004 59 #define REG_SC_PLL_CTRL2 0x3005 60 #define REG_SC_PLL_CTRL3 0x3006 61 #define REG_SC_CHIP_ID_H 0x300a 62 #define REG_SC_CHIP_ID_L 0x300b 63 #define REG_SC_PWC 0x3014 64 #define REG_SC_CLKRST0 0x301a 65 #define REG_SC_CLKRST1 0x301b 66 #define REG_SC_CLKRST2 0x301c 67 #define REG_SC_CLKRST3 0x301d 68 #define REG_SC_SUB_ID 0x302a 69 #define REG_SC_SCCB_ID 0x302b 70 71 #define REG_GROUP_ADDRESS_00 0x3200 72 #define REG_GROUP_ADDRESS_01 0x3201 73 #define REG_GROUP_ADDRESS_02 0x3202 74 #define REG_GROUP_ADDRESS_03 0x3203 75 #define REG_GROUP_ACCESS 0x3208 76 77 #define REG_AWB_R_GAIN_H 0x3400 78 #define REG_AWB_R_GAIN_L 0x3401 79 #define REG_AWB_G_GAIN_H 0x3402 80 #define REG_AWB_G_GAIN_L 0x3403 81 #define REG_AWB_B_GAIN_H 0x3404 82 #define REG_AWB_B_GAIN_L 0x3405 83 #define REG_AWB_MANUAL_CONTROL 0x3406 84 85 #define REG_TIMING_HS_H 0x3800 86 #define REG_TIMING_HS_L 0x3801 87 #define REG_TIMING_VS_H 0x3802 88 #define REG_TIMING_VS_L 0x3803 89 #define REG_TIMING_HW_H 0x3804 90 #define REG_TIMING_HW_L 0x3805 91 #define REG_TIMING_VH_H 0x3806 92 #define REG_TIMING_VH_L 0x3807 93 #define REG_TIMING_DVPHO_H 0x3808 94 #define REG_TIMING_DVPHO_L 0x3809 95 #define REG_TIMING_DVPVO_H 0x380a 96 #define REG_TIMING_DVPVO_L 0x380b 97 #define REG_TIMING_HTS_H 0x380c 98 #define REG_TIMING_HTS_L 0x380d 99 #define REG_TIMING_VTS_H 0x380e 100 #define REG_TIMING_VTS_L 0x380f 101 #define REG_TIMING_HOFFS_H 0x3810 102 #define REG_TIMING_HOFFS_L 0x3811 103 #define REG_TIMING_VOFFS_H 0x3812 104 #define REG_TIMING_VOFFS_L 0x3813 105 #define REG_TIMING_XINC 0x3814 106 #define REG_TIMING_YINC 0x3815 107 #define REG_TIMING_VERT_FORMAT 0x3820 108 #define REG_TIMING_HORIZ_FORMAT 0x3821 109 110 #define REG_FORMAT_CTRL00 0x4300 111 112 #define REG_VFIFO_READ_START_H 0x4608 113 #define REG_VFIFO_READ_START_L 0x4609 114 115 #define REG_DVP_CTRL02 0x4708 116 117 #define REG_ISP_CTRL00 0x5000 118 #define REG_ISP_CTRL01 0x5001 119 #define REG_ISP_CTRL02 0x5002 120 121 #define REG_LENC_RED_X0_H 0x500c 122 #define REG_LENC_RED_X0_L 0x500d 123 #define REG_LENC_RED_Y0_H 0x500e 124 #define REG_LENC_RED_Y0_L 0x500f 125 #define REG_LENC_RED_A1 0x5010 126 #define REG_LENC_RED_B1 0x5011 127 #define REG_LENC_RED_A2_B2 0x5012 128 #define REG_LENC_GREEN_X0_H 0x5013 129 #define REG_LENC_GREEN_X0_L 0x5014 130 #define REG_LENC_GREEN_Y0_H 0x5015 131 #define REG_LENC_GREEN_Y0_L 0x5016 132 #define REG_LENC_GREEN_A1 0x5017 133 #define REG_LENC_GREEN_B1 0x5018 134 #define REG_LENC_GREEN_A2_B2 0x5019 135 #define REG_LENC_BLUE_X0_H 0x501a 136 #define REG_LENC_BLUE_X0_L 0x501b 137 #define REG_LENC_BLUE_Y0_H 0x501c 138 #define REG_LENC_BLUE_Y0_L 0x501d 139 #define REG_LENC_BLUE_A1 0x501e 140 #define REG_LENC_BLUE_B1 0x501f 141 #define REG_LENC_BLUE_A2_B2 0x5020 142 143 #define REG_AWB_CTRL00 0x5035 144 #define REG_AWB_CTRL01 0x5036 145 #define REG_AWB_CTRL02 0x5037 146 #define REG_AWB_CTRL03 0x5038 147 #define REG_AWB_CTRL04 0x5039 148 #define REG_AWB_LOCAL_LIMIT 0x503a 149 #define REG_AWB_CTRL12 0x5049 150 #define REG_AWB_CTRL13 0x504a 151 #define REG_AWB_CTRL14 0x504b 152 153 #define REG_SHARPENMT_THRESH1 0x5064 154 #define REG_SHARPENMT_THRESH2 0x5065 155 #define REG_SHARPENMT_OFFSET1 0x5066 156 #define REG_SHARPENMT_OFFSET2 0x5067 157 #define REG_DENOISE_THRESH1 0x5068 158 #define REG_DENOISE_THRESH2 0x5069 159 #define REG_DENOISE_OFFSET1 0x506a 160 #define REG_DENOISE_OFFSET2 0x506b 161 #define REG_SHARPEN_THRESH1 0x506c 162 #define REG_SHARPEN_THRESH2 0x506d 163 #define REG_CIP_CTRL00 0x506e 164 #define REG_CIP_CTRL01 0x506f 165 166 #define REG_CMX_SIGN 0x5079 167 #define REG_CMX_MISC_CTRL 0x507a 168 169 #define REG_PRE_ISP_CTRL00 0x50a0 170 #define TEST_PATTERN_ENABLE BIT(7) 171 #define VERTICAL_COLOR_BAR_MASK 0x53 172 173 #define REG_NULL 0x0000 /* Array end token */ 174 175 #define OV265X_ID(_msb, _lsb) ((_msb) << 8 | (_lsb)) 176 #define OV2659_ID 0x2656 177 178 struct sensor_register { 179 u16 addr; 180 u8 value; 181 }; 182 183 struct ov2659_framesize { 184 u16 width; 185 u16 height; 186 u16 max_exp_lines; 187 const struct sensor_register *regs; 188 }; 189 190 struct ov2659_pll_ctrl { 191 u8 ctrl1; 192 u8 ctrl2; 193 u8 ctrl3; 194 }; 195 196 struct ov2659_pixfmt { 197 u32 code; 198 /* Output format Register Value (REG_FORMAT_CTRL00) */ 199 struct sensor_register *format_ctrl_regs; 200 }; 201 202 struct pll_ctrl_reg { 203 unsigned int div; 204 unsigned char reg; 205 }; 206 207 struct ov2659 { 208 struct v4l2_subdev sd; 209 struct media_pad pad; 210 struct v4l2_mbus_framefmt format; 211 unsigned int xvclk_frequency; 212 const struct ov2659_platform_data *pdata; 213 struct mutex lock; 214 struct i2c_client *client; 215 struct v4l2_ctrl_handler ctrls; 216 struct v4l2_ctrl *link_frequency; 217 const struct ov2659_framesize *frame_size; 218 struct sensor_register *format_ctrl_regs; 219 struct ov2659_pll_ctrl pll; 220 int streaming; 221 }; 222 223 static const struct sensor_register ov2659_init_regs[] = { 224 { REG_IO_CTRL00, 0x03 }, 225 { REG_IO_CTRL01, 0xff }, 226 { REG_IO_CTRL02, 0xe0 }, 227 { 0x3633, 0x3d }, 228 { 0x3620, 0x02 }, 229 { 0x3631, 0x11 }, 230 { 0x3612, 0x04 }, 231 { 0x3630, 0x20 }, 232 { 0x4702, 0x02 }, 233 { 0x370c, 0x34 }, 234 { REG_TIMING_HS_H, 0x00 }, 235 { REG_TIMING_HS_L, 0x00 }, 236 { REG_TIMING_VS_H, 0x00 }, 237 { REG_TIMING_VS_L, 0x00 }, 238 { REG_TIMING_HW_H, 0x06 }, 239 { REG_TIMING_HW_L, 0x5f }, 240 { REG_TIMING_VH_H, 0x04 }, 241 { REG_TIMING_VH_L, 0xb7 }, 242 { REG_TIMING_DVPHO_H, 0x03 }, 243 { REG_TIMING_DVPHO_L, 0x20 }, 244 { REG_TIMING_DVPVO_H, 0x02 }, 245 { REG_TIMING_DVPVO_L, 0x58 }, 246 { REG_TIMING_HTS_H, 0x05 }, 247 { REG_TIMING_HTS_L, 0x14 }, 248 { REG_TIMING_VTS_H, 0x02 }, 249 { REG_TIMING_VTS_L, 0x68 }, 250 { REG_TIMING_HOFFS_L, 0x08 }, 251 { REG_TIMING_VOFFS_L, 0x02 }, 252 { REG_TIMING_XINC, 0x31 }, 253 { REG_TIMING_YINC, 0x31 }, 254 { 0x3a02, 0x02 }, 255 { 0x3a03, 0x68 }, 256 { 0x3a08, 0x00 }, 257 { 0x3a09, 0x5c }, 258 { 0x3a0a, 0x00 }, 259 { 0x3a0b, 0x4d }, 260 { 0x3a0d, 0x08 }, 261 { 0x3a0e, 0x06 }, 262 { 0x3a14, 0x02 }, 263 { 0x3a15, 0x28 }, 264 { REG_DVP_CTRL02, 0x01 }, 265 { 0x3623, 0x00 }, 266 { 0x3634, 0x76 }, 267 { 0x3701, 0x44 }, 268 { 0x3702, 0x18 }, 269 { 0x3703, 0x24 }, 270 { 0x3704, 0x24 }, 271 { 0x3705, 0x0c }, 272 { REG_TIMING_VERT_FORMAT, 0x81 }, 273 { REG_TIMING_HORIZ_FORMAT, 0x01 }, 274 { 0x370a, 0x52 }, 275 { REG_VFIFO_READ_START_H, 0x00 }, 276 { REG_VFIFO_READ_START_L, 0x80 }, 277 { REG_FORMAT_CTRL00, 0x30 }, 278 { 0x5086, 0x02 }, 279 { REG_ISP_CTRL00, 0xfb }, 280 { REG_ISP_CTRL01, 0x1f }, 281 { REG_ISP_CTRL02, 0x00 }, 282 { 0x5025, 0x0e }, 283 { 0x5026, 0x18 }, 284 { 0x5027, 0x34 }, 285 { 0x5028, 0x4c }, 286 { 0x5029, 0x62 }, 287 { 0x502a, 0x74 }, 288 { 0x502b, 0x85 }, 289 { 0x502c, 0x92 }, 290 { 0x502d, 0x9e }, 291 { 0x502e, 0xb2 }, 292 { 0x502f, 0xc0 }, 293 { 0x5030, 0xcc }, 294 { 0x5031, 0xe0 }, 295 { 0x5032, 0xee }, 296 { 0x5033, 0xf6 }, 297 { 0x5034, 0x11 }, 298 { 0x5070, 0x1c }, 299 { 0x5071, 0x5b }, 300 { 0x5072, 0x05 }, 301 { 0x5073, 0x20 }, 302 { 0x5074, 0x94 }, 303 { 0x5075, 0xb4 }, 304 { 0x5076, 0xb4 }, 305 { 0x5077, 0xaf }, 306 { 0x5078, 0x05 }, 307 { REG_CMX_SIGN, 0x98 }, 308 { REG_CMX_MISC_CTRL, 0x21 }, 309 { REG_AWB_CTRL00, 0x6a }, 310 { REG_AWB_CTRL01, 0x11 }, 311 { REG_AWB_CTRL02, 0x92 }, 312 { REG_AWB_CTRL03, 0x21 }, 313 { REG_AWB_CTRL04, 0xe1 }, 314 { REG_AWB_LOCAL_LIMIT, 0x01 }, 315 { 0x503c, 0x05 }, 316 { 0x503d, 0x08 }, 317 { 0x503e, 0x08 }, 318 { 0x503f, 0x64 }, 319 { 0x5040, 0x58 }, 320 { 0x5041, 0x2a }, 321 { 0x5042, 0xc5 }, 322 { 0x5043, 0x2e }, 323 { 0x5044, 0x3a }, 324 { 0x5045, 0x3c }, 325 { 0x5046, 0x44 }, 326 { 0x5047, 0xf8 }, 327 { 0x5048, 0x08 }, 328 { REG_AWB_CTRL12, 0x70 }, 329 { REG_AWB_CTRL13, 0xf0 }, 330 { REG_AWB_CTRL14, 0xf0 }, 331 { REG_LENC_RED_X0_H, 0x03 }, 332 { REG_LENC_RED_X0_L, 0x20 }, 333 { REG_LENC_RED_Y0_H, 0x02 }, 334 { REG_LENC_RED_Y0_L, 0x5c }, 335 { REG_LENC_RED_A1, 0x48 }, 336 { REG_LENC_RED_B1, 0x00 }, 337 { REG_LENC_RED_A2_B2, 0x66 }, 338 { REG_LENC_GREEN_X0_H, 0x03 }, 339 { REG_LENC_GREEN_X0_L, 0x30 }, 340 { REG_LENC_GREEN_Y0_H, 0x02 }, 341 { REG_LENC_GREEN_Y0_L, 0x7c }, 342 { REG_LENC_GREEN_A1, 0x40 }, 343 { REG_LENC_GREEN_B1, 0x00 }, 344 { REG_LENC_GREEN_A2_B2, 0x66 }, 345 { REG_LENC_BLUE_X0_H, 0x03 }, 346 { REG_LENC_BLUE_X0_L, 0x10 }, 347 { REG_LENC_BLUE_Y0_H, 0x02 }, 348 { REG_LENC_BLUE_Y0_L, 0x7c }, 349 { REG_LENC_BLUE_A1, 0x3a }, 350 { REG_LENC_BLUE_B1, 0x00 }, 351 { REG_LENC_BLUE_A2_B2, 0x66 }, 352 { REG_CIP_CTRL00, 0x44 }, 353 { REG_SHARPENMT_THRESH1, 0x08 }, 354 { REG_SHARPENMT_THRESH2, 0x10 }, 355 { REG_SHARPENMT_OFFSET1, 0x12 }, 356 { REG_SHARPENMT_OFFSET2, 0x02 }, 357 { REG_SHARPEN_THRESH1, 0x08 }, 358 { REG_SHARPEN_THRESH2, 0x10 }, 359 { REG_CIP_CTRL01, 0xa6 }, 360 { REG_DENOISE_THRESH1, 0x08 }, 361 { REG_DENOISE_THRESH2, 0x10 }, 362 { REG_DENOISE_OFFSET1, 0x04 }, 363 { REG_DENOISE_OFFSET2, 0x12 }, 364 { 0x507e, 0x40 }, 365 { 0x507f, 0x20 }, 366 { 0x507b, 0x02 }, 367 { REG_CMX_MISC_CTRL, 0x01 }, 368 { 0x5084, 0x0c }, 369 { 0x5085, 0x3e }, 370 { 0x5005, 0x80 }, 371 { 0x3a0f, 0x30 }, 372 { 0x3a10, 0x28 }, 373 { 0x3a1b, 0x32 }, 374 { 0x3a1e, 0x26 }, 375 { 0x3a11, 0x60 }, 376 { 0x3a1f, 0x14 }, 377 { 0x5060, 0x69 }, 378 { 0x5061, 0x7d }, 379 { 0x5062, 0x7d }, 380 { 0x5063, 0x69 }, 381 { REG_NULL, 0x00 }, 382 }; 383 384 /* 1280X720 720p */ 385 static struct sensor_register ov2659_720p[] = { 386 { REG_TIMING_HS_H, 0x00 }, 387 { REG_TIMING_HS_L, 0xa0 }, 388 { REG_TIMING_VS_H, 0x00 }, 389 { REG_TIMING_VS_L, 0xf0 }, 390 { REG_TIMING_HW_H, 0x05 }, 391 { REG_TIMING_HW_L, 0xbf }, 392 { REG_TIMING_VH_H, 0x03 }, 393 { REG_TIMING_VH_L, 0xcb }, 394 { REG_TIMING_DVPHO_H, 0x05 }, 395 { REG_TIMING_DVPHO_L, 0x00 }, 396 { REG_TIMING_DVPVO_H, 0x02 }, 397 { REG_TIMING_DVPVO_L, 0xd0 }, 398 { REG_TIMING_HTS_H, 0x06 }, 399 { REG_TIMING_HTS_L, 0x4c }, 400 { REG_TIMING_VTS_H, 0x02 }, 401 { REG_TIMING_VTS_L, 0xe8 }, 402 { REG_TIMING_HOFFS_L, 0x10 }, 403 { REG_TIMING_VOFFS_L, 0x06 }, 404 { REG_TIMING_XINC, 0x11 }, 405 { REG_TIMING_YINC, 0x11 }, 406 { REG_TIMING_VERT_FORMAT, 0x80 }, 407 { REG_TIMING_HORIZ_FORMAT, 0x00 }, 408 { 0x3a03, 0xe8 }, 409 { 0x3a09, 0x6f }, 410 { 0x3a0b, 0x5d }, 411 { 0x3a15, 0x9a }, 412 { REG_NULL, 0x00 }, 413 }; 414 415 /* 1600X1200 UXGA */ 416 static struct sensor_register ov2659_uxga[] = { 417 { REG_TIMING_HS_H, 0x00 }, 418 { REG_TIMING_HS_L, 0x00 }, 419 { REG_TIMING_VS_H, 0x00 }, 420 { REG_TIMING_VS_L, 0x00 }, 421 { REG_TIMING_HW_H, 0x06 }, 422 { REG_TIMING_HW_L, 0x5f }, 423 { REG_TIMING_VH_H, 0x04 }, 424 { REG_TIMING_VH_L, 0xbb }, 425 { REG_TIMING_DVPHO_H, 0x06 }, 426 { REG_TIMING_DVPHO_L, 0x40 }, 427 { REG_TIMING_DVPVO_H, 0x04 }, 428 { REG_TIMING_DVPVO_L, 0xb0 }, 429 { REG_TIMING_HTS_H, 0x07 }, 430 { REG_TIMING_HTS_L, 0x9f }, 431 { REG_TIMING_VTS_H, 0x04 }, 432 { REG_TIMING_VTS_L, 0xd0 }, 433 { REG_TIMING_HOFFS_L, 0x10 }, 434 { REG_TIMING_VOFFS_L, 0x06 }, 435 { REG_TIMING_XINC, 0x11 }, 436 { REG_TIMING_YINC, 0x11 }, 437 { 0x3a02, 0x04 }, 438 { 0x3a03, 0xd0 }, 439 { 0x3a08, 0x00 }, 440 { 0x3a09, 0xb8 }, 441 { 0x3a0a, 0x00 }, 442 { 0x3a0b, 0x9a }, 443 { 0x3a0d, 0x08 }, 444 { 0x3a0e, 0x06 }, 445 { 0x3a14, 0x04 }, 446 { 0x3a15, 0x50 }, 447 { 0x3623, 0x00 }, 448 { 0x3634, 0x44 }, 449 { 0x3701, 0x44 }, 450 { 0x3702, 0x30 }, 451 { 0x3703, 0x48 }, 452 { 0x3704, 0x48 }, 453 { 0x3705, 0x18 }, 454 { REG_TIMING_VERT_FORMAT, 0x80 }, 455 { REG_TIMING_HORIZ_FORMAT, 0x00 }, 456 { 0x370a, 0x12 }, 457 { REG_VFIFO_READ_START_H, 0x00 }, 458 { REG_VFIFO_READ_START_L, 0x80 }, 459 { REG_ISP_CTRL02, 0x00 }, 460 { REG_NULL, 0x00 }, 461 }; 462 463 /* 1280X1024 SXGA */ 464 static struct sensor_register ov2659_sxga[] = { 465 { REG_TIMING_HS_H, 0x00 }, 466 { REG_TIMING_HS_L, 0x00 }, 467 { REG_TIMING_VS_H, 0x00 }, 468 { REG_TIMING_VS_L, 0x00 }, 469 { REG_TIMING_HW_H, 0x06 }, 470 { REG_TIMING_HW_L, 0x5f }, 471 { REG_TIMING_VH_H, 0x04 }, 472 { REG_TIMING_VH_L, 0xb7 }, 473 { REG_TIMING_DVPHO_H, 0x05 }, 474 { REG_TIMING_DVPHO_L, 0x00 }, 475 { REG_TIMING_DVPVO_H, 0x04 }, 476 { REG_TIMING_DVPVO_L, 0x00 }, 477 { REG_TIMING_HTS_H, 0x07 }, 478 { REG_TIMING_HTS_L, 0x9c }, 479 { REG_TIMING_VTS_H, 0x04 }, 480 { REG_TIMING_VTS_L, 0xd0 }, 481 { REG_TIMING_HOFFS_L, 0x10 }, 482 { REG_TIMING_VOFFS_L, 0x06 }, 483 { REG_TIMING_XINC, 0x11 }, 484 { REG_TIMING_YINC, 0x11 }, 485 { 0x3a02, 0x02 }, 486 { 0x3a03, 0x68 }, 487 { 0x3a08, 0x00 }, 488 { 0x3a09, 0x5c }, 489 { 0x3a0a, 0x00 }, 490 { 0x3a0b, 0x4d }, 491 { 0x3a0d, 0x08 }, 492 { 0x3a0e, 0x06 }, 493 { 0x3a14, 0x02 }, 494 { 0x3a15, 0x28 }, 495 { 0x3623, 0x00 }, 496 { 0x3634, 0x76 }, 497 { 0x3701, 0x44 }, 498 { 0x3702, 0x18 }, 499 { 0x3703, 0x24 }, 500 { 0x3704, 0x24 }, 501 { 0x3705, 0x0c }, 502 { REG_TIMING_VERT_FORMAT, 0x80 }, 503 { REG_TIMING_HORIZ_FORMAT, 0x00 }, 504 { 0x370a, 0x52 }, 505 { REG_VFIFO_READ_START_H, 0x00 }, 506 { REG_VFIFO_READ_START_L, 0x80 }, 507 { REG_ISP_CTRL02, 0x00 }, 508 { REG_NULL, 0x00 }, 509 }; 510 511 /* 1024X768 SXGA */ 512 static struct sensor_register ov2659_xga[] = { 513 { REG_TIMING_HS_H, 0x00 }, 514 { REG_TIMING_HS_L, 0x00 }, 515 { REG_TIMING_VS_H, 0x00 }, 516 { REG_TIMING_VS_L, 0x00 }, 517 { REG_TIMING_HW_H, 0x06 }, 518 { REG_TIMING_HW_L, 0x5f }, 519 { REG_TIMING_VH_H, 0x04 }, 520 { REG_TIMING_VH_L, 0xb7 }, 521 { REG_TIMING_DVPHO_H, 0x04 }, 522 { REG_TIMING_DVPHO_L, 0x00 }, 523 { REG_TIMING_DVPVO_H, 0x03 }, 524 { REG_TIMING_DVPVO_L, 0x00 }, 525 { REG_TIMING_HTS_H, 0x07 }, 526 { REG_TIMING_HTS_L, 0x9c }, 527 { REG_TIMING_VTS_H, 0x04 }, 528 { REG_TIMING_VTS_L, 0xd0 }, 529 { REG_TIMING_HOFFS_L, 0x10 }, 530 { REG_TIMING_VOFFS_L, 0x06 }, 531 { REG_TIMING_XINC, 0x11 }, 532 { REG_TIMING_YINC, 0x11 }, 533 { 0x3a02, 0x02 }, 534 { 0x3a03, 0x68 }, 535 { 0x3a08, 0x00 }, 536 { 0x3a09, 0x5c }, 537 { 0x3a0a, 0x00 }, 538 { 0x3a0b, 0x4d }, 539 { 0x3a0d, 0x08 }, 540 { 0x3a0e, 0x06 }, 541 { 0x3a14, 0x02 }, 542 { 0x3a15, 0x28 }, 543 { 0x3623, 0x00 }, 544 { 0x3634, 0x76 }, 545 { 0x3701, 0x44 }, 546 { 0x3702, 0x18 }, 547 { 0x3703, 0x24 }, 548 { 0x3704, 0x24 }, 549 { 0x3705, 0x0c }, 550 { REG_TIMING_VERT_FORMAT, 0x80 }, 551 { REG_TIMING_HORIZ_FORMAT, 0x00 }, 552 { 0x370a, 0x52 }, 553 { REG_VFIFO_READ_START_H, 0x00 }, 554 { REG_VFIFO_READ_START_L, 0x80 }, 555 { REG_ISP_CTRL02, 0x00 }, 556 { REG_NULL, 0x00 }, 557 }; 558 559 /* 800X600 SVGA */ 560 static struct sensor_register ov2659_svga[] = { 561 { REG_TIMING_HS_H, 0x00 }, 562 { REG_TIMING_HS_L, 0x00 }, 563 { REG_TIMING_VS_H, 0x00 }, 564 { REG_TIMING_VS_L, 0x00 }, 565 { REG_TIMING_HW_H, 0x06 }, 566 { REG_TIMING_HW_L, 0x5f }, 567 { REG_TIMING_VH_H, 0x04 }, 568 { REG_TIMING_VH_L, 0xb7 }, 569 { REG_TIMING_DVPHO_H, 0x03 }, 570 { REG_TIMING_DVPHO_L, 0x20 }, 571 { REG_TIMING_DVPVO_H, 0x02 }, 572 { REG_TIMING_DVPVO_L, 0x58 }, 573 { REG_TIMING_HTS_H, 0x05 }, 574 { REG_TIMING_HTS_L, 0x14 }, 575 { REG_TIMING_VTS_H, 0x02 }, 576 { REG_TIMING_VTS_L, 0x68 }, 577 { REG_TIMING_HOFFS_L, 0x08 }, 578 { REG_TIMING_VOFFS_L, 0x02 }, 579 { REG_TIMING_XINC, 0x31 }, 580 { REG_TIMING_YINC, 0x31 }, 581 { 0x3a02, 0x02 }, 582 { 0x3a03, 0x68 }, 583 { 0x3a08, 0x00 }, 584 { 0x3a09, 0x5c }, 585 { 0x3a0a, 0x00 }, 586 { 0x3a0b, 0x4d }, 587 { 0x3a0d, 0x08 }, 588 { 0x3a0e, 0x06 }, 589 { 0x3a14, 0x02 }, 590 { 0x3a15, 0x28 }, 591 { 0x3623, 0x00 }, 592 { 0x3634, 0x76 }, 593 { 0x3701, 0x44 }, 594 { 0x3702, 0x18 }, 595 { 0x3703, 0x24 }, 596 { 0x3704, 0x24 }, 597 { 0x3705, 0x0c }, 598 { REG_TIMING_VERT_FORMAT, 0x81 }, 599 { REG_TIMING_HORIZ_FORMAT, 0x01 }, 600 { 0x370a, 0x52 }, 601 { REG_VFIFO_READ_START_H, 0x00 }, 602 { REG_VFIFO_READ_START_L, 0x80 }, 603 { REG_ISP_CTRL02, 0x00 }, 604 { REG_NULL, 0x00 }, 605 }; 606 607 /* 640X480 VGA */ 608 static struct sensor_register ov2659_vga[] = { 609 { REG_TIMING_HS_H, 0x00 }, 610 { REG_TIMING_HS_L, 0x00 }, 611 { REG_TIMING_VS_H, 0x00 }, 612 { REG_TIMING_VS_L, 0x00 }, 613 { REG_TIMING_HW_H, 0x06 }, 614 { REG_TIMING_HW_L, 0x5f }, 615 { REG_TIMING_VH_H, 0x04 }, 616 { REG_TIMING_VH_L, 0xb7 }, 617 { REG_TIMING_DVPHO_H, 0x02 }, 618 { REG_TIMING_DVPHO_L, 0x80 }, 619 { REG_TIMING_DVPVO_H, 0x01 }, 620 { REG_TIMING_DVPVO_L, 0xe0 }, 621 { REG_TIMING_HTS_H, 0x05 }, 622 { REG_TIMING_HTS_L, 0x14 }, 623 { REG_TIMING_VTS_H, 0x02 }, 624 { REG_TIMING_VTS_L, 0x68 }, 625 { REG_TIMING_HOFFS_L, 0x08 }, 626 { REG_TIMING_VOFFS_L, 0x02 }, 627 { REG_TIMING_XINC, 0x31 }, 628 { REG_TIMING_YINC, 0x31 }, 629 { 0x3a02, 0x02 }, 630 { 0x3a03, 0x68 }, 631 { 0x3a08, 0x00 }, 632 { 0x3a09, 0x5c }, 633 { 0x3a0a, 0x00 }, 634 { 0x3a0b, 0x4d }, 635 { 0x3a0d, 0x08 }, 636 { 0x3a0e, 0x06 }, 637 { 0x3a14, 0x02 }, 638 { 0x3a15, 0x28 }, 639 { 0x3623, 0x00 }, 640 { 0x3634, 0x76 }, 641 { 0x3701, 0x44 }, 642 { 0x3702, 0x18 }, 643 { 0x3703, 0x24 }, 644 { 0x3704, 0x24 }, 645 { 0x3705, 0x0c }, 646 { REG_TIMING_VERT_FORMAT, 0x81 }, 647 { REG_TIMING_HORIZ_FORMAT, 0x01 }, 648 { 0x370a, 0x52 }, 649 { REG_VFIFO_READ_START_H, 0x00 }, 650 { REG_VFIFO_READ_START_L, 0xa0 }, 651 { REG_ISP_CTRL02, 0x10 }, 652 { REG_NULL, 0x00 }, 653 }; 654 655 /* 320X240 QVGA */ 656 static struct sensor_register ov2659_qvga[] = { 657 { REG_TIMING_HS_H, 0x00 }, 658 { REG_TIMING_HS_L, 0x00 }, 659 { REG_TIMING_VS_H, 0x00 }, 660 { REG_TIMING_VS_L, 0x00 }, 661 { REG_TIMING_HW_H, 0x06 }, 662 { REG_TIMING_HW_L, 0x5f }, 663 { REG_TIMING_VH_H, 0x04 }, 664 { REG_TIMING_VH_L, 0xb7 }, 665 { REG_TIMING_DVPHO_H, 0x01 }, 666 { REG_TIMING_DVPHO_L, 0x40 }, 667 { REG_TIMING_DVPVO_H, 0x00 }, 668 { REG_TIMING_DVPVO_L, 0xf0 }, 669 { REG_TIMING_HTS_H, 0x05 }, 670 { REG_TIMING_HTS_L, 0x14 }, 671 { REG_TIMING_VTS_H, 0x02 }, 672 { REG_TIMING_VTS_L, 0x68 }, 673 { REG_TIMING_HOFFS_L, 0x08 }, 674 { REG_TIMING_VOFFS_L, 0x02 }, 675 { REG_TIMING_XINC, 0x31 }, 676 { REG_TIMING_YINC, 0x31 }, 677 { 0x3a02, 0x02 }, 678 { 0x3a03, 0x68 }, 679 { 0x3a08, 0x00 }, 680 { 0x3a09, 0x5c }, 681 { 0x3a0a, 0x00 }, 682 { 0x3a0b, 0x4d }, 683 { 0x3a0d, 0x08 }, 684 { 0x3a0e, 0x06 }, 685 { 0x3a14, 0x02 }, 686 { 0x3a15, 0x28 }, 687 { 0x3623, 0x00 }, 688 { 0x3634, 0x76 }, 689 { 0x3701, 0x44 }, 690 { 0x3702, 0x18 }, 691 { 0x3703, 0x24 }, 692 { 0x3704, 0x24 }, 693 { 0x3705, 0x0c }, 694 { REG_TIMING_VERT_FORMAT, 0x81 }, 695 { REG_TIMING_HORIZ_FORMAT, 0x01 }, 696 { 0x370a, 0x52 }, 697 { REG_VFIFO_READ_START_H, 0x00 }, 698 { REG_VFIFO_READ_START_L, 0xa0 }, 699 { REG_ISP_CTRL02, 0x10 }, 700 { REG_NULL, 0x00 }, 701 }; 702 703 static const struct pll_ctrl_reg ctrl3[] = { 704 { 1, 0x00 }, 705 { 2, 0x02 }, 706 { 3, 0x03 }, 707 { 4, 0x06 }, 708 { 6, 0x0d }, 709 { 8, 0x0e }, 710 { 12, 0x0f }, 711 { 16, 0x12 }, 712 { 24, 0x13 }, 713 { 32, 0x16 }, 714 { 48, 0x1b }, 715 { 64, 0x1e }, 716 { 96, 0x1f }, 717 { 0, 0x00 }, 718 }; 719 720 static const struct pll_ctrl_reg ctrl1[] = { 721 { 2, 0x10 }, 722 { 4, 0x20 }, 723 { 6, 0x30 }, 724 { 8, 0x40 }, 725 { 10, 0x50 }, 726 { 12, 0x60 }, 727 { 14, 0x70 }, 728 { 16, 0x80 }, 729 { 18, 0x90 }, 730 { 20, 0xa0 }, 731 { 22, 0xb0 }, 732 { 24, 0xc0 }, 733 { 26, 0xd0 }, 734 { 28, 0xe0 }, 735 { 30, 0xf0 }, 736 { 0, 0x00 }, 737 }; 738 739 static const struct ov2659_framesize ov2659_framesizes[] = { 740 { /* QVGA */ 741 .width = 320, 742 .height = 240, 743 .regs = ov2659_qvga, 744 .max_exp_lines = 248, 745 }, { /* VGA */ 746 .width = 640, 747 .height = 480, 748 .regs = ov2659_vga, 749 .max_exp_lines = 498, 750 }, { /* SVGA */ 751 .width = 800, 752 .height = 600, 753 .regs = ov2659_svga, 754 .max_exp_lines = 498, 755 }, { /* XGA */ 756 .width = 1024, 757 .height = 768, 758 .regs = ov2659_xga, 759 .max_exp_lines = 498, 760 }, { /* 720P */ 761 .width = 1280, 762 .height = 720, 763 .regs = ov2659_720p, 764 .max_exp_lines = 498, 765 }, { /* SXGA */ 766 .width = 1280, 767 .height = 1024, 768 .regs = ov2659_sxga, 769 .max_exp_lines = 1048, 770 }, { /* UXGA */ 771 .width = 1600, 772 .height = 1200, 773 .regs = ov2659_uxga, 774 .max_exp_lines = 498, 775 }, 776 }; 777 778 /* YUV422 YUYV*/ 779 static struct sensor_register ov2659_format_yuyv[] = { 780 { REG_FORMAT_CTRL00, 0x30 }, 781 { REG_NULL, 0x0 }, 782 }; 783 784 /* YUV422 UYVY */ 785 static struct sensor_register ov2659_format_uyvy[] = { 786 { REG_FORMAT_CTRL00, 0x32 }, 787 { REG_NULL, 0x0 }, 788 }; 789 790 /* Raw Bayer BGGR */ 791 static struct sensor_register ov2659_format_bggr[] = { 792 { REG_FORMAT_CTRL00, 0x00 }, 793 { REG_NULL, 0x0 }, 794 }; 795 796 /* RGB565 */ 797 static struct sensor_register ov2659_format_rgb565[] = { 798 { REG_FORMAT_CTRL00, 0x60 }, 799 { REG_NULL, 0x0 }, 800 }; 801 802 static const struct ov2659_pixfmt ov2659_formats[] = { 803 { 804 .code = MEDIA_BUS_FMT_YUYV8_2X8, 805 .format_ctrl_regs = ov2659_format_yuyv, 806 }, { 807 .code = MEDIA_BUS_FMT_UYVY8_2X8, 808 .format_ctrl_regs = ov2659_format_uyvy, 809 }, { 810 .code = MEDIA_BUS_FMT_RGB565_2X8_BE, 811 .format_ctrl_regs = ov2659_format_rgb565, 812 }, { 813 .code = MEDIA_BUS_FMT_SBGGR8_1X8, 814 .format_ctrl_regs = ov2659_format_bggr, 815 }, 816 }; 817 818 static inline struct ov2659 *to_ov2659(struct v4l2_subdev *sd) 819 { 820 return container_of(sd, struct ov2659, sd); 821 } 822 823 /* sensor register write */ 824 static int ov2659_write(struct i2c_client *client, u16 reg, u8 val) 825 { 826 struct i2c_msg msg; 827 u8 buf[3]; 828 int ret; 829 830 buf[0] = reg >> 8; 831 buf[1] = reg & 0xFF; 832 buf[2] = val; 833 834 msg.addr = client->addr; 835 msg.flags = client->flags; 836 msg.buf = buf; 837 msg.len = sizeof(buf); 838 839 ret = i2c_transfer(client->adapter, &msg, 1); 840 if (ret >= 0) 841 return 0; 842 843 dev_dbg(&client->dev, 844 "ov2659 write reg(0x%x val:0x%x) failed !\n", reg, val); 845 846 return ret; 847 } 848 849 /* sensor register read */ 850 static int ov2659_read(struct i2c_client *client, u16 reg, u8 *val) 851 { 852 struct i2c_msg msg[2]; 853 u8 buf[2]; 854 int ret; 855 856 buf[0] = reg >> 8; 857 buf[1] = reg & 0xFF; 858 859 msg[0].addr = client->addr; 860 msg[0].flags = client->flags; 861 msg[0].buf = buf; 862 msg[0].len = sizeof(buf); 863 864 msg[1].addr = client->addr; 865 msg[1].flags = client->flags | I2C_M_RD; 866 msg[1].buf = buf; 867 msg[1].len = 1; 868 869 ret = i2c_transfer(client->adapter, msg, 2); 870 if (ret >= 0) { 871 *val = buf[0]; 872 return 0; 873 } 874 875 dev_dbg(&client->dev, 876 "ov2659 read reg(0x%x val:0x%x) failed !\n", reg, *val); 877 878 return ret; 879 } 880 881 static int ov2659_write_array(struct i2c_client *client, 882 const struct sensor_register *regs) 883 { 884 int i, ret = 0; 885 886 for (i = 0; ret == 0 && regs[i].addr; i++) 887 ret = ov2659_write(client, regs[i].addr, regs[i].value); 888 889 return ret; 890 } 891 892 static void ov2659_pll_calc_params(struct ov2659 *ov2659) 893 { 894 const struct ov2659_platform_data *pdata = ov2659->pdata; 895 u8 ctrl1_reg = 0, ctrl2_reg = 0, ctrl3_reg = 0; 896 struct i2c_client *client = ov2659->client; 897 unsigned int desired = pdata->link_frequency; 898 u32 prediv, postdiv, mult; 899 u32 bestdelta = -1; 900 u32 delta, actual; 901 int i, j; 902 903 for (i = 0; ctrl1[i].div != 0; i++) { 904 postdiv = ctrl1[i].div; 905 for (j = 0; ctrl3[j].div != 0; j++) { 906 prediv = ctrl3[j].div; 907 for (mult = 1; mult <= 63; mult++) { 908 actual = ov2659->xvclk_frequency; 909 actual *= mult; 910 actual /= prediv; 911 actual /= postdiv; 912 delta = actual - desired; 913 delta = abs(delta); 914 915 if ((delta < bestdelta) || (bestdelta == -1)) { 916 bestdelta = delta; 917 ctrl1_reg = ctrl1[i].reg; 918 ctrl2_reg = mult; 919 ctrl3_reg = ctrl3[j].reg; 920 } 921 } 922 } 923 } 924 925 ov2659->pll.ctrl1 = ctrl1_reg; 926 ov2659->pll.ctrl2 = ctrl2_reg; 927 ov2659->pll.ctrl3 = ctrl3_reg; 928 929 dev_dbg(&client->dev, 930 "Actual reg config: ctrl1_reg: %02x ctrl2_reg: %02x ctrl3_reg: %02x\n", 931 ctrl1_reg, ctrl2_reg, ctrl3_reg); 932 } 933 934 static int ov2659_set_pixel_clock(struct ov2659 *ov2659) 935 { 936 struct i2c_client *client = ov2659->client; 937 struct sensor_register pll_regs[] = { 938 {REG_SC_PLL_CTRL1, ov2659->pll.ctrl1}, 939 {REG_SC_PLL_CTRL2, ov2659->pll.ctrl2}, 940 {REG_SC_PLL_CTRL3, ov2659->pll.ctrl3}, 941 {REG_NULL, 0x00}, 942 }; 943 944 dev_dbg(&client->dev, "%s\n", __func__); 945 946 return ov2659_write_array(client, pll_regs); 947 }; 948 949 static void ov2659_get_default_format(struct v4l2_mbus_framefmt *format) 950 { 951 format->width = ov2659_framesizes[2].width; 952 format->height = ov2659_framesizes[2].height; 953 format->colorspace = V4L2_COLORSPACE_SRGB; 954 format->code = ov2659_formats[0].code; 955 format->field = V4L2_FIELD_NONE; 956 } 957 958 static void ov2659_set_streaming(struct ov2659 *ov2659, int on) 959 { 960 struct i2c_client *client = ov2659->client; 961 int ret; 962 963 on = !!on; 964 965 dev_dbg(&client->dev, "%s: on: %d\n", __func__, on); 966 967 ret = ov2659_write(client, REG_SOFTWARE_STANDBY, on); 968 if (ret) 969 dev_err(&client->dev, "ov2659 soft standby failed\n"); 970 } 971 972 static int ov2659_init(struct v4l2_subdev *sd, u32 val) 973 { 974 struct i2c_client *client = v4l2_get_subdevdata(sd); 975 976 return ov2659_write_array(client, ov2659_init_regs); 977 } 978 979 /* 980 * V4L2 subdev video and pad level operations 981 */ 982 983 static int ov2659_enum_mbus_code(struct v4l2_subdev *sd, 984 struct v4l2_subdev_pad_config *cfg, 985 struct v4l2_subdev_mbus_code_enum *code) 986 { 987 struct i2c_client *client = v4l2_get_subdevdata(sd); 988 989 dev_dbg(&client->dev, "%s:\n", __func__); 990 991 if (code->index >= ARRAY_SIZE(ov2659_formats)) 992 return -EINVAL; 993 994 code->code = ov2659_formats[code->index].code; 995 996 return 0; 997 } 998 999 static int ov2659_enum_frame_sizes(struct v4l2_subdev *sd, 1000 struct v4l2_subdev_pad_config *cfg, 1001 struct v4l2_subdev_frame_size_enum *fse) 1002 { 1003 struct i2c_client *client = v4l2_get_subdevdata(sd); 1004 int i = ARRAY_SIZE(ov2659_formats); 1005 1006 dev_dbg(&client->dev, "%s:\n", __func__); 1007 1008 if (fse->index >= ARRAY_SIZE(ov2659_framesizes)) 1009 return -EINVAL; 1010 1011 while (--i) 1012 if (fse->code == ov2659_formats[i].code) 1013 break; 1014 1015 fse->code = ov2659_formats[i].code; 1016 1017 fse->min_width = ov2659_framesizes[fse->index].width; 1018 fse->max_width = fse->min_width; 1019 fse->max_height = ov2659_framesizes[fse->index].height; 1020 fse->min_height = fse->max_height; 1021 1022 return 0; 1023 } 1024 1025 static int ov2659_get_fmt(struct v4l2_subdev *sd, 1026 struct v4l2_subdev_pad_config *cfg, 1027 struct v4l2_subdev_format *fmt) 1028 { 1029 struct i2c_client *client = v4l2_get_subdevdata(sd); 1030 struct ov2659 *ov2659 = to_ov2659(sd); 1031 1032 dev_dbg(&client->dev, "ov2659_get_fmt\n"); 1033 1034 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 1035 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1036 struct v4l2_mbus_framefmt *mf; 1037 1038 mf = v4l2_subdev_get_try_format(sd, cfg, 0); 1039 mutex_lock(&ov2659->lock); 1040 fmt->format = *mf; 1041 mutex_unlock(&ov2659->lock); 1042 return 0; 1043 #else 1044 return -EINVAL; 1045 #endif 1046 } 1047 1048 mutex_lock(&ov2659->lock); 1049 fmt->format = ov2659->format; 1050 mutex_unlock(&ov2659->lock); 1051 1052 dev_dbg(&client->dev, "ov2659_get_fmt: %x %dx%d\n", 1053 ov2659->format.code, ov2659->format.width, 1054 ov2659->format.height); 1055 1056 return 0; 1057 } 1058 1059 static void __ov2659_try_frame_size(struct v4l2_mbus_framefmt *mf, 1060 const struct ov2659_framesize **size) 1061 { 1062 const struct ov2659_framesize *fsize = &ov2659_framesizes[0]; 1063 const struct ov2659_framesize *match = NULL; 1064 int i = ARRAY_SIZE(ov2659_framesizes); 1065 unsigned int min_err = UINT_MAX; 1066 1067 while (i--) { 1068 int err = abs(fsize->width - mf->width) 1069 + abs(fsize->height - mf->height); 1070 if ((err < min_err) && (fsize->regs[0].addr)) { 1071 min_err = err; 1072 match = fsize; 1073 } 1074 fsize++; 1075 } 1076 1077 if (!match) 1078 match = &ov2659_framesizes[2]; 1079 1080 mf->width = match->width; 1081 mf->height = match->height; 1082 1083 if (size) 1084 *size = match; 1085 } 1086 1087 static int ov2659_set_fmt(struct v4l2_subdev *sd, 1088 struct v4l2_subdev_pad_config *cfg, 1089 struct v4l2_subdev_format *fmt) 1090 { 1091 struct i2c_client *client = v4l2_get_subdevdata(sd); 1092 int index = ARRAY_SIZE(ov2659_formats); 1093 struct v4l2_mbus_framefmt *mf = &fmt->format; 1094 const struct ov2659_framesize *size = NULL; 1095 struct ov2659 *ov2659 = to_ov2659(sd); 1096 int ret = 0; 1097 1098 dev_dbg(&client->dev, "ov2659_set_fmt\n"); 1099 1100 __ov2659_try_frame_size(mf, &size); 1101 1102 while (--index >= 0) 1103 if (ov2659_formats[index].code == mf->code) 1104 break; 1105 1106 if (index < 0) { 1107 index = 0; 1108 mf->code = ov2659_formats[index].code; 1109 } 1110 1111 mf->colorspace = V4L2_COLORSPACE_SRGB; 1112 mf->field = V4L2_FIELD_NONE; 1113 1114 mutex_lock(&ov2659->lock); 1115 1116 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { 1117 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1118 mf = v4l2_subdev_get_try_format(sd, cfg, fmt->pad); 1119 *mf = fmt->format; 1120 #endif 1121 } else { 1122 s64 val; 1123 1124 if (ov2659->streaming) { 1125 mutex_unlock(&ov2659->lock); 1126 return -EBUSY; 1127 } 1128 1129 ov2659->frame_size = size; 1130 ov2659->format = fmt->format; 1131 ov2659->format_ctrl_regs = 1132 ov2659_formats[index].format_ctrl_regs; 1133 1134 if (ov2659->format.code != MEDIA_BUS_FMT_SBGGR8_1X8) 1135 val = ov2659->pdata->link_frequency / 2; 1136 else 1137 val = ov2659->pdata->link_frequency; 1138 1139 ret = v4l2_ctrl_s_ctrl_int64(ov2659->link_frequency, val); 1140 if (ret < 0) 1141 dev_warn(&client->dev, 1142 "failed to set link_frequency rate (%d)\n", 1143 ret); 1144 } 1145 1146 mutex_unlock(&ov2659->lock); 1147 return ret; 1148 } 1149 1150 static int ov2659_set_frame_size(struct ov2659 *ov2659) 1151 { 1152 struct i2c_client *client = ov2659->client; 1153 1154 dev_dbg(&client->dev, "%s\n", __func__); 1155 1156 return ov2659_write_array(ov2659->client, ov2659->frame_size->regs); 1157 } 1158 1159 static int ov2659_set_format(struct ov2659 *ov2659) 1160 { 1161 struct i2c_client *client = ov2659->client; 1162 1163 dev_dbg(&client->dev, "%s\n", __func__); 1164 1165 return ov2659_write_array(ov2659->client, ov2659->format_ctrl_regs); 1166 } 1167 1168 static int ov2659_s_stream(struct v4l2_subdev *sd, int on) 1169 { 1170 struct i2c_client *client = v4l2_get_subdevdata(sd); 1171 struct ov2659 *ov2659 = to_ov2659(sd); 1172 int ret = 0; 1173 1174 dev_dbg(&client->dev, "%s: on: %d\n", __func__, on); 1175 1176 mutex_lock(&ov2659->lock); 1177 1178 on = !!on; 1179 1180 if (ov2659->streaming == on) 1181 goto unlock; 1182 1183 if (!on) { 1184 /* Stop Streaming Sequence */ 1185 ov2659_set_streaming(ov2659, 0); 1186 ov2659->streaming = on; 1187 goto unlock; 1188 } 1189 1190 ret = ov2659_set_pixel_clock(ov2659); 1191 if (!ret) 1192 ret = ov2659_set_frame_size(ov2659); 1193 if (!ret) 1194 ret = ov2659_set_format(ov2659); 1195 if (!ret) { 1196 ov2659_set_streaming(ov2659, 1); 1197 ov2659->streaming = on; 1198 } 1199 1200 unlock: 1201 mutex_unlock(&ov2659->lock); 1202 return ret; 1203 } 1204 1205 static int ov2659_set_test_pattern(struct ov2659 *ov2659, int value) 1206 { 1207 struct i2c_client *client = v4l2_get_subdevdata(&ov2659->sd); 1208 int ret; 1209 u8 val; 1210 1211 ret = ov2659_read(client, REG_PRE_ISP_CTRL00, &val); 1212 if (ret < 0) 1213 return ret; 1214 1215 switch (value) { 1216 case 0: 1217 val &= ~TEST_PATTERN_ENABLE; 1218 break; 1219 case 1: 1220 val &= VERTICAL_COLOR_BAR_MASK; 1221 val |= TEST_PATTERN_ENABLE; 1222 break; 1223 } 1224 1225 return ov2659_write(client, REG_PRE_ISP_CTRL00, val); 1226 } 1227 1228 static int ov2659_s_ctrl(struct v4l2_ctrl *ctrl) 1229 { 1230 struct ov2659 *ov2659 = 1231 container_of(ctrl->handler, struct ov2659, ctrls); 1232 1233 switch (ctrl->id) { 1234 case V4L2_CID_TEST_PATTERN: 1235 return ov2659_set_test_pattern(ov2659, ctrl->val); 1236 } 1237 1238 return 0; 1239 } 1240 1241 static const struct v4l2_ctrl_ops ov2659_ctrl_ops = { 1242 .s_ctrl = ov2659_s_ctrl, 1243 }; 1244 1245 static const char * const ov2659_test_pattern_menu[] = { 1246 "Disabled", 1247 "Vertical Color Bars", 1248 }; 1249 1250 /* ----------------------------------------------------------------------------- 1251 * V4L2 subdev internal operations 1252 */ 1253 1254 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1255 static int ov2659_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) 1256 { 1257 struct i2c_client *client = v4l2_get_subdevdata(sd); 1258 struct v4l2_mbus_framefmt *format = 1259 v4l2_subdev_get_try_format(sd, fh->pad, 0); 1260 1261 dev_dbg(&client->dev, "%s:\n", __func__); 1262 1263 ov2659_get_default_format(format); 1264 1265 return 0; 1266 } 1267 #endif 1268 1269 static const struct v4l2_subdev_core_ops ov2659_subdev_core_ops = { 1270 .log_status = v4l2_ctrl_subdev_log_status, 1271 .subscribe_event = v4l2_ctrl_subdev_subscribe_event, 1272 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 1273 }; 1274 1275 static const struct v4l2_subdev_video_ops ov2659_subdev_video_ops = { 1276 .s_stream = ov2659_s_stream, 1277 }; 1278 1279 static const struct v4l2_subdev_pad_ops ov2659_subdev_pad_ops = { 1280 .enum_mbus_code = ov2659_enum_mbus_code, 1281 .enum_frame_size = ov2659_enum_frame_sizes, 1282 .get_fmt = ov2659_get_fmt, 1283 .set_fmt = ov2659_set_fmt, 1284 }; 1285 1286 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1287 static const struct v4l2_subdev_ops ov2659_subdev_ops = { 1288 .core = &ov2659_subdev_core_ops, 1289 .video = &ov2659_subdev_video_ops, 1290 .pad = &ov2659_subdev_pad_ops, 1291 }; 1292 1293 static const struct v4l2_subdev_internal_ops ov2659_subdev_internal_ops = { 1294 .open = ov2659_open, 1295 }; 1296 #endif 1297 1298 static int ov2659_detect(struct v4l2_subdev *sd) 1299 { 1300 struct i2c_client *client = v4l2_get_subdevdata(sd); 1301 u8 pid = 0; 1302 u8 ver = 0; 1303 int ret; 1304 1305 dev_dbg(&client->dev, "%s:\n", __func__); 1306 1307 ret = ov2659_write(client, REG_SOFTWARE_RESET, 0x01); 1308 if (ret != 0) { 1309 dev_err(&client->dev, "Sensor soft reset failed\n"); 1310 return -ENODEV; 1311 } 1312 usleep_range(1000, 2000); 1313 1314 /* Check sensor revision */ 1315 ret = ov2659_read(client, REG_SC_CHIP_ID_H, &pid); 1316 if (!ret) 1317 ret = ov2659_read(client, REG_SC_CHIP_ID_L, &ver); 1318 1319 if (!ret) { 1320 unsigned short id; 1321 1322 id = OV265X_ID(pid, ver); 1323 if (id != OV2659_ID) { 1324 dev_err(&client->dev, 1325 "Sensor detection failed (%04X, %d)\n", 1326 id, ret); 1327 ret = -ENODEV; 1328 } else { 1329 dev_info(&client->dev, "Found OV%04X sensor\n", id); 1330 ret = ov2659_init(sd, 0); 1331 } 1332 } 1333 1334 return ret; 1335 } 1336 1337 static struct ov2659_platform_data * 1338 ov2659_get_pdata(struct i2c_client *client) 1339 { 1340 struct ov2659_platform_data *pdata; 1341 struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 }; 1342 struct device_node *endpoint; 1343 int ret; 1344 1345 if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node) 1346 return client->dev.platform_data; 1347 1348 endpoint = of_graph_get_next_endpoint(client->dev.of_node, NULL); 1349 if (!endpoint) 1350 return NULL; 1351 1352 ret = v4l2_fwnode_endpoint_alloc_parse(of_fwnode_handle(endpoint), 1353 &bus_cfg); 1354 if (ret) { 1355 pdata = NULL; 1356 goto done; 1357 } 1358 1359 pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL); 1360 if (!pdata) 1361 goto done; 1362 1363 if (!bus_cfg.nr_of_link_frequencies) { 1364 dev_err(&client->dev, 1365 "link-frequencies property not found or too many\n"); 1366 pdata = NULL; 1367 goto done; 1368 } 1369 1370 pdata->link_frequency = bus_cfg.link_frequencies[0]; 1371 1372 done: 1373 v4l2_fwnode_endpoint_free(&bus_cfg); 1374 of_node_put(endpoint); 1375 return pdata; 1376 } 1377 1378 static int ov2659_probe(struct i2c_client *client) 1379 { 1380 const struct ov2659_platform_data *pdata = ov2659_get_pdata(client); 1381 struct v4l2_subdev *sd; 1382 struct ov2659 *ov2659; 1383 struct clk *clk; 1384 int ret; 1385 1386 if (!pdata) { 1387 dev_err(&client->dev, "platform data not specified\n"); 1388 return -EINVAL; 1389 } 1390 1391 ov2659 = devm_kzalloc(&client->dev, sizeof(*ov2659), GFP_KERNEL); 1392 if (!ov2659) 1393 return -ENOMEM; 1394 1395 ov2659->pdata = pdata; 1396 ov2659->client = client; 1397 1398 clk = devm_clk_get(&client->dev, "xvclk"); 1399 if (IS_ERR(clk)) 1400 return PTR_ERR(clk); 1401 1402 ov2659->xvclk_frequency = clk_get_rate(clk); 1403 if (ov2659->xvclk_frequency < 6000000 || 1404 ov2659->xvclk_frequency > 27000000) 1405 return -EINVAL; 1406 1407 v4l2_ctrl_handler_init(&ov2659->ctrls, 2); 1408 ov2659->link_frequency = 1409 v4l2_ctrl_new_std(&ov2659->ctrls, &ov2659_ctrl_ops, 1410 V4L2_CID_PIXEL_RATE, 1411 pdata->link_frequency / 2, 1412 pdata->link_frequency, 1, 1413 pdata->link_frequency); 1414 v4l2_ctrl_new_std_menu_items(&ov2659->ctrls, &ov2659_ctrl_ops, 1415 V4L2_CID_TEST_PATTERN, 1416 ARRAY_SIZE(ov2659_test_pattern_menu) - 1, 1417 0, 0, ov2659_test_pattern_menu); 1418 ov2659->sd.ctrl_handler = &ov2659->ctrls; 1419 1420 if (ov2659->ctrls.error) { 1421 dev_err(&client->dev, "%s: control initialization error %d\n", 1422 __func__, ov2659->ctrls.error); 1423 return ov2659->ctrls.error; 1424 } 1425 1426 sd = &ov2659->sd; 1427 client->flags |= I2C_CLIENT_SCCB; 1428 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1429 v4l2_i2c_subdev_init(sd, client, &ov2659_subdev_ops); 1430 1431 sd->internal_ops = &ov2659_subdev_internal_ops; 1432 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | 1433 V4L2_SUBDEV_FL_HAS_EVENTS; 1434 #endif 1435 1436 #if defined(CONFIG_MEDIA_CONTROLLER) 1437 ov2659->pad.flags = MEDIA_PAD_FL_SOURCE; 1438 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR; 1439 ret = media_entity_pads_init(&sd->entity, 1, &ov2659->pad); 1440 if (ret < 0) { 1441 v4l2_ctrl_handler_free(&ov2659->ctrls); 1442 return ret; 1443 } 1444 #endif 1445 1446 mutex_init(&ov2659->lock); 1447 1448 ov2659_get_default_format(&ov2659->format); 1449 ov2659->frame_size = &ov2659_framesizes[2]; 1450 ov2659->format_ctrl_regs = ov2659_formats[0].format_ctrl_regs; 1451 1452 ret = ov2659_detect(sd); 1453 if (ret < 0) 1454 goto error; 1455 1456 /* Calculate the PLL register value needed */ 1457 ov2659_pll_calc_params(ov2659); 1458 1459 ret = v4l2_async_register_subdev(&ov2659->sd); 1460 if (ret) 1461 goto error; 1462 1463 dev_info(&client->dev, "%s sensor driver registered !!\n", sd->name); 1464 1465 return 0; 1466 1467 error: 1468 v4l2_ctrl_handler_free(&ov2659->ctrls); 1469 media_entity_cleanup(&sd->entity); 1470 mutex_destroy(&ov2659->lock); 1471 return ret; 1472 } 1473 1474 static int ov2659_remove(struct i2c_client *client) 1475 { 1476 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1477 struct ov2659 *ov2659 = to_ov2659(sd); 1478 1479 v4l2_ctrl_handler_free(&ov2659->ctrls); 1480 v4l2_async_unregister_subdev(sd); 1481 media_entity_cleanup(&sd->entity); 1482 mutex_destroy(&ov2659->lock); 1483 1484 return 0; 1485 } 1486 1487 static const struct i2c_device_id ov2659_id[] = { 1488 { "ov2659", 0 }, 1489 { /* sentinel */ }, 1490 }; 1491 MODULE_DEVICE_TABLE(i2c, ov2659_id); 1492 1493 #if IS_ENABLED(CONFIG_OF) 1494 static const struct of_device_id ov2659_of_match[] = { 1495 { .compatible = "ovti,ov2659", }, 1496 { /* sentinel */ }, 1497 }; 1498 MODULE_DEVICE_TABLE(of, ov2659_of_match); 1499 #endif 1500 1501 static struct i2c_driver ov2659_i2c_driver = { 1502 .driver = { 1503 .name = DRIVER_NAME, 1504 .of_match_table = of_match_ptr(ov2659_of_match), 1505 }, 1506 .probe_new = ov2659_probe, 1507 .remove = ov2659_remove, 1508 .id_table = ov2659_id, 1509 }; 1510 1511 module_i2c_driver(ov2659_i2c_driver); 1512 1513 MODULE_AUTHOR("Benoit Parrot <bparrot@ti.com>"); 1514 MODULE_DESCRIPTION("OV2659 CMOS Image Sensor driver"); 1515 MODULE_LICENSE("GPL v2"); 1516