1 /* 2 * ov2640 Camera Driver 3 * 4 * Copyright (C) 2010 Alberto Panizzo <maramaopercheseimorto@gmail.com> 5 * 6 * Based on ov772x, ov9640 drivers and previous non merged implementations. 7 * 8 * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. 9 * Copyright (C) 2006, OmniVision 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #include <linux/init.h> 17 #include <linux/module.h> 18 #include <linux/i2c.h> 19 #include <linux/clk.h> 20 #include <linux/slab.h> 21 #include <linux/delay.h> 22 #include <linux/gpio.h> 23 #include <linux/gpio/consumer.h> 24 #include <linux/of_gpio.h> 25 #include <linux/v4l2-mediabus.h> 26 #include <linux/videodev2.h> 27 28 #include <media/v4l2-device.h> 29 #include <media/v4l2-subdev.h> 30 #include <media/v4l2-ctrls.h> 31 #include <media/v4l2-image-sizes.h> 32 33 #define VAL_SET(x, mask, rshift, lshift) \ 34 ((((x) >> rshift) & mask) << lshift) 35 /* 36 * DSP registers 37 * register offset for BANK_SEL == BANK_SEL_DSP 38 */ 39 #define R_BYPASS 0x05 /* Bypass DSP */ 40 #define R_BYPASS_DSP_BYPAS 0x01 /* Bypass DSP, sensor out directly */ 41 #define R_BYPASS_USE_DSP 0x00 /* Use the internal DSP */ 42 #define QS 0x44 /* Quantization Scale Factor */ 43 #define CTRLI 0x50 44 #define CTRLI_LP_DP 0x80 45 #define CTRLI_ROUND 0x40 46 #define CTRLI_V_DIV_SET(x) VAL_SET(x, 0x3, 0, 3) 47 #define CTRLI_H_DIV_SET(x) VAL_SET(x, 0x3, 0, 0) 48 #define HSIZE 0x51 /* H_SIZE[7:0] (real/4) */ 49 #define HSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0) 50 #define VSIZE 0x52 /* V_SIZE[7:0] (real/4) */ 51 #define VSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0) 52 #define XOFFL 0x53 /* OFFSET_X[7:0] */ 53 #define XOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0) 54 #define YOFFL 0x54 /* OFFSET_Y[7:0] */ 55 #define YOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0) 56 #define VHYX 0x55 /* Offset and size completion */ 57 #define VHYX_VSIZE_SET(x) VAL_SET(x, 0x1, (8+2), 7) 58 #define VHYX_HSIZE_SET(x) VAL_SET(x, 0x1, (8+2), 3) 59 #define VHYX_YOFF_SET(x) VAL_SET(x, 0x3, 8, 4) 60 #define VHYX_XOFF_SET(x) VAL_SET(x, 0x3, 8, 0) 61 #define DPRP 0x56 62 #define TEST 0x57 /* Horizontal size completion */ 63 #define TEST_HSIZE_SET(x) VAL_SET(x, 0x1, (9+2), 7) 64 #define ZMOW 0x5A /* Zoom: Out Width OUTW[7:0] (real/4) */ 65 #define ZMOW_OUTW_SET(x) VAL_SET(x, 0xFF, 2, 0) 66 #define ZMOH 0x5B /* Zoom: Out Height OUTH[7:0] (real/4) */ 67 #define ZMOH_OUTH_SET(x) VAL_SET(x, 0xFF, 2, 0) 68 #define ZMHH 0x5C /* Zoom: Speed and H&W completion */ 69 #define ZMHH_ZSPEED_SET(x) VAL_SET(x, 0x0F, 0, 4) 70 #define ZMHH_OUTH_SET(x) VAL_SET(x, 0x1, (8+2), 2) 71 #define ZMHH_OUTW_SET(x) VAL_SET(x, 0x3, (8+2), 0) 72 #define BPADDR 0x7C /* SDE Indirect Register Access: Address */ 73 #define BPDATA 0x7D /* SDE Indirect Register Access: Data */ 74 #define CTRL2 0x86 /* DSP Module enable 2 */ 75 #define CTRL2_DCW_EN 0x20 76 #define CTRL2_SDE_EN 0x10 77 #define CTRL2_UV_ADJ_EN 0x08 78 #define CTRL2_UV_AVG_EN 0x04 79 #define CTRL2_CMX_EN 0x01 80 #define CTRL3 0x87 /* DSP Module enable 3 */ 81 #define CTRL3_BPC_EN 0x80 82 #define CTRL3_WPC_EN 0x40 83 #define SIZEL 0x8C /* Image Size Completion */ 84 #define SIZEL_HSIZE8_11_SET(x) VAL_SET(x, 0x1, 11, 6) 85 #define SIZEL_HSIZE8_SET(x) VAL_SET(x, 0x7, 0, 3) 86 #define SIZEL_VSIZE8_SET(x) VAL_SET(x, 0x7, 0, 0) 87 #define HSIZE8 0xC0 /* Image Horizontal Size HSIZE[10:3] */ 88 #define HSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0) 89 #define VSIZE8 0xC1 /* Image Vertical Size VSIZE[10:3] */ 90 #define VSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0) 91 #define CTRL0 0xC2 /* DSP Module enable 0 */ 92 #define CTRL0_AEC_EN 0x80 93 #define CTRL0_AEC_SEL 0x40 94 #define CTRL0_STAT_SEL 0x20 95 #define CTRL0_VFIRST 0x10 96 #define CTRL0_YUV422 0x08 97 #define CTRL0_YUV_EN 0x04 98 #define CTRL0_RGB_EN 0x02 99 #define CTRL0_RAW_EN 0x01 100 #define CTRL1 0xC3 /* DSP Module enable 1 */ 101 #define CTRL1_CIP 0x80 102 #define CTRL1_DMY 0x40 103 #define CTRL1_RAW_GMA 0x20 104 #define CTRL1_DG 0x10 105 #define CTRL1_AWB 0x08 106 #define CTRL1_AWB_GAIN 0x04 107 #define CTRL1_LENC 0x02 108 #define CTRL1_PRE 0x01 109 /* REG 0xC7 (unknown name): affects Auto White Balance (AWB) 110 * AWB_OFF 0x40 111 * AWB_SIMPLE 0x10 112 * AWB_ON 0x00 (Advanced AWB ?) */ 113 #define R_DVP_SP 0xD3 /* DVP output speed control */ 114 #define R_DVP_SP_AUTO_MODE 0x80 115 #define R_DVP_SP_DVP_MASK 0x3F /* DVP PCLK = sysclk (48)/[6:0] (YUV0); 116 * = sysclk (48)/(2*[6:0]) (RAW);*/ 117 #define IMAGE_MODE 0xDA /* Image Output Format Select */ 118 #define IMAGE_MODE_Y8_DVP_EN 0x40 119 #define IMAGE_MODE_JPEG_EN 0x10 120 #define IMAGE_MODE_YUV422 0x00 121 #define IMAGE_MODE_RAW10 0x04 /* (DVP) */ 122 #define IMAGE_MODE_RGB565 0x08 123 #define IMAGE_MODE_HREF_VSYNC 0x02 /* HREF timing select in DVP JPEG output 124 * mode (0 for HREF is same as sensor) */ 125 #define IMAGE_MODE_LBYTE_FIRST 0x01 /* Byte swap enable for DVP 126 * 1: Low byte first UYVY (C2[4] =0) 127 * VYUY (C2[4] =1) 128 * 0: High byte first YUYV (C2[4]=0) 129 * YVYU (C2[4] = 1) */ 130 #define RESET 0xE0 /* Reset */ 131 #define RESET_MICROC 0x40 132 #define RESET_SCCB 0x20 133 #define RESET_JPEG 0x10 134 #define RESET_DVP 0x04 135 #define RESET_IPU 0x02 136 #define RESET_CIF 0x01 137 #define REGED 0xED /* Register ED */ 138 #define REGED_CLK_OUT_DIS 0x10 139 #define MS_SP 0xF0 /* SCCB Master Speed */ 140 #define SS_ID 0xF7 /* SCCB Slave ID */ 141 #define SS_CTRL 0xF8 /* SCCB Slave Control */ 142 #define SS_CTRL_ADD_AUTO_INC 0x20 143 #define SS_CTRL_EN 0x08 144 #define SS_CTRL_DELAY_CLK 0x04 145 #define SS_CTRL_ACC_EN 0x02 146 #define SS_CTRL_SEN_PASS_THR 0x01 147 #define MC_BIST 0xF9 /* Microcontroller misc register */ 148 #define MC_BIST_RESET 0x80 /* Microcontroller Reset */ 149 #define MC_BIST_BOOT_ROM_SEL 0x40 150 #define MC_BIST_12KB_SEL 0x20 151 #define MC_BIST_12KB_MASK 0x30 152 #define MC_BIST_512KB_SEL 0x08 153 #define MC_BIST_512KB_MASK 0x0C 154 #define MC_BIST_BUSY_BIT_R 0x02 155 #define MC_BIST_MC_RES_ONE_SH_W 0x02 156 #define MC_BIST_LAUNCH 0x01 157 #define BANK_SEL 0xFF /* Register Bank Select */ 158 #define BANK_SEL_DSP 0x00 159 #define BANK_SEL_SENS 0x01 160 161 /* 162 * Sensor registers 163 * register offset for BANK_SEL == BANK_SEL_SENS 164 */ 165 #define GAIN 0x00 /* AGC - Gain control gain setting */ 166 #define COM1 0x03 /* Common control 1 */ 167 #define COM1_1_DUMMY_FR 0x40 168 #define COM1_3_DUMMY_FR 0x80 169 #define COM1_7_DUMMY_FR 0xC0 170 #define COM1_VWIN_LSB_UXGA 0x0F 171 #define COM1_VWIN_LSB_SVGA 0x0A 172 #define COM1_VWIN_LSB_CIF 0x06 173 #define REG04 0x04 /* Register 04 */ 174 #define REG04_DEF 0x20 /* Always set */ 175 #define REG04_HFLIP_IMG 0x80 /* Horizontal mirror image ON/OFF */ 176 #define REG04_VFLIP_IMG 0x40 /* Vertical flip image ON/OFF */ 177 #define REG04_VREF_EN 0x10 178 #define REG04_HREF_EN 0x08 179 #define REG04_AEC_SET(x) VAL_SET(x, 0x3, 0, 0) 180 #define REG08 0x08 /* Frame Exposure One-pin Control Pre-charge Row Num */ 181 #define COM2 0x09 /* Common control 2 */ 182 #define COM2_SOFT_SLEEP_MODE 0x10 /* Soft sleep mode */ 183 /* Output drive capability */ 184 #define COM2_OCAP_Nx_SET(N) (((N) - 1) & 0x03) /* N = [1x .. 4x] */ 185 #define PID 0x0A /* Product ID Number MSB */ 186 #define VER 0x0B /* Product ID Number LSB */ 187 #define COM3 0x0C /* Common control 3 */ 188 #define COM3_BAND_50H 0x04 /* 0 For Banding at 60H */ 189 #define COM3_BAND_AUTO 0x02 /* Auto Banding */ 190 #define COM3_SING_FR_SNAPSH 0x01 /* 0 For enable live video output after the 191 * snapshot sequence*/ 192 #define AEC 0x10 /* AEC[9:2] Exposure Value */ 193 #define CLKRC 0x11 /* Internal clock */ 194 #define CLKRC_EN 0x80 195 #define CLKRC_DIV_SET(x) (((x) - 1) & 0x1F) /* CLK = XVCLK/(x) */ 196 #define COM7 0x12 /* Common control 7 */ 197 #define COM7_SRST 0x80 /* Initiates system reset. All registers are 198 * set to factory default values after which 199 * the chip resumes normal operation */ 200 #define COM7_RES_UXGA 0x00 /* Resolution selectors for UXGA */ 201 #define COM7_RES_SVGA 0x40 /* SVGA */ 202 #define COM7_RES_CIF 0x20 /* CIF */ 203 #define COM7_ZOOM_EN 0x04 /* Enable Zoom mode */ 204 #define COM7_COLOR_BAR_TEST 0x02 /* Enable Color Bar Test Pattern */ 205 #define COM8 0x13 /* Common control 8 */ 206 #define COM8_DEF 0xC0 207 #define COM8_BNDF_EN 0x20 /* Banding filter ON/OFF */ 208 #define COM8_AGC_EN 0x04 /* AGC Auto/Manual control selection */ 209 #define COM8_AEC_EN 0x01 /* Auto/Manual Exposure control */ 210 #define COM9 0x14 /* Common control 9 211 * Automatic gain ceiling - maximum AGC value [7:5]*/ 212 #define COM9_AGC_GAIN_2x 0x00 /* 000 : 2x */ 213 #define COM9_AGC_GAIN_4x 0x20 /* 001 : 4x */ 214 #define COM9_AGC_GAIN_8x 0x40 /* 010 : 8x */ 215 #define COM9_AGC_GAIN_16x 0x60 /* 011 : 16x */ 216 #define COM9_AGC_GAIN_32x 0x80 /* 100 : 32x */ 217 #define COM9_AGC_GAIN_64x 0xA0 /* 101 : 64x */ 218 #define COM9_AGC_GAIN_128x 0xC0 /* 110 : 128x */ 219 #define COM10 0x15 /* Common control 10 */ 220 #define COM10_PCLK_HREF 0x20 /* PCLK output qualified by HREF */ 221 #define COM10_PCLK_RISE 0x10 /* Data is updated at the rising edge of 222 * PCLK (user can latch data at the next 223 * falling edge of PCLK). 224 * 0 otherwise. */ 225 #define COM10_HREF_INV 0x08 /* Invert HREF polarity: 226 * HREF negative for valid data*/ 227 #define COM10_VSINC_INV 0x02 /* Invert VSYNC polarity */ 228 #define HSTART 0x17 /* Horizontal Window start MSB 8 bit */ 229 #define HEND 0x18 /* Horizontal Window end MSB 8 bit */ 230 #define VSTART 0x19 /* Vertical Window start MSB 8 bit */ 231 #define VEND 0x1A /* Vertical Window end MSB 8 bit */ 232 #define MIDH 0x1C /* Manufacturer ID byte - high */ 233 #define MIDL 0x1D /* Manufacturer ID byte - low */ 234 #define AEW 0x24 /* AGC/AEC - Stable operating region (upper limit) */ 235 #define AEB 0x25 /* AGC/AEC - Stable operating region (lower limit) */ 236 #define VV 0x26 /* AGC/AEC Fast mode operating region */ 237 #define VV_HIGH_TH_SET(x) VAL_SET(x, 0xF, 0, 4) 238 #define VV_LOW_TH_SET(x) VAL_SET(x, 0xF, 0, 0) 239 #define REG2A 0x2A /* Dummy pixel insert MSB */ 240 #define FRARL 0x2B /* Dummy pixel insert LSB */ 241 #define ADDVFL 0x2D /* LSB of insert dummy lines in Vertical direction */ 242 #define ADDVFH 0x2E /* MSB of insert dummy lines in Vertical direction */ 243 #define YAVG 0x2F /* Y/G Channel Average value */ 244 #define REG32 0x32 /* Common Control 32 */ 245 #define REG32_PCLK_DIV_2 0x80 /* PCLK freq divided by 2 */ 246 #define REG32_PCLK_DIV_4 0xC0 /* PCLK freq divided by 4 */ 247 #define ARCOM2 0x34 /* Zoom: Horizontal start point */ 248 #define REG45 0x45 /* Register 45 */ 249 #define FLL 0x46 /* Frame Length Adjustment LSBs */ 250 #define FLH 0x47 /* Frame Length Adjustment MSBs */ 251 #define COM19 0x48 /* Zoom: Vertical start point */ 252 #define ZOOMS 0x49 /* Zoom: Vertical start point */ 253 #define COM22 0x4B /* Flash light control */ 254 #define COM25 0x4E /* For Banding operations */ 255 #define COM25_50HZ_BANDING_AEC_MSBS_MASK 0xC0 /* 50Hz Bd. AEC 2 MSBs */ 256 #define COM25_60HZ_BANDING_AEC_MSBS_MASK 0x30 /* 60Hz Bd. AEC 2 MSBs */ 257 #define COM25_50HZ_BANDING_AEC_MSBS_SET(x) VAL_SET(x, 0x3, 8, 6) 258 #define COM25_60HZ_BANDING_AEC_MSBS_SET(x) VAL_SET(x, 0x3, 8, 4) 259 #define BD50 0x4F /* 50Hz Banding AEC 8 LSBs */ 260 #define BD50_50HZ_BANDING_AEC_LSBS_SET(x) VAL_SET(x, 0xFF, 0, 0) 261 #define BD60 0x50 /* 60Hz Banding AEC 8 LSBs */ 262 #define BD60_60HZ_BANDING_AEC_LSBS_SET(x) VAL_SET(x, 0xFF, 0, 0) 263 #define REG5A 0x5A /* 50/60Hz Banding Maximum AEC Step */ 264 #define BD50_MAX_AEC_STEP_MASK 0xF0 /* 50Hz Banding Max. AEC Step */ 265 #define BD60_MAX_AEC_STEP_MASK 0x0F /* 60Hz Banding Max. AEC Step */ 266 #define BD50_MAX_AEC_STEP_SET(x) VAL_SET((x - 1), 0x0F, 0, 4) 267 #define BD60_MAX_AEC_STEP_SET(x) VAL_SET((x - 1), 0x0F, 0, 0) 268 #define REG5D 0x5D /* AVGsel[7:0], 16-zone average weight option */ 269 #define REG5E 0x5E /* AVGsel[15:8], 16-zone average weight option */ 270 #define REG5F 0x5F /* AVGsel[23:16], 16-zone average weight option */ 271 #define REG60 0x60 /* AVGsel[31:24], 16-zone average weight option */ 272 #define HISTO_LOW 0x61 /* Histogram Algorithm Low Level */ 273 #define HISTO_HIGH 0x62 /* Histogram Algorithm High Level */ 274 275 /* 276 * ID 277 */ 278 #define MANUFACTURER_ID 0x7FA2 279 #define PID_OV2640 0x2642 280 #define VERSION(pid, ver) ((pid << 8) | (ver & 0xFF)) 281 282 /* 283 * Struct 284 */ 285 struct regval_list { 286 u8 reg_num; 287 u8 value; 288 }; 289 290 struct ov2640_win_size { 291 char *name; 292 u32 width; 293 u32 height; 294 const struct regval_list *regs; 295 }; 296 297 298 struct ov2640_priv { 299 struct v4l2_subdev subdev; 300 #if defined(CONFIG_MEDIA_CONTROLLER) 301 struct media_pad pad; 302 #endif 303 struct v4l2_ctrl_handler hdl; 304 u32 cfmt_code; 305 struct clk *clk; 306 const struct ov2640_win_size *win; 307 308 struct gpio_desc *resetb_gpio; 309 struct gpio_desc *pwdn_gpio; 310 311 struct mutex lock; /* lock to protect streaming and power_count */ 312 bool streaming; 313 int power_count; 314 }; 315 316 /* 317 * Registers settings 318 */ 319 320 #define ENDMARKER { 0xff, 0xff } 321 322 static const struct regval_list ov2640_init_regs[] = { 323 { BANK_SEL, BANK_SEL_DSP }, 324 { 0x2c, 0xff }, 325 { 0x2e, 0xdf }, 326 { BANK_SEL, BANK_SEL_SENS }, 327 { 0x3c, 0x32 }, 328 { CLKRC, CLKRC_DIV_SET(1) }, 329 { COM2, COM2_OCAP_Nx_SET(3) }, 330 { REG04, REG04_DEF | REG04_HREF_EN }, 331 { COM8, COM8_DEF | COM8_BNDF_EN | COM8_AGC_EN | COM8_AEC_EN }, 332 { COM9, COM9_AGC_GAIN_8x | 0x08}, 333 { 0x2c, 0x0c }, 334 { 0x33, 0x78 }, 335 { 0x3a, 0x33 }, 336 { 0x3b, 0xfb }, 337 { 0x3e, 0x00 }, 338 { 0x43, 0x11 }, 339 { 0x16, 0x10 }, 340 { 0x39, 0x02 }, 341 { 0x35, 0x88 }, 342 { 0x22, 0x0a }, 343 { 0x37, 0x40 }, 344 { 0x23, 0x00 }, 345 { ARCOM2, 0xa0 }, 346 { 0x06, 0x02 }, 347 { 0x06, 0x88 }, 348 { 0x07, 0xc0 }, 349 { 0x0d, 0xb7 }, 350 { 0x0e, 0x01 }, 351 { 0x4c, 0x00 }, 352 { 0x4a, 0x81 }, 353 { 0x21, 0x99 }, 354 { AEW, 0x40 }, 355 { AEB, 0x38 }, 356 { VV, VV_HIGH_TH_SET(0x08) | VV_LOW_TH_SET(0x02) }, 357 { 0x5c, 0x00 }, 358 { 0x63, 0x00 }, 359 { FLL, 0x22 }, 360 { COM3, 0x38 | COM3_BAND_AUTO }, 361 { REG5D, 0x55 }, 362 { REG5E, 0x7d }, 363 { REG5F, 0x7d }, 364 { REG60, 0x55 }, 365 { HISTO_LOW, 0x70 }, 366 { HISTO_HIGH, 0x80 }, 367 { 0x7c, 0x05 }, 368 { 0x20, 0x80 }, 369 { 0x28, 0x30 }, 370 { 0x6c, 0x00 }, 371 { 0x6d, 0x80 }, 372 { 0x6e, 0x00 }, 373 { 0x70, 0x02 }, 374 { 0x71, 0x94 }, 375 { 0x73, 0xc1 }, 376 { 0x3d, 0x34 }, 377 { COM7, COM7_RES_UXGA | COM7_ZOOM_EN }, 378 { REG5A, BD50_MAX_AEC_STEP_SET(6) 379 | BD60_MAX_AEC_STEP_SET(8) }, /* 0x57 */ 380 { COM25, COM25_50HZ_BANDING_AEC_MSBS_SET(0x0bb) 381 | COM25_60HZ_BANDING_AEC_MSBS_SET(0x09c) }, /* 0x00 */ 382 { BD50, BD50_50HZ_BANDING_AEC_LSBS_SET(0x0bb) }, /* 0xbb */ 383 { BD60, BD60_60HZ_BANDING_AEC_LSBS_SET(0x09c) }, /* 0x9c */ 384 { BANK_SEL, BANK_SEL_DSP }, 385 { 0xe5, 0x7f }, 386 { MC_BIST, MC_BIST_RESET | MC_BIST_BOOT_ROM_SEL }, 387 { 0x41, 0x24 }, 388 { RESET, RESET_JPEG | RESET_DVP }, 389 { 0x76, 0xff }, 390 { 0x33, 0xa0 }, 391 { 0x42, 0x20 }, 392 { 0x43, 0x18 }, 393 { 0x4c, 0x00 }, 394 { CTRL3, CTRL3_BPC_EN | CTRL3_WPC_EN | 0x10 }, 395 { 0x88, 0x3f }, 396 { 0xd7, 0x03 }, 397 { 0xd9, 0x10 }, 398 { R_DVP_SP, R_DVP_SP_AUTO_MODE | 0x2 }, 399 { 0xc8, 0x08 }, 400 { 0xc9, 0x80 }, 401 { BPADDR, 0x00 }, 402 { BPDATA, 0x00 }, 403 { BPADDR, 0x03 }, 404 { BPDATA, 0x48 }, 405 { BPDATA, 0x48 }, 406 { BPADDR, 0x08 }, 407 { BPDATA, 0x20 }, 408 { BPDATA, 0x10 }, 409 { BPDATA, 0x0e }, 410 { 0x90, 0x00 }, 411 { 0x91, 0x0e }, 412 { 0x91, 0x1a }, 413 { 0x91, 0x31 }, 414 { 0x91, 0x5a }, 415 { 0x91, 0x69 }, 416 { 0x91, 0x75 }, 417 { 0x91, 0x7e }, 418 { 0x91, 0x88 }, 419 { 0x91, 0x8f }, 420 { 0x91, 0x96 }, 421 { 0x91, 0xa3 }, 422 { 0x91, 0xaf }, 423 { 0x91, 0xc4 }, 424 { 0x91, 0xd7 }, 425 { 0x91, 0xe8 }, 426 { 0x91, 0x20 }, 427 { 0x92, 0x00 }, 428 { 0x93, 0x06 }, 429 { 0x93, 0xe3 }, 430 { 0x93, 0x03 }, 431 { 0x93, 0x03 }, 432 { 0x93, 0x00 }, 433 { 0x93, 0x02 }, 434 { 0x93, 0x00 }, 435 { 0x93, 0x00 }, 436 { 0x93, 0x00 }, 437 { 0x93, 0x00 }, 438 { 0x93, 0x00 }, 439 { 0x93, 0x00 }, 440 { 0x93, 0x00 }, 441 { 0x96, 0x00 }, 442 { 0x97, 0x08 }, 443 { 0x97, 0x19 }, 444 { 0x97, 0x02 }, 445 { 0x97, 0x0c }, 446 { 0x97, 0x24 }, 447 { 0x97, 0x30 }, 448 { 0x97, 0x28 }, 449 { 0x97, 0x26 }, 450 { 0x97, 0x02 }, 451 { 0x97, 0x98 }, 452 { 0x97, 0x80 }, 453 { 0x97, 0x00 }, 454 { 0x97, 0x00 }, 455 { 0xa4, 0x00 }, 456 { 0xa8, 0x00 }, 457 { 0xc5, 0x11 }, 458 { 0xc6, 0x51 }, 459 { 0xbf, 0x80 }, 460 { 0xc7, 0x10 }, /* simple AWB */ 461 { 0xb6, 0x66 }, 462 { 0xb8, 0xA5 }, 463 { 0xb7, 0x64 }, 464 { 0xb9, 0x7C }, 465 { 0xb3, 0xaf }, 466 { 0xb4, 0x97 }, 467 { 0xb5, 0xFF }, 468 { 0xb0, 0xC5 }, 469 { 0xb1, 0x94 }, 470 { 0xb2, 0x0f }, 471 { 0xc4, 0x5c }, 472 { 0xa6, 0x00 }, 473 { 0xa7, 0x20 }, 474 { 0xa7, 0xd8 }, 475 { 0xa7, 0x1b }, 476 { 0xa7, 0x31 }, 477 { 0xa7, 0x00 }, 478 { 0xa7, 0x18 }, 479 { 0xa7, 0x20 }, 480 { 0xa7, 0xd8 }, 481 { 0xa7, 0x19 }, 482 { 0xa7, 0x31 }, 483 { 0xa7, 0x00 }, 484 { 0xa7, 0x18 }, 485 { 0xa7, 0x20 }, 486 { 0xa7, 0xd8 }, 487 { 0xa7, 0x19 }, 488 { 0xa7, 0x31 }, 489 { 0xa7, 0x00 }, 490 { 0xa7, 0x18 }, 491 { 0x7f, 0x00 }, 492 { 0xe5, 0x1f }, 493 { 0xe1, 0x77 }, 494 { 0xdd, 0x7f }, 495 { CTRL0, CTRL0_YUV422 | CTRL0_YUV_EN | CTRL0_RGB_EN }, 496 ENDMARKER, 497 }; 498 499 /* 500 * Register settings for window size 501 * The preamble, setup the internal DSP to input an UXGA (1600x1200) image. 502 * Then the different zooming configurations will setup the output image size. 503 */ 504 static const struct regval_list ov2640_size_change_preamble_regs[] = { 505 { BANK_SEL, BANK_SEL_DSP }, 506 { RESET, RESET_DVP }, 507 { SIZEL, SIZEL_HSIZE8_11_SET(UXGA_WIDTH) | 508 SIZEL_HSIZE8_SET(UXGA_WIDTH) | 509 SIZEL_VSIZE8_SET(UXGA_HEIGHT) }, 510 { HSIZE8, HSIZE8_SET(UXGA_WIDTH) }, 511 { VSIZE8, VSIZE8_SET(UXGA_HEIGHT) }, 512 { CTRL2, CTRL2_DCW_EN | CTRL2_SDE_EN | 513 CTRL2_UV_AVG_EN | CTRL2_CMX_EN | CTRL2_UV_ADJ_EN }, 514 { HSIZE, HSIZE_SET(UXGA_WIDTH) }, 515 { VSIZE, VSIZE_SET(UXGA_HEIGHT) }, 516 { XOFFL, XOFFL_SET(0) }, 517 { YOFFL, YOFFL_SET(0) }, 518 { VHYX, VHYX_HSIZE_SET(UXGA_WIDTH) | VHYX_VSIZE_SET(UXGA_HEIGHT) | 519 VHYX_XOFF_SET(0) | VHYX_YOFF_SET(0)}, 520 { TEST, TEST_HSIZE_SET(UXGA_WIDTH) }, 521 ENDMARKER, 522 }; 523 524 #define PER_SIZE_REG_SEQ(x, y, v_div, h_div, pclk_div) \ 525 { CTRLI, CTRLI_LP_DP | CTRLI_V_DIV_SET(v_div) | \ 526 CTRLI_H_DIV_SET(h_div)}, \ 527 { ZMOW, ZMOW_OUTW_SET(x) }, \ 528 { ZMOH, ZMOH_OUTH_SET(y) }, \ 529 { ZMHH, ZMHH_OUTW_SET(x) | ZMHH_OUTH_SET(y) }, \ 530 { R_DVP_SP, pclk_div }, \ 531 { RESET, 0x00} 532 533 static const struct regval_list ov2640_qcif_regs[] = { 534 PER_SIZE_REG_SEQ(QCIF_WIDTH, QCIF_HEIGHT, 3, 3, 4), 535 ENDMARKER, 536 }; 537 538 static const struct regval_list ov2640_qvga_regs[] = { 539 PER_SIZE_REG_SEQ(QVGA_WIDTH, QVGA_HEIGHT, 2, 2, 4), 540 ENDMARKER, 541 }; 542 543 static const struct regval_list ov2640_cif_regs[] = { 544 PER_SIZE_REG_SEQ(CIF_WIDTH, CIF_HEIGHT, 2, 2, 8), 545 ENDMARKER, 546 }; 547 548 static const struct regval_list ov2640_vga_regs[] = { 549 PER_SIZE_REG_SEQ(VGA_WIDTH, VGA_HEIGHT, 0, 0, 2), 550 ENDMARKER, 551 }; 552 553 static const struct regval_list ov2640_svga_regs[] = { 554 PER_SIZE_REG_SEQ(SVGA_WIDTH, SVGA_HEIGHT, 1, 1, 2), 555 ENDMARKER, 556 }; 557 558 static const struct regval_list ov2640_xga_regs[] = { 559 PER_SIZE_REG_SEQ(XGA_WIDTH, XGA_HEIGHT, 0, 0, 2), 560 { CTRLI, 0x00}, 561 ENDMARKER, 562 }; 563 564 static const struct regval_list ov2640_sxga_regs[] = { 565 PER_SIZE_REG_SEQ(SXGA_WIDTH, SXGA_HEIGHT, 0, 0, 2), 566 { CTRLI, 0x00}, 567 { R_DVP_SP, 2 | R_DVP_SP_AUTO_MODE }, 568 ENDMARKER, 569 }; 570 571 static const struct regval_list ov2640_uxga_regs[] = { 572 PER_SIZE_REG_SEQ(UXGA_WIDTH, UXGA_HEIGHT, 0, 0, 0), 573 { CTRLI, 0x00}, 574 { R_DVP_SP, 0 | R_DVP_SP_AUTO_MODE }, 575 ENDMARKER, 576 }; 577 578 #define OV2640_SIZE(n, w, h, r) \ 579 {.name = n, .width = w , .height = h, .regs = r } 580 581 static const struct ov2640_win_size ov2640_supported_win_sizes[] = { 582 OV2640_SIZE("QCIF", QCIF_WIDTH, QCIF_HEIGHT, ov2640_qcif_regs), 583 OV2640_SIZE("QVGA", QVGA_WIDTH, QVGA_HEIGHT, ov2640_qvga_regs), 584 OV2640_SIZE("CIF", CIF_WIDTH, CIF_HEIGHT, ov2640_cif_regs), 585 OV2640_SIZE("VGA", VGA_WIDTH, VGA_HEIGHT, ov2640_vga_regs), 586 OV2640_SIZE("SVGA", SVGA_WIDTH, SVGA_HEIGHT, ov2640_svga_regs), 587 OV2640_SIZE("XGA", XGA_WIDTH, XGA_HEIGHT, ov2640_xga_regs), 588 OV2640_SIZE("SXGA", SXGA_WIDTH, SXGA_HEIGHT, ov2640_sxga_regs), 589 OV2640_SIZE("UXGA", UXGA_WIDTH, UXGA_HEIGHT, ov2640_uxga_regs), 590 }; 591 592 /* 593 * Register settings for pixel formats 594 */ 595 static const struct regval_list ov2640_format_change_preamble_regs[] = { 596 { BANK_SEL, BANK_SEL_DSP }, 597 { R_BYPASS, R_BYPASS_USE_DSP }, 598 ENDMARKER, 599 }; 600 601 static const struct regval_list ov2640_yuyv_regs[] = { 602 { IMAGE_MODE, IMAGE_MODE_YUV422 }, 603 { 0xd7, 0x03 }, 604 { 0x33, 0xa0 }, 605 { 0xe5, 0x1f }, 606 { 0xe1, 0x67 }, 607 { RESET, 0x00 }, 608 { R_BYPASS, R_BYPASS_USE_DSP }, 609 ENDMARKER, 610 }; 611 612 static const struct regval_list ov2640_uyvy_regs[] = { 613 { IMAGE_MODE, IMAGE_MODE_LBYTE_FIRST | IMAGE_MODE_YUV422 }, 614 { 0xd7, 0x01 }, 615 { 0x33, 0xa0 }, 616 { 0xe1, 0x67 }, 617 { RESET, 0x00 }, 618 { R_BYPASS, R_BYPASS_USE_DSP }, 619 ENDMARKER, 620 }; 621 622 static const struct regval_list ov2640_rgb565_be_regs[] = { 623 { IMAGE_MODE, IMAGE_MODE_RGB565 }, 624 { 0xd7, 0x03 }, 625 { RESET, 0x00 }, 626 { R_BYPASS, R_BYPASS_USE_DSP }, 627 ENDMARKER, 628 }; 629 630 static const struct regval_list ov2640_rgb565_le_regs[] = { 631 { IMAGE_MODE, IMAGE_MODE_LBYTE_FIRST | IMAGE_MODE_RGB565 }, 632 { 0xd7, 0x03 }, 633 { RESET, 0x00 }, 634 { R_BYPASS, R_BYPASS_USE_DSP }, 635 ENDMARKER, 636 }; 637 638 static u32 ov2640_codes[] = { 639 MEDIA_BUS_FMT_YUYV8_2X8, 640 MEDIA_BUS_FMT_UYVY8_2X8, 641 MEDIA_BUS_FMT_YVYU8_2X8, 642 MEDIA_BUS_FMT_VYUY8_2X8, 643 MEDIA_BUS_FMT_RGB565_2X8_BE, 644 MEDIA_BUS_FMT_RGB565_2X8_LE, 645 }; 646 647 /* 648 * General functions 649 */ 650 static struct ov2640_priv *to_ov2640(const struct i2c_client *client) 651 { 652 return container_of(i2c_get_clientdata(client), struct ov2640_priv, 653 subdev); 654 } 655 656 static int ov2640_write_array(struct i2c_client *client, 657 const struct regval_list *vals) 658 { 659 int ret; 660 661 while ((vals->reg_num != 0xff) || (vals->value != 0xff)) { 662 ret = i2c_smbus_write_byte_data(client, 663 vals->reg_num, vals->value); 664 dev_vdbg(&client->dev, "array: 0x%02x, 0x%02x", 665 vals->reg_num, vals->value); 666 667 if (ret < 0) 668 return ret; 669 vals++; 670 } 671 return 0; 672 } 673 674 static int ov2640_mask_set(struct i2c_client *client, 675 u8 reg, u8 mask, u8 set) 676 { 677 s32 val = i2c_smbus_read_byte_data(client, reg); 678 if (val < 0) 679 return val; 680 681 val &= ~mask; 682 val |= set & mask; 683 684 dev_vdbg(&client->dev, "masks: 0x%02x, 0x%02x", reg, val); 685 686 return i2c_smbus_write_byte_data(client, reg, val); 687 } 688 689 static int ov2640_reset(struct i2c_client *client) 690 { 691 int ret; 692 static const struct regval_list reset_seq[] = { 693 {BANK_SEL, BANK_SEL_SENS}, 694 {COM7, COM7_SRST}, 695 ENDMARKER, 696 }; 697 698 ret = ov2640_write_array(client, reset_seq); 699 if (ret) 700 goto err; 701 702 msleep(5); 703 err: 704 dev_dbg(&client->dev, "%s: (ret %d)", __func__, ret); 705 return ret; 706 } 707 708 /* 709 * functions 710 */ 711 static int ov2640_s_ctrl(struct v4l2_ctrl *ctrl) 712 { 713 struct v4l2_subdev *sd = 714 &container_of(ctrl->handler, struct ov2640_priv, hdl)->subdev; 715 struct i2c_client *client = v4l2_get_subdevdata(sd); 716 struct ov2640_priv *priv = to_ov2640(client); 717 u8 val; 718 int ret; 719 720 /* v4l2_ctrl_lock() locks our own mutex */ 721 722 /* 723 * If the device is not powered up by the host driver, do not apply any 724 * controls to H/W at this time. Instead the controls will be restored 725 * when the streaming is started. 726 */ 727 if (!priv->power_count) 728 return 0; 729 730 ret = i2c_smbus_write_byte_data(client, BANK_SEL, BANK_SEL_SENS); 731 if (ret < 0) 732 return ret; 733 734 switch (ctrl->id) { 735 case V4L2_CID_VFLIP: 736 val = ctrl->val ? REG04_VFLIP_IMG | REG04_VREF_EN : 0x00; 737 return ov2640_mask_set(client, REG04, 738 REG04_VFLIP_IMG | REG04_VREF_EN, val); 739 /* NOTE: REG04_VREF_EN: 1 line shift / even/odd line swap */ 740 case V4L2_CID_HFLIP: 741 val = ctrl->val ? REG04_HFLIP_IMG : 0x00; 742 return ov2640_mask_set(client, REG04, REG04_HFLIP_IMG, val); 743 } 744 745 return -EINVAL; 746 } 747 748 #ifdef CONFIG_VIDEO_ADV_DEBUG 749 static int ov2640_g_register(struct v4l2_subdev *sd, 750 struct v4l2_dbg_register *reg) 751 { 752 struct i2c_client *client = v4l2_get_subdevdata(sd); 753 int ret; 754 755 reg->size = 1; 756 if (reg->reg > 0xff) 757 return -EINVAL; 758 759 ret = i2c_smbus_read_byte_data(client, reg->reg); 760 if (ret < 0) 761 return ret; 762 763 reg->val = ret; 764 765 return 0; 766 } 767 768 static int ov2640_s_register(struct v4l2_subdev *sd, 769 const struct v4l2_dbg_register *reg) 770 { 771 struct i2c_client *client = v4l2_get_subdevdata(sd); 772 773 if (reg->reg > 0xff || 774 reg->val > 0xff) 775 return -EINVAL; 776 777 return i2c_smbus_write_byte_data(client, reg->reg, reg->val); 778 } 779 #endif 780 781 static void ov2640_set_power(struct ov2640_priv *priv, int on) 782 { 783 #ifdef CONFIG_GPIOLIB 784 if (priv->pwdn_gpio) 785 gpiod_direction_output(priv->pwdn_gpio, !on); 786 if (on && priv->resetb_gpio) { 787 /* Active the resetb pin to perform a reset pulse */ 788 gpiod_direction_output(priv->resetb_gpio, 1); 789 usleep_range(3000, 5000); 790 gpiod_set_value(priv->resetb_gpio, 0); 791 } 792 #endif 793 } 794 795 static int ov2640_s_power(struct v4l2_subdev *sd, int on) 796 { 797 struct i2c_client *client = v4l2_get_subdevdata(sd); 798 struct ov2640_priv *priv = to_ov2640(client); 799 800 mutex_lock(&priv->lock); 801 802 /* 803 * If the power count is modified from 0 to != 0 or from != 0 to 0, 804 * update the power state. 805 */ 806 if (priv->power_count == !on) 807 ov2640_set_power(priv, on); 808 priv->power_count += on ? 1 : -1; 809 WARN_ON(priv->power_count < 0); 810 mutex_unlock(&priv->lock); 811 812 return 0; 813 } 814 815 /* Select the nearest higher resolution for capture */ 816 static const struct ov2640_win_size *ov2640_select_win(u32 width, u32 height) 817 { 818 int i, default_size = ARRAY_SIZE(ov2640_supported_win_sizes) - 1; 819 820 for (i = 0; i < ARRAY_SIZE(ov2640_supported_win_sizes); i++) { 821 if (ov2640_supported_win_sizes[i].width >= width && 822 ov2640_supported_win_sizes[i].height >= height) 823 return &ov2640_supported_win_sizes[i]; 824 } 825 826 return &ov2640_supported_win_sizes[default_size]; 827 } 828 829 static int ov2640_set_params(struct i2c_client *client, 830 const struct ov2640_win_size *win, u32 code) 831 { 832 const struct regval_list *selected_cfmt_regs; 833 u8 val; 834 int ret; 835 836 if (!win) 837 return -EINVAL; 838 839 switch (code) { 840 case MEDIA_BUS_FMT_RGB565_2X8_BE: 841 dev_dbg(&client->dev, "%s: Selected cfmt RGB565 BE", __func__); 842 selected_cfmt_regs = ov2640_rgb565_be_regs; 843 break; 844 case MEDIA_BUS_FMT_RGB565_2X8_LE: 845 dev_dbg(&client->dev, "%s: Selected cfmt RGB565 LE", __func__); 846 selected_cfmt_regs = ov2640_rgb565_le_regs; 847 break; 848 case MEDIA_BUS_FMT_YUYV8_2X8: 849 dev_dbg(&client->dev, "%s: Selected cfmt YUYV (YUV422)", __func__); 850 selected_cfmt_regs = ov2640_yuyv_regs; 851 break; 852 case MEDIA_BUS_FMT_UYVY8_2X8: 853 default: 854 dev_dbg(&client->dev, "%s: Selected cfmt UYVY", __func__); 855 selected_cfmt_regs = ov2640_uyvy_regs; 856 break; 857 case MEDIA_BUS_FMT_YVYU8_2X8: 858 dev_dbg(&client->dev, "%s: Selected cfmt YVYU", __func__); 859 selected_cfmt_regs = ov2640_yuyv_regs; 860 break; 861 case MEDIA_BUS_FMT_VYUY8_2X8: 862 dev_dbg(&client->dev, "%s: Selected cfmt VYUY", __func__); 863 selected_cfmt_regs = ov2640_uyvy_regs; 864 break; 865 } 866 867 /* reset hardware */ 868 ov2640_reset(client); 869 870 /* initialize the sensor with default data */ 871 dev_dbg(&client->dev, "%s: Init default", __func__); 872 ret = ov2640_write_array(client, ov2640_init_regs); 873 if (ret < 0) 874 goto err; 875 876 /* select preamble */ 877 dev_dbg(&client->dev, "%s: Set size to %s", __func__, win->name); 878 ret = ov2640_write_array(client, ov2640_size_change_preamble_regs); 879 if (ret < 0) 880 goto err; 881 882 /* set size win */ 883 ret = ov2640_write_array(client, win->regs); 884 if (ret < 0) 885 goto err; 886 887 /* cfmt preamble */ 888 dev_dbg(&client->dev, "%s: Set cfmt", __func__); 889 ret = ov2640_write_array(client, ov2640_format_change_preamble_regs); 890 if (ret < 0) 891 goto err; 892 893 /* set cfmt */ 894 ret = ov2640_write_array(client, selected_cfmt_regs); 895 if (ret < 0) 896 goto err; 897 val = (code == MEDIA_BUS_FMT_YVYU8_2X8) 898 || (code == MEDIA_BUS_FMT_VYUY8_2X8) ? CTRL0_VFIRST : 0x00; 899 ret = ov2640_mask_set(client, CTRL0, CTRL0_VFIRST, val); 900 if (ret < 0) 901 goto err; 902 903 return 0; 904 905 err: 906 dev_err(&client->dev, "%s: Error %d", __func__, ret); 907 ov2640_reset(client); 908 909 return ret; 910 } 911 912 static int ov2640_get_fmt(struct v4l2_subdev *sd, 913 struct v4l2_subdev_pad_config *cfg, 914 struct v4l2_subdev_format *format) 915 { 916 struct v4l2_mbus_framefmt *mf = &format->format; 917 struct i2c_client *client = v4l2_get_subdevdata(sd); 918 struct ov2640_priv *priv = to_ov2640(client); 919 920 if (format->pad) 921 return -EINVAL; 922 923 if (!priv->win) { 924 priv->win = ov2640_select_win(SVGA_WIDTH, SVGA_HEIGHT); 925 priv->cfmt_code = MEDIA_BUS_FMT_UYVY8_2X8; 926 } 927 928 mf->width = priv->win->width; 929 mf->height = priv->win->height; 930 mf->code = priv->cfmt_code; 931 mf->colorspace = V4L2_COLORSPACE_SRGB; 932 mf->field = V4L2_FIELD_NONE; 933 934 return 0; 935 } 936 937 static int ov2640_set_fmt(struct v4l2_subdev *sd, 938 struct v4l2_subdev_pad_config *cfg, 939 struct v4l2_subdev_format *format) 940 { 941 struct v4l2_mbus_framefmt *mf = &format->format; 942 struct i2c_client *client = v4l2_get_subdevdata(sd); 943 struct ov2640_priv *priv = to_ov2640(client); 944 const struct ov2640_win_size *win; 945 int ret = 0; 946 947 if (format->pad) 948 return -EINVAL; 949 950 mutex_lock(&priv->lock); 951 952 /* select suitable win */ 953 win = ov2640_select_win(mf->width, mf->height); 954 mf->width = win->width; 955 mf->height = win->height; 956 957 mf->field = V4L2_FIELD_NONE; 958 mf->colorspace = V4L2_COLORSPACE_SRGB; 959 960 switch (mf->code) { 961 case MEDIA_BUS_FMT_RGB565_2X8_BE: 962 case MEDIA_BUS_FMT_RGB565_2X8_LE: 963 case MEDIA_BUS_FMT_YUYV8_2X8: 964 case MEDIA_BUS_FMT_UYVY8_2X8: 965 case MEDIA_BUS_FMT_YVYU8_2X8: 966 case MEDIA_BUS_FMT_VYUY8_2X8: 967 break; 968 default: 969 mf->code = MEDIA_BUS_FMT_UYVY8_2X8; 970 break; 971 } 972 973 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 974 struct ov2640_priv *priv = to_ov2640(client); 975 976 if (priv->streaming) { 977 ret = -EBUSY; 978 goto out; 979 } 980 /* select win */ 981 priv->win = win; 982 /* select format */ 983 priv->cfmt_code = mf->code; 984 } else { 985 cfg->try_fmt = *mf; 986 } 987 out: 988 mutex_unlock(&priv->lock); 989 990 return ret; 991 } 992 993 static int ov2640_enum_mbus_code(struct v4l2_subdev *sd, 994 struct v4l2_subdev_pad_config *cfg, 995 struct v4l2_subdev_mbus_code_enum *code) 996 { 997 if (code->pad || code->index >= ARRAY_SIZE(ov2640_codes)) 998 return -EINVAL; 999 1000 code->code = ov2640_codes[code->index]; 1001 return 0; 1002 } 1003 1004 static int ov2640_get_selection(struct v4l2_subdev *sd, 1005 struct v4l2_subdev_pad_config *cfg, 1006 struct v4l2_subdev_selection *sel) 1007 { 1008 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE) 1009 return -EINVAL; 1010 1011 switch (sel->target) { 1012 case V4L2_SEL_TGT_CROP_BOUNDS: 1013 case V4L2_SEL_TGT_CROP_DEFAULT: 1014 case V4L2_SEL_TGT_CROP: 1015 sel->r.left = 0; 1016 sel->r.top = 0; 1017 sel->r.width = UXGA_WIDTH; 1018 sel->r.height = UXGA_HEIGHT; 1019 return 0; 1020 default: 1021 return -EINVAL; 1022 } 1023 } 1024 1025 static int ov2640_s_stream(struct v4l2_subdev *sd, int on) 1026 { 1027 struct i2c_client *client = v4l2_get_subdevdata(sd); 1028 struct ov2640_priv *priv = to_ov2640(client); 1029 int ret = 0; 1030 1031 mutex_lock(&priv->lock); 1032 if (priv->streaming == !on) { 1033 if (on) { 1034 ret = ov2640_set_params(client, priv->win, 1035 priv->cfmt_code); 1036 if (!ret) 1037 ret = __v4l2_ctrl_handler_setup(&priv->hdl); 1038 } 1039 } 1040 if (!ret) 1041 priv->streaming = on; 1042 mutex_unlock(&priv->lock); 1043 1044 return ret; 1045 } 1046 1047 static int ov2640_video_probe(struct i2c_client *client) 1048 { 1049 struct ov2640_priv *priv = to_ov2640(client); 1050 u8 pid, ver, midh, midl; 1051 const char *devname; 1052 int ret; 1053 1054 ret = ov2640_s_power(&priv->subdev, 1); 1055 if (ret < 0) 1056 return ret; 1057 1058 /* 1059 * check and show product ID and manufacturer ID 1060 */ 1061 i2c_smbus_write_byte_data(client, BANK_SEL, BANK_SEL_SENS); 1062 pid = i2c_smbus_read_byte_data(client, PID); 1063 ver = i2c_smbus_read_byte_data(client, VER); 1064 midh = i2c_smbus_read_byte_data(client, MIDH); 1065 midl = i2c_smbus_read_byte_data(client, MIDL); 1066 1067 switch (VERSION(pid, ver)) { 1068 case PID_OV2640: 1069 devname = "ov2640"; 1070 break; 1071 default: 1072 dev_err(&client->dev, 1073 "Product ID error %x:%x\n", pid, ver); 1074 ret = -ENODEV; 1075 goto done; 1076 } 1077 1078 dev_info(&client->dev, 1079 "%s Product ID %0x:%0x Manufacturer ID %x:%x\n", 1080 devname, pid, ver, midh, midl); 1081 1082 done: 1083 ov2640_s_power(&priv->subdev, 0); 1084 return ret; 1085 } 1086 1087 static const struct v4l2_ctrl_ops ov2640_ctrl_ops = { 1088 .s_ctrl = ov2640_s_ctrl, 1089 }; 1090 1091 static const struct v4l2_subdev_core_ops ov2640_subdev_core_ops = { 1092 #ifdef CONFIG_VIDEO_ADV_DEBUG 1093 .g_register = ov2640_g_register, 1094 .s_register = ov2640_s_register, 1095 #endif 1096 .s_power = ov2640_s_power, 1097 }; 1098 1099 static const struct v4l2_subdev_pad_ops ov2640_subdev_pad_ops = { 1100 .enum_mbus_code = ov2640_enum_mbus_code, 1101 .get_selection = ov2640_get_selection, 1102 .get_fmt = ov2640_get_fmt, 1103 .set_fmt = ov2640_set_fmt, 1104 }; 1105 1106 static const struct v4l2_subdev_video_ops ov2640_subdev_video_ops = { 1107 .s_stream = ov2640_s_stream, 1108 }; 1109 1110 static const struct v4l2_subdev_ops ov2640_subdev_ops = { 1111 .core = &ov2640_subdev_core_ops, 1112 .pad = &ov2640_subdev_pad_ops, 1113 .video = &ov2640_subdev_video_ops, 1114 }; 1115 1116 static int ov2640_probe_dt(struct i2c_client *client, 1117 struct ov2640_priv *priv) 1118 { 1119 int ret; 1120 1121 /* Request the reset GPIO deasserted */ 1122 priv->resetb_gpio = devm_gpiod_get_optional(&client->dev, "resetb", 1123 GPIOD_OUT_LOW); 1124 1125 if (!priv->resetb_gpio) 1126 dev_dbg(&client->dev, "resetb gpio is not assigned!\n"); 1127 1128 ret = PTR_ERR_OR_ZERO(priv->resetb_gpio); 1129 if (ret && ret != -ENOSYS) { 1130 dev_dbg(&client->dev, 1131 "Error %d while getting resetb gpio\n", ret); 1132 return ret; 1133 } 1134 1135 /* Request the power down GPIO asserted */ 1136 priv->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "pwdn", 1137 GPIOD_OUT_HIGH); 1138 1139 if (!priv->pwdn_gpio) 1140 dev_dbg(&client->dev, "pwdn gpio is not assigned!\n"); 1141 1142 ret = PTR_ERR_OR_ZERO(priv->pwdn_gpio); 1143 if (ret && ret != -ENOSYS) { 1144 dev_dbg(&client->dev, 1145 "Error %d while getting pwdn gpio\n", ret); 1146 return ret; 1147 } 1148 1149 return 0; 1150 } 1151 1152 /* 1153 * i2c_driver functions 1154 */ 1155 static int ov2640_probe(struct i2c_client *client, 1156 const struct i2c_device_id *did) 1157 { 1158 struct ov2640_priv *priv; 1159 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); 1160 int ret; 1161 1162 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) { 1163 dev_err(&adapter->dev, 1164 "OV2640: I2C-Adapter doesn't support SMBUS\n"); 1165 return -EIO; 1166 } 1167 1168 priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL); 1169 if (!priv) 1170 return -ENOMEM; 1171 1172 if (client->dev.of_node) { 1173 priv->clk = devm_clk_get(&client->dev, "xvclk"); 1174 if (IS_ERR(priv->clk)) 1175 return PTR_ERR(priv->clk); 1176 ret = clk_prepare_enable(priv->clk); 1177 if (ret) 1178 return ret; 1179 } 1180 1181 ret = ov2640_probe_dt(client, priv); 1182 if (ret) 1183 goto err_clk; 1184 1185 v4l2_i2c_subdev_init(&priv->subdev, client, &ov2640_subdev_ops); 1186 priv->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1187 mutex_init(&priv->lock); 1188 v4l2_ctrl_handler_init(&priv->hdl, 2); 1189 priv->hdl.lock = &priv->lock; 1190 v4l2_ctrl_new_std(&priv->hdl, &ov2640_ctrl_ops, 1191 V4L2_CID_VFLIP, 0, 1, 1, 0); 1192 v4l2_ctrl_new_std(&priv->hdl, &ov2640_ctrl_ops, 1193 V4L2_CID_HFLIP, 0, 1, 1, 0); 1194 priv->subdev.ctrl_handler = &priv->hdl; 1195 if (priv->hdl.error) { 1196 ret = priv->hdl.error; 1197 goto err_hdl; 1198 } 1199 #if defined(CONFIG_MEDIA_CONTROLLER) 1200 priv->pad.flags = MEDIA_PAD_FL_SOURCE; 1201 priv->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1202 ret = media_entity_pads_init(&priv->subdev.entity, 1, &priv->pad); 1203 if (ret < 0) 1204 goto err_hdl; 1205 #endif 1206 1207 ret = ov2640_video_probe(client); 1208 if (ret < 0) 1209 goto err_videoprobe; 1210 1211 ret = v4l2_async_register_subdev(&priv->subdev); 1212 if (ret < 0) 1213 goto err_videoprobe; 1214 1215 dev_info(&adapter->dev, "OV2640 Probed\n"); 1216 1217 return 0; 1218 1219 err_videoprobe: 1220 media_entity_cleanup(&priv->subdev.entity); 1221 err_hdl: 1222 v4l2_ctrl_handler_free(&priv->hdl); 1223 mutex_destroy(&priv->lock); 1224 err_clk: 1225 clk_disable_unprepare(priv->clk); 1226 return ret; 1227 } 1228 1229 static int ov2640_remove(struct i2c_client *client) 1230 { 1231 struct ov2640_priv *priv = to_ov2640(client); 1232 1233 v4l2_async_unregister_subdev(&priv->subdev); 1234 v4l2_ctrl_handler_free(&priv->hdl); 1235 mutex_destroy(&priv->lock); 1236 media_entity_cleanup(&priv->subdev.entity); 1237 v4l2_device_unregister_subdev(&priv->subdev); 1238 clk_disable_unprepare(priv->clk); 1239 return 0; 1240 } 1241 1242 static const struct i2c_device_id ov2640_id[] = { 1243 { "ov2640", 0 }, 1244 { } 1245 }; 1246 MODULE_DEVICE_TABLE(i2c, ov2640_id); 1247 1248 static const struct of_device_id ov2640_of_match[] = { 1249 {.compatible = "ovti,ov2640", }, 1250 {}, 1251 }; 1252 MODULE_DEVICE_TABLE(of, ov2640_of_match); 1253 1254 static struct i2c_driver ov2640_i2c_driver = { 1255 .driver = { 1256 .name = "ov2640", 1257 .of_match_table = of_match_ptr(ov2640_of_match), 1258 }, 1259 .probe = ov2640_probe, 1260 .remove = ov2640_remove, 1261 .id_table = ov2640_id, 1262 }; 1263 1264 module_i2c_driver(ov2640_i2c_driver); 1265 1266 MODULE_DESCRIPTION("Driver for Omni Vision 2640 sensor"); 1267 MODULE_AUTHOR("Alberto Panizzo"); 1268 MODULE_LICENSE("GPL v2"); 1269