1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ov2640 Camera Driver 4 * 5 * Copyright (C) 2010 Alberto Panizzo <maramaopercheseimorto@gmail.com> 6 * 7 * Based on ov772x, ov9640 drivers and previous non merged implementations. 8 * 9 * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. 10 * Copyright (C) 2006, OmniVision 11 */ 12 13 #include <linux/init.h> 14 #include <linux/module.h> 15 #include <linux/i2c.h> 16 #include <linux/clk.h> 17 #include <linux/slab.h> 18 #include <linux/delay.h> 19 #include <linux/gpio/consumer.h> 20 #include <linux/v4l2-mediabus.h> 21 #include <linux/videodev2.h> 22 23 #include <media/v4l2-device.h> 24 #include <media/v4l2-event.h> 25 #include <media/v4l2-subdev.h> 26 #include <media/v4l2-ctrls.h> 27 #include <media/v4l2-image-sizes.h> 28 29 #define VAL_SET(x, mask, rshift, lshift) \ 30 ((((x) >> rshift) & mask) << lshift) 31 /* 32 * DSP registers 33 * register offset for BANK_SEL == BANK_SEL_DSP 34 */ 35 #define R_BYPASS 0x05 /* Bypass DSP */ 36 #define R_BYPASS_DSP_BYPAS 0x01 /* Bypass DSP, sensor out directly */ 37 #define R_BYPASS_USE_DSP 0x00 /* Use the internal DSP */ 38 #define QS 0x44 /* Quantization Scale Factor */ 39 #define CTRLI 0x50 40 #define CTRLI_LP_DP 0x80 41 #define CTRLI_ROUND 0x40 42 #define CTRLI_V_DIV_SET(x) VAL_SET(x, 0x3, 0, 3) 43 #define CTRLI_H_DIV_SET(x) VAL_SET(x, 0x3, 0, 0) 44 #define HSIZE 0x51 /* H_SIZE[7:0] (real/4) */ 45 #define HSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0) 46 #define VSIZE 0x52 /* V_SIZE[7:0] (real/4) */ 47 #define VSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0) 48 #define XOFFL 0x53 /* OFFSET_X[7:0] */ 49 #define XOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0) 50 #define YOFFL 0x54 /* OFFSET_Y[7:0] */ 51 #define YOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0) 52 #define VHYX 0x55 /* Offset and size completion */ 53 #define VHYX_VSIZE_SET(x) VAL_SET(x, 0x1, (8+2), 7) 54 #define VHYX_HSIZE_SET(x) VAL_SET(x, 0x1, (8+2), 3) 55 #define VHYX_YOFF_SET(x) VAL_SET(x, 0x3, 8, 4) 56 #define VHYX_XOFF_SET(x) VAL_SET(x, 0x3, 8, 0) 57 #define DPRP 0x56 58 #define TEST 0x57 /* Horizontal size completion */ 59 #define TEST_HSIZE_SET(x) VAL_SET(x, 0x1, (9+2), 7) 60 #define ZMOW 0x5A /* Zoom: Out Width OUTW[7:0] (real/4) */ 61 #define ZMOW_OUTW_SET(x) VAL_SET(x, 0xFF, 2, 0) 62 #define ZMOH 0x5B /* Zoom: Out Height OUTH[7:0] (real/4) */ 63 #define ZMOH_OUTH_SET(x) VAL_SET(x, 0xFF, 2, 0) 64 #define ZMHH 0x5C /* Zoom: Speed and H&W completion */ 65 #define ZMHH_ZSPEED_SET(x) VAL_SET(x, 0x0F, 0, 4) 66 #define ZMHH_OUTH_SET(x) VAL_SET(x, 0x1, (8+2), 2) 67 #define ZMHH_OUTW_SET(x) VAL_SET(x, 0x3, (8+2), 0) 68 #define BPADDR 0x7C /* SDE Indirect Register Access: Address */ 69 #define BPDATA 0x7D /* SDE Indirect Register Access: Data */ 70 #define CTRL2 0x86 /* DSP Module enable 2 */ 71 #define CTRL2_DCW_EN 0x20 72 #define CTRL2_SDE_EN 0x10 73 #define CTRL2_UV_ADJ_EN 0x08 74 #define CTRL2_UV_AVG_EN 0x04 75 #define CTRL2_CMX_EN 0x01 76 #define CTRL3 0x87 /* DSP Module enable 3 */ 77 #define CTRL3_BPC_EN 0x80 78 #define CTRL3_WPC_EN 0x40 79 #define SIZEL 0x8C /* Image Size Completion */ 80 #define SIZEL_HSIZE8_11_SET(x) VAL_SET(x, 0x1, 11, 6) 81 #define SIZEL_HSIZE8_SET(x) VAL_SET(x, 0x7, 0, 3) 82 #define SIZEL_VSIZE8_SET(x) VAL_SET(x, 0x7, 0, 0) 83 #define HSIZE8 0xC0 /* Image Horizontal Size HSIZE[10:3] */ 84 #define HSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0) 85 #define VSIZE8 0xC1 /* Image Vertical Size VSIZE[10:3] */ 86 #define VSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0) 87 #define CTRL0 0xC2 /* DSP Module enable 0 */ 88 #define CTRL0_AEC_EN 0x80 89 #define CTRL0_AEC_SEL 0x40 90 #define CTRL0_STAT_SEL 0x20 91 #define CTRL0_VFIRST 0x10 92 #define CTRL0_YUV422 0x08 93 #define CTRL0_YUV_EN 0x04 94 #define CTRL0_RGB_EN 0x02 95 #define CTRL0_RAW_EN 0x01 96 #define CTRL1 0xC3 /* DSP Module enable 1 */ 97 #define CTRL1_CIP 0x80 98 #define CTRL1_DMY 0x40 99 #define CTRL1_RAW_GMA 0x20 100 #define CTRL1_DG 0x10 101 #define CTRL1_AWB 0x08 102 #define CTRL1_AWB_GAIN 0x04 103 #define CTRL1_LENC 0x02 104 #define CTRL1_PRE 0x01 105 /* REG 0xC7 (unknown name): affects Auto White Balance (AWB) 106 * AWB_OFF 0x40 107 * AWB_SIMPLE 0x10 108 * AWB_ON 0x00 (Advanced AWB ?) */ 109 #define R_DVP_SP 0xD3 /* DVP output speed control */ 110 #define R_DVP_SP_AUTO_MODE 0x80 111 #define R_DVP_SP_DVP_MASK 0x3F /* DVP PCLK = sysclk (48)/[6:0] (YUV0); 112 * = sysclk (48)/(2*[6:0]) (RAW);*/ 113 #define IMAGE_MODE 0xDA /* Image Output Format Select */ 114 #define IMAGE_MODE_Y8_DVP_EN 0x40 115 #define IMAGE_MODE_JPEG_EN 0x10 116 #define IMAGE_MODE_YUV422 0x00 117 #define IMAGE_MODE_RAW10 0x04 /* (DVP) */ 118 #define IMAGE_MODE_RGB565 0x08 119 #define IMAGE_MODE_HREF_VSYNC 0x02 /* HREF timing select in DVP JPEG output 120 * mode (0 for HREF is same as sensor) */ 121 #define IMAGE_MODE_LBYTE_FIRST 0x01 /* Byte swap enable for DVP 122 * 1: Low byte first UYVY (C2[4] =0) 123 * VYUY (C2[4] =1) 124 * 0: High byte first YUYV (C2[4]=0) 125 * YVYU (C2[4] = 1) */ 126 #define RESET 0xE0 /* Reset */ 127 #define RESET_MICROC 0x40 128 #define RESET_SCCB 0x20 129 #define RESET_JPEG 0x10 130 #define RESET_DVP 0x04 131 #define RESET_IPU 0x02 132 #define RESET_CIF 0x01 133 #define REGED 0xED /* Register ED */ 134 #define REGED_CLK_OUT_DIS 0x10 135 #define MS_SP 0xF0 /* SCCB Master Speed */ 136 #define SS_ID 0xF7 /* SCCB Slave ID */ 137 #define SS_CTRL 0xF8 /* SCCB Slave Control */ 138 #define SS_CTRL_ADD_AUTO_INC 0x20 139 #define SS_CTRL_EN 0x08 140 #define SS_CTRL_DELAY_CLK 0x04 141 #define SS_CTRL_ACC_EN 0x02 142 #define SS_CTRL_SEN_PASS_THR 0x01 143 #define MC_BIST 0xF9 /* Microcontroller misc register */ 144 #define MC_BIST_RESET 0x80 /* Microcontroller Reset */ 145 #define MC_BIST_BOOT_ROM_SEL 0x40 146 #define MC_BIST_12KB_SEL 0x20 147 #define MC_BIST_12KB_MASK 0x30 148 #define MC_BIST_512KB_SEL 0x08 149 #define MC_BIST_512KB_MASK 0x0C 150 #define MC_BIST_BUSY_BIT_R 0x02 151 #define MC_BIST_MC_RES_ONE_SH_W 0x02 152 #define MC_BIST_LAUNCH 0x01 153 #define BANK_SEL 0xFF /* Register Bank Select */ 154 #define BANK_SEL_DSP 0x00 155 #define BANK_SEL_SENS 0x01 156 157 /* 158 * Sensor registers 159 * register offset for BANK_SEL == BANK_SEL_SENS 160 */ 161 #define GAIN 0x00 /* AGC - Gain control gain setting */ 162 #define COM1 0x03 /* Common control 1 */ 163 #define COM1_1_DUMMY_FR 0x40 164 #define COM1_3_DUMMY_FR 0x80 165 #define COM1_7_DUMMY_FR 0xC0 166 #define COM1_VWIN_LSB_UXGA 0x0F 167 #define COM1_VWIN_LSB_SVGA 0x0A 168 #define COM1_VWIN_LSB_CIF 0x06 169 #define REG04 0x04 /* Register 04 */ 170 #define REG04_DEF 0x20 /* Always set */ 171 #define REG04_HFLIP_IMG 0x80 /* Horizontal mirror image ON/OFF */ 172 #define REG04_VFLIP_IMG 0x40 /* Vertical flip image ON/OFF */ 173 #define REG04_VREF_EN 0x10 174 #define REG04_HREF_EN 0x08 175 #define REG04_AEC_SET(x) VAL_SET(x, 0x3, 0, 0) 176 #define REG08 0x08 /* Frame Exposure One-pin Control Pre-charge Row Num */ 177 #define COM2 0x09 /* Common control 2 */ 178 #define COM2_SOFT_SLEEP_MODE 0x10 /* Soft sleep mode */ 179 /* Output drive capability */ 180 #define COM2_OCAP_Nx_SET(N) (((N) - 1) & 0x03) /* N = [1x .. 4x] */ 181 #define PID 0x0A /* Product ID Number MSB */ 182 #define VER 0x0B /* Product ID Number LSB */ 183 #define COM3 0x0C /* Common control 3 */ 184 #define COM3_BAND_50H 0x04 /* 0 For Banding at 60H */ 185 #define COM3_BAND_AUTO 0x02 /* Auto Banding */ 186 #define COM3_SING_FR_SNAPSH 0x01 /* 0 For enable live video output after the 187 * snapshot sequence*/ 188 #define AEC 0x10 /* AEC[9:2] Exposure Value */ 189 #define CLKRC 0x11 /* Internal clock */ 190 #define CLKRC_EN 0x80 191 #define CLKRC_DIV_SET(x) (((x) - 1) & 0x1F) /* CLK = XVCLK/(x) */ 192 #define COM7 0x12 /* Common control 7 */ 193 #define COM7_SRST 0x80 /* Initiates system reset. All registers are 194 * set to factory default values after which 195 * the chip resumes normal operation */ 196 #define COM7_RES_UXGA 0x00 /* Resolution selectors for UXGA */ 197 #define COM7_RES_SVGA 0x40 /* SVGA */ 198 #define COM7_RES_CIF 0x20 /* CIF */ 199 #define COM7_ZOOM_EN 0x04 /* Enable Zoom mode */ 200 #define COM7_COLOR_BAR_TEST 0x02 /* Enable Color Bar Test Pattern */ 201 #define COM8 0x13 /* Common control 8 */ 202 #define COM8_DEF 0xC0 203 #define COM8_BNDF_EN 0x20 /* Banding filter ON/OFF */ 204 #define COM8_AGC_EN 0x04 /* AGC Auto/Manual control selection */ 205 #define COM8_AEC_EN 0x01 /* Auto/Manual Exposure control */ 206 #define COM9 0x14 /* Common control 9 207 * Automatic gain ceiling - maximum AGC value [7:5]*/ 208 #define COM9_AGC_GAIN_2x 0x00 /* 000 : 2x */ 209 #define COM9_AGC_GAIN_4x 0x20 /* 001 : 4x */ 210 #define COM9_AGC_GAIN_8x 0x40 /* 010 : 8x */ 211 #define COM9_AGC_GAIN_16x 0x60 /* 011 : 16x */ 212 #define COM9_AGC_GAIN_32x 0x80 /* 100 : 32x */ 213 #define COM9_AGC_GAIN_64x 0xA0 /* 101 : 64x */ 214 #define COM9_AGC_GAIN_128x 0xC0 /* 110 : 128x */ 215 #define COM10 0x15 /* Common control 10 */ 216 #define COM10_PCLK_HREF 0x20 /* PCLK output qualified by HREF */ 217 #define COM10_PCLK_RISE 0x10 /* Data is updated at the rising edge of 218 * PCLK (user can latch data at the next 219 * falling edge of PCLK). 220 * 0 otherwise. */ 221 #define COM10_HREF_INV 0x08 /* Invert HREF polarity: 222 * HREF negative for valid data*/ 223 #define COM10_VSINC_INV 0x02 /* Invert VSYNC polarity */ 224 #define HSTART 0x17 /* Horizontal Window start MSB 8 bit */ 225 #define HEND 0x18 /* Horizontal Window end MSB 8 bit */ 226 #define VSTART 0x19 /* Vertical Window start MSB 8 bit */ 227 #define VEND 0x1A /* Vertical Window end MSB 8 bit */ 228 #define MIDH 0x1C /* Manufacturer ID byte - high */ 229 #define MIDL 0x1D /* Manufacturer ID byte - low */ 230 #define AEW 0x24 /* AGC/AEC - Stable operating region (upper limit) */ 231 #define AEB 0x25 /* AGC/AEC - Stable operating region (lower limit) */ 232 #define VV 0x26 /* AGC/AEC Fast mode operating region */ 233 #define VV_HIGH_TH_SET(x) VAL_SET(x, 0xF, 0, 4) 234 #define VV_LOW_TH_SET(x) VAL_SET(x, 0xF, 0, 0) 235 #define REG2A 0x2A /* Dummy pixel insert MSB */ 236 #define FRARL 0x2B /* Dummy pixel insert LSB */ 237 #define ADDVFL 0x2D /* LSB of insert dummy lines in Vertical direction */ 238 #define ADDVFH 0x2E /* MSB of insert dummy lines in Vertical direction */ 239 #define YAVG 0x2F /* Y/G Channel Average value */ 240 #define REG32 0x32 /* Common Control 32 */ 241 #define REG32_PCLK_DIV_2 0x80 /* PCLK freq divided by 2 */ 242 #define REG32_PCLK_DIV_4 0xC0 /* PCLK freq divided by 4 */ 243 #define ARCOM2 0x34 /* Zoom: Horizontal start point */ 244 #define REG45 0x45 /* Register 45 */ 245 #define FLL 0x46 /* Frame Length Adjustment LSBs */ 246 #define FLH 0x47 /* Frame Length Adjustment MSBs */ 247 #define COM19 0x48 /* Zoom: Vertical start point */ 248 #define ZOOMS 0x49 /* Zoom: Vertical start point */ 249 #define COM22 0x4B /* Flash light control */ 250 #define COM25 0x4E /* For Banding operations */ 251 #define COM25_50HZ_BANDING_AEC_MSBS_MASK 0xC0 /* 50Hz Bd. AEC 2 MSBs */ 252 #define COM25_60HZ_BANDING_AEC_MSBS_MASK 0x30 /* 60Hz Bd. AEC 2 MSBs */ 253 #define COM25_50HZ_BANDING_AEC_MSBS_SET(x) VAL_SET(x, 0x3, 8, 6) 254 #define COM25_60HZ_BANDING_AEC_MSBS_SET(x) VAL_SET(x, 0x3, 8, 4) 255 #define BD50 0x4F /* 50Hz Banding AEC 8 LSBs */ 256 #define BD50_50HZ_BANDING_AEC_LSBS_SET(x) VAL_SET(x, 0xFF, 0, 0) 257 #define BD60 0x50 /* 60Hz Banding AEC 8 LSBs */ 258 #define BD60_60HZ_BANDING_AEC_LSBS_SET(x) VAL_SET(x, 0xFF, 0, 0) 259 #define REG5A 0x5A /* 50/60Hz Banding Maximum AEC Step */ 260 #define BD50_MAX_AEC_STEP_MASK 0xF0 /* 50Hz Banding Max. AEC Step */ 261 #define BD60_MAX_AEC_STEP_MASK 0x0F /* 60Hz Banding Max. AEC Step */ 262 #define BD50_MAX_AEC_STEP_SET(x) VAL_SET((x - 1), 0x0F, 0, 4) 263 #define BD60_MAX_AEC_STEP_SET(x) VAL_SET((x - 1), 0x0F, 0, 0) 264 #define REG5D 0x5D /* AVGsel[7:0], 16-zone average weight option */ 265 #define REG5E 0x5E /* AVGsel[15:8], 16-zone average weight option */ 266 #define REG5F 0x5F /* AVGsel[23:16], 16-zone average weight option */ 267 #define REG60 0x60 /* AVGsel[31:24], 16-zone average weight option */ 268 #define HISTO_LOW 0x61 /* Histogram Algorithm Low Level */ 269 #define HISTO_HIGH 0x62 /* Histogram Algorithm High Level */ 270 271 /* 272 * ID 273 */ 274 #define MANUFACTURER_ID 0x7FA2 275 #define PID_OV2640 0x2642 276 #define VERSION(pid, ver) ((pid << 8) | (ver & 0xFF)) 277 278 /* 279 * Struct 280 */ 281 struct regval_list { 282 u8 reg_num; 283 u8 value; 284 }; 285 286 struct ov2640_win_size { 287 char *name; 288 u32 width; 289 u32 height; 290 const struct regval_list *regs; 291 }; 292 293 294 struct ov2640_priv { 295 struct v4l2_subdev subdev; 296 #if defined(CONFIG_MEDIA_CONTROLLER) 297 struct media_pad pad; 298 #endif 299 struct v4l2_ctrl_handler hdl; 300 u32 cfmt_code; 301 struct clk *clk; 302 const struct ov2640_win_size *win; 303 304 struct gpio_desc *resetb_gpio; 305 struct gpio_desc *pwdn_gpio; 306 307 struct mutex lock; /* lock to protect streaming and power_count */ 308 bool streaming; 309 int power_count; 310 }; 311 312 /* 313 * Registers settings 314 */ 315 316 #define ENDMARKER { 0xff, 0xff } 317 318 static const struct regval_list ov2640_init_regs[] = { 319 { BANK_SEL, BANK_SEL_DSP }, 320 { 0x2c, 0xff }, 321 { 0x2e, 0xdf }, 322 { BANK_SEL, BANK_SEL_SENS }, 323 { 0x3c, 0x32 }, 324 { CLKRC, CLKRC_DIV_SET(1) }, 325 { COM2, COM2_OCAP_Nx_SET(3) }, 326 { REG04, REG04_DEF | REG04_HREF_EN }, 327 { COM8, COM8_DEF | COM8_BNDF_EN | COM8_AGC_EN | COM8_AEC_EN }, 328 { COM9, COM9_AGC_GAIN_8x | 0x08}, 329 { 0x2c, 0x0c }, 330 { 0x33, 0x78 }, 331 { 0x3a, 0x33 }, 332 { 0x3b, 0xfb }, 333 { 0x3e, 0x00 }, 334 { 0x43, 0x11 }, 335 { 0x16, 0x10 }, 336 { 0x39, 0x02 }, 337 { 0x35, 0x88 }, 338 { 0x22, 0x0a }, 339 { 0x37, 0x40 }, 340 { 0x23, 0x00 }, 341 { ARCOM2, 0xa0 }, 342 { 0x06, 0x02 }, 343 { 0x06, 0x88 }, 344 { 0x07, 0xc0 }, 345 { 0x0d, 0xb7 }, 346 { 0x0e, 0x01 }, 347 { 0x4c, 0x00 }, 348 { 0x4a, 0x81 }, 349 { 0x21, 0x99 }, 350 { AEW, 0x40 }, 351 { AEB, 0x38 }, 352 { VV, VV_HIGH_TH_SET(0x08) | VV_LOW_TH_SET(0x02) }, 353 { 0x5c, 0x00 }, 354 { 0x63, 0x00 }, 355 { FLL, 0x22 }, 356 { COM3, 0x38 | COM3_BAND_AUTO }, 357 { REG5D, 0x55 }, 358 { REG5E, 0x7d }, 359 { REG5F, 0x7d }, 360 { REG60, 0x55 }, 361 { HISTO_LOW, 0x70 }, 362 { HISTO_HIGH, 0x80 }, 363 { 0x7c, 0x05 }, 364 { 0x20, 0x80 }, 365 { 0x28, 0x30 }, 366 { 0x6c, 0x00 }, 367 { 0x6d, 0x80 }, 368 { 0x6e, 0x00 }, 369 { 0x70, 0x02 }, 370 { 0x71, 0x94 }, 371 { 0x73, 0xc1 }, 372 { 0x3d, 0x34 }, 373 { COM7, COM7_RES_UXGA | COM7_ZOOM_EN }, 374 { REG5A, BD50_MAX_AEC_STEP_SET(6) 375 | BD60_MAX_AEC_STEP_SET(8) }, /* 0x57 */ 376 { COM25, COM25_50HZ_BANDING_AEC_MSBS_SET(0x0bb) 377 | COM25_60HZ_BANDING_AEC_MSBS_SET(0x09c) }, /* 0x00 */ 378 { BD50, BD50_50HZ_BANDING_AEC_LSBS_SET(0x0bb) }, /* 0xbb */ 379 { BD60, BD60_60HZ_BANDING_AEC_LSBS_SET(0x09c) }, /* 0x9c */ 380 { BANK_SEL, BANK_SEL_DSP }, 381 { 0xe5, 0x7f }, 382 { MC_BIST, MC_BIST_RESET | MC_BIST_BOOT_ROM_SEL }, 383 { 0x41, 0x24 }, 384 { RESET, RESET_JPEG | RESET_DVP }, 385 { 0x76, 0xff }, 386 { 0x33, 0xa0 }, 387 { 0x42, 0x20 }, 388 { 0x43, 0x18 }, 389 { 0x4c, 0x00 }, 390 { CTRL3, CTRL3_BPC_EN | CTRL3_WPC_EN | 0x10 }, 391 { 0x88, 0x3f }, 392 { 0xd7, 0x03 }, 393 { 0xd9, 0x10 }, 394 { R_DVP_SP, R_DVP_SP_AUTO_MODE | 0x2 }, 395 { 0xc8, 0x08 }, 396 { 0xc9, 0x80 }, 397 { BPADDR, 0x00 }, 398 { BPDATA, 0x00 }, 399 { BPADDR, 0x03 }, 400 { BPDATA, 0x48 }, 401 { BPDATA, 0x48 }, 402 { BPADDR, 0x08 }, 403 { BPDATA, 0x20 }, 404 { BPDATA, 0x10 }, 405 { BPDATA, 0x0e }, 406 { 0x90, 0x00 }, 407 { 0x91, 0x0e }, 408 { 0x91, 0x1a }, 409 { 0x91, 0x31 }, 410 { 0x91, 0x5a }, 411 { 0x91, 0x69 }, 412 { 0x91, 0x75 }, 413 { 0x91, 0x7e }, 414 { 0x91, 0x88 }, 415 { 0x91, 0x8f }, 416 { 0x91, 0x96 }, 417 { 0x91, 0xa3 }, 418 { 0x91, 0xaf }, 419 { 0x91, 0xc4 }, 420 { 0x91, 0xd7 }, 421 { 0x91, 0xe8 }, 422 { 0x91, 0x20 }, 423 { 0x92, 0x00 }, 424 { 0x93, 0x06 }, 425 { 0x93, 0xe3 }, 426 { 0x93, 0x03 }, 427 { 0x93, 0x03 }, 428 { 0x93, 0x00 }, 429 { 0x93, 0x02 }, 430 { 0x93, 0x00 }, 431 { 0x93, 0x00 }, 432 { 0x93, 0x00 }, 433 { 0x93, 0x00 }, 434 { 0x93, 0x00 }, 435 { 0x93, 0x00 }, 436 { 0x93, 0x00 }, 437 { 0x96, 0x00 }, 438 { 0x97, 0x08 }, 439 { 0x97, 0x19 }, 440 { 0x97, 0x02 }, 441 { 0x97, 0x0c }, 442 { 0x97, 0x24 }, 443 { 0x97, 0x30 }, 444 { 0x97, 0x28 }, 445 { 0x97, 0x26 }, 446 { 0x97, 0x02 }, 447 { 0x97, 0x98 }, 448 { 0x97, 0x80 }, 449 { 0x97, 0x00 }, 450 { 0x97, 0x00 }, 451 { 0xa4, 0x00 }, 452 { 0xa8, 0x00 }, 453 { 0xc5, 0x11 }, 454 { 0xc6, 0x51 }, 455 { 0xbf, 0x80 }, 456 { 0xc7, 0x10 }, /* simple AWB */ 457 { 0xb6, 0x66 }, 458 { 0xb8, 0xA5 }, 459 { 0xb7, 0x64 }, 460 { 0xb9, 0x7C }, 461 { 0xb3, 0xaf }, 462 { 0xb4, 0x97 }, 463 { 0xb5, 0xFF }, 464 { 0xb0, 0xC5 }, 465 { 0xb1, 0x94 }, 466 { 0xb2, 0x0f }, 467 { 0xc4, 0x5c }, 468 { 0xa6, 0x00 }, 469 { 0xa7, 0x20 }, 470 { 0xa7, 0xd8 }, 471 { 0xa7, 0x1b }, 472 { 0xa7, 0x31 }, 473 { 0xa7, 0x00 }, 474 { 0xa7, 0x18 }, 475 { 0xa7, 0x20 }, 476 { 0xa7, 0xd8 }, 477 { 0xa7, 0x19 }, 478 { 0xa7, 0x31 }, 479 { 0xa7, 0x00 }, 480 { 0xa7, 0x18 }, 481 { 0xa7, 0x20 }, 482 { 0xa7, 0xd8 }, 483 { 0xa7, 0x19 }, 484 { 0xa7, 0x31 }, 485 { 0xa7, 0x00 }, 486 { 0xa7, 0x18 }, 487 { 0x7f, 0x00 }, 488 { 0xe5, 0x1f }, 489 { 0xe1, 0x77 }, 490 { 0xdd, 0x7f }, 491 { CTRL0, CTRL0_YUV422 | CTRL0_YUV_EN | CTRL0_RGB_EN }, 492 ENDMARKER, 493 }; 494 495 /* 496 * Register settings for window size 497 * The preamble, setup the internal DSP to input an UXGA (1600x1200) image. 498 * Then the different zooming configurations will setup the output image size. 499 */ 500 static const struct regval_list ov2640_size_change_preamble_regs[] = { 501 { BANK_SEL, BANK_SEL_DSP }, 502 { RESET, RESET_DVP }, 503 { SIZEL, SIZEL_HSIZE8_11_SET(UXGA_WIDTH) | 504 SIZEL_HSIZE8_SET(UXGA_WIDTH) | 505 SIZEL_VSIZE8_SET(UXGA_HEIGHT) }, 506 { HSIZE8, HSIZE8_SET(UXGA_WIDTH) }, 507 { VSIZE8, VSIZE8_SET(UXGA_HEIGHT) }, 508 { CTRL2, CTRL2_DCW_EN | CTRL2_SDE_EN | 509 CTRL2_UV_AVG_EN | CTRL2_CMX_EN | CTRL2_UV_ADJ_EN }, 510 { HSIZE, HSIZE_SET(UXGA_WIDTH) }, 511 { VSIZE, VSIZE_SET(UXGA_HEIGHT) }, 512 { XOFFL, XOFFL_SET(0) }, 513 { YOFFL, YOFFL_SET(0) }, 514 { VHYX, VHYX_HSIZE_SET(UXGA_WIDTH) | VHYX_VSIZE_SET(UXGA_HEIGHT) | 515 VHYX_XOFF_SET(0) | VHYX_YOFF_SET(0)}, 516 { TEST, TEST_HSIZE_SET(UXGA_WIDTH) }, 517 ENDMARKER, 518 }; 519 520 #define PER_SIZE_REG_SEQ(x, y, v_div, h_div, pclk_div) \ 521 { CTRLI, CTRLI_LP_DP | CTRLI_V_DIV_SET(v_div) | \ 522 CTRLI_H_DIV_SET(h_div)}, \ 523 { ZMOW, ZMOW_OUTW_SET(x) }, \ 524 { ZMOH, ZMOH_OUTH_SET(y) }, \ 525 { ZMHH, ZMHH_OUTW_SET(x) | ZMHH_OUTH_SET(y) }, \ 526 { R_DVP_SP, pclk_div }, \ 527 { RESET, 0x00} 528 529 static const struct regval_list ov2640_qcif_regs[] = { 530 PER_SIZE_REG_SEQ(QCIF_WIDTH, QCIF_HEIGHT, 3, 3, 4), 531 ENDMARKER, 532 }; 533 534 static const struct regval_list ov2640_qvga_regs[] = { 535 PER_SIZE_REG_SEQ(QVGA_WIDTH, QVGA_HEIGHT, 2, 2, 4), 536 ENDMARKER, 537 }; 538 539 static const struct regval_list ov2640_cif_regs[] = { 540 PER_SIZE_REG_SEQ(CIF_WIDTH, CIF_HEIGHT, 2, 2, 8), 541 ENDMARKER, 542 }; 543 544 static const struct regval_list ov2640_vga_regs[] = { 545 PER_SIZE_REG_SEQ(VGA_WIDTH, VGA_HEIGHT, 0, 0, 2), 546 ENDMARKER, 547 }; 548 549 static const struct regval_list ov2640_svga_regs[] = { 550 PER_SIZE_REG_SEQ(SVGA_WIDTH, SVGA_HEIGHT, 1, 1, 2), 551 ENDMARKER, 552 }; 553 554 static const struct regval_list ov2640_xga_regs[] = { 555 PER_SIZE_REG_SEQ(XGA_WIDTH, XGA_HEIGHT, 0, 0, 2), 556 { CTRLI, 0x00}, 557 ENDMARKER, 558 }; 559 560 static const struct regval_list ov2640_sxga_regs[] = { 561 PER_SIZE_REG_SEQ(SXGA_WIDTH, SXGA_HEIGHT, 0, 0, 2), 562 { CTRLI, 0x00}, 563 { R_DVP_SP, 2 | R_DVP_SP_AUTO_MODE }, 564 ENDMARKER, 565 }; 566 567 static const struct regval_list ov2640_uxga_regs[] = { 568 PER_SIZE_REG_SEQ(UXGA_WIDTH, UXGA_HEIGHT, 0, 0, 0), 569 { CTRLI, 0x00}, 570 { R_DVP_SP, 0 | R_DVP_SP_AUTO_MODE }, 571 ENDMARKER, 572 }; 573 574 #define OV2640_SIZE(n, w, h, r) \ 575 {.name = n, .width = w , .height = h, .regs = r } 576 577 static const struct ov2640_win_size ov2640_supported_win_sizes[] = { 578 OV2640_SIZE("QCIF", QCIF_WIDTH, QCIF_HEIGHT, ov2640_qcif_regs), 579 OV2640_SIZE("QVGA", QVGA_WIDTH, QVGA_HEIGHT, ov2640_qvga_regs), 580 OV2640_SIZE("CIF", CIF_WIDTH, CIF_HEIGHT, ov2640_cif_regs), 581 OV2640_SIZE("VGA", VGA_WIDTH, VGA_HEIGHT, ov2640_vga_regs), 582 OV2640_SIZE("SVGA", SVGA_WIDTH, SVGA_HEIGHT, ov2640_svga_regs), 583 OV2640_SIZE("XGA", XGA_WIDTH, XGA_HEIGHT, ov2640_xga_regs), 584 OV2640_SIZE("SXGA", SXGA_WIDTH, SXGA_HEIGHT, ov2640_sxga_regs), 585 OV2640_SIZE("UXGA", UXGA_WIDTH, UXGA_HEIGHT, ov2640_uxga_regs), 586 }; 587 588 /* 589 * Register settings for pixel formats 590 */ 591 static const struct regval_list ov2640_format_change_preamble_regs[] = { 592 { BANK_SEL, BANK_SEL_DSP }, 593 { R_BYPASS, R_BYPASS_USE_DSP }, 594 ENDMARKER, 595 }; 596 597 static const struct regval_list ov2640_yuyv_regs[] = { 598 { IMAGE_MODE, IMAGE_MODE_YUV422 }, 599 { 0xd7, 0x03 }, 600 { 0x33, 0xa0 }, 601 { 0xe5, 0x1f }, 602 { 0xe1, 0x67 }, 603 { RESET, 0x00 }, 604 { R_BYPASS, R_BYPASS_USE_DSP }, 605 ENDMARKER, 606 }; 607 608 static const struct regval_list ov2640_uyvy_regs[] = { 609 { IMAGE_MODE, IMAGE_MODE_LBYTE_FIRST | IMAGE_MODE_YUV422 }, 610 { 0xd7, 0x01 }, 611 { 0x33, 0xa0 }, 612 { 0xe1, 0x67 }, 613 { RESET, 0x00 }, 614 { R_BYPASS, R_BYPASS_USE_DSP }, 615 ENDMARKER, 616 }; 617 618 static const struct regval_list ov2640_rgb565_be_regs[] = { 619 { IMAGE_MODE, IMAGE_MODE_RGB565 }, 620 { 0xd7, 0x03 }, 621 { RESET, 0x00 }, 622 { R_BYPASS, R_BYPASS_USE_DSP }, 623 ENDMARKER, 624 }; 625 626 static const struct regval_list ov2640_rgb565_le_regs[] = { 627 { IMAGE_MODE, IMAGE_MODE_LBYTE_FIRST | IMAGE_MODE_RGB565 }, 628 { 0xd7, 0x03 }, 629 { RESET, 0x00 }, 630 { R_BYPASS, R_BYPASS_USE_DSP }, 631 ENDMARKER, 632 }; 633 634 static u32 ov2640_codes[] = { 635 MEDIA_BUS_FMT_YUYV8_2X8, 636 MEDIA_BUS_FMT_UYVY8_2X8, 637 MEDIA_BUS_FMT_YVYU8_2X8, 638 MEDIA_BUS_FMT_VYUY8_2X8, 639 MEDIA_BUS_FMT_RGB565_2X8_BE, 640 MEDIA_BUS_FMT_RGB565_2X8_LE, 641 }; 642 643 /* 644 * General functions 645 */ 646 static struct ov2640_priv *to_ov2640(const struct i2c_client *client) 647 { 648 return container_of(i2c_get_clientdata(client), struct ov2640_priv, 649 subdev); 650 } 651 652 static int ov2640_write_array(struct i2c_client *client, 653 const struct regval_list *vals) 654 { 655 int ret; 656 657 while ((vals->reg_num != 0xff) || (vals->value != 0xff)) { 658 ret = i2c_smbus_write_byte_data(client, 659 vals->reg_num, vals->value); 660 dev_vdbg(&client->dev, "array: 0x%02x, 0x%02x", 661 vals->reg_num, vals->value); 662 663 if (ret < 0) 664 return ret; 665 vals++; 666 } 667 return 0; 668 } 669 670 static int ov2640_mask_set(struct i2c_client *client, 671 u8 reg, u8 mask, u8 set) 672 { 673 s32 val = i2c_smbus_read_byte_data(client, reg); 674 if (val < 0) 675 return val; 676 677 val &= ~mask; 678 val |= set & mask; 679 680 dev_vdbg(&client->dev, "masks: 0x%02x, 0x%02x", reg, val); 681 682 return i2c_smbus_write_byte_data(client, reg, val); 683 } 684 685 static int ov2640_reset(struct i2c_client *client) 686 { 687 int ret; 688 static const struct regval_list reset_seq[] = { 689 {BANK_SEL, BANK_SEL_SENS}, 690 {COM7, COM7_SRST}, 691 ENDMARKER, 692 }; 693 694 ret = ov2640_write_array(client, reset_seq); 695 if (ret) 696 goto err; 697 698 msleep(5); 699 err: 700 dev_dbg(&client->dev, "%s: (ret %d)", __func__, ret); 701 return ret; 702 } 703 704 static const char * const ov2640_test_pattern_menu[] = { 705 "Disabled", 706 "Eight Vertical Colour Bars", 707 }; 708 709 /* 710 * functions 711 */ 712 static int ov2640_s_ctrl(struct v4l2_ctrl *ctrl) 713 { 714 struct v4l2_subdev *sd = 715 &container_of(ctrl->handler, struct ov2640_priv, hdl)->subdev; 716 struct i2c_client *client = v4l2_get_subdevdata(sd); 717 struct ov2640_priv *priv = to_ov2640(client); 718 u8 val; 719 int ret; 720 721 /* v4l2_ctrl_lock() locks our own mutex */ 722 723 /* 724 * If the device is not powered up by the host driver, do not apply any 725 * controls to H/W at this time. Instead the controls will be restored 726 * when the streaming is started. 727 */ 728 if (!priv->power_count) 729 return 0; 730 731 ret = i2c_smbus_write_byte_data(client, BANK_SEL, BANK_SEL_SENS); 732 if (ret < 0) 733 return ret; 734 735 switch (ctrl->id) { 736 case V4L2_CID_VFLIP: 737 val = ctrl->val ? REG04_VFLIP_IMG | REG04_VREF_EN : 0x00; 738 return ov2640_mask_set(client, REG04, 739 REG04_VFLIP_IMG | REG04_VREF_EN, val); 740 /* NOTE: REG04_VREF_EN: 1 line shift / even/odd line swap */ 741 case V4L2_CID_HFLIP: 742 val = ctrl->val ? REG04_HFLIP_IMG : 0x00; 743 return ov2640_mask_set(client, REG04, REG04_HFLIP_IMG, val); 744 case V4L2_CID_TEST_PATTERN: 745 val = ctrl->val ? COM7_COLOR_BAR_TEST : 0x00; 746 return ov2640_mask_set(client, COM7, COM7_COLOR_BAR_TEST, val); 747 } 748 749 return -EINVAL; 750 } 751 752 #ifdef CONFIG_VIDEO_ADV_DEBUG 753 static int ov2640_g_register(struct v4l2_subdev *sd, 754 struct v4l2_dbg_register *reg) 755 { 756 struct i2c_client *client = v4l2_get_subdevdata(sd); 757 int ret; 758 759 reg->size = 1; 760 if (reg->reg > 0xff) 761 return -EINVAL; 762 763 ret = i2c_smbus_read_byte_data(client, reg->reg); 764 if (ret < 0) 765 return ret; 766 767 reg->val = ret; 768 769 return 0; 770 } 771 772 static int ov2640_s_register(struct v4l2_subdev *sd, 773 const struct v4l2_dbg_register *reg) 774 { 775 struct i2c_client *client = v4l2_get_subdevdata(sd); 776 777 if (reg->reg > 0xff || 778 reg->val > 0xff) 779 return -EINVAL; 780 781 return i2c_smbus_write_byte_data(client, reg->reg, reg->val); 782 } 783 #endif 784 785 static void ov2640_set_power(struct ov2640_priv *priv, int on) 786 { 787 #ifdef CONFIG_GPIOLIB 788 if (priv->pwdn_gpio) 789 gpiod_direction_output(priv->pwdn_gpio, !on); 790 if (on && priv->resetb_gpio) { 791 /* Active the resetb pin to perform a reset pulse */ 792 gpiod_direction_output(priv->resetb_gpio, 1); 793 usleep_range(3000, 5000); 794 gpiod_set_value(priv->resetb_gpio, 0); 795 } 796 #endif 797 } 798 799 static int ov2640_s_power(struct v4l2_subdev *sd, int on) 800 { 801 struct i2c_client *client = v4l2_get_subdevdata(sd); 802 struct ov2640_priv *priv = to_ov2640(client); 803 804 mutex_lock(&priv->lock); 805 806 /* 807 * If the power count is modified from 0 to != 0 or from != 0 to 0, 808 * update the power state. 809 */ 810 if (priv->power_count == !on) 811 ov2640_set_power(priv, on); 812 priv->power_count += on ? 1 : -1; 813 WARN_ON(priv->power_count < 0); 814 mutex_unlock(&priv->lock); 815 816 return 0; 817 } 818 819 /* Select the nearest higher resolution for capture */ 820 static const struct ov2640_win_size *ov2640_select_win(u32 width, u32 height) 821 { 822 int i, default_size = ARRAY_SIZE(ov2640_supported_win_sizes) - 1; 823 824 for (i = 0; i < ARRAY_SIZE(ov2640_supported_win_sizes); i++) { 825 if (ov2640_supported_win_sizes[i].width >= width && 826 ov2640_supported_win_sizes[i].height >= height) 827 return &ov2640_supported_win_sizes[i]; 828 } 829 830 return &ov2640_supported_win_sizes[default_size]; 831 } 832 833 static int ov2640_set_params(struct i2c_client *client, 834 const struct ov2640_win_size *win, u32 code) 835 { 836 const struct regval_list *selected_cfmt_regs; 837 u8 val; 838 int ret; 839 840 switch (code) { 841 case MEDIA_BUS_FMT_RGB565_2X8_BE: 842 dev_dbg(&client->dev, "%s: Selected cfmt RGB565 BE", __func__); 843 selected_cfmt_regs = ov2640_rgb565_be_regs; 844 break; 845 case MEDIA_BUS_FMT_RGB565_2X8_LE: 846 dev_dbg(&client->dev, "%s: Selected cfmt RGB565 LE", __func__); 847 selected_cfmt_regs = ov2640_rgb565_le_regs; 848 break; 849 case MEDIA_BUS_FMT_YUYV8_2X8: 850 dev_dbg(&client->dev, "%s: Selected cfmt YUYV (YUV422)", __func__); 851 selected_cfmt_regs = ov2640_yuyv_regs; 852 break; 853 case MEDIA_BUS_FMT_UYVY8_2X8: 854 default: 855 dev_dbg(&client->dev, "%s: Selected cfmt UYVY", __func__); 856 selected_cfmt_regs = ov2640_uyvy_regs; 857 break; 858 case MEDIA_BUS_FMT_YVYU8_2X8: 859 dev_dbg(&client->dev, "%s: Selected cfmt YVYU", __func__); 860 selected_cfmt_regs = ov2640_yuyv_regs; 861 break; 862 case MEDIA_BUS_FMT_VYUY8_2X8: 863 dev_dbg(&client->dev, "%s: Selected cfmt VYUY", __func__); 864 selected_cfmt_regs = ov2640_uyvy_regs; 865 break; 866 } 867 868 /* reset hardware */ 869 ov2640_reset(client); 870 871 /* initialize the sensor with default data */ 872 dev_dbg(&client->dev, "%s: Init default", __func__); 873 ret = ov2640_write_array(client, ov2640_init_regs); 874 if (ret < 0) 875 goto err; 876 877 /* select preamble */ 878 dev_dbg(&client->dev, "%s: Set size to %s", __func__, win->name); 879 ret = ov2640_write_array(client, ov2640_size_change_preamble_regs); 880 if (ret < 0) 881 goto err; 882 883 /* set size win */ 884 ret = ov2640_write_array(client, win->regs); 885 if (ret < 0) 886 goto err; 887 888 /* cfmt preamble */ 889 dev_dbg(&client->dev, "%s: Set cfmt", __func__); 890 ret = ov2640_write_array(client, ov2640_format_change_preamble_regs); 891 if (ret < 0) 892 goto err; 893 894 /* set cfmt */ 895 ret = ov2640_write_array(client, selected_cfmt_regs); 896 if (ret < 0) 897 goto err; 898 val = (code == MEDIA_BUS_FMT_YVYU8_2X8) 899 || (code == MEDIA_BUS_FMT_VYUY8_2X8) ? CTRL0_VFIRST : 0x00; 900 ret = ov2640_mask_set(client, CTRL0, CTRL0_VFIRST, val); 901 if (ret < 0) 902 goto err; 903 904 return 0; 905 906 err: 907 dev_err(&client->dev, "%s: Error %d", __func__, ret); 908 ov2640_reset(client); 909 910 return ret; 911 } 912 913 static int ov2640_get_fmt(struct v4l2_subdev *sd, 914 struct v4l2_subdev_state *sd_state, 915 struct v4l2_subdev_format *format) 916 { 917 struct v4l2_mbus_framefmt *mf = &format->format; 918 struct i2c_client *client = v4l2_get_subdevdata(sd); 919 struct ov2640_priv *priv = to_ov2640(client); 920 921 if (format->pad) 922 return -EINVAL; 923 924 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 925 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 926 mf = v4l2_subdev_get_try_format(sd, sd_state, 0); 927 format->format = *mf; 928 return 0; 929 #else 930 return -EINVAL; 931 #endif 932 } 933 934 mf->width = priv->win->width; 935 mf->height = priv->win->height; 936 mf->code = priv->cfmt_code; 937 mf->colorspace = V4L2_COLORSPACE_SRGB; 938 mf->field = V4L2_FIELD_NONE; 939 mf->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 940 mf->quantization = V4L2_QUANTIZATION_DEFAULT; 941 mf->xfer_func = V4L2_XFER_FUNC_DEFAULT; 942 943 return 0; 944 } 945 946 static int ov2640_set_fmt(struct v4l2_subdev *sd, 947 struct v4l2_subdev_state *sd_state, 948 struct v4l2_subdev_format *format) 949 { 950 struct v4l2_mbus_framefmt *mf = &format->format; 951 struct i2c_client *client = v4l2_get_subdevdata(sd); 952 struct ov2640_priv *priv = to_ov2640(client); 953 const struct ov2640_win_size *win; 954 int ret = 0; 955 956 if (format->pad) 957 return -EINVAL; 958 959 mutex_lock(&priv->lock); 960 961 /* select suitable win */ 962 win = ov2640_select_win(mf->width, mf->height); 963 mf->width = win->width; 964 mf->height = win->height; 965 966 mf->field = V4L2_FIELD_NONE; 967 mf->colorspace = V4L2_COLORSPACE_SRGB; 968 mf->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 969 mf->quantization = V4L2_QUANTIZATION_DEFAULT; 970 mf->xfer_func = V4L2_XFER_FUNC_DEFAULT; 971 972 switch (mf->code) { 973 case MEDIA_BUS_FMT_RGB565_2X8_BE: 974 case MEDIA_BUS_FMT_RGB565_2X8_LE: 975 case MEDIA_BUS_FMT_YUYV8_2X8: 976 case MEDIA_BUS_FMT_UYVY8_2X8: 977 case MEDIA_BUS_FMT_YVYU8_2X8: 978 case MEDIA_BUS_FMT_VYUY8_2X8: 979 break; 980 default: 981 mf->code = MEDIA_BUS_FMT_UYVY8_2X8; 982 break; 983 } 984 985 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 986 struct ov2640_priv *priv = to_ov2640(client); 987 988 if (priv->streaming) { 989 ret = -EBUSY; 990 goto out; 991 } 992 /* select win */ 993 priv->win = win; 994 /* select format */ 995 priv->cfmt_code = mf->code; 996 } else { 997 sd_state->pads->try_fmt = *mf; 998 } 999 out: 1000 mutex_unlock(&priv->lock); 1001 1002 return ret; 1003 } 1004 1005 static int ov2640_init_cfg(struct v4l2_subdev *sd, 1006 struct v4l2_subdev_state *sd_state) 1007 { 1008 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1009 struct v4l2_mbus_framefmt *try_fmt = 1010 v4l2_subdev_get_try_format(sd, sd_state, 0); 1011 const struct ov2640_win_size *win = 1012 ov2640_select_win(SVGA_WIDTH, SVGA_HEIGHT); 1013 1014 try_fmt->width = win->width; 1015 try_fmt->height = win->height; 1016 try_fmt->code = MEDIA_BUS_FMT_UYVY8_2X8; 1017 try_fmt->colorspace = V4L2_COLORSPACE_SRGB; 1018 try_fmt->field = V4L2_FIELD_NONE; 1019 try_fmt->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 1020 try_fmt->quantization = V4L2_QUANTIZATION_DEFAULT; 1021 try_fmt->xfer_func = V4L2_XFER_FUNC_DEFAULT; 1022 #endif 1023 return 0; 1024 } 1025 1026 static int ov2640_enum_mbus_code(struct v4l2_subdev *sd, 1027 struct v4l2_subdev_state *sd_state, 1028 struct v4l2_subdev_mbus_code_enum *code) 1029 { 1030 if (code->pad || code->index >= ARRAY_SIZE(ov2640_codes)) 1031 return -EINVAL; 1032 1033 code->code = ov2640_codes[code->index]; 1034 return 0; 1035 } 1036 1037 static int ov2640_get_selection(struct v4l2_subdev *sd, 1038 struct v4l2_subdev_state *sd_state, 1039 struct v4l2_subdev_selection *sel) 1040 { 1041 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE) 1042 return -EINVAL; 1043 1044 switch (sel->target) { 1045 case V4L2_SEL_TGT_CROP_BOUNDS: 1046 case V4L2_SEL_TGT_CROP: 1047 sel->r.left = 0; 1048 sel->r.top = 0; 1049 sel->r.width = UXGA_WIDTH; 1050 sel->r.height = UXGA_HEIGHT; 1051 return 0; 1052 default: 1053 return -EINVAL; 1054 } 1055 } 1056 1057 static int ov2640_s_stream(struct v4l2_subdev *sd, int on) 1058 { 1059 struct i2c_client *client = v4l2_get_subdevdata(sd); 1060 struct ov2640_priv *priv = to_ov2640(client); 1061 int ret = 0; 1062 1063 mutex_lock(&priv->lock); 1064 if (priv->streaming == !on) { 1065 if (on) { 1066 ret = ov2640_set_params(client, priv->win, 1067 priv->cfmt_code); 1068 if (!ret) 1069 ret = __v4l2_ctrl_handler_setup(&priv->hdl); 1070 } 1071 } 1072 if (!ret) 1073 priv->streaming = on; 1074 mutex_unlock(&priv->lock); 1075 1076 return ret; 1077 } 1078 1079 static int ov2640_video_probe(struct i2c_client *client) 1080 { 1081 struct ov2640_priv *priv = to_ov2640(client); 1082 u8 pid, ver, midh, midl; 1083 const char *devname; 1084 int ret; 1085 1086 ret = ov2640_s_power(&priv->subdev, 1); 1087 if (ret < 0) 1088 return ret; 1089 1090 /* 1091 * check and show product ID and manufacturer ID 1092 */ 1093 i2c_smbus_write_byte_data(client, BANK_SEL, BANK_SEL_SENS); 1094 pid = i2c_smbus_read_byte_data(client, PID); 1095 ver = i2c_smbus_read_byte_data(client, VER); 1096 midh = i2c_smbus_read_byte_data(client, MIDH); 1097 midl = i2c_smbus_read_byte_data(client, MIDL); 1098 1099 switch (VERSION(pid, ver)) { 1100 case PID_OV2640: 1101 devname = "ov2640"; 1102 break; 1103 default: 1104 dev_err(&client->dev, 1105 "Product ID error %x:%x\n", pid, ver); 1106 ret = -ENODEV; 1107 goto done; 1108 } 1109 1110 dev_info(&client->dev, 1111 "%s Product ID %0x:%0x Manufacturer ID %x:%x\n", 1112 devname, pid, ver, midh, midl); 1113 1114 done: 1115 ov2640_s_power(&priv->subdev, 0); 1116 return ret; 1117 } 1118 1119 static const struct v4l2_ctrl_ops ov2640_ctrl_ops = { 1120 .s_ctrl = ov2640_s_ctrl, 1121 }; 1122 1123 static const struct v4l2_subdev_core_ops ov2640_subdev_core_ops = { 1124 .log_status = v4l2_ctrl_subdev_log_status, 1125 .subscribe_event = v4l2_ctrl_subdev_subscribe_event, 1126 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 1127 #ifdef CONFIG_VIDEO_ADV_DEBUG 1128 .g_register = ov2640_g_register, 1129 .s_register = ov2640_s_register, 1130 #endif 1131 .s_power = ov2640_s_power, 1132 }; 1133 1134 static const struct v4l2_subdev_pad_ops ov2640_subdev_pad_ops = { 1135 .init_cfg = ov2640_init_cfg, 1136 .enum_mbus_code = ov2640_enum_mbus_code, 1137 .get_selection = ov2640_get_selection, 1138 .get_fmt = ov2640_get_fmt, 1139 .set_fmt = ov2640_set_fmt, 1140 }; 1141 1142 static const struct v4l2_subdev_video_ops ov2640_subdev_video_ops = { 1143 .s_stream = ov2640_s_stream, 1144 }; 1145 1146 static const struct v4l2_subdev_ops ov2640_subdev_ops = { 1147 .core = &ov2640_subdev_core_ops, 1148 .pad = &ov2640_subdev_pad_ops, 1149 .video = &ov2640_subdev_video_ops, 1150 }; 1151 1152 static int ov2640_probe_dt(struct i2c_client *client, 1153 struct ov2640_priv *priv) 1154 { 1155 int ret; 1156 1157 /* Request the reset GPIO deasserted */ 1158 priv->resetb_gpio = devm_gpiod_get_optional(&client->dev, "resetb", 1159 GPIOD_OUT_LOW); 1160 1161 if (!priv->resetb_gpio) 1162 dev_dbg(&client->dev, "resetb gpio is not assigned!\n"); 1163 1164 ret = PTR_ERR_OR_ZERO(priv->resetb_gpio); 1165 if (ret && ret != -ENOSYS) { 1166 dev_dbg(&client->dev, 1167 "Error %d while getting resetb gpio\n", ret); 1168 return ret; 1169 } 1170 1171 /* Request the power down GPIO asserted */ 1172 priv->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "pwdn", 1173 GPIOD_OUT_HIGH); 1174 1175 if (!priv->pwdn_gpio) 1176 dev_dbg(&client->dev, "pwdn gpio is not assigned!\n"); 1177 1178 ret = PTR_ERR_OR_ZERO(priv->pwdn_gpio); 1179 if (ret && ret != -ENOSYS) { 1180 dev_dbg(&client->dev, 1181 "Error %d while getting pwdn gpio\n", ret); 1182 return ret; 1183 } 1184 1185 return 0; 1186 } 1187 1188 /* 1189 * i2c_driver functions 1190 */ 1191 static int ov2640_probe(struct i2c_client *client) 1192 { 1193 struct ov2640_priv *priv; 1194 struct i2c_adapter *adapter = client->adapter; 1195 int ret; 1196 1197 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) { 1198 dev_err(&adapter->dev, 1199 "OV2640: I2C-Adapter doesn't support SMBUS\n"); 1200 return -EIO; 1201 } 1202 1203 priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL); 1204 if (!priv) 1205 return -ENOMEM; 1206 1207 if (client->dev.of_node) { 1208 priv->clk = devm_clk_get(&client->dev, "xvclk"); 1209 if (IS_ERR(priv->clk)) 1210 return PTR_ERR(priv->clk); 1211 ret = clk_prepare_enable(priv->clk); 1212 if (ret) 1213 return ret; 1214 } 1215 1216 ret = ov2640_probe_dt(client, priv); 1217 if (ret) 1218 goto err_clk; 1219 1220 priv->win = ov2640_select_win(SVGA_WIDTH, SVGA_HEIGHT); 1221 priv->cfmt_code = MEDIA_BUS_FMT_UYVY8_2X8; 1222 1223 v4l2_i2c_subdev_init(&priv->subdev, client, &ov2640_subdev_ops); 1224 priv->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | 1225 V4L2_SUBDEV_FL_HAS_EVENTS; 1226 mutex_init(&priv->lock); 1227 v4l2_ctrl_handler_init(&priv->hdl, 3); 1228 priv->hdl.lock = &priv->lock; 1229 v4l2_ctrl_new_std(&priv->hdl, &ov2640_ctrl_ops, 1230 V4L2_CID_VFLIP, 0, 1, 1, 0); 1231 v4l2_ctrl_new_std(&priv->hdl, &ov2640_ctrl_ops, 1232 V4L2_CID_HFLIP, 0, 1, 1, 0); 1233 v4l2_ctrl_new_std_menu_items(&priv->hdl, &ov2640_ctrl_ops, 1234 V4L2_CID_TEST_PATTERN, 1235 ARRAY_SIZE(ov2640_test_pattern_menu) - 1, 0, 0, 1236 ov2640_test_pattern_menu); 1237 priv->subdev.ctrl_handler = &priv->hdl; 1238 if (priv->hdl.error) { 1239 ret = priv->hdl.error; 1240 goto err_hdl; 1241 } 1242 #if defined(CONFIG_MEDIA_CONTROLLER) 1243 priv->pad.flags = MEDIA_PAD_FL_SOURCE; 1244 priv->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1245 ret = media_entity_pads_init(&priv->subdev.entity, 1, &priv->pad); 1246 if (ret < 0) 1247 goto err_hdl; 1248 #endif 1249 1250 ret = ov2640_video_probe(client); 1251 if (ret < 0) 1252 goto err_videoprobe; 1253 1254 ret = v4l2_async_register_subdev(&priv->subdev); 1255 if (ret < 0) 1256 goto err_videoprobe; 1257 1258 dev_info(&adapter->dev, "OV2640 Probed\n"); 1259 1260 return 0; 1261 1262 err_videoprobe: 1263 media_entity_cleanup(&priv->subdev.entity); 1264 err_hdl: 1265 v4l2_ctrl_handler_free(&priv->hdl); 1266 mutex_destroy(&priv->lock); 1267 err_clk: 1268 clk_disable_unprepare(priv->clk); 1269 return ret; 1270 } 1271 1272 static void ov2640_remove(struct i2c_client *client) 1273 { 1274 struct ov2640_priv *priv = to_ov2640(client); 1275 1276 v4l2_async_unregister_subdev(&priv->subdev); 1277 v4l2_ctrl_handler_free(&priv->hdl); 1278 mutex_destroy(&priv->lock); 1279 media_entity_cleanup(&priv->subdev.entity); 1280 v4l2_device_unregister_subdev(&priv->subdev); 1281 clk_disable_unprepare(priv->clk); 1282 } 1283 1284 static const struct i2c_device_id ov2640_id[] = { 1285 { "ov2640", 0 }, 1286 { } 1287 }; 1288 MODULE_DEVICE_TABLE(i2c, ov2640_id); 1289 1290 static const struct of_device_id ov2640_of_match[] = { 1291 {.compatible = "ovti,ov2640", }, 1292 {}, 1293 }; 1294 MODULE_DEVICE_TABLE(of, ov2640_of_match); 1295 1296 static struct i2c_driver ov2640_i2c_driver = { 1297 .driver = { 1298 .name = "ov2640", 1299 .of_match_table = of_match_ptr(ov2640_of_match), 1300 }, 1301 .probe = ov2640_probe, 1302 .remove = ov2640_remove, 1303 .id_table = ov2640_id, 1304 }; 1305 1306 module_i2c_driver(ov2640_i2c_driver); 1307 1308 MODULE_DESCRIPTION("Driver for Omni Vision 2640 sensor"); 1309 MODULE_AUTHOR("Alberto Panizzo"); 1310 MODULE_LICENSE("GPL v2"); 1311